APPARATUS AND METHOD FOR PERFORMING INTRA-PIXEL CROSSTALK REDUCTION FOR MULTIMODE IMAGING DEVICES - Patent application

Abstract

A pixelated imager capable of simultaneously supporting an EVS mode and an image frame capture mode of operation. Each pixel of the sensor comprises two separate sets of sub-pixels, each involved in the two modes, and at least two corresponding functionally distinct and independent electrical circuits. The metal interconnect structure of the imager IC is implemented with a wiring topology in which the spatial overlap between the wiring of the two electrical circuits is optimized (e.g., minimized) to reduce crosstalk between the circuits when the two circuits are simultaneously active. Such a wiring topology may be beneficial, for example, to provide improved image quality for both modes of operation.

Description

[Technical field]

[0001] Various exemplary embodiments relate to imaging devices, and more particularly, but not exclusively, to pixelated imagers that can support two or more modes of operation. [Background technology]

[0002] This section introduces aspects that may be helpful to facilitate a better understanding of the present disclosure. Accordingly, the statements in this section should be read in this light and not understood as admissions about what is in the prior art or what is not in the prior art.

[0003] Imagers are used in a variety of electronic imaging devices and systems, such as digital cameras, smartphones, medical imaging equipment, and night vision equipment. The two main types of imagers used in such imaging devices are charge-coupled device (CCD) sensors and active pixel complementary metal-oxide semiconductor (CMOS) sensors. In addition to the primary task of collecting light, CMOS image sensors may typically provide some processing and / or control functions directly in the sensor's integrated circuit (IC) and / or IC assembly. For example, the functional circuits of some CMOS sensors may enable one or more of timing and exposure control, analog-to-digital conversion, shuttering, white balancing, gain adjustment, and initial signal and / or image processing. Proper integration of such functional circuits into the sensor is typically necessary for optimal performance. Summary of the Invention [Problem to be solved by the invention]

[0004] Disclosed herein are various embodiments of a pixelated imager capable of simultaneously supporting an event-based vision sensor (EVS) mode and an image frame capture mode of operation. Each pixel of the sensor comprises two separate sets of sub-pixels, each involved in the two modes, and at least two corresponding functionally distinct and independent electrical circuits. The metal interconnect structure of the imager IC is implemented with a wiring topology in which the spatial overlap between the wiring of the two electrical circuits is optimized (e.g., minimized) to reduce crosstalk between the circuits when the two circuits are simultaneously active. Such a wiring topology may be beneficial, for example, to provide improved image quality for both operating modes. [Means for solving the problem]

[0005] According to an exemplary embodiment, an apparatus is provided that includes a first electronic chip having an array of light sensitive pixels along a light receiving surface of the first electronic chip, the pixels of the array including one or more first photodiodes and one or more second photodiodes, first and second transistors, and an interconnect structure vertically below the first and second photodiodes and the first and second transistors, the interconnect structure including a first conductor interconnecting the one or more first photodiodes and the first transistor to form a first electrical circuit. and an interconnect structure including a first photodiode and a second transistor and further including a second conductor interconnecting one or more second photodiodes and a second transistor to form a second electrical circuit, the first and second electrical circuits being functionally distinct and independent of one another, wherein the first conductor is disposed substantially in a portion of the interconnect structure vertically below a first area of ​​the light receiving surface within the pixel and the second conductor is disposed substantially in a portion of the interconnect structure vertically below a second area of ​​the light receiving surface within the pixel, the second area not overlapping the first area.

[0006] According to another exemplary embodiment, a method for fabricating a semiconductor device includes the steps of: (A) fabricating an electronic chip having an array of light sensitive pixels along a light receiving surface of the electronic chip, the pixels of the array comprising one or more first photodiodes and one or more second photodiodes and first and second transistors; and (B) forming an interconnect structure vertically below the first and second photodiodes and the first and second transistors, the interconnect structure comprising a first conductor that interconnects the one or more first photodiodes and the first transistor to form a first electrical circuit. and further including a second conductor interconnecting one or more second photodiodes and the second transistor to form a second electrical circuit, the first and second electrical circuits being functionally distinct and independent of one another, wherein the forming steps include: (B1) disposing the first conductor substantially within a portion of the interconnect structure vertically below a first area of ​​the light receiving surface within the pixel; and (B2) disposing the second conductor substantially within a portion of the interconnect structure vertically below a second area of ​​the light receiving surface within the pixel, wherein the second area does not overlap the first area.

[0007] Other aspects, features, and advantages of the various disclosed embodiments will become more fully apparent, by way of example, from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 shows a block diagram of an imaging system according to one embodiment. [Diagram 2] FIG. 2 illustrates a simplified three-dimensional perspective view of an IC assembly that can be used in the imaging system of FIG. 1 according to one embodiment. [Diagram 3] FIG. 3 shows a circuit block diagram of the IC assembly of FIG. 2 according to one embodiment. [Figure 4A] FIG. 4A illustrates an individual pixel of the IC assembly of FIG. 2 according to one embodiment. [Figure 4B]FIG. 4B illustrates an individual pixel of the IC assembly of FIG. 2 according to one embodiment. [Diagram 5] FIG. 5 illustrates a perspective three-dimensional cutaway view of a portion of the metal interconnect structure of the IC assembly of FIG. 2 according to one embodiment. [Figure 6A] FIG. 6A illustrates a circuit diagram of an exemplary on-chip electrical circuit that may be implemented on the photodetector chip of the IC assembly of FIG. 2 according to one embodiment. [Figure 6B] FIG. 6B illustrates a schematic diagram of an exemplary on-chip electrical circuit that may be implemented on the photodetector chip of the IC assembly of FIG. 2 according to one embodiment. [Figure 7] FIG. 7 illustrates an on-chip circuit layout of an individual pixel of the IC assembly of FIG. 2 according to one embodiment. [Figure 8] FIG. 8 shows an on-chip wiring layout of an individual pixel of the IC assembly of FIG. 2 according to one embodiment. [Figure 9] FIG. 9 shows an on-chip wiring layout of an individual pixel of the IC assembly of FIG. 2 according to another embodiment. [Figure 10] FIG. 10 shows an on-chip wiring layout of an individual pixel of the IC assembly of FIG. 2 according to yet another embodiment. [Figure 11] FIG. 11 shows an on-chip wiring layout of an individual pixel of the IC assembly of FIG. 2 according to yet another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] 1 shows a block diagram of an imaging system 100 according to one embodiment. The system 100 can be used, for example, in a camera of an industrial robot or an autonomous vehicle. Other uses of the system 100 are also conceivable.

[0010] As shown, the system 100 comprises an imaging lens 110, an electronic imaging device 120, a recording unit 130, and a control unit 140. In operation, the lens 110 directs incident light 112 to form an image of a corresponding object or scene on a light receiving surface of the imaging device 120. Such light receiving surface typically comprises a two-dimensional array of photodetectors (not explicitly shown in FIG. 1, see, e.g., FIG. 7) configured to perform light-to-electrical conversion to generate electrical signals representative of the image. In an exemplary embodiment, the imaging device 120 may also operate to apply some signal processing to the electrical signals, e.g., before outputting a corresponding digital signal 122 to the recording unit 130 for storage in its memory. Such memory may include, e.g., a solid-state memory device or other suitable form of memory. The control unit 140 may use the control signals 124, 126 to control and coordinate various operations and / or functions performed by the imaging device 120 and the recording unit 130.

[0011] 2 illustrates a simplified three-dimensional perspective view of an integrated circuit (IC) assembly 200 that may be used in imaging device 120 (FIG. 1) according to one embodiment. Assembly 200 includes a photodetector chip 210 and a logic chip 220 arranged in a vertical stack as shown in FIG.

[0012] As used herein, the term "stack" refers to an ordered arrangement of packaged or unpackaged dies in which the major planes of the stacked dies are opposed and in close proximity to one another. The opposing dies or chips may be electrically connected using, for example, patterned conductive (metallic or other) layers, ball grid arrays, solder bumps, wire bonds, or the like. In some such embodiments, the dies or chips of the stack may be mounted on a mechanical carrier in an orientation in which the major planes of the stacked dies are parallel to one another and / or to the major plane of the mechanical carrier. In some such embodiments, one of the dies or chips of the stack may function as the mechanical carrier. In some embodiments, the individual ICs of the stack may include any combination of one or more respective substrates, one or more redistribution layers (RDLs), one or more interposers, one or more laminates, or the like.

[0013] In this specification, the "major plane" of an object such as a die, a substrate, or an IC is a plane parallel to the substantially flat surface of the object that has the largest area among the outer surfaces of the object. This substantially flat surface may be referred to as the main surface. The outer surface of the object that has one relatively large size, e.g., length, but has a much smaller area, e.g., an area less than 1 / 2 of the main surface area, is typically referred to as the edge of the object.

[0014] In this specification, the term "vertical" refers to a direction approximately perpendicular to the main plane of the photodetector chip 210 or logic chip 220. In Fig. 2, the vertical direction is parallel to the Z coordinate axis. The term "horizontal" refers to a direction approximately parallel to the main plane. In Fig. 2, the horizontal plane is parallel to the XY coordinate plane.

[0015] In some embodiments, chips 210 and 220 may be flip-chip bonded using direct bonding, where opposing surfaces of the chips are planarized and the chips are stacked on one another to form assembly 200. In some other embodiments, chips 210 and 220 may be flip-chip bonded using Cu-Cu bonding, where copper (Cu) pads formed on opposing surfaces of the chips are bonded to provide electrical connections between the chips in assembly 200. In some alternative embodiments, other suitable chip stacking techniques may also be used.

[0016] FIG. 3 shows a circuit block diagram of the assembly 200 (FIG. 2) according to one embodiment. As shown in FIG. 3, the assembly 200 includes a pixel array unit 300, a driving circuit 310, a signal processing unit 320, an arbiter 330, and a column analog-to-digital converter (ADC) circuit 340. In an exemplary embodiment, the photodetector chip 210 (FIG. 2) may typically include the pixel array unit 300, while the logic chip 220 may typically include the driving circuit 310 and the arbiter 330. In alternative embodiments, some other practically feasible and / or functionally suitable partitions of the circuits 310, 320, 330, and 340 between the chips 210 and 220 may also be implemented.

[0017] The pixel array unit 300 comprises a plurality of pixels 302 arranged in a two-dimensional matrix array, with the individual pixels 302 arranged in mutually orthogonal rows and columns. The matrix array of pixels 302 occupies at least a portion of the above-mentioned light receiving surface of the imaging device 120. Each of the pixels 302 may typically include two or more sub-pixels, for example, as described in more detail below with reference to FIGS. 4A-4B. Some of the different sub-pixels of the same individual pixel 302 may differ, for example, in their respective sensitivity to different colors of light, the manner in which they are connected or not connected to the arbiter 330, the manner in which they are driven by the drive circuit 310, and / or the manner in which they are accessed by an external circuit. In an exemplary embodiment, the pixel array unit 300 may have a size in which the pixels 302 are arranged in 1280 columns and 720 rows. In other embodiments, other array sizes may also be used.

[0018] In operation, the sub-pixels of the pixel 302 may generate charge in response to received light. The drive circuit 320 may apply drive signals (e.g., voltages) to the pixel 302 and its sub-pixels to enable the pixel / sub-pixels to accumulate charge and then output corresponding electrical signals to the column ADC circuit 340. The arbiter 330 may be used for EVS mode, where the acronym EVS stands for "event-based vision sensor". More specifically, the arbiter 330 may operate to arbitrate requests from the different pixels 302 such that event-triggered readouts therefrom are performed in order of occurrence of the corresponding events. The column ADC circuit 340 may operate to convert the received analog electrical signals into digital form and direct the resulting digital signal 318 to the signal processing unit 320. The signal processing unit 320 may operate to perform appropriate signal processing such as correlated double sampling (CDS) processing, white balance adjustment, etc. The resulting processed signal 122 and the addresses of the event-triggered pixels may then be provided to a recording unit 130 (see also FIG. 1).

[0019] Some embodiments disclosed herein may benefit from at least some EVS features disclosed, for example, in U.S. Pat. No. 11,195,869, the entirety of which is incorporated herein by reference.

[0020] Figures 4A-4B show an individual pixel 302 according to one embodiment. More specifically, Figure 4A shows a schematic plan view of pixel 302. Figure 4B shows a side cross-sectional view of assembly 200 corresponding to the vertical cross-sectional plane AA marked in Figure 4A.

[0021] 4A, pixel 302 comprises 16 sub-pixels arranged in a 4×4 two-dimensional matrix array, i.e., 4 rows and 4 columns. The sub-pixels include (i) 4 EVS sub-pixels labeled E, and (ii) 12 imaging sub-pixels labeled R, G, B. The differently labeled imaging sub-pixels have different color filters, for example according to a conventional RGB color scheme. In alternative embodiments, other color schemes known to those skilled in the art (e.g., CMY, etc.) may also be used.

[0022] The 16 sub-pixels E, R, G, B of pixel 302 are arranged in four groups of four sub-pixels each. Each of the groups has exactly one of the E, R, G, and B sub-pixels arranged in a 2×2 array and is located in a respective one of the four quadrants of pixel 302. In the illustrated embodiment, each of the groups has the same arrangement and orientation of the sub-pixels, e.g., can be considered to have respective copies of the same 2×2 ERGB sub-pixel array. In alternative embodiments, some of the groups may differ from one another, e.g., in the relative order and / or location of the E, R, G, B sub-pixels therein. In some alternative embodiments, pixel 302 may include different numbers of sub-pixels and / or groups of sub-pixels.

[0023] Referring to FIG. 4B, each of the subpixels of the pixel 302 may have a respective optional lens 402 disposed adjacent to and along a major surface of the photoreceptor chip 210. Rear deep trench isolation (RDTI) is used at the subpixel boundaries to physically separate and laterally surround the photodiodes (PDs) of adjacent subpixels, as shown in FIG. 4B. Red, green, and blue color filters 404 may be located between the top surface of the corresponding PD in the R, G, and B subpixels, respectively, and the bottom surface of the corresponding lens 402. In the cross section shown, only the blue filter 404 is visible. The corresponding space 403 in the E subpixel may not have any color filter therein and may be filled with a suitable optically transparent colorless fill material, such as silicon oxide.

[0024] On-chip transistors 410i (where i=1, 2, ..., 5, ...) of the photo-receiver chip 210 are located in the device layer 406 of the chip, typically near the embedded edge of its RDTI structure. Metal interconnect structures 408 of the photo-receiver chip 210 are used to properly electrically connect the PDs and transistors 410i, and also to route electrical connections between the various circuit elements of the photo-receiver chip 210 and the logic chip 220.

[0025] For illustrative purposes, and without any implied limitation, the metal interconnect structure 408 is shown in FIG. 4B as having five vertically offset metal levels, labeled M1-M5. In alternative embodiments, a different number of such vertically offset metal levels may be used in the photoreceiver chip 210 as well. The spaces between the different conductors of the metal levels M1-M5 are typically filled with an interlevel dielectric (ILD), for example, as known in the art. The ILD layer may have metal filled vias therein to provide intended electrical connections between selected conductors of the different metal levels of the metal interconnect structure 408. The M5 level metal interconnect structure 408 is illustratively shown as having a plurality of metal pads 412 that mate with a corresponding plurality of metal pads 414 of the logic chip 220 to provide electrical connections between the chips.

[0026] 5 illustrates a perspective three-dimensional cutaway view of a portion 500 of interconnect structure 408 according to one embodiment. Portion 500 includes conductors 502a and 502b of metal level Mn and conductors 506a and 506b of metal level M(n+1), where n can be 1, 2, 3, or 4. Corresponding ILD layers are not explicitly shown in FIG. 5 for greater clarity of depiction.

[0027] As shown, conductors 502a,b and 506a,b are substantially flat horizontal metal tracks. In general, some of such metal tracks of the interconnect structure 408 may have, for example, L-shaped turns similar to those of conductor 506a. Some of the metal tracks, such as those of the Mn level conductors 502a and those of the M(n+1) level conductors 506b, may be directly electrically connected to each other using one or more metal-filled vertical vias, such as via 504. Some of such metal-filled vertical vias (not explicitly shown in FIG. 5) may span more than two metal levels of the interconnect structure 408 and may be implemented as stacks of vias corresponding to the individual levels of the structure.

[0028] 6A-6B show schematic diagrams of exemplary on-chip electrical circuitry that may be implemented on the photosensor chip 210 according to one embodiment. More specifically, FIG 6A shows circuitry 602 corresponding to the E sub-pixel of pixel 302. FIG 6B shows circuitry 604 corresponding to a subset of the R, G, and B sub-pixels of pixel 302.

[0029] In an exemplary embodiment, pixel 302 may include one instance of circuit 602 and two instances of circuit 604. The various transistors of such circuits 602 and 604 may be implemented using device layers 406 of the photosensor chip 210, for example, as described with reference to FIG. 4B. At least some of the electrical connections between the various circuit elements of circuit 602 and circuit 604 may be implemented using interconnect structures 408 of the photosensor chip 210 (see also FIGS. 4B and 5).

[0030] Referring to FIG. 6A, the photodiodes EPD1, EPD2, EPD3, and EPD4 of the circuit 602 are photodiodes of the E subpixel of the pixel 302 (see also FIGS. 4A-4B). The transistors LGT1, LGT2, AMP1, and AMP2 of the circuit 602 are configured to form a logarithmic current-to-voltage conversion circuit for processing the photocurrents generated by the photodiodes EPD1-EPD4. The voltage generated by this current-to-voltage conversion circuit appears at the terminal VPR. The terminals VDD, VSS, and VRL are connected to receive a fixed supply voltage. The voltage applied to the VRL terminal can be selected such that the photodiodes EPD1, EPD2, EPD3, and EPD4 are appropriately biased (e.g., negatively) to perform more efficient charge separation.

[0031] 6B, photodiodes PD1, PD2, PD3, PD4, PD5, and PD6 of circuit 604 are photodiodes of six R, G, and B subpixels of pixel 302, including two R, two G, and two B subpixels. Transistors AMP, SEL, and RST are shared by photodiodes PD1-PD6. Transistors TG1-TG6 are connected between each of photodiodes PD1-PD6 and the gate of transistor AMP. Terminal VSL is a signal readout terminal. Terminals VDD and VRL of circuit 604 may be connected to receive the same fixed supply voltages as the correspondingly labeled terminals of circuit 602.

[0032] FIG. 7 shows an on-chip circuit layout of an individual pixel 302 according to an embodiment. More specifically, FIG. 7 shows a plan view of the pixel 302 corresponding to the plan view shown in FIG. 4A. The labeling of the different circuit elements in FIG. 7 is the same as in FIG. 6A-6B. As already indicated above, an individual pixel 302 has one instance of the circuit 602 (FIG. 6A) and two instances of the circuit 604 (FIG. 6B). The label FD in FIG. 6B and FIG. 7 indicates a floating diffusion layer. The label EVS_SN in FIG. 7 indicates the nodes of the photodiodes EPD1-EPD4, which are used to electrically connect the photodiodes to the metal conductors of the interconnect structure 408. The label RDTI indicates the RDTI structure of the pixel 302, which is used to physically separate the different photodiodes of the pixel from each other (see also FIG. 4B).

[0033] Fabrication of the photodetector chip 210 having the array of pixels 302 of FIG. 7 can typically be carried out using two separate processing stages, commonly referred to as front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing.

[0034] During FEOL processing, individual circuit devices such as transistors, capacitors, resistors, etc., can be patterned and formed using the corresponding device layer of the wafer (see, for example, layer 406 in FIG. 6A) and any necessary additional semiconductor layers adjacent thereto. In the context of CMOS processing, FEOL processing typically encompasses fabrication steps directed to forming photodiodes and / or isolated electrical CMOS elements. Such fabrication steps can include, but are not limited to, (a) chemical mechanical planarization (CMP) and cleaning of the wafer, (b) device layer patterning, (c) trench isolation, e.g., RSTI, (d) well formation, (e) gate formation, (f) source and drain module formation, etc.

[0035] During BEOL processing, the individual circuit devices formed during FEOL processing may be electrically interconnected by forming appropriate metal interconnect structures, e.g., 408 of FIG. 4B. For example, contact pads, interconnect wires, vias, and various ILD layers may be formed. Example BEOL assembly steps may include, but are not limited to, (g) silicidation of source, drain, and polysilicon regions, (h) forming and patterning various dielectric layers, some of which may be used as optical cladding, (i) forming and patterning various metal layers, e.g., to create metal levels M1-M5 of FIG. 4B, (j) creating vias, e.g., 504 of FIG. 5, (k) forming passivation layers, etc.

[0036] After BEOL processing, the wafer may be subjected to post-assembly processing. Such processing may include, but is not limited to, wafer testing, wafer backgrinding, dicing, die testing, and chip packaging. In contrast to FEOL and BEOL processing, at least some of the steps of post-assembly processing may be performed outside a clean room environment. The circuits 602 and 604 may typically be operated with different operating modes of the imaging device 120. For example, as already mentioned above, the circuit 602 may be used in an EVS operating mode, where the E sub-pixels of the different pixels 302 may be continuously on, and the arbiter 330 may arbitrate event-triggered requests from the different pixels 302 for signal readout from their E sub-pixels. In contrast, the circuit 604 may be used for image frame capture, where the R, G, and B sub-pixels of the different pixels 302 may operate under the control of the frame capture circuitry of the imaging device 120. Thus, in some circumstances, the circuits 602 and 604 of the same pixel 302 may be active simultaneously. In such a situation, the signals generated by circuits 602 and 604 may interfere with and interact with each other, for example, due to electromagnetic crosstalk phenomena, thereby adversely affecting the quality of images generated in both the EVS mode and the image frame capture mode.

[0037] Various embodiments disclosed below are generally directed to reducing such interference and interactions.

[0038] For example, according to one possible embodiment, by using a metal interconnect structure 408 of the photoreceiver chip 210 specifically designed to reduce the above-mentioned crosstalk, a significant reduction in inter-modal interference in the imaging device 120 may be achieved by optimizing (e.g., minimizing) the spatial overlap within the pixel 302 between the metal wiring corresponding to the circuits 602 and 604. This and other related features of various embodiments of such a metal interconnect structure 408 are described in more detail below with reference to Figures 8-11. The described embodiments may beneficially improve the quality of images produced in both the EVS and image frame capture operating modes of the imaging device 120 due to the relatively low levels of inter-modal interference and interactions therein.

[0039] Each of Figures 8-11 illustrates a respective embodiment with a transparent plan view of the metal interconnect structure 408 that visualizes the on-chip circuit layout of the pixel 302 (see also Figure 7). The XY coordinate plane of Figures 8-11 represents the "main plane" of the photosensor chip 210 as defined above. The Z coordinate axis represents the "vertical" direction as defined above. The conductors of only some of the metal levels M1-M5 of the interconnect structure 408 are shown in Figures 8-11 for clarity. Figures 8-11 will be subsequently described below with reference to the circuit diagrams shown in Figures 6A-6B.

[0040] Figure 8 shows an on-chip wiring layout of an individual pixel 302 according to one embodiment. For clarity, only the conductors of metal levels M1 and M2 are explicitly shown in Figure 8. Also explicitly shown in Figure 8 is the VPR terminal of circuit 602 (see also Figure 6A), which is implemented as a rectangular pad in metal level M4 of interconnect structure 408.

[0041] In an exemplary embodiment, the conductors of metal level M1 extend primarily parallel to the X coordinate axis, i.e., are oriented such that their longitudinal directions are parallel to the X coordinate axis. The conductors of metal level M2 extend primarily parallel to the Y coordinate axis. As used herein, the term "primarily" means that more than 50% (preferably more than 75%) of the total conductor length of the indicated metal level has the indicated orientation.

[0042] Due to their mutually orthogonal orientation, the conductors of metal levels M1 and M2 form a substantially rectangular metal mesh vertically below the photodiode of pixel 302. In this specification, the term "below" is used with respect to the vertical propagation direction of incident light 112 (see also FIG. 4B). More specifically, in this context, "below" means in the downstream direction and "upward" means in the upstream direction.

[0043] In an exemplary embodiment, the conductors of metal levels M1 and M2 may be configured such that the corresponding metal meshes have approximately the same effective fill factor (e.g., within 10-15%) in their areas vertically below different photodiodes EPD1-EPD4 and PD1-PD6. As a result, such meshes may provide similar levels of optical reflection, scattering, and shielding for different sub-pixels of pixel 302, which may be beneficial for obtaining better image quality.

[0044] In FIG. 8, dashed lines indicate some of the relevant conductors in levels M1 and M2 used to implement the electrical connections of circuit 602. For example, electrical connection D0 (see also FIG. 6A) connecting the gate of transistor LGT1 to transistors AMP1 and AMP2 has a relatively long segment in metal level M1 and a relatively short segment in metal level M2. Electrical connection D1 (see also FIG. 6A) connecting the gate of transistor AMP2 to transistors LGT1 and LGT2 has a relatively long segment in both metal levels M1 and M2. Electrical connection Vpr (see also FIG. 6A) connecting the gate of transistor LGT2 to transistor AMP2 likewise has a relatively long segment in both metal levels M1 and M2. The VPR terminal (large rectangular pad in FIG. 8) located in metal level M4 is connected to one or more segments of electrical connection Vpr in metal levels M1 / M2 using a vertical stack of metal-filled vias. The four sensor nodes EVS_SN are connected in pairs using relatively long conductors in metal level M1. The two resulting connected EVS_SN node pairs are connected to each other using a relatively long conductor in level M2, which is further connected (i) to the gate of transistor AMP1 using a relatively short conductor in metal level M2, thereby implementing electrical connection Vpd (see also FIG. 6A), and (ii) to transistor LGT1 using another relatively short conductor in metal level M2.

[0045] The above configuration of the Vpr and Vpd connections may result in relatively low corresponding associated capacitances (hereinafter Cpr and Cpd, respectively), which is beneficial for achieving a fast EVS mode response of the pixel 302. Furthermore, a particular layout of the Vpr and Vpd connections may be selected such that the Cpr / Cpd ratio is about 0.3, e.g., 0.2-0.4, which is beneficial for achieving a relatively stable transfer function of the current-to-voltage converter of the circuit 602 under various operating conditions.

[0046] It should be noted that the above-mentioned wiring of the circuit 602 in levels M1 and M2 is concentrated primarily in a portion of the interconnect structure 408 that is vertically below a central section of the footprint of the pixels 302 on the light receiving surface of the light receiving chip 210 in the assembly 200 (see also FIG. 4B). In contrast, the wiring of the two instances of the circuit 604 in levels M1 and M2 is primarily distributed in other portions of the interconnect structure 408, e.g., portions that are primarily vertically below peripheral sections of the footprint of the pixels 302 that do not spatially overlap with the footprint of the central section. This feature of the interconnect structure 408 can be beneficial for suppressing inter-mode crosstalk, as explained above.

[0047] Figure 9 shows an on-chip wiring layout of an individual pixel 302 according to another embodiment. Figure 9 can be better understood by comparing it with Figure 8. Thus, the description of Figure 9 focuses primarily on the differences between the embodiments of Figures 8 and 9. The VPR terminal of circuit 602 (see also Figures 6A and 8), which is implemented as a rectangular pad in metal level M4, is not explicitly shown in Figure 9.

[0048] In the embodiment of Figure 9, at least one of the relatively long segments of electrical connection D1 is located in metal level M3 By comparison, in the embodiment of Figure 8, the corresponding portion of electrical connection D1 is located in metal level M2.

[0049] In the embodiment of Figure 9, at least some of the relatively long segments of electrical connection Vpr are located in metal level M3 By comparison, in the embodiment of Figure 8, corresponding portions of electrical connection Vpr are located in metal level M2.

[0050] In the embodiment of Figure 9, the two connected EVS_SN node pairs are connected to each other using relatively long conductors in metal level M3 By comparison, in the embodiment of Figure 8, the same electrical connections are implemented in metal level M2.

[0051] Implementation of these modifications may help to further suppress inter-mode crosstalk between circuits 602 and 604 of pixel 302 by increasing the effective physical separation between the wiring of these circuits within interconnect structure 408. However, this improvement may come with an associated cost of additional complexity in the BEOL manufacturability of interconnect structure 408, as more complex via stacks may be present within interconnect structure 408.

[0052] FIG. 10 shows an on-chip wiring layout of an individual pixel 302 according to yet another embodiment.

[0053] Figure 10 can be better understood by comparing it with Figure 9. Thus, the description of Figure 10 will focus primarily on the differences between the embodiments of Figures 9 and 10.

[0054] In the embodiment of Figure 10, another one of the relatively long segments of electrical connection D1 is now located on metal level M4, in comparison, in the embodiment of Figure 9, the corresponding portion of electrical connection D1 is located in metal level M1.

[0055] In the embodiment of Figure 10, the four sensor nodes EVS_SN are connected in pairs using relatively long conductors in metal level M4 By comparison, in the embodiment of Figure 9, the four sensor nodes EVS_SN are connected in pairs using relatively long conductors in metal level M1.

[0056] Implementation of these further modifications may help to further suppress inter-mode crosstalk between the circuits 602 and 604 of the pixel 302 by further increasing the effective physical separation between the wiring of these circuits within the interconnect structure 408. However, this improvement may come with an associated cost of additional complexity in the BEOL manufacturability of the interconnect structure 408, as there may be many more relatively complex via stacks.

[0057] 11 shows an on-chip wiring layout of an individual pixel 302 according to yet another embodiment. FIG. 11 can be better understood by comparing it with FIG.

[0058] Such a comparison immediately reveals in the embodiments of FIGS. 8 and 11 the different respective positions of the rectangular metal pad of terminal VPR in metal level M4.

[0059] In the embodiment of Fig. 11, the metal pad of terminal VPR has a portion thereof that is located vertically below each of the four quadrants of the light receiving surface of pixel 302. For example, the metal pad has a portion thereof that is located vertically below the geometric center of the light receiving surface of pixel 302. For a rectangular pixel shape, the geometric center is at the intersection of the two diagonals of the shape. In contrast, in the embodiment of Fig. 8, the metal pad of terminal VPR has a portion thereof that is located vertically below only two of the four quadrants of the light receiving surface of pixel 302.

[0060] Varying the location of the metal pads of terminal VPR may be used, for example, to optimize the Cpr / Cpd ratio described above. However, some care may be required in implementing such a change, since some locations of the metal pads may create a relatively high Cpr capacitance, which may detrimentally increase the effective response time of the pixel 302 in the EVS mode of operation.

[0061] In some embodiments, further optimization of pixel 302 may be performed using one or more of the following: (i) changing the size of one or more of the EVS_SN nodes; (ii) changing (e.g., decreasing) the amount of level M1 metal connected to the EVS_SN node; (iii) using heavy doping of device layer 406 to create conductors therein for electrically connecting some of the on-chip transistors of pixel 302 while removing corresponding conductors from metal interconnect structure 408; and (iv) changing the relative positions of the EVS_SN node and the FD layer of pixel 302 (e.g., increasing the distance between the EVS_SN node and the FD layer).

[0062] According to the exemplary embodiments disclosed above, e.g., in the Overview section and / or with reference to any one or any combination of some or all of FIGS. 1-11, a device may be provided that includes a first electronic chip (e.g., 210 in FIG. 2), the first electronic chip having an array (e.g., 300 in FIG. 3) of light sensitive pixels (e.g., 302 in FIG. 3) along a light receiving surface of the first electronic chip, the pixels of the array including one or more first photodiodes (e.g., EPD1-EPD4 in FIG. 7) and one or more second photodiodes (e.g., PD1-PD6 in FIG. 7), first and second transistors (e.g., LGT1, LGT2, AMP1, AMP2 in FIG. 6A, AMP, SEL, RST, TG1-TG6 in FIG. 6B), and a vertical arrangement of the first and second photodiodes and the first and second transistors. and a vertically downward interconnect structure (e.g., 408 in FIG. 4B ), the interconnect structure including a first conductor interconnecting one or more first photodiodes and a first transistor to form a first electrical circuit (e.g., 602 in FIG. 6A ) and further including a second conductor interconnecting one or more second photodiodes and a second transistor to form a second electrical circuit (e.g., 604 in FIG. 6B ), the first and second electrical circuits being functionally distinct and independent of one another, wherein the first conductor is disposed substantially in a portion of the interconnect structure vertically below a first area of ​​the light receiving surface within the pixel and the second conductor is disposed substantially in a portion of the interconnect structure vertically below a second area of ​​the light receiving surface within the pixel, the second area not overlapping the first area.

[0063] As used herein, the term "substantially" should be interpreted to mean that more than a certain percentage of the metal wiring in a described "portion of the interconnect structure" is of the described type, i.e., "first conductor" or "second conductor." Depending on the embodiment, the certain percentage may be, for example, 50%, 33.3%, or other suitable threshold. For example, for a pixel having two different circuits of approximately the same size, the threshold may be 50%, or possibly 75%. For a pixel having three different circuits of approximately the same size, the threshold may be 33.3%, or possibly 50%. In general, such thresholds may be determined in a relatively straightforward manner based on the number and relative sizes of the circuits in the pixel.

[0064] For example, for three circuits of approximately the same size, uniformly distributed wiring would result in 33% of the individual circuit wiring in any one-third sized portion of the metal interconnect. In contrast, according to an exemplary embodiment, the wiring distribution per circuit in such one-third sized portions may be, for example, 50:25:25, 25:50:25, and 25:25:50, respectively. Such selective wiring localization may be advantageous for at least some of the reasons already discussed above.

[0065] In some embodiments of the above device, the pixel further comprises an RDTI structure (e.g., RDTI of 4B, FIG. 7) that laterally surrounds each of the first and second photodiodes individually, where at least some of the first and second transistors are vertically below and adjacent to the buried edges of the RDTI structure (e.g., as shown in FIG. 4B, FIG. 7).

[0066] In some embodiments of any of the above devices, the pixel further comprises a plurality of color filters (e.g., 404 in FIG. 4B), each of the color filters being vertically above a respective one of the second photodiodes.

[0067] In some embodiments of any of the above devices, the pixel further comprises a plurality of lenses (e.g., 402 in FIG. 4B), each of the lenses being vertically above a respective one of the first and second photodiodes.

[0068] In some embodiments of any of the above devices, the interconnect structure comprises a vertical stack of metal levels (eg, M1-M5 in FIG. 4B).

[0069] In some embodiments of any of the above devices, the first conductors are present in two different metal levels of a vertical stack (eg, M1, M2 in FIG. 8).

[0070] In some embodiments of any of the above devices, the first conductors are present in three different metal levels of a vertical stack (eg, M1, M2, M3 in FIG. 9).

[0071] In some embodiments of any of the above devices, the first conductors are present in four different metal levels of a vertical stack (eg, M1, M2, M3, M4 in FIG. 10).

[0072] In any some embodiments of the above devices, most of the conductors in the top metal level of the stack (e.g., M1 in FIG. 8) are oriented parallel to a first direction in the major plane of the first electronic chip, where most of the conductors in the next-to-top metal level of the stack (e.g., M2 in FIG. 8) are oriented parallel to a second direction in the major plane, the second direction being orthogonal to the first direction.

[0073] In any some embodiments of the above apparatus, the conductors of the top and penultimate metal levels are positioned to provide a substantially uniform metal fill vertically below the first and second photodiodes.

[0074] In any of some embodiments of the above devices, the interconnect structure includes a metal pad at a bottom level of the stack (e.g., M4 in FIG. 8, FIG. 11), which is configured as an output terminal of the first circuit (e.g., VPR in FIG. 6A).

[0075] In some embodiments of any of the above apparatus, the metal pad has a portion thereof vertically below four different ones of the first and second photodiodes (e.g., as in Figures 8, 11).

[0076] In some embodiments of any of the above devices, the metal pad has a portion thereof vertically below the geometric center of the light-receiving surface within the pixel (eg, as in FIG. 11).

[0077] In some embodiments of any of the above devices, the first circuit comprises a logarithmic current-to-voltage converter (FIG. 6A) where the second circuit comprises a floating diffusion layer (e.g., FIG. 6B, FD in FIG. 7).

[0078] In any some embodiments of the above apparatus, the first circuit includes four first photodiodes.

[0079] In any some embodiments of the above apparatus, the second circuit includes six second photodiodes.

[0080] In some embodiments of any of the above apparatus, the pixel includes two instances of the second circuit.

[0081] In some embodiments of any of the above devices, the device further comprises a second electronic chip (e.g., 220 in FIG. 2 ) attached to the interconnect structure to form a vertical chip stack (e.g., 200 in FIG. 2 ), the second electronic chip including circuitry electrically connected to the first and second circuits via the interconnect structure.

[0082] In some embodiments of any of the above apparatus, the circuitry is configured to operate the first circuit using a first operating mode (e.g., an EVS mode) and is further configured to operate the second circuit using a functionally different second operating mode (e.g., an image frame capture mode).

[0083] In any some embodiments of the above apparatus, the circuitry is configurable to operate the first and second circuits by simultaneously performing the first and second modes of operation.

[0084] According to another exemplary embodiment disclosed above, for example, in the Overview section and / or with reference to any one or any combination of some or all of FIGS. 1-11, a method for fabricating a semiconductor device comprising the steps of: (A) fabricating an electronic chip (e.g., 210 in FIG. 2 ), the electronic chip having an array (e.g., 300 in FIG. 3 ) of light sensitive pixels (e.g., 302 in FIG. 3 ) along a light receiving surface of the electronic chip, the pixels of the array comprising one or more first photodiodes (e.g., EPD1-EPD4 in FIG. 7 ) and one or more second photodiodes (e.g., PD1-PD6 in FIG. 7 ) and first and second transistors (e.g., LGT1, LGT2, AMP1, AMP2 in FIG. 6A ; AMP, SEL, RST, TG1-TG6 in FIG. 6B ); and (B) fabricating an interconnect structure vertically below the first and second photodiodes and the first and second transistors. and forming an interconnect structure (e.g., 408 in FIG. 4B ), wherein the interconnect structure includes a first conductor interconnecting one or more first photodiodes and a first transistor to form a first electrical circuit (e.g., 602 in FIG. 6A ), and further includes a second conductor interconnecting one or more second photodiodes and a second transistor to form a second electrical circuit (e.g., 604 in FIG. 6B ), wherein the first and second electrical circuits are functionally distinct and independent of each other, wherein the forming includes the substeps of (B1) disposing the first conductor within a portion of the interconnect structure substantially vertically below a first area of ​​the light receiving surface within the pixel, and (B2) disposing the second conductor within a portion of the interconnect structure substantially vertically below a second area of ​​the light receiving surface within the pixel, wherein the second area does not overlap the first area.

[0085] Although the present disclosure includes reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications of the described embodiments, as well as other embodiments within the scope of the present disclosure that are apparent to those skilled in the art to which the present disclosure pertains, are deemed to be within the scope of the present disclosure, for example, as set forth in the following claims.

[0086] Some embodiments may be implemented as circuit-based processes, including possible implementations on a single integrated circuit.

[0087] Unless otherwise stated, each numerical value and range should be construed as an approximation, as if the word "about" or "approximately" were added before the value or range.

[0088] It will be further understood that various changes in the details, materials, and arrangements of parts described and illustrated to explain the nature and principles of the present disclosure may be made by those skilled in the art without departing from the scope of the present disclosure, as set forth, for example, in the following claims.

[0089] The use of figure numbers and / or figure reference characters (if any) in the claims is intended to identify one or more possible embodiments of the claimed subject matter to facilitate interpretation of the claims, and such use should not be construed as necessarily limiting the scope of those claims to the embodiment(s) shown in the corresponding figure.

[0090] Although the elements in the method claims which follow are recited in a particular order with corresponding labeling, if present, the elements are not necessarily intended to be limited to performance in that particular order, unless the recitation of the claims otherwise implies a particular order for performing some or all of the elements.

[0091] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present disclosure. The appearances of the phrase "in one embodiment" in various places in this specification do not necessarily all refer to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive with other embodiments. The same applies to the term "implementation form."

[0092] Unless otherwise specified herein, the use of the ordinal adjectives "first," "second," "third," etc. to refer to an object among a plurality of similar objects is intended only to indicate that different instances of such similar objects are being referenced, and is not intended to imply that the similar objects so referenced must be in a corresponding order or sequence in time, space, ranking, or otherwise.

[0093] Unless otherwise specified herein, the conjunction "if" may be construed to mean "when" or "when" or "response to determining" or "response to detecting" in addition to, or in addition to, its plain meaning, and the interpretation may depend on the particular context to which it corresponds. For example, the phrase "if determined" or "if [predetermined condition] is detected" may be construed to mean "upon determining" or "in response to determining" or "upon detection of [predetermined condition or event]" or "in response to detecting [predetermined condition or event]."

[0094] Throughout the detailed description, drawings that are not to scale are merely illustrative and are used to explain, rather than limit, the present disclosure. The use of terms such as height, length, width, top, bottom, etc., is strictly to facilitate the description of the embodiments and is not intended to limit the embodiments to a particular orientation. For example, height is used to identify one of the three dimensions of a three-dimensional structure as shown in the figures, rather than implying only a vertical lift limit. Such a "height" may be vertical if the electrodes are horizontal, horizontal if the electrodes are vertical, etc. Similarly, while some of the figures show different layers as horizontal layers, such an orientation is merely illustrative and should not be construed as limiting.

[0095] Also, for purposes of this specification, the terms "couple," "coupling," "coupled," "connect," "connecting," or "connected" refer to any manner known in the art or later developed in which energy is enabled to be transferred between two or more elements, the intervening presence of one or more additional elements being contemplated, but not required. Conversely, terms such as "directly coupled," "directly connected," and the like, imply the absence of such additional elements. The same type of distinction applies to the use of the terms "attached" and "directly attached" as applied to descriptions of physical structures. For example, a relatively thin layer of adhesive or other suitable bonding agent may be used to effect such a "direct attachment" of two corresponding components in such a physical structure.

[0096] The described embodiments are to be considered in all respects only as illustrative and not restrictive. In particular, the scope of the present disclosure is indicated by the appended claims rather than by the description and drawings of this specification. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0097] The description and drawings merely illustrate the principles of the present disclosure. Thus, it will be understood that those skilled in the art can devise various configurations that embody the principles of the present disclosure and are included within its scope, although not explicitly described or illustrated herein. Furthermore, all examples listed herein are expressly intended to be merely for educational purposes to help the reader understand the principles of the present disclosure and the concepts contributed by the inventor to advance the art, and should not be construed as being limited to such specifically listed examples and conditions. Furthermore, all statements herein that list the principles, aspects, and embodiments of the present disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0098] The functionality of the various elements illustrated in the figures, including any functional blocks labeled "processor" and / or "controller", may be provided through the use of dedicated hardware and hardware capable of executing software in association with appropriate software. When provided by a processor, the functionality may be provided by a single dedicated processor, by a single shared processor, or by multiple individual processors, some of which may be shared. Furthermore, the explicit use of the terms "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, but is not limited to, digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and / or customary, may also be included. Similarly, any switches illustrated in the figures are conceptual only. Their functionality may be performed through the operation of program logic, through dedicated logic, through the interaction of program control with dedicated logic, or even manually, with the particular technique being selectable by the implementer as more specifically understood from the context.

[0099] As used in this application, the term "circuitry" may refer to one or more or all of the following: (a) hardware-only circuit implementations (such as implementations with only analog and / or digital circuitry); (b) (where applicable) (i) combinations of analog and / or digital hardware circuitry and software / firmware; and (ii) combinations of hardware circuitry and software, such as any portion of a hardware processor having software (including digital signal processors), software, and memory that cooperate to cause a device such as a cell phone or server to perform various functions; and (c) hardware circuitry and a processor, such as a microprocessor and / or a portion of a microprocessor, that requires software (e.g., firmware) to operate, but may not be present if not required for operation. This definition of circuitry applies to all uses of the term in this application, including any claims. As a further example, as used in this application, the term circuitry also covers implementations of just a hardware circuit or processor (or processors), or a portion of a hardware circuit or processor, and the software and / or firmware associated therewith (or therewith). The term circuitry also covers, for example, baseband or processor integrated circuits for mobile devices, or similar integrated circuits in servers, cellular network devices, or other computing or network devices, where applicable to particular claim elements.

[0100] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the present disclosure.

[0101] This Summary is intended to introduce some example embodiments, with additional embodiments described in the Detailed Description and / or with reference to one or more of the Figures. This Summary is not intended to identify essential elements or features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

Claims

1. 1. An apparatus comprising a first electronic chip having an array of light sensitive pixels along a light receiving surface of the first electronic chip, the pixels of the array comprising: one or more first photodiodes and one or more second photodiodes; first and second transistors; an interconnect structure vertically below the first and second photodiodes and the first and second transistors, the interconnect structure including a first conductor interconnecting the one or more first photodiodes and the first transistor to form a first electrical circuit, and further including a second conductor interconnecting the one or more second photodiodes and the second transistor to form a second electrical circuit, the first and second electrical circuits being functionally distinct and independent of one another; Equipped with the first conductor is disposed within a portion of the interconnect structure substantially vertically below a first area of ​​the light receiving surface within the pixel; the second conductor is disposed within a portion of the interconnect structure substantially vertically below a second area of ​​the light receiving surface within the pixel, the second area not overlapping the first area; Device.

2. the pixel further comprising a RDTI structure laterally surrounding each of the first and second photodiodes individually; at least some of the first and second transistors are vertically below and adjacent to a buried edge of the RDTI structure; 2. The apparatus of claim 1.

3. 2. The apparatus of claim 1, wherein the pixel further comprises a plurality of color filters, each of the color filters being vertically above a respective one of the second photodiodes.

4. 2. The apparatus of claim 1, wherein the pixel further comprises a plurality of lenses, each of the lenses being vertically above a respective one of the first and second photodiodes.

5. The device of claim 1 , wherein the interconnect structure comprises a vertical stack of metal levels.

6. The device of claim 5 , wherein the first conductor is in two different metal levels of the vertical stack.

7. The device of claim 5 , wherein the first conductor is present in three different metal levels of the vertical stack.

8. The device of claim 5 , wherein the first conductors are present in four different metal levels of the vertical stack.

9. a majority of conductors in a top metal level of the vertical stack are oriented parallel to a first direction in a major plane of the first electronic chip; a majority of the conductors in a second-uppermost metal level of the vertical stack are oriented parallel to a second direction in the major plane, the second direction being orthogonal to the first direction; 6. The apparatus of claim 5.

10. 10. The apparatus of claim 9, wherein the conductors of the top and penultimate metal levels are positioned to provide a substantially uniform metal fill vertically below the first and second photodiodes.

11. The apparatus of claim 5 , wherein the interconnect structure includes a metal pad in a bottom level of the vertical stack, the metal pad configured as an output terminal of the first electrical circuit.

12. 12. The apparatus of claim 11, wherein the metal pad has a portion of the metal pad vertically below four different ones of the first and second photodiodes.

13. The device of claim 11 , wherein the metal pad has a portion of the metal pad vertically below a geometric center of the light-receiving surface within the pixel.

14. the first electrical circuit comprises a logarithmic current-to-voltage converter; the second electrical circuit comprises a floating diffusion layer; 2. The apparatus of claim 1.

15. The apparatus of claim 1 , wherein the first electrical circuit includes four of the first photodiodes.

16. The apparatus of claim 1 , wherein the second electrical circuit includes six of the second photodiodes.

17. The device of claim 1 , wherein the pixel comprises two instances of the second electrical circuit.

18. 10. The apparatus of claim 1, further comprising a second electronic chip attached to the interconnect structure to form a vertical chip stack, the second electronic chip including circuitry electrically connected to the first and second electrical circuits by the interconnect structure.

19. the circuitry is configured to operate the first electrical circuit using a first mode of operation and is further configured to operate the second electrical circuit using a functionally different second mode of operation; the circuitry being configurable to operate the first and second electrical circuits by simultaneously executing the first and second modes of operation; 20. The apparatus of claim 18.

20. 1. Assembling an electronic chip, the electronic chip having an array of light sensitive pixels along a light receiving surface of the electronic chip, the pixels of the array comprising: one or more first photodiodes and one or more second photodiodes; first and second transistors; and assembling the forming an interconnect structure vertically below the first and second photodiodes and the first and second transistors, the interconnect structure including a first conductor interconnecting the one or more first photodiodes and the first transistor to form a first electrical circuit, and further including a second conductor interconnecting the one or more second photodiodes and the second transistor to form a second electrical circuit, the first and second electrical circuits being functionally distinct and independent of one another, wherein the forming disposing the first conductor within a portion of the interconnect structure substantially vertically below a first area of ​​the light receiving surface within the pixel; disposing a second conductor within a portion of the interconnect structure substantially vertically below a second area of ​​the light receiving surface within the pixel, the second area not overlapping the first area; Manufacturing method.

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