Metal silicide contact formation

Abstract

A metal silicide contact formation process is provided that includes providing a substrate having an underlying crystalline silicon and a dielectric sidewall. This may be followed by a metal layer deposition using a metal halide precursor and a reducing agent to selectively form a metal layer on the underlying crystalline silicon. The ratio of the reducing agent flow rate to the metal halide precursor flow rate is at least 10:1, or between 10:1 and 10,000:1. After metal layer deposition, the substrate is annealed to convert the metal layer to a metal silicide layer without substrate contamination.

Description

[Technical field]

[0001] Incorporation by Reference A PCT application form is being filed contemporaneously herewith as part of this application. Each application to which this application claims benefit or priority, as identified in the contemporaneously filed PCT application form, is hereby incorporated by reference in its entirety and for all purposes. [Background technology]

[0002] Metal silicides may be formed in the fabrication of various semiconductor devices. For example, dynamic random access memories (DRAMs) may include metal silicide contacts on crystalline silicon. Formation of silicides for complex structures such as 3D-DRAM structures can be challenging.

[0003] The discussion of the background art provided herein is intended to generally present the context of the present disclosure. The work of the presently named inventors, to the extent that their work is described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure. Summary of the Invention

[0004] A method is provided for forming a metal silicide contact in a feature including an underlying crystalline silicon surface and an oxide or nitride sidewall surface. The method may involve depositing tungsten (W) or molybdenum (Mo) on the underlying crystalline silicon without depositing W or Mo on the sidewall surface. The W or Mo film is then deposited with tungsten silicide (WSi x ) or molybdenum silicide (MoSi x ) The annealing can be performed in situ without breaking vacuum. In some embodiments, the annealing is performed without a capping layer.

[0005] One aspect of the disclosure relates to a method that includes providing a feature having a feature bottom and a feature sidewall. The feature bottom includes a crystalline silicon surface and the feature sidewall includes an oxide or nitride surface. The method further includes exposing the feature to a metal halide precursor flow including a metal halide precursor and a reducing agent flow including a reducing agent, thereby selectively forming a metal layer on the crystalline silicon surface. The metal halide precursor flow and the reducing agent flow have a flow ratio of at least 10:1. The method still further includes annealing the metal layer to form a metal silicide layer from the metal layer.

[0006] In some embodiments, the method further includes cleaning the feature bottom and feature sidewalls prior to exposing the feature to the metal halide precursor flow.

[0007] In some embodiments, the metal halide precursor comprises a metal chloride or a metal fluoride.

[0008] In some such embodiments, the metal halide precursor comprises tungsten hexafluoride, tungsten pentachloride, molybdenum hexafluoride, or molybdenum pentachloride.

[0009] In some embodiments, the metal layer comprises tungsten or molybdenum.

[0010] In some embodiments, the reducing agent comprises hydrogen, a silane, or a combination thereof.

[0011] In some embodiments, the flow ratio ranges from about 10:1 to about 10,000:1.

[0012] In some embodiments, the thickness of the metal layer ranges from about 2 nm to about 20 nm thick.

[0013] In some embodiments, the crystalline silicon of the crystalline silicon surface is doped or undoped single crystalline silicon crystal or doped or undoped polycrystalline silicon.

[0014] In some embodiments, annealing the metal layer is performed at between about 500°C and about 800°C.

[0015] In some embodiments, annealing the metal layer is performed under a pressure ranging from 1 to 100 Torr.

[0016] In some embodiments, the flow of a metal halide precursor and the flow of a reducing agent are alternated to form a metal layer by atomic layer deposition (ALD).

[0017] In some embodiments, a flow of a metal halide precursor and a flow of a reducing agent are co-flowed to form a metal layer by chemical vapor deposition (CVD).

[0018] In some embodiments, to form a metal layer by pulsed CVD, the metal halide precursor flow is pulsed and the reducing agent flow is continuous.

[0019] In some embodiments, the metal suicide layer forms an ohmic connection with the crystalline silicon surface.

[0020] In some embodiments, the metal silicide layer comprises tungsten silicide or molybdenum silicide.

[0021] Another aspect of the disclosure relates to a method including providing a feature having a feature bottom and a feature sidewall. The feature bottom includes a crystalline silicon surface and the feature sidewall includes an oxide or nitride surface. The method further includes exposing the feature to a first metal halide precursor flow including a first metal halide precursor and a first reducing agent flow including a first reducing agent, thereby selectively forming a first metal layer on the crystalline silicon surface. The first metal halide precursor flow and the first reducing agent flow have a flow ratio of at least 10:1. The method still further includes providing a second metal halide precursor flow including a second metal halide precursor and a second reducing agent flow including a second reducing agent to the first metal layer to form a second metal layer. The second metal halide precursor flow and the second reducing agent flow have a flow ratio of at least 10:1. The method still further includes annealing the second metal layer to form a metal silicide layer.

[0022] In some embodiments, the first metal halide precursor and the second metal halide precursor are each selected from tungsten hexafluoride, tungsten pentachloride, molybdenum hexafluoride, and molybdenum pentachloride.

[0023] In some embodiments, the first reducing agent and the second reducing agent are each selected from hydrogen, silane, or a combination thereof.

[0024] In some embodiments, the metal silicide layer comprises tungsten silicide or molybdenum silicide.

[0025] In some embodiments, the first and second metal halide precursors and the first and second reducing agents are provided by chemical vapor deposition or atomic layer deposition.

[0026] These and other aspects are further described below with reference to the drawings. [Brief description of the drawings]

[0027] [Figure 1A] 1A-1D are schematic diagrams illustrating cross-sectional views of concave lateral contacts in a 3D dynamic random access memory (3D-DRAM) prior to metal silicide layer formation, according to various embodiments. [Figure 1B] 1A-1C are schematic diagrams illustrating cross-sectional views of lateral contacts in a 3D-DRAM structure after forming a metal silicide layer and a barrier metal / bottom electrode according to various embodiments.

[0028] [Diagram 2] 1A-1C are schematic diagrams illustrating cross-sectional views of features in a vertical structure according to various embodiments.

[0029] [Diagram 3] FIG. 1 is a process flow diagram illustrating some operations in a method, according to various embodiments.

[0030] [Figure 4A] FIG. 2 is a schematic diagram illustrating providing tungsten hexafluoride (WF6) and hydrogen (H2) to a silicon (Si) surface in accordance with various embodiments.

[0031] [Figure 4B] 1A-1C are schematic diagrams illustrating cross-sectional views of tungsten (W) layer formation on Si using WF6 / H2 according to various embodiments.

[0032] [Diagram 5] 1A-1C are schematic diagrams illustrating cross-sectional views of W metal layer formation using WF6 / H2 according to various embodiments.

[0033] [Figure 6A] 1A-1C are schematic diagrams illustrating cross-sectional views of W metal layer formation using WF6 / SiH4 according to various embodiments. [Figure 6B] 1A-1C are schematic diagrams illustrating cross-sectional views of W metal layer formation using WF6 / H2 according to various embodiments.

[0034] [Figure 7A]1A-1C are schematic diagrams illustrating cross-sectional views of W metal layer formation using WF6 / H2 according to various embodiments. [Figure 7B] 1A-1C are schematic diagrams illustrating cross-sectional views of W metal layer formation using WCl5 / H2 according to various embodiments.

[0035] [Figure 8A] FIG. 2 is a diagram of an example of a flow sequence for a pulsed chemical vapor deposition (CVD) process that may be used to form a metal layer.

[0036] [Figure 8B] FIG. 2 is a diagram of an example of a flow sequence for a co-flow CVD process that may be used to form a metal layer.

[0037] [Figure 8C] FIG. 2 is a diagram of another example of a flow sequence for a parallel flow CVD process that may be used to form a metal layer.

[0038] [Figure 8D] FIG. 1 illustrates an example of a flow sequence for an atomic layer deposition (ALD) process that may be used to form a metal layer.

[0039] [Figure 9] FIG. 1 illustrates an example of an apparatus that can be used to implement the methods described herein.

[0040] [Figure 10A] FIG. 1 illustrates an example of an apparatus that can be used to implement the methods described herein.

[0041] [Figure 10B] FIG. 1 illustrates an example of an apparatus that can be used to implement the methods described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] A method of forming a metal silicide contact with crystalline silicon is provided. The method involves forming a metal layer including tungsten (W) or molybdenum (Mo) followed by annealing to convert the metal layer to a metal silicide layer. The metal layer may be formed in a pulsed chemical vapor deposition (CVD) process, a parallel flow CVD process, or an atomic layer deposition (ALD) process. In some embodiments, the annealing is performed without first forming a capping layer.

[0043] In semiconductor device fabrication, forming electrical contacts may involve forming a metal layer in a recessed feature with tungsten, molybdenum, or other conductive material. The features may include holes, trenches, and vias. The metal layer in the feature may be annealed to form a metal silicide. The metal silicide may form an ohmic connection with the semiconductor silicon and reduce the contact resistance. For example, W provides a low resistance and low stress layer and has a thermal expansion coefficient close to that of silicon. Tungsten also has a high resistance to electromigration.

[0044] When metal layers such as tungsten are formed from halide precursors, uncontrolled metal growth can result in non-uniform interfaces between the metal and silicon, depending on the nature and reactions of competing precursors and other reactants. These defects can be the cause of non-uniform contact resistance at the contact or semiconductor device failure. These defects can be critical for devices with smaller technology nodes and more complex patterning structures, where uniform metal growth is a major challenge.

[0045] Uniform metal growth can be a particular challenge in 3D dynamic random access memory (3D DRAM) structures, which may include hundreds of vertically stacked lateral features. 3D DRAMs include an increased number of contacts, but the contact area is reduced compared to previous semiconductor devices. Deposition in 3D DRAM structures by methods such as sputtering a metal target in a physical vapor deposition (PVD) method can be particularly challenging with most of the structure outside the line of sight of the deposition species. Plasma-based methods such as plasma-enhanced CVD (PECVD) can also have poor step coverage in complex geometries. Uniform metal growth can also be a challenge in vertical structures, such as in vertical DRAM or logic structures that include multiple vertical features. In particular, deposition in high or high aspect ratio structures formed during many stacks can be challenging.

[0046] In some embodiments, the methods described herein include deposition of a metal layer using a metal halide precursor. In some embodiments, the methods described herein include deposition of a thin tungsten layer using a tungsten halide precursor. The tungsten halide precursor has the formula WX z where X is a halogen (fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)) and z is 2, 3, 4, 5, or 6. WX z Examples of precursors include tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), and tungsten pentachloride (WCl5). In some embodiments, the desired thickness of the W layer can range from about 3 nm to 5 nm.

[0047] In some embodiments, the processes described herein involve the deposition of a thin molybdenum layer using a molybdenum halide precursor having the formula MoX z where X is a halogen (fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)) and z is 2, 3, 4, 5, or 6. MoX zAn example of a precursor includes molybdenum hexafluoride (MoF6). A molybdenum chloride precursor has the formula MoCl x where x is 2, 3, 4, 5, or 6, and the molybdenum chloride precursors include molybdenum dichloride (MoCl2), molybdenum trichloride (MoCl3), molybdenum tetrachloride (MoCl4), molybdenum pentachloride (MoCl5), and molybdenum hexachloride (MoCl6). In some embodiments, the desired thickness of the Mo layer can range from about 3 to 5 nm.

[0048] Using a non-oxygen containing precursor to deposit the first W or Mo layer prevents oxidation of the surface of the feature. It also prevents oxygen from being incorporated into the first W or Mo layer. Oxidation increases the contact resistance. The lack of oxidation and oxygen incorporation ensures that the contact resistance remains low.

[0049] Examples of reducing agents include hydrogen (H2), silane (SiH4), diborane (B2H6), germane (GeH4), ammonia (NH3), and hydrazine (N2H4). In some embodiments, two or more reducing agents in a predetermined mixing ratio may be pulsed with a tungsten halide precursor or a molybdenum halide precursor to form tungsten or molybdenum metal.

[0050] 1(a) and 1(b) are schematic diagrams illustrating cross-sectional features in a 3D DRAM structure according to various embodiments. A concave feature 102 has a sidewall 106 with a sidewall surface 116 and a bottom portion including crystalline silicon 108. The crystalline silicon 108 includes a crystalline silicon surface 110. The concave feature 102 can be, for example, a hole or a trench. The sidewall 106 can be made of one or more layers. The sidewall 106 includes a dielectric layer. Examples of dielectric materials include oxides such as silicon oxide (SiO2) and aluminum oxide (Al2O3), nitrides such as silicon nitride (SiN), carbides such as nitrogen-doped silicon carbide (NDC) and oxygen-doped silicon carbide (ODC), and low-k dielectrics such as carbon-doped SiO2.

[0051] The crystalline silicon 108 may extend from a first sidewall in the feature to a second sidewall in the feature and may be made in one or more layers. The crystalline silicon 108 of the crystalline silicon surface 110 may be doped or undoped single crystal silicon, or doped or undoped polycrystalline silicon. In one embodiment, the crystalline silicon 108 may be doped polycrystalline silicon (doped poly-Si). In some embodiments, the crystalline silicon 108 may form a gate electrode.

[0052] As shown in FIG. 1(b), a metal silicide layer 112 may be selectively formed on the crystalline silicon 108 to form an ohmic connection. The thickness of the metal silicide layer 112 on the crystalline silicon 108 may range from 2 to 10 nm. As described further below, the metal silicide layer 112 may be formed by forming a metal layer on the crystalline silicon 108, followed by annealing to convert the metal layer to the metal silicide layer 112. In some embodiments, the metal layer may be formed using parallel flow CVD, pulsed CVD, or ALD. Following the formation of the metal silicide layer 112, a conformal layer 114 may be formed on the metal silicide layer and the sidewall surface 116. In some embodiments, the conformal layer 114 may be a barrier layer, or a bottom electrode of a capacitor. For example, titanium nitride (TiN) may be used as a barrier metal.

[0053] A challenge associated with the 3D-DRAM fabrication process described above is the formation of metal silicide contacts at the bottom of each concave feature. Controlled and selective formation of a metal layer on the bottom of each concave feature before the metal layer is annealed to form a metal silicide layer can be difficult. Forming a metal layer selectively and uniformly on the Si can be affected by the dimensions of the feature on which the metal layer is formed. In some embodiments, the concave feature 102 has a depth "A" of 100-300 nm and a height "B" of 10-30 nm, resulting in an aspect ratio (depth to height) of 3-30. These small feature sizes and high aspect ratios present challenges in forming the metal layer. In some embodiments, the 3D-DRAM structure can include a stack including over 400 layers (features) stacked vertically. The total stack height "C" can range from about 6-12 μm. This configuration can also add additional complexity in achieving uniform, selective metal layer formation on each. In some embodiments, techniques used for selective deposition in other structures, such as PVD or PECVD, may not be suitable for uniformly and selectively forming metal layers in the recessed features of a 3D-DRAM structure.

[0054] FIG. 2 is a schematic diagram showing cross-sectional features in a vertically oriented feature. Such features may be used, for example, in a DRAM or logic device. The device may include one or more concave features 202 having a lower surface 210 and sidewalls 206. The concave features 202 may extend in a vertical direction relative to the substrate. The method of selectively forming a metal silicide layer 214 from a metal layer described herein for horizontally oriented concave features in a 3D-DRAM structure may also be used for vertically oriented structures, such as those in a DRAM and / or logic device.

[0055] 3 is a process flow diagram illustrating a method for forming a metal silicide ohmic connection from a metal layer to the underlying crystalline silicon according to some embodiments. The metal layer can be a tungsten (W) film or a molybdenum (Mo) film. Example applications include 3D-NAND, 3D-DRAM, 2D-DRAM, and logic applications.

[0056] Method 300 begins in operation 301 with providing a substrate including features having an underlying silicon and an oxide or nitride sidewall onto which tungsten or molybdenum will be deposited depending on device and / or processing requirements. The substrate may be provided to a semiconductor processing tool. For example, the substrate may be placed in a deposition chamber.

[0057] After providing a substrate including a feature having an underlying crystalline silicon and an oxide or nitride sidewall, an optional clean, operation 302, may be performed. The optional clean may be used to remove an oxide layer formed on the surface of the feature. In some embodiments, atomic layer cleaning with a Cl-based plasma, hydrogen fluoride (HF) vapor cleaning, ammonium fluoride (NH4F) cleaning, or treatment using other reducing agents may be used to reduce the oxide of Si at the bottom of the feature. In some embodiments, hydrogen fluoride may be diluted to about 100:1 prior to cleaning. The optional clean may be performed in the deposition chamber. Alternatively, the optional clean may be performed in a separate process prior to being provided to the deposition chamber.

[0058] Once the substrate is provided in the deposition chamber, a metal layer is formed in the feature in operation 303. The metal layer, including a tungsten layer or a molybdenum layer, may be deposited by parallel flow CVD, pulsed CVD, or ALD.

[0059] In parallel flow CVD, the metal halide precursor and the reducing agent are pulsed sequentially, thus exposing the substrate to the metal halide precursor, including but not limited to tungsten hexafluoride, tungsten pentachloride, molybdenum hexafluoride, or molybdenum pentachloride, and the reducing agent sequentially. Pulsing can continue until a metal layer with a predetermined thickness is formed. Alternatively, the metal halide precursor and the reducing agent can be pulsed for parallel flow with a carrier gas, such as an inert gas, purging between parallel flow pulses. In a pulsed CVD process, the reducing agent can be flowed continuously, but the metal halide precursor is pulsed with an interval between pulses, thus exposing the substrate to the precursor during the pulse. In an ALD process, the metal halide precursor, the reducing agent, and the carrier gas can be pulsed sequentially to form one cycle. In some embodiments, the pulsed cycle can include a pulsed sequence of the metal halide precursor, the carrier gas, the reducing agent, and the carrier gas.

[0060] In some embodiments, pulsing may include two or more pulsing steps. For example, two or more metal halide precursors and / or reducing agents may be pulsed sequentially in multiple pulsing steps. In a first pulsing step, the substrate may be exposed to a first precursor and a first reducing agent to form a first metal layer on the substrate. In a second pulsing step, the substrate may be exposed to a second precursor and a second reducing agent to form a second metal layer on the first metal layer formed in the first pulsing step. In some embodiments, the metal layer may be formed conformally to the underlying crystalline silicon. The metal layer may be about 2-20 nm thick in some embodiments. The metal layer may be about 2-10 nm thick, 3-7 nm thick, or 3-5 nm thick in some embodiments.

[0061] During metal layer formation, the temperature of the substrate and the pressure of the chamber can be controlled. For parallel flow CVD and pulsed CVD, the substrate can be heated to between 250° C. and 350° C. In some embodiments, the chamber can be pressurized to at least 10 Torr, such as at least 30 Torr, or at least 50 Torr. For ALD processes, in some embodiments, the substrate can be heated to between 300° C. and 500° C., such as between 350° C. and 450° C. In some embodiments, the chamber can be pressurized to at least 10 Torr, such as at least 30 Torr, or at least 50 Torr.

[0062] After the metal layer is selectively deposited on the silicon surface, in operation 304, the feature is annealed to convert the metal layer to a metal silicide layer. In some embodiments, the metal layer may be annealed by rapid thermal annealing. In some embodiments, the thickness of the metal silicide layer after annealing may range from about 2 to 10 nm. The annealing is generally performed at between 500° C. and 800° C., for example, between 500° C. and 700° C. The metal layer may be annealed in situ in the deposition chamber in which the metal layer is formed, without exposing the metal layer to an ambient atmosphere. In some embodiments, the substrate including the metal layer is transferred from one pedestal to another pedestal for annealing. After the metal silicide layer formation, a barrier layer (or bottom electrode) may be formed on the metal silicide layer and the sidewalls.

[0063] 4A and 4B show schematic diagrams illustrating the formation of a tungsten layer from the reaction between WF6 / H2 and Si, according to various embodiments. In some embodiments, in a CVD or ALD process, when a metal halide precursor, such as tungsten hexafluoride (WF6), and a reducing agent, such as hydrogen (H2), reach crystalline silicon (FIG. 4A), the following reactions (1) and (2) can occur to form a W layer on Si.

[0064] 2WF6(g)+3Si(s)→2W(s)+3SiF4(g) (1)

[0065] WF6(g)+3H2(g)→W(s)+6HF(g) (2)

[0066] Reaction (1) may occur first, followed by reaction (2). Alternatively, reactions (1) and (2) may occur substantially simultaneously with each other. Reaction (1) causes WF6(g) to react with silicon to form tungsten and SiF4 as gas-phase by-products. As the tungsten layer forms, one or more atomic layers of silicon are consumed in a downward direction from the surface of the silicon. As reaction (1) proceeds, the thickness of the silicon decreases and the thickness of the tungsten layer increases. The rate of reaction (1) may slow down as the tungsten layer forms a diffusion barrier between the silicon and WF6, until the diffusion layer prevents further reaction between the silicon and WF6. The tungsten layer may grow until the layer thickness reaches a self-limiting thickness, which in some embodiments may be about 10 nm (or 100 Å).

[0067] In some embodiments, reaction (1) may be reactive enough to consume too much crystalline silicon. As a result, the tungsten metal layer growth may result in the formation of defects such as "wormholes" as shown in FIG. 4B. Wormhole defects may form from locally non-uniform erosion of silicon. Wormhole defects may result in the formation of needle-like tungsten that permeate through the crystalline silicon, which may result in short circuits in the device. Wormhole defects may cause non-uniform layer thickness of tungsten in the feature, which may increase the variation in contact resistance in the device.

[0068] As reaction (1) slows over time, reaction (2) may become dominant and eventually replace reaction (1). In reaction (2), WF6(g) is reduced by a reducing agent, e.g., H2, to form a tungsten metal layer. Hydrogen fluoride (HF) may be a gas-phase by-product. The tungsten metal formed from reaction (2) may be selectively formed on the tungsten metal layer already formed by reaction (1). That is, tungsten forms on the underlying tungsten without forming on the dielectric sidewalls. Furthermore, the tungsten metal layer from reaction (2) is substantially free of defect formation, such as wormholes, that may be observed in reaction (1). In some embodiments, the thickness of the tungsten layer and remaining silicon after reactions (1) and (2) may be less than the thickness of the silicon thickness prior to the reactions.

[0069] Although the reactions of Si with WF6 and H2 with WF6 are described above for purposes of illustrating competing reaction considerations, the above discussion also applies to other metal halide precursors and reducing agents.

[0070] FIG. 5 shows a schematic example of metal layer formation according to various embodiments. FIG. 5 shows that metal halide precursors and reducing agents, such as WF6 and H2, can be provided in a deposition chamber to form a tungsten layer on the bottom silicon in a substrate using an ALD or CVD process. A tungsten layer 504 can be selectively formed on the upper surface of the crystalline silicon 502 without forming on the dielectric sidewall 506. During tungsten layer formation, the substrate can be exposed to WF6 and H2 flowing in parallel continuously. Alternatively, WF6 can be pulsed and H2 flows continuously. Alternatively, WF6 and H2 are pulsed consecutively without overlap. Flow sequences for precursors, reducing agents, and carrier gases according to various embodiments are described in more detail in FIG. 8A-FIG. 8D.

[0071] Although WF6 is shown as an example of a metal halide precursor for tungsten layer deposition, other metal halide precursors, such as WCl6 or WCl5, can be pulsed with hydrogen (H2). To form molybdenum, MoF6, MoCl6, or MoCl5 can be used as precursors. In some embodiments, hydrogen (H2), silane (SiH4), or a mixture thereof can be used as a reducing agent.

[0072] In some embodiments, the gas flow rates of the metal halide precursor, e.g., WF6, WCl6, or WCl5, and the reducing agent, e.g., H2 or SiH4, during the tungsten layer formation can be controlled. In some embodiments, the flow rate of the reducing agent is at least 10 times higher than the flow rate of the metal halide precursor. For example, the gas flow rate of H2 can be controlled to be at least 10 times higher than the gas flow rate of WF6 to achieve a high H2 flow condition. In some embodiments, the gas flow rate of H2 to WF6 can be set to be 10:1 to 10,000:1.

[0073] This high H2 flow condition may also be applied to forming a molybdenum layer. The gas flow rate of H2 may be at least 10 times higher than the gas flow rate of the molybdenum halide precursor, e.g., MoF6, MoCl6, or MoCl5. In some embodiments, the gas flow rate of H2 to MoF6 may be set to be 10:1 to 10,000:1.

[0074] At this high H2 flow condition, the rates of reactions (1) and (2) can be controlled such that reaction (1) only persists for a limited time before reaction (2) becomes dominant. In situations where reaction (1) is rapidly outcompeted, the formation of wormholes or other defects can be minimized or significantly suppressed. Reaction (2) forms a tungsten layer on the tungsten formed by the preceding reaction (1) without forming wormholes or other defects. In some embodiments, at high H2 flow conditions, the resulting tungsten layer can contain a substantially reduced number of wormholes or other defects, which is beneficial in reducing short circuits and / or resistance variations, thereby improving device lifetime and reliability.

[0075] 6A and 6B show a schematic example of forming a tungsten metal layer on a bottom Si by combining two successive steps providing different sets of reactants according to various embodiments. In the first step shown in FIG. 6A, the substrate is exposed to WF6 and SiH4. In some embodiments, WF6 and SiH4 can be delivered in pulsed or continuous co-flows. Alternatively, WF6 and SiH4 can be pulsed continuously. A tungsten layer 604 can be selectively formed on the upper surface of the crystalline silicon 602 without forming tungsten on the dielectric sidewall 606. The flow rate of SiH4 to WF6 in the first gas mixture can be controlled to be at least 10:1. In some embodiments, the flow rate of SiH4 to WF6 can be set within the range of 10:1 to 10,000:1.

[0076] In some embodiments, introducing SiH4 as a reducing agent at high flow rates may be advantageous in that the bottom crystalline silicon consumption in SiH4 reduction may not be as reactive as the silicon consumption in reaction (1) where only H2 is used as the reducing agent. Thus, wormhole or other defect formation may be suppressed or prevented compared to reaction (1), and a tungsten layer may still be formed on the crystalline silicon.

[0077] In some embodiments, two or more reducing agents may be pulsed in the first step. For example, a mixture of SiH4 and H2 with a predetermined flow ratio may be used instead of SiH4. Adding H2 to SiH4 may modify the reactivity of WF6 with silicon. The flow rate of (SiH4+H2) to WF6 may be controlled to be at least 10:1. In some embodiments, the flow rate of (SiH4+H2) to WF6 may be set within the range of 10:1 to 10,000:1.

[0078] After the first step is completed, the first gas mixture may be purged to remove any gaseous reactants, such as WF6 and SiH4 (or SiH4+H2), remaining in the deposition chamber. Then, in a second step shown in FIG. 6B, WF6 and H2 may be introduced to further form a tungsten layer on the tungsten layer previously formed in the first step. The flow rate of H2 to WF6 in the second step may be controlled to be at least 10:1. In some embodiments, the flow rate of H2 to WF6 may be set within the range of 10:1 to 10,000:1. Although FIGS. 6A and 6B describe steps for forming a tungsten layer with minimized or suppressed wormhole or other defect formation, molybdenum may also be formed according to the embodiment shown in FIGS. 6A and 6B. For example, MoF6, SiH4, and H2 may be pulsed to form a molybdenum layer on crystalline silicon.

[0079] 7A and 7B show schematic examples of forming a tungsten layer on bottom Si by combining two successive steps providing different sets of reactants, according to various embodiments. In some embodiments, in the first step shown in FIG. 7A, a substrate including features on which tungsten will be formed is exposed to a first set of reactants including WF6 and H2. WF6 and H2 can be pulsed or flowed in parallel continuously. Alternatively, WF6 and H2 can be pulsed continuously. A tungsten layer 704 can be selectively formed on the upper surface of crystalline silicon 702 without forming tungsten on the dielectric sidewalls 706. In some embodiments, the flow rate of H2 to WF6 can be controlled to be at least 10:1. In some embodiments, the flow rate of H2 to WF6 can be between 10:1 and 10,000:1.

[0080] In this high flow H2 condition, the formation of wormholes or other defects may be substantially suppressed or prevented. After the first step is completed, the remaining WF6 and H2 in the gas phase may be purged to remove unwanted reactions in the deposition chamber. Then, in the second step shown in FIG. 7B, a second set of reactants may be introduced into the deposition chamber. The second set of reactants may be different from the first set of reactants. For example, the second set of reactants may include tungsten pentachloride (WCl5) and H2. Chloride precursors such as WCl5 may be advantageous over fluoride precursors such as WF6 in that the incorporation of fluorine (F) ions into tungsten increases its resistivity. As with the flow rates for the first set of reactants, the flow rates of H2 to WCl5 may be controlled to be at least 10:1. In some embodiments, the flow rates of H2 to WCl5 may be set within the range of 10:1 to 10,000:1. In some embodiments, tungsten hexachloride (WCl6) may be used in place of tungsten pentachloride (WCl5) in the second step while maintaining the flow rate of H2 to WCl6. The use of tungsten chloride precursors such as tungsten pentachloride (WCl5) or tungsten hexachloride (WCl6) under high flow H2 conditions may also be advantageous in suppressing the formation of wormholes or other defects.

[0081] In some embodiments, WCl5 (or another WCl x Reactants WCl5 and H2 can be pulsed or continuously flowed in parallel to form a tungsten layer on a substrate without the use of WF6 or other gas reactants. From the beginning of the deposition process, forming a tungsten layer from only WCl5 and H2 can be advantageous to prevent the formation of defects such as wormholes.

[0082] It should be noted that according to the embodiment shown in Figures 7A and 7B, a molybdenum layer can be formed. For example, MoF6 and H2 can be flowed in parallel, either continuously or continuously, into the deposition chamber. After an optional purge, MoCl5 (or MoCl6) and H2 can be pulsed to form molybdenum on the molybdenum formed by the reaction between MoF6 and H2.

[0083] According to various embodiments, after a metal layer, such as tungsten or molybdenum, is formed on the crystalline silicon, the metal layer is annealed to convert the metal layer to a metal silicide layer. The annealing can be a rapid thermal anneal between about 500-800° C. In some embodiments, the annealing can be performed in-situ in a deposition chamber previously used for metal layer formation without breaking vacuum. A chamber pressure of 1-100 Torr can be used. For in-situ annealing in a deposition chamber with multiple pedestals, a substrate on which a metal layer is to be formed can be placed in one pedestal for metal layer formation. After the metal is formed, the substrate with the metal layer can be transferred to another pedestal in the same deposition chamber without breaking vacuum. Alternatively, the substrate with the metal layer can be removed from the deposition chamber for subsequent annealing in a different annealing chamber. Compared to removing the substrate from the deposition chamber, in-situ annealing can be beneficial in preventing the formation of an undesired oxide layer on the metal layer prior to annealing.

[0084] FIG. 8A shows an example of a timing sequence for pulsed CVD to deposit metals, according to various embodiments. In the example of FIG. 8A, H2 is flowed continuously. H2 can be flowed alone, but in some embodiments, a carrier gas, such as nitrogen (N2), argon (Ar), helium (He), or other inert gas, can flow in parallel with H2. In some embodiments, H2, or a mixture of H2 and a carrier gas, flows in parallel continuously. To form tungsten, WF6 is pulsed into a deposition chamber housing a substrate on which tungsten will be deposited. WF6 is pulsed with an interval between pulses. The interval is labeled "purge" because the continuous flow of H2 (or H2 / Ar) has the effect of purging WF6 out of the chamber. In some embodiments, the pressure during pulsed CVD can be less than 20 Torr, for example, 10 Torr, or less than 10 Torr. The temperature during the pulsed CVD process is the same as during the pyrolysis of the precursors and can be between 250°C and 350°C.

[0085] FIG. 8B shows an example of a timing sequence for parallel flow CVD to deposit metals, according to various embodiments. The substrate temperature during the parallel flow CVD process can be 250° C. to 350° C. For tungsten formation, the WF6 precursor and H2 are pulsed, so that the WF6 precursor and H2 flow continuously in parallel into the deposition chamber where the substrate on which the tungsten is to be formed is located. The parallel flow can be completed after a period of time when a tungsten layer with a predetermined thickness is formed. H2 can flow alone, but in some embodiments, argon (Ar) or other inert gas can flow in parallel with H2. In some embodiments, the flow rate of H2 to WF6 is controlled to at least 10:1. In some embodiments, the flow rate of H2 to WF6 can be 10:1 to 10,000:1. The tungsten thickness can be monitored in situ. Alternatively, a separate measurement can be performed to determine the tungsten thickness.

[0086] FIG. 8C shows another example of a time sequence for parallel flow CVD to deposit metals, according to various embodiments. In some embodiments, a gas mixture including WF6 and H2 can be pulsed with an interval between pulses, followed by pulsing a carrier gas for intermediate tungsten deposition to purge WF6 and H2 in the gas phase. In some embodiments, WF6 and H2 can form a gas mixture with a predetermined flow ratio. The flow rate of H2 to WF6 in the gas mixture during parallel flow CVD can be controlled to at least 10:1. In some embodiments, the flow rate of H2 to WF6 can be 10:1 to 10,000:1.

[0087] When the gas mixture (e.g., WF6 and H2) is pulsed to expose the substrate to WF6 and H2, WF6 may react with silicon to form tungsten and SiF4 in the gas phase. WF6 may then react with H2 to form tungsten on the tungsten formed from the reaction between WF6 and Si and form HF in the gas phase. At the end of the gas mixture pulsing, the co-flow of WF6 and H2 is stopped and tungsten is no longer formed. The deposition chamber may contain unreacted H2 and / or WF6. An inert gas such as argon (Ar) may be pulsed for a predetermined time to purge the remaining gas from the deposition chamber to prevent unwanted gas reactions that may follow. After the inert gas purge, the gas mixture including WF6 and H2 is pulsed again to expose the substrate to WF6 and H2, thereby forming additional tungsten and HF in the gas phase. In some embodiments, the reaction between WF6 and silicon may not be completed in the first pulse of WF6 / H2. Instead, the reaction may continue in the subsequent pulse(s).

[0088] The sequence of WF6 / H2 pulses and carrier gas pulses can be repeated until a tungsten layer with a predetermined thickness is formed. The tungsten layer thickness can be monitored in situ during tungsten layer formation. Alternatively, a separate measurement can be performed to determine the tungsten thickness. The substrate temperature during parallel flow CVD can be 250°C to 350°C.

[0089] FIG. 8D shows an example of a time sequence for ALD to deposit metal according to various embodiments. The ALD process is a surface-mediated deposition technique in which a dose of reactants (e.g., precursors and reducing agents) and a carrier purge are introduced sequentially into the deposition chamber. FIG. 8D shows a timing sequence for tungsten deposition, in which a WF6 precursor and a reducing agent (e.g., H2) can be pulsed alternately into the deposition chamber. In FIG. 8D, H2 is pulsed first to expose the substrate to H2 in the deposition chamber. Then, the carrier gas is pulsed to remove H2 from the chamber that is not at or near the surface of the substrate. During the carrier gas pulsing, the deposition chamber can be under a pressure of about 1 Torr. After the purge is completed, the WF6 precursor is pulsed to expose the substrate to the WF6 precursor on which the tungsten metal will be formed. WF6 can react with silicon to form tungsten on the surface of the silicon. SiF4 can be released in the gas phase. In some embodiments, WF6 may chemically react with H2 at or near the substrate to form tungsten on the tungsten already formed from the reaction between WF6 and H2 and form HF in the gas phase. After WF6 pulsing is completed, the carrier gas is pulsed again to purge the deposition chamber to remove WF6 and H2 in the gas phase. In some embodiments, the flow rate of H2 to WF6 may be controlled to at least 10:1. In some embodiments, the flow rate of H2 to WF6 may be between 10:1 and 10,000:1.

[0090] Instead of pulsing H2 first, in some embodiments, WF6 is pulsed first to expose the substrate to WF6, which causes a reaction between WF6 and silicon, and tungsten is first formed on the surface of the silicon. Then, a carrier gas may be pulsed to remove WF6 that is not at or near the silicon. After the carrier gas pulsing, H2 is pulsed to expose the substrate to H2. In some embodiments, WF6 may continue to react with Si in the presence of H2 to form tungsten and SiF4 in the gas phase. In some embodiments, WF6 may react with H2 to form tungsten on the tungsten formed by the reaction between WF6 and Si, and form HF in the gas phase. After the H2 pulsing step, a carrier gas pulsing follows to remove the gas phase that is not at or near the surface of the Si. In some embodiments, the flow rate of H2 to WF6 may be controlled to at least 10:1. In some embodiments, the flow rate of H2 to WF6 may be 10:1 to 10,000:1.

[0091] It should be noted that the y-axes in the exemplary timing sequences in Figures 8A-8D do not necessarily have the same scale, but rather the timing sequences are given to illustrate the relative pulse and purge durations. It should also be noted that the purge:dose durations in the exemplary timing sequences in Figures 8A, 8C, and 8D do not necessarily reflect actual durations, but rather the purge:dose durations illustrate the timing sequences between the metal halide precursor, the reducing agent, and the carrier gas.

[0092] It is also noted that the exemplary timing sequences in Figures 8A-8D may be used in forming a molybdenum (Mo) layer. For example, a Mo metal layer may be formed by a pulsed CVD process according to Figure 8A by using MoF6 precursor and H2. In another example, a Mo metal layer may be formed by a parallel flow CVD process according to Figure 8B by sequentially pulsing MoF6 and H2. In another example, a Mo metal layer may be formed by a parallel flow CVD process according to Figure 8C by sequentially pulsing MoF6 and H2 and sequentially purging the carrier gas between the pulses for MoF6 / H2. In yet another example, a Mo metal layer may be formed by an ALD process according to Figure 8D by alternating and sequentially pulsing MoF6, H2, and a carrier gas.

[0093] According to various embodiments, one or more of the following advantages may be realized by the methods described herein: In some embodiments, a metal layer, such as a tungsten or molybdenum layer, is formed while significantly suppressing the formation of wormholes or other defects between the metal layer and the underlying crystalline silicon. Control of these defects is responsible for improving device reliability. In some embodiments, following metal layer formation, the substrate with the metal layer may be annealed in the same chamber without exposure to ambient atmosphere, thereby preventing contamination and oxidation of the metal layer. This in-situ annealing provides the added advantage of not requiring multiple process steps, including capping the metal deposition, annealing, stripping the capping metal, and pre-cleaning before barrier mill or capacitor bottom electrode deposition. This in-situ annealing also improves production yields and reduces manufacturing costs.

[0094] In some embodiments, the metal silicide layer may be formed in a quad-station module (QSM), ALTUS® W, or ALTUS® Halo, available from Lam Research Corp., Fremont, Calif., or any of a variety of other commercially available processing systems. These products may include a deposition chamber including multiple pedestals. In some embodiments, a deposition station may include four pedestals, where a first, second, and third pedestal may be used to selectively form a metal layer and a fourth pedestal may be used for a metal anneal to form a metal silicide. This product configuration may maximize the productivity of the process by reducing process integration steps and manufacturing costs.

[0095] FIG. 9 shows a schematic diagram of one embodiment of a process station 900 having a process chamber 902 for maintaining a low pressure environment. In some embodiments, multiple process stations may be included in a common low pressure process tool environment. For example, FIG. 10A shows one embodiment of a processing tool 1000. In some embodiments, one or more hardware parameters of the process station 900, including those described in detail below, may be programmatically adjusted by one or more computer controllers (e.g., controller 950). In some other embodiments, the process chamber may be a single station chamber.

[0096] In some embodiments, the process station 900 may include an ALD process station and is in fluid communication with a reactant delivery system 901a for delivering process gases to a distribution showerhead 906. The reactant delivery system 901a includes a mixing vessel 904 for mixing and / or conditioning process gases, such as a W precursor-containing gas, a Mo precursor-containing gas, a hydrogen-containing gas, an argon or other carrier gas, or other reactant-containing gas, for delivery to the showerhead 906. One or more mixing vessel inlet valves 920 may control the introduction of process gases to the mixing vessel 904. In various embodiments, deposition of a W or Mo layer is performed in the process station 900, and in some embodiments, other operations, such as in-situ cleaning, may be performed in the same or another station of a processing tool 1000 including multiple stations, as described further below with respect to FIG. 10A.

[0097] As an example, the embodiment of FIG. 9 includes a vaporization point 903 for vaporizing a liquid reactant to be delivered to the mixing vessel 904. In some embodiments, the vaporization point 903 can be a heated vaporizer. In some embodiments, the liquid precursor or liquid reactant can be vaporized in a liquid injector (not shown). For example, the liquid injector can inject a pulse of the liquid reactant into the carrier gas flow upstream of the mixing vessel 904. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed microdroplets that are then vaporized in a heated delivery tube. Smaller droplets vaporize faster than larger droplets, which can reduce the delay between liquid injection and complete vaporization. Faster vaporization can reduce the length of tubing downstream from the vaporization point 903. In one scenario, the liquid injector can be attached directly to the mixing vessel 904. In another scenario, the liquid injector may be attached directly to the showerhead 906.

[0098] In some embodiments, a liquid flow controller (LFC) upstream of the vaporization point 903 may be provided to control the mass flow rate of liquid for vaporization and delivery to the process chamber 902. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted to respond to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take a second or more to stabilize the liquid flow rate using feedback control. This may extend the time to dose the liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this may be implemented by disabling the detector tube and PID controller of the LFC.

[0099] The showerhead 906 distributes process gases to the substrate 912. In the embodiment shown in Figure 9, the substrate 912 is shown positioned below the showerhead 906 and resting on a pedestal 908. The showerhead 906 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 912.

[0100] In some embodiments, the pedestal 908 may be raised or lowered to expose the substrate 912 to a volume between the substrate 912 and the showerhead 906. In some embodiments, the pedestal 908 may be temperature controlled via a heater 910. The pedestal 908 may be set to any suitable temperature, such as between about 300° C. and about 500° C., during operation to perform various disclosed embodiments. It will be appreciated that in some embodiments, the pedestal height may be programmatically adjusted by a suitable controller 950. At the end of a process phase, the pedestal 908 may be lowered during another substrate transfer phase to allow removal of the substrate 912 from the pedestal 908.

[0101] In some embodiments, the position of the showerhead 906 may be adjusted relative to the pedestal 908 to vary the volume between the substrate 912 and the showerhead 906. Additionally, it will be appreciated that the vertical position of the pedestal 908 and / or the showerhead 906 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 908 may include a rotation axis for rotating the orientation of the substrate 912. It will be appreciated that in some embodiments, one or more of these exemplary adjustments may be implemented programmatically by one or more suitable controllers (e.g., computer controller 950). The controller 950 may include any of the features described below with respect to the controller 950 of FIG. 9.

[0102] In some embodiments, instructions for the controller 950 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be arranged in sequence such that all instructions for a process phase are executed simultaneously with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a first recipe phase may include instructions for setting flow rates of an inert and / or reactant gas (e.g., W or Mo precursor, H2, or SiH4, etc.), instructions for setting a flow rate of a carrier gas (such as argon), and a time delay instruction for the first recipe phase. A second subsequent recipe phase may include instructions for adjusting or stopping flow rates of an inert and / or reactant gas, instructions for adjusting a flow rate of a carrier gas or purge gas, and a time delay instruction for the second recipe phase. A third recipe phase may include instructions for adjusting the flow rate of a second reactant gas, such as H2, instructions for adjusting the flow rate of a carrier or purge gas, and a time delay instruction for the third recipe phase. A fourth subsequent recipe phase may include instructions for adjusting or stopping the flow rate of an inert gas and / or a reactant gas, instructions for adjusting the flow rate of a carrier or purge gas, and a time delay instruction for the fourth recipe phase. It will be appreciated that these recipe phases may be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0103] Additionally, in some embodiments, pressure control for the process station 900 may be provided by a butterfly valve 918. As shown in the embodiment of Figure 9, the butterfly valve 918 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 900 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 900.

[0104] 10A and 10B show an example of a processing system. FIG. 10A shows an example of a processing tool including multiple stations. The processing tool 1000 includes a transfer module 1003. The transfer module 1003 provides a clean vacuum environment to minimize the risk of contamination of substrates being processed as they are moved between various modules. A chamber 1009 (e.g., a multi-station chamber) capable of performing the in-situ cleaning and / or ALD processes described above is mounted on the transfer module 1003.

[0105] The chamber 1009 may include multiple stations 1011, 1013, 1015, and 1017 that may perform operations in succession according to the disclosed embodiment. For example, the chamber 1009 may be configured such that the stations 1011 and 1013 perform in-situ cleaning of the substrate using diluted hydrogen fluoride and subsequent deposition of a metal layer. For example, a tungsten layer may be formed using a WF6 precursor and H2. As such, the stations 1011 and 1013 may be configured for parallel processing of substrates, each station performing cleaning and deposition processes in succession. The stations 1015 and 1017 may be configured to receive a substrate with a metal layer formed in the stations 1011 and 1013, respectively, to perform annealing to convert the metal layer into a metal silicide layer without contaminating the substrate to the ambient atmosphere. In another example, chamber 1009 can be configured such that station 1011 performs in-situ cleaning, stations 1013 and 1015 perform metal layer deposition, and station 1017 performs metal layer annealing. In another example, chamber 1009 can be configured such that stations 1011, 1013, and 1015 perform parallel processing of substrates, with each station performing multiple processes in succession, including in-situ cleaning and metal deposition. After metal layer deposition in stations 1011, 1013, and 1015, station 1017 can receive substrates from stations 1013, 1015, and 1017 for annealing.

[0106] Two or more, e.g., 2-6 stations with appropriately distributed operations may be included in a multi-station chamber. For example, a two-station chamber may be configured to perform substrate cleaning in a first station followed by metal layer deposition in a second station. The stations may include a heated pedestal or substrate support, one or more gas inlets or showerheads or distribution plates.

[0107] Also, a module 1007 may be mounted on the transfer module 1003. In some embodiments, the pre-cleaning described above may be performed in module 1007, after which the substrate is transferred under vacuum to another module (not shown) similar to module 1007 or to chamber 1009 for ALD.

[0108] The processing tool 1000 also includes one or more wafer source modules 1001 where wafers are stored before and after processing. An atmospheric robot (not shown) in an atmospheric transfer chamber 1019 may initially transfer the wafer from the source module 1001 to a load lock 1021. A wafer transfer device (typically a robot arm unit) in a transfer module 1003 moves the wafer from the load lock 1021 to and between modules mounted on the transfer module 1003.

[0109] FIG. 10B is an embodiment of the processing tool 1000 described in 10A. The processing tool 1000 in FIG. 10B has a wafer source module 1001, a transfer module 1003, an atmospheric transfer chamber 1019, and a load lock 1021, as described above with reference to FIG. 10A. The system in FIG. 10B has three single station modules 1057A-1057C. The processing tool 1000 may be configured to perform operations sequentially according to some embodiments herein. For example, the station modules may be configured such that the single station module 1057A performs a cleaning operation, the single station module 1057B performs a metal formation, e.g., using a metal halide precursor, and the single station module 1057C performs an in situ annealing. The station modules may include a heated pedestal or substrate support, one or more gas inlets or showerheads or distribution plates, as described above with reference to FIG. 9.

[0110] In various embodiments, a controller 1029 (e.g., a system controller) is employed to control process conditions during deposition. The controller 1029 will generally include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0111] The controller 1029 may control all activity of the apparatus. The controller 1029 executes system control software that includes sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored in memory devices associated with the controller 1029 may be employed in some embodiments.

[0112] Generally, there is a user interface associated with the controller 1029. The user interface may include a display screen, a graphical software representation of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0113] The system control logic may be configured in any suitable manner. In general, the logic may be designed or configured in hardware and / or software. The instructions for controlling the drive circuits may be hard-coded or provided as software. The instructions may be provided by "programming." Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices that have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general-purpose processor. The system control software may be coded in any suitable computer-readable programming language.

[0114] The computer program code for controlling the Mo precursor pulse, hydrogen pulse, and argon flow, as well as other processes in the process sequence, can be written in any conventional computer readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. Compiled object code or script is executed by the processor to perform the tasks identified in the program. As also shown, the program code can be hard coded.

[0115] The controller parameters relate to process conditions, such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and may be entered using a user interface.

[0116] Signals for monitoring the process may be provided by analog and / or digital input connections of the controller 1029. Signals for controlling the process are output on analog and digital output connections of the deposition device.

[0117] The system software can be designed or configured in many ways. For example, various chamber component subroutines or control objects can be written to control the operation of chamber components necessary to perform a deposition process according to disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0118] In some implementations, the controller 1029 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.) for processing. These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller," which may control various components or sub-portions of one or more systems. The controller 1029 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transport in and out of tools and other transport tools and / or load locks connected to or interfaced with a particular system, depending on the processing requirements and / or type of system.

[0119] In general, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. Integrated circuits may include firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or chips in the form of one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0120] The controller 1029 may, in some implementations, be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller 1029 may be in the "cloud" or in all or part of a fab host computer system that may enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, and examine trends or performance metrics from multiple fabrication operations in order to change parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. The parameters may be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and working toward a common purpose, such as the process and control described herein. One example of a distributed controller for such purposes would be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (such as at the platform level or as part of a remote computer) combined to control the process on the chamber.

[0121] Without being limited thereto, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a chamfer edge etch chamber or module, a PVD chamber or module, a CVD chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0122] As described above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transfers carrying containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0123] The controller 1029 may include a variety of programs. A substrate positioning program may include program code for controlling chamber components used to load the substrate onto the pedestal or chuck and to control the spacing between the substrate and other parts of the chamber, such as the gas inlets and / or targets. A process gas control program may include code for controlling gas composition, flow rates, pulse times, and optionally flowing gases into the chamber prior to deposition to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber, for example, by adjusting a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to the wafer chuck.

[0124] Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain desired process conditions.

[0125] The above describes the implementation of the disclosed embodiments in a single or multi-chamber semiconductor processing tool. The apparatus and processes described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools / processes will be used or performed together in a common fabrication facility. Lithographic patterning of a film generally involves some or all of the following steps: (1) application of photoresist to a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist, thereby patterning the resist, using a tool such as a wet bench; (5) transferring the resist pattern to the underlying film or workpiece by using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF resist stripper or a microwave plasma resist stripper, with each step being enabled using several possible tools.

Claims

1. 1. A method comprising: providing a feature having a feature bottom and a feature sidewall, the feature bottom having a crystalline silicon surface and the feature sidewall having an oxide or nitride surface; exposing the feature to a metal halide precursor flow having a metal halide precursor and a reducing agent flow having a reducing agent, thereby selectively forming a metal layer on the crystalline silicon surface, the metal halide precursor flow and the reducing agent flow having a flow ratio of at least 10:1; annealing the metal layer to form a metal silicide layer; A method comprising:

2. 2. The method of claim 1 , cleaning the feature bottom and the feature sidewalls prior to exposing the feature to the metal halide precursor flow. The method further comprising:

3. 2. The method of claim 1, wherein the metal halide precursor comprises a metal chloride or a metal fluoride.

4. 4. The method of claim 3, wherein the metal halide precursor comprises tungsten hexafluoride, tungsten pentachloride, molybdenum hexafluoride, or molybdenum pentachloride.

5. The method of claim 1 , wherein the metal layer comprises tungsten or molybdenum.

6. 10. The method of claim 1, wherein the reducing agent comprises hydrogen, silane, or a combination thereof.

7. 2. The method of claim 1, wherein the ratio is in the range of about 10:1 to about 10,000:

1.

8. The method of claim 1 , wherein the metal layer has a thickness in the range of about 2 to 20 nm.

9. 2. The method of claim 1, wherein the crystalline silicon of the crystalline silicon surface is a doped or undoped monocrystalline silicon crystal or a doped or undoped polycrystalline silicon.

10. 10. The method of claim 1, wherein the annealing of the metal layer is performed at between about 500-800 degrees Celsius.

11. 10. The method of claim 1, wherein the annealing of the metal layer is performed under a pressure in the range of 1 to 100 Torr.

12. 10. The method of claim 1, wherein the metal halide precursor flow and the reducing agent flow are alternated to form the metal layer by atomic layer deposition.

13. 10. The method of claim 1, wherein the metal halide precursor flow and the reducing agent flow are flowed in parallel to form the metal layer by chemical vapor deposition.

14. 10. The method of claim 1, wherein the metal halide precursor flow is pulsed and the reducing agent flow is continuous to form the metal layer by pulsed chemical vapor deposition.

15. 2. The method of claim 1, wherein the metal silicide layer forms an ohmic connection with the crystalline silicon surface.

16. 2. The method of claim 1, wherein the metal silicide layer comprises tungsten silicide or molybdenum silicide.

17. 1. A method comprising: providing a feature having a feature bottom and a feature sidewall, the feature bottom having a crystalline silicon surface and the feature sidewall having an oxide or nitride surface; exposing the feature to a first metal halide precursor flow comprising a first metal halide precursor and a first reducing agent flow comprising a first reducing agent, thereby selectively forming a first metal layer on the crystalline silicon surface, wherein the first metal halide precursor flow and the first reducing agent flow have a flow ratio of at least 10:1; providing a second metal halide precursor flow having a second metal halide precursor and a second reducing agent flow having a second reducing agent to the first metal layer to form a second metal layer, the second metal halide precursor flow and the second reducing agent flow having a flow ratio of at least 10:1; annealing the second metal layer to form a metal silicide layer; A method comprising:

18. 18. The method of claim 17, wherein the first metal halide precursor and the second metal halide precursor are each selected from tungsten hexafluoride, tungsten pentachloride, molybdenum hexafluoride, and molybdenum pentachloride.

19. 20. The method of claim 17, wherein the first reducing agent and the second reducing agent are each selected from hydrogen, silane, or a combination thereof.

20. 20. The method of claim 17, wherein the metal silicide layer comprises tungsten silicide or molybdenum silicide.

21. 20. The method of claim 17, wherein the first and second metal halide precursors and the first and second reducing agents are provided by chemical vapor deposition or atomic layer deposition.

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