Methods for increasing etch rate and improving feature critical dimensions and mask selectivity

Abstract

A method for generating a voltage pulse includes generating a first non-sinusoidal continuous wave voltage (NSCWV) waveform for a first duration of a clock cycle. The first NSCWV signal includes a first base voltage and a first frequency. The method further includes performing a first transition to change from the first NSCWV signal to a second NSCWV signal. The second NSCWV signal is generated for a second duration of the clock cycle. The second NSCWV signal includes a second base voltage and a second frequency. The method further includes performing a second transition to change from the second NSCWV signal back to the first NSCWV signal. The first transition and the second transition are repeated over the clock cycle.

Description

[Technical field]

[0001] Claiming priority This application is a continuation of, and claims the benefit of priority to, U.S. patent application Ser. No. 63 / 363,558, entitled "METHOD TO ENHANCE ETCH RATE AND IMPROVE CRITICAL DIMENSION OF FEATURES AND MASK SELECTIVITY," filed April 25, 2022, which is incorporated by reference in its entirety. [Background technology]

[0002] Etching and deposition processes are essential elements of modern semiconductor processing. Although various plasma processing techniques are available, inductively coupled plasma offers advantageous features such as a method to control ion energy and ion angular spread. Controlling ion energy and ion angular spread can provide many advantages for inductively coupled plasma based etching and deposition processes. Ion behavior can be controlled by modifying parameters that affect bulk plasma properties and by modifying electrical parameters on the electrostatic chuck (such as bias voltage). Of these two control knobs, methods to modify electrical parameters on the electrostatic chuck are constantly being developed to solve various problems in semiconductor device fabrication. Summary of the Invention

[0003] The materials described herein are illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements shown in the figures are not necessarily drawn to scale. For example, dimensions of some elements may be exaggerated relative to other elements for clarity. Also, for clarity of illustration, various physical features may be represented in their simplified "ideal" forms and geometries, but it will nevertheless be understood that actual implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be depicted while ignoring finite roughness, rounded corners, and imperfect angular intersections that are characteristic of structures formed by nanofabrication techniques. Additionally, where considered appropriate, reference labels are repeated among the figures to indicate corresponding or similar elements. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a schematic diagram of an apparatus including an electrostatic chuck coupled to a non-sinusoidal continuous wave voltage source in accordance with at least one embodiment of the present disclosure.

[0005] [Diagram 2] FIG. 2 is a diagram illustrating the relationship between temperature, electric field, and angular spread of ions in the sheath region of a plasma in accordance with at least one embodiment of the present disclosure.

[0006] [Diagram 3] FIG. 3 illustrates a plot of a voltage generated by a non-sine continuous wave voltage (NSCWV) source, in accordance with at least one embodiment of the present disclosure, where the voltage level varies between a first level and a second level.

[0007] [Figure 4]FIG. 4 illustrates a plot of a first portion of the voltage generated by the non-sine continuous wave voltage source of FIG. 3 in accordance with at least one embodiment of the present disclosure.

[0008] [Diagram 5] FIG. 5 illustrates a plot of a second portion of the voltage generated by the non-sine continuous wave voltage source of FIG. 3 in accordance with at least one embodiment of the present disclosure.

[0009] [Figure 6] FIG. 6 illustrates a plot of a portion of the applied voltage generated by the non-sinusoidal continuous wave voltage source of FIG. 3 superimposed with a plot of the induced voltage resulting on the surface of a substrate in accordance with at least one embodiment of the present disclosure.

[0010] [Figure 7] FIG. 7 is a flow diagram of a method for increasing ion energy and reducing mask erosion at a patterned substrate mounted in an inductively coupled plasma processing tool in accordance with at least one embodiment of the present disclosure.

[0011] [Figure 8A] FIG. 8A is a cross-sectional view of a mask formed over a substrate in accordance with at least one embodiment of the present disclosure.

[0012] [Figure 8B] FIG. 8B is a cross-sectional view of a trench profile of a high aspect ratio trench formed in a substrate in accordance with at least one embodiment of the present disclosure.

[0013] [Figure 9A] FIG. 9A illustrates plots of ion energy distribution functions within a plasma sheath resulting from a single voltage level and a dual voltage level discharge generated by a non-sinusoidal continuous wave voltage source in accordance with at least one embodiment of the present disclosure. [Figure 9B]FIG. 9B illustrates plots of ion energy distribution functions within a plasma sheath resulting from a single voltage level and a dual voltage level discharge generated by a non-sinusoidal continuous wave voltage source in accordance with at least one embodiment of the present disclosure. [Figure 9C] FIG. 9C illustrates plots of ion energy distribution functions within a plasma sheath resulting from a single voltage level and a dual voltage level discharge generated by a non-sinusoidal continuous wave voltage source in accordance with at least one embodiment of the present disclosure. [Figure 9D] FIG. 9D illustrates plots of ion energy distribution functions within a plasma sheath resulting from a single voltage level and a dual voltage level discharge generated by a non-sinusoidal continuous wave voltage source in accordance with at least one embodiment of the present disclosure.

[0014] [Figure 10A] FIG. 10A is a cross-sectional view of a simulation of a trench formed in a silicon substrate corresponding to different voltage bias conditions on an electrostatic chuck in accordance with at least one embodiment of the present disclosure. [Figure 10B] FIG. 10B is a cross-sectional view of a simulation of a trench formed in a silicon substrate corresponding to different voltage bias conditions on an electrostatic chuck in accordance with at least one embodiment of the present disclosure. [Figure 10C] FIG. 10C is a cross-sectional view of a simulation of a trench formed in a silicon substrate corresponding to different voltage bias conditions on an electrostatic chuck in accordance with at least one embodiment of the present disclosure. [Figure 10D] FIG. 10D illustrates a cross-sectional view of a simulation of a trench formed in a silicon substrate corresponding to different voltage bias conditions on an electrostatic chuck in accordance with at least one embodiment of the present disclosure.

[0015] [Figure 11A] FIG. 11A is a cross-sectional view of simulated mask profiles corresponding to different voltage bias conditions on an electrostatic chuck after a trench etching process in accordance with at least one embodiment of the present disclosure. [Figure 11B] FIG. 11B is a cross-sectional view of simulated mask profiles corresponding to different voltage bias conditions on an electrostatic chuck after a trench etching process in accordance with at least one embodiment of the present disclosure. [Figure 11C] FIG. 11C is a cross-sectional view of simulated mask profiles corresponding to different voltage bias conditions on an electrostatic chuck after a trench etching process in accordance with at least one embodiment of the present disclosure. [Figure 11D] FIG. 11D is a cross-sectional view of simulated mask profiles corresponding to different voltage bias conditions on an electrostatic chuck after a trench etching process in accordance with at least one embodiment of the present disclosure.

[0016] [Figure 12] FIG. 12 illustrates a processor system with a machine-readable storage medium having instructions that, when executed, cause a processor to control ion energy spread in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A method for enhancing etch rates and improving feature critical dimensions and mask selectivity in an inductively coupled plasma is described. Numerous specific details, such as structural schemes, are described herein to provide a thorough understanding of at least one embodiment. It will be apparent to one of ordinary skill in the art that at least one embodiment can be practiced without these specific details. In other instances, well-known features, such as radio frequency sources, are not described in particular detail so as not to unnecessarily obscure at least one embodiment. Furthermore, it should be understood that at least one embodiment depicted in the figures is an illustrative representation and is not necessarily drawn to scale.

[0018] In some cases, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring at least one embodiment. Throughout this specification, reference to "one embodiment" or "one embodiment" or "several embodiments" or "at least one embodiment" means that a particular feature, structure, function, or characteristic described in connection with one embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in one embodiment" or "at least one embodiment" or "several embodiments" appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, functions, or characteristics can be combined in any suitable manner in at least one embodiment. For example, a first embodiment may be combined with a second embodiment, unless particular features, structures, functions, or characteristics associated with the first and second embodiments are mutually exclusive.

[0019] Here, "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. These terms are not intended as synonyms for each other. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other elements between them) physical, electrical, or magnetic contact with each other and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0020] Here, "on," "under," "between," and "on" as used herein refer to the relative location of one component or material with respect to other components or materials for which such physical relationship is noteworthy. Unless these terms are modified with "direct" or "directly," one or more intervening components or materials may be present. A similar distinction is made with respect to component assemblies. As used throughout this specification and claims, a list of items linked by "at least one of" or "one or more of" can mean any combination of the listed terms.

[0021] As used herein, "adjacent" may generally refer to the location of an object that is next to (e.g., immediately adjacent or nearby with one or more objects between) or in close proximity to (e.g., abutting) another object.

[0022] Unless otherwise specified by the explicit context in which they are used, the terms "substantially equal," "about equal," and "approximately equal" may mean that there is only an incidental variation between the two items so described. In at least one embodiment, such variation is typically no more than + / - 10% of the reference value.

[0023] Plasma etching is essential in modern semiconductor device manufacturing. Here, "plasma etching" may generally refer to a process of removing material from a surface by charged particles and / or reactive species generated by a plasma. In at least one embodiment, plasma can be utilized to etch masked materials as well as unmasked structures during the fabrication of semiconductor devices. In at least one embodiment, etching the masked material includes forming a photoresist mask over the material and using the pattern in the mask to etch and selectively mask the underlying material. In at least one embodiment, etching the unmasked structure includes selectively removing some or all of the material formed in a pocket relative to the surrounding material or forming a spacer on the sidewall of a gate electrode in a transistor.

[0024] There are various types of tools that generate and sustain plasma, referred to as plasma etch process tools. Here, "plasma etch process tools" may generally refer to devices that utilize plasma to generate ions and reactive species to etch materials. Here, "plasma" may generally refer to a collection of ionized gases that are electrically neutral. In at least one embodiment, plasma etch process tools may generate plasma by transformer action, electron cyclotron resonance, or capacitive methods. In at least one embodiment, a wafer containing the material to be etched is transferred to an electrostatic chuck that is housed in a plasma processing chamber or plasma chamber under vacuum conditions. Here, "wafer" may generally refer to a substrate that is either conductive or insulating, and includes one or more materials that are dielectric, insulating, metallic, or semiconductive. Here, "electrostatic chuck" may generally refer to a support structure that utilizes an electrostatic clamp between the wafer and the top surface of the chuck.

[0025] In at least one embodiment, the gas mixture is flowed into the chamber and the plasma is turned on by one of the methods described above. In at least one embodiment, the plasma is formed in the vicinity of the wafer resting on the electrostatic chuck. In at least one embodiment, the high energy electrons generated after impacting the plasma generate reactive radical species and ions by dissociation of the gas mixture (known as the source gas). In at least one embodiment, the plasma used for processing is weakly ionized, with the density of ions and electrons being a fraction of the neutral atoms in the plasma. In at least one embodiment, the plasma is quasi-neutral, with the density of electrons being roughly equal to the density of ions. In at least one embodiment, of the ions and electrons generated in the plasma, the electrons are more mobile and escape from the edge of the plasma to the chamber walls and wafer surface. The loss of electrons at the plasma edge leads to the formation of a plasma sheath at the edge. Here, "plasma sheath or sheath" may generally refer to a region of net positive charge density at the edge of the plasma.

[0026] In at least one embodiment, the plasma may have three regions: a bulk region where the potential may be positive but small, e.g., less than 50V, and a pre-sheath region between the bulk and sheath regions. In at least one embodiment, the plasma potential at the pre-sheath / sheath boundary is close to zero and drops to negative values ​​near the wall or wafer surface. In at least one embodiment, the sheath region acts as a potential crest for electrons and a trough for ions. In at least one embodiment, ions enter the sheath at the sheath / pre-sheath boundary with a velocity defined by the ion temperature in the bulk plasma. In at least one embodiment, ions accelerate toward the wafer surface, which is at a lower potential relative to the sheath / pre-sheath boundary.

[0027] In at least one embodiment, ions bombarding the wafer surface are utilized in processing plasma to etch feature profiles in semiconductor, dielectric, and conductive materials that may be deposited on the wafer surface. In at least one embodiment, understanding and controlling ion energy at the wafer surface is advantageous to enable fine control of processes utilized for various etching features to fabricate semiconductor devices. In at least one embodiment, a relatively thin sheath (e.g., less than 10 mm) and low pressure discharge (e.g., less than 0.1 Pa) can provide a collision-free sheath that can be used to reduce ion angular spread at the wafer surface. In at least one embodiment, a collision-free sheath is one in which the sheath thickness is substantially less than the ion mean free path in the sheath. Here, "ion angular spread" may generally refer to the spread of angles that ions with a given energy have at the wafer surface. In at least one embodiment, ions passing through the plasma sheath on their way to the wafer surface may have a small, but non-zero, ion energy distribution. Here, "ion energy distribution" may generally refer to the distribution of ions that reach the wafer surface after leaving the plasma.

[0028] The ion energy distribution can be caused by oscillations of the plasma and by oscillations of the sheath potential and can be affected by the oscillation frequency. In at least one embodiment, the ion energy distribution can be adjusted by superimposing an externally driven, time-varying voltage on the electrostatic chuck.

[0029] In at least one embodiment, inductively coupled plasmas can provide an advantage over plasmas generated by other methods in that ion energy at the wafer surface can be controlled independently from ion temperature in the plasma. Here, "inductively coupled plasma" may generally refer to a plasma that is generated and maintained by transformer action outside the chamber. In at least one embodiment, the plasma potential and ion temperature are directly controlled by power delivered through transformer action. In at least one embodiment, the ion temperature can be controlled by transformer coupling that induces an electric field in the etch chamber. Here, "etch chamber" may generally refer to a chamber in which a plasma is generated and in which a wafer is plasma etched. In at least one embodiment, the induced electric field helps to ignite and maintain the plasma and control global parameters such as electron and ion temperature, density, etc. Plasma etching and deposition systems include electrostatic chucks. Here, "electrostatic chuck" may generally refer to a support structure in an etch chamber on which a wafer or substrate for processing rests. In at least one embodiment, the wafer contacts the plasma sheath at the edge of the plasma boundary during processing. In at least one embodiment, the ions exit the sheath with an ion energy spread and an ion angular spread, which in at least one embodiment is controlled by the bulk plasma potential, but can also be controlled by biasing the electrostatic chuck.

[0030] In at least one embodiment, the electrostatic chuck includes a conductive electrode and an insulator layer on the conductive electrode, where the substrate typically resides. In at least one embodiment, the electrostatic chuck is typically voltage biased by a radio frequency (RF) voltage waveform to induce an RF voltage on the wafer. In at least one embodiment, the RF voltage induced on the wafer overcomes the capacitive effect of the insulator. In at least one embodiment, the RF voltage waveform is adjusted to overcome the steady rise in potential at the wafer due to the steady ion flux. In at least one embodiment, the sheath voltage may also be changed by RF biasing the electrostatic chuck. In at least one embodiment, the low pressure discharge sheath typical of an inductively coupled plasma may be considered to be generally collision-free and relatively narrow (e.g., on the order of a few millimeters). When the bias voltage approaches kV levels, for example, in a dielectric chamber, the sheath may become collisional. In at least one embodiment, the plasma potential in the bulk may also be considered to have a low level of voltage fluctuation.

[0031] In at least one embodiment, the ion energy, or more precisely the ion energy distribution at the wafer, depends on (a) the time-varying flux of ions entering the sheath, and (b) the time-varying sheath voltage. If (b) is more dominant, the voltage oscillations in the sheath may be primarily due to the frequency of the RF voltage waveform biasing the electrostatic chuck. In at least one embodiment, the response of the ions to the RF voltage waveform affects the etching characteristics on the wafer surface. In at least one embodiment, in addition to the voltage amplitude, the oscillation frequency is also useful to affect the etching characteristics. In at least one embodiment, the voltage magnitude and oscillation frequency can shape the ion energy distribution at the wafer surface as well as the ion angular spread. The former can control the etch rate, while the latter can affect the shape of the different features being etched. In at least one embodiment, the ions traverse the sheath for a finite period of time. In at least one embodiment, this is determined by the initial ion velocity, which is determined by the ion temperature and the thickness of the sheath when the ions enter the sheath. In at least one embodiment, the thickness of the sheath also varies with the oscillating voltage amplitude and oscillation frequency. In at least one embodiment, the ion energy distribution is highly dependent on the time scale over which the voltage amplitude is changed.

[0032] In at least one embodiment, programming the voltage amplitude in the sheath region to vary in time can advantageously provide a path to reduce the angular spread of ions exiting the plasma. In at least one embodiment, the reduction in angular spread can positively impact etching parameters such as the anisotropy of the etch or the degree of vertical etching versus lateral etching. In at least one embodiment, the reduction in ion angular spread can be useful for anisotropically etching high aspect ratio features during semiconductor device fabrication. Aspect ratio is defined as the ratio of depth:width of a feature. In at least one embodiment, high aspect ratio features (such as aspect ratios greater than 20:1) include trenches. In at least one embodiment, the trenches can have widths in the range of 10 nm to 20 nm and depths of at least 200 nm. In at least one embodiment, obtaining substantially vertical sidewalls in the trenches can advantageously provide a structure for fabricating capacitors with improved electrical characteristics or for fabricating source and drain isolation regions in transistors.

[0033] In at least one embodiment, the ion angular spread at the wafer surface is proportional to the square root of the ion temperature in the bulk plasma and the sheath voltage V s In at least one embodiment, one approach to reducing the ion angle spread may be to increase the bias power on the electrostatic chuck. Increasing the bias voltage reduces V s and reduces ion angular spread. In at least one embodiment, a pulsed DC-like voltage waveform can be used to reduce ion energy distribution and improve etch characteristics such as uniformity and anisotropy. In at least one embodiment, the pulsed DC-like voltage signal is a non-sine continuous wave voltage (NSCWV) signal. Here, "non-sine continuous wave voltage" may generally refer to continuous electrical pulses characterized by a shape that is periodic but non-monotonic increasing or decreasing in amplitude.

[0034] In at least one embodiment, the NSCWV signal has a frequency range, for example, 100 kHz to 400 kHz. In at least one embodiment, the low frequency signal (e.g., less than 400 KHz) ensures that it is not blocked by the capacitance of the insulator layer present between the wafer and the electrostatic chuck electrode (e.g., electrostatic chuck). In at least one embodiment, the magnitude of the NSCWV signal can also be adjusted to provide an effective voltage that overcomes the increase in ion current on the wafer during operation. In at least one embodiment, the NSCWV signal differs from a typical RF waveform. In at least one embodiment, the RF waveform has a defined oscillating frequency and an oscillating peak amplitude. In at least one embodiment, the NSCWV signal can include multiple voltage ramps, as described below.

[0035] Reducing the ion energy spread without reducing the absolute voltage level in the NCSWV waveform may not be beneficial. The mask utilized to pattern the trench may be eroded by the continuous bombardment of the wafer surface by ions, even with a distribution of ion energies. Simply reducing the absolute voltage level may slow the etch rate, but this may also reduce the anisotropy of the etch, e.g., it may become more isotropic.

[0036] In at least one embodiment, the NCSWV waveform is superimposed with a high frequency RF bias to provide a combined voltage pulse to the electrostatic chuck. In at least one embodiment, the high frequency RF bias has a frequency, for example, greater than 1 MHz. In at least one embodiment, above 1 MHz, ions passing through the sheath may experience many cycles of voltage oscillations as the ions respond to the time-averaged sheath voltage. In at least one embodiment, the time-averaged sheath voltage has a magnitude that depends on the magnitude of the applied voltage bias. In at least one embodiment, the time-averaged sheath voltage corresponding to the high frequency RF bias may not have the same effect as the NCSWV waveform. In at least one embodiment, the ion energy distribution in the high frequency RF bias modulated sheath may have a larger ion energy distribution. However, the ions in the NCSW sheath may have a very narrow energy spread. In at least one embodiment, the application of the NCSWV waveform alone may be advantageously utilized for etching.

[0037] In at least one embodiment, the NSCWV signal can be used to enhance the ion distribution and therefore control the anisotropy of the etch. However, to also reduce damage to the mask, according to at least one embodiment, a dual voltage pulse sequence can be implemented. In at least one embodiment, the dual voltage pulse sequence includes changing the voltage level between two voltage levels. In at least one embodiment, a higher voltage level can be used to reduce the ion energy distribution, increase the anisotropy, and preserve the etch rate. In at least one embodiment, a lower voltage can be used to give the mask a relaxation time by reducing continuous high energy ion bombardment. In at least one embodiment, the higher voltage level can be part of a first voltage envelope that lasts for a first finite duration. In at least one embodiment, the higher voltage level can be measured relative to a first reference voltage.

[0038] In at least one embodiment, a higher voltage level within the first voltage envelope is achieved during the first portion of the first pulse train. In at least one embodiment, additional features of the first pulse train include a second portion including a gradually ramping voltage phase and a third portion at a first reference voltage. In at least one embodiment, the first and second portions of the first pulse train can have a duty cycle greater than the third portion. In at least one embodiment, the first portion of the first pulse train is designed to reduce ion angular spread. In at least one embodiment, the ramping voltage phase can be designed to counteract the increase in ion current at the wafer substrate. Here, "duty cycle" may generally refer to the ratio of time the NSCWV signal is at a first defined voltage level compared to the time the NSCWV signal is at a second defined voltage level. In at least one embodiment, the first voltage may be finite, both positive or negative, and the second voltage may be finite, either positive, negative, or zero.

[0039] In at least one embodiment, the lower voltage level may be a portion of a second voltage envelope that lasts for a second finite duration. In at least one embodiment, the lower voltage level may be measured relative to a second reference voltage. In at least one embodiment, within the second voltage envelope, the lower voltage level may be achieved during a first portion of the second pulse train. In at least one embodiment, additional features of the second pulse train include a second portion that includes a gradually ramping voltage phase and a third portion that is at the second reference voltage. In at least one embodiment, the first and second portions of the second pulse train may have a greater duty cycle than the third portion. In at least one embodiment, the first portion of the second pulse train may be designed to reduce ion bombardment to provide some respite to the mask. In at least one embodiment, the ramped voltage phase may be designed to counteract the increase in ion current at the wafer substrate.

[0040] In at least one embodiment, the dual voltage pulse sequence can have a duty cycle that prioritizes the first voltage envelope over the second voltage envelope. In at least one embodiment, the first and second reference levels can be the same level or different levels. In at least one embodiment, the difference between the higher voltage level and the first reference voltage can be greater than the difference between the lower voltage level and the second reference voltage.

[0041] Although the NCSWV waveform has been described with respect to implementation in an inductively coupled plasma, in accordance with at least one embodiment, it may also be generally implemented in other plasma processing tools.

[0042] 1 illustrates a schematic diagram of a plasma processing tool 100 according to at least one embodiment. In at least one embodiment, the plasma processing tool 100 is an example of an inductively coupled etch tool that includes an electrostatic chuck 102 in a process chamber 104 and an RF generator 106 coupled to a coil above the process chamber 104. In at least one embodiment, the plasma processing tool 100 may further include a non-sine continuous wave voltage (NSCWV) generator 108 coupled in series with the electrostatic chuck 102.

[0043] In at least one embodiment, the electrostatic chuck 102 includes an electrode plate 102A coupled to an NSCWV generator 108 and an insulator 102B on the electrode plate 102A. In at least one embodiment, the insulator 102B is made of alumina (Al 2 O 3 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and dielectric materials including alloys and ceramics such as sapphire.

[0044] In at least one embodiment, the NSCWV generator 108 can be configured to generate a pulsed voltage waveform 110 at the electrostatic chuck 102. In at least one embodiment, the NSCWV generator 108 can generate a peak voltage of up to 100 kV. In at least one embodiment, the NSCWV generator 108 can be configured to generate a voltage in a range of 2 kV to 10 kV. In at least one embodiment, the NSCWV generator 108 can generate voltage pulses in a range of 50 kHz to 500 kHz.

[0045] In at least one embodiment, during operation, a plasma 112 may be generated in the process chamber 104. In at least one embodiment, ions are emitted from a plasma sheath, which is an outermost portion of the plasma 112 that may be near the insulator 102B. In at least one embodiment, the plasma sheath may be a non-neutral region formed at the plasma boundary to balance electron and ion losses to maintain quasi-neutrality. In at least one embodiment, the ions impact a substrate 114 mounted on the electrostatic chuck 102 to perform various etching (e.g., chemical, mechanical, etc.) of one or materials in the substrate 114.

[0046] In at least one embodiment, the characteristics (e.g., velocity and angular distribution) of the ions in the sheath region of the plasma 112 may depend on (a) the plasma potential, and (b) the potential at the surface of the substrate 114, which may be controlled by the voltage applied to the electrostatic chuck 102. In at least one embodiment, the velocity of the ions may be directly affected by both (a) and (b), since an increase in both (a) and (b) increases the electric field that drives the ions toward the electrostatic chuck 102. In at least one embodiment, the electric field in the bulk portion of the plasma may be substantially small (e.g., 10 V / cm or less), while the electric field in the sheath region (e.g., adjacent to the substrate 114) may be between 1 KV / cm.

[0047] In at least one embodiment, the plasma sheath oscillates in response to the pulsed voltage waveform 110, which may be applied to the electrostatic chuck by the NSCWV generator 108. In at least one embodiment, application of the pulsed voltage waveform 110 changes the width (and potential) of the sheath. In at least one embodiment, the change in the sheath width or sheath-pre-sheath boundary relative to the substrate 114 may be defined by a rapid oscillation of the sheath width at this boundary in response to the frequency of the pulsed voltage waveform 110. In at least one embodiment, ions are significantly less mobile than electrons, so they respond slowly and over a time averaged over the frequency of the pulsed voltage waveform 110. In at least one embodiment, the slow response may result in a spread in ion energy or may result in an ion energy distribution. In at least one embodiment, the oscillations in the sheath may be due to oscillations resulting from an induced electric field driving the plasma oscillations in the bulk plasma as well as oscillations resulting from the pulsed voltage waveform 110 applied to the electrostatic chuck 102. In at least one embodiment, the pulsed voltage waveform 110 plays a substantially dominant role in terms of the effects of voltage oscillations for the purposes of affecting ion distribution in an inductively coupled plasma system. In at least one embodiment, the morphology of the pulsed voltage waveform 110 and its effects on the etch features in the substrate 114 and the mask are described in detail below.

[0048] The relationship between the temperature of ions in plasma 112, the voltage applied to sheath 202A, and the angular spread, according to at least one embodiment, is shown in diagram 200 of Figure 2. In at least one embodiment, plasma 202 includes a sheath 202A and a pre-sheath 202B adjacent to sheath 202A. In at least one embodiment, a voltage V S The voltage on the ions at the boundary 203 between the sheath 202A and the pre-sheath 202B relative to V creates a net electric field E in the sheath 202A. In at least one embodiment, the voltage V Salso determines the thickness D of the sheath 202A. In at least one embodiment, the electric field E is a function of the power coupled to sustain the plasma 112 and raises the potential of the plasma to a level used to sustain the plasma. In at least one embodiment, the electric field E is directed to the electrostatic chuck 102. In at least one embodiment, T i The transverse component of the ion velocity due to T arises from the random motion of ions in the plasma. i Ion velocity due to V s The vector sum of the velocities due to gives sigma theta, the maximum ion angular spread.

[0049] In at least one embodiment, the relationship between the temperature of the ions, the voltage supplied to the ions in the sheath, and the angular spread of the ion velocity shown in FIG. 2 is expressed by Equation 1.1.

[0050] Sigma Theta = Tan -1 [square root(T i / eV s )], (1.1) where sigma-theta is the angular spread and T i is the temperature of the ion, and V S is the sheath voltage of the plasma sheath of the plasma 112 in the process chamber 104 (FIG. 1).

[0051] In at least one embodiment, the angular spread, theta, of ions accelerating towards the electrostatic chuck 102 is T i and V S In at least one embodiment, the voltage V S is set by the pulse voltage applied to the electrostatic chuck 102. In at least one embodiment, T i without increasing V S A method for increasing T is highly desirable for controlling ion energy and ion angular spread. In at least one embodiment, in an ICP, the transformer action of coupling RF power from the RF generator 106 (FIG. 1) determines the plasma potential and therefore Ti Determine.

[0052] 3 illustrates a schematic diagram of a pulsed voltage waveform 300 generated by the NSCWV generator 108 (FIG. 1) according to at least one embodiment. In at least one embodiment, generating the pulsed voltage waveform 300 includes a first duration T 1 The NSCWV signal 302 includes generating an NSCWV signal 302 over a first base voltage V 1 and frequency f 1 In at least one embodiment, as shown, T 1 contains three pulses, but the number of pulses can be arbitrary.

[0053] In at least one embodiment, generating the pulsed voltage waveform 300 further includes performing a transition that includes changing from generating the NSCWV signal 302 to generating the NSCWV signal 304. In at least one embodiment, the NSCWV signal 304 is a pulsed voltage waveform having a duration of a clock cycle T 2 In at least one embodiment, the NSCWV signal 304 is generated over a second base voltage V 2 and frequency f 2 As shown, T 2 contains three pulses, but the number of pulses can be arbitrary.

[0054] In at least one embodiment, generating the pulsed voltage waveform 300 further includes performing a second transition including transitioning from the NSCWV signal 304 back to the NSCWV signal 302. In at least one embodiment, the first transition and the second transition are repeated over a clock cycle, where a "clock cycle" may generally refer to the total period of time of the pulsed voltage waveform 300. In at least one embodiment, V 1 and V 2 By transitioning between , the pulsed voltage waveform 300 may be an example of a level-to-level voltage pulse.

[0055] In at least one embodiment, V 1 and the first reference voltage V R1 and V 2 and the second reference voltage V R2 In at least one embodiment, the difference between |V 1 -V R1 | and the difference |V 1 -V R2 In at least one embodiment, V R1 and V R2 In at least one embodiment, V R1 V R2 In at least one embodiment, a key feature of the pulse voltage waveform 300 is |V 1 -V R1 | is |V 1 -V R2 | is greater than.

[0056] In at least one embodiment, |V 1 -V R1 | and |V 1 -V R2 The difference between | translates directly into differences in ion energy distribution and subsequent etching of features in the substrate 114 (FIG. 1).

[0057] In at least one embodiment, the first duration T 1 and the second duration T 2 The inverse of the sum of defines the duty cycle of the pulsed voltage waveform 300. In at least one embodiment, the duty cycle of the NSCWV signal 302 is at least 50-75%. 2 is T 1 In at least one embodiment, T 2 is T 1In at least one embodiment, the duty cycle of the NSCWV signal 302 determines how long the plasma discharge is used to generate the high and low etch rate phases.

[0058] In at least one embodiment, the sum of the first duration and the second duration, i.e., T 1 +T 2 is the pulse frequency f p In at least one embodiment, f p In at least one embodiment, f p f 1 and f 2 It cannot be smaller than

[0059] 4 illustrates a plot 400 of an actual applied first NSCWV signal 302, according to at least one embodiment. In at least one embodiment, the NSCWV generator 108 described in connection with FIG. 1 may be utilized to generate the NSCWV signal 302. In at least one embodiment, and referring again to FIG. 4, applying or generating the NSCWV signal 302 may be performed over a first time interval T 3 The magnitude of the voltage level over the R1 to the first base voltage V 1 In at least one embodiment, the first operation includes increasing V R1 is the "zero level." In at least one embodiment, V R1 In at least one embodiment, the first time interval T 3 can be quasi-instantaneous.

[0060] In at least one embodiment, the magnitude of the voltage level is increased over a second time interval T 4 A first base voltage V 1 to the first peak voltage V 3 In at least one embodiment, a second operation is performed in which the voltage V3 The size of V 1 In at least one embodiment, V 3 The size of V 1 In at least one embodiment, the individual harmonics are integer multiples of the fundamental frequency, such as 400 kHz. In at least one embodiment, the NSCWV signal 302 includes up to the 10th harmonic (e.g., 4000 kHz). In at least one embodiment, the V 1 From V 3 The ramp down to contains low frequency oscillations between 400 kHz and 4000 kHz due to superposition between different harmonics.

[0061] In at least one embodiment, generating the NSCWV signal 302 includes a third time interval T 5 The voltage level is set to a first peak voltage V 3 to the reference voltage V R1 In at least one embodiment, the method further comprises performing a third operation comprising decreasing V 3 The size of V R In at least one embodiment, the magnitude of T 5 can be quasi-instantaneous.

[0062] In at least one embodiment, generating the NSCWV signal 302 includes a fourth time interval T 6 Over the entire range, the reference voltage V R1 The method further includes performing a fourth action including maintaining the voltage level at a positive voltage. In at least one embodiment, the voltage overshoots to a positive voltage.

[0063] In at least one embodiment, the first operation, the second operation, the third operation, and the fourth operation constitute a single cycle of the NSCWV signal 302 and have a first duration T 1 is repeated over

[0064] In at least one embodiment, the NSCWV signal 302 is 3, the second time interval T 4 , the third time interval T 5 , and a fourth time interval T 6 The frequency f is equal to 1 divided by the sum of 1 In at least one embodiment, the frequency f 1 In at least one embodiment, the second time interval T 4 and the fourth time interval T 6 In at least one embodiment, the ratio between the second time interval T 4 and the fourth time interval T 6 In at least one embodiment, the NSCWV signal 302 has a non-zero negative voltage portion (V R1 In at least one embodiment, the NSCWV signal 302 has a duty cycle of 75%. In at least one embodiment, the second time interval T 4 is the first time interval T 3 or a third time interval T 5 is at least 100 times larger than

[0065] 5 illustrates a plot 500 of an actual applied NSCWV signal 304, according to at least one embodiment. In at least one embodiment, the NSCWV generator 108 described in connection with FIG. 1 may be utilized to generate the NSCWV signal 304. Referring again to FIG. 5, in at least one embodiment, applying or generating the NSCWV signal 304 may be performed over a first time interval T 7 The magnitude of the voltage level across the R2 to the first base voltage V 2 In at least one embodiment, performing a fifth operation includes increasing V R2 is the "zero level." In at least one embodiment, V R2 can be a positive voltage level. R2 V R1(FIG. 4) may be the same as or different from the first time interval T 7 can be quasi-instantaneous.

[0066] In at least one embodiment, the magnitude of the voltage level is increased over a second time interval T 8 A first base voltage V 2 to the first peak voltage V 4 In at least one embodiment, a second operation is performed in which the voltage V 4 The magnitude of V 2 In at least one embodiment, V 4 The size of V 2 In at least one embodiment, the individual harmonics are integer multiples of the fundamental frequency, such as 400 kHz. In at least one embodiment, the NSCWV signal 304 includes up to the 10th harmonic (e.g., 4000 kHz). In at least one embodiment, the V 2 From V 4 The ramp down to contains low frequency oscillations between 400 kHz and 4000 kHz due to superposition between different harmonics.

[0067] In at least one embodiment, generating the NSCWV signal 304 includes a third time interval T 9 The voltage level is set to a first peak voltage V 4 to the second reference voltage V R2 In at least one embodiment, the method further comprises performing a third operation comprising decreasing V 4 The size of V R2 In at least one embodiment, the third time interval T 9 In at least one embodiment, the second time interval T 8 is the first time interval T 7 or a third time interval T 9 is at least 100 times larger than

[0068] In at least one embodiment, generating the NSCWV signal 304 includes a fourth time interval T 10 Over the entire range, the reference voltage V R2 The method further includes performing a fourth action including maintaining the voltage level at a positive voltage. In at least one embodiment, the voltage overshoots to a positive voltage.

[0069] In at least one embodiment, the first operation, the second operation, the third operation, and the fourth operation constitute a single cycle of the NSCWV signal 304 and have a first duration T 1 is repeated over

[0070] In at least one embodiment, the NSCWV signal 304 is 7 , the second time interval T 8 , the third time interval T 9 , and a fourth time interval T 10 The frequency f is equal to 1 divided by the sum of 1 In at least one embodiment, the frequency is less than 100 KHz. In at least one embodiment, the second time interval T 8 and the fourth time interval T 10 In at least one embodiment, the ratio between the second time interval T 8 and the fourth time interval T 10 In at least one embodiment, the NSCWV signal 304 has a non-zero negative voltage portion (V R2 In at least one embodiment, the NSCWV signal 304 has a duty cycle of 75%. In at least one embodiment, the second time interval T 8 is the first time interval T 7 or a third time interval T 9 In at least one embodiment, T 7 is T 3 (Figure 4) and T 9 is T 5 (Figure 4).

[0071] In at least one embodiment, the frequency f 2 is the frequency f 1 In at least one embodiment, depending on the embodiment, f 2 f 1 Even if it is larger than f 1 Even if it is equivalent to f 1 In at least one embodiment, T 8 is T 4 (Figure 4) may or may not be comparable to T 10 is T 6 (FIG. 4). In at least one embodiment, T 4 :T 8 The ratio of T may be at least 1:1. In at least one embodiment, 4 :T 8 The ratio is 3:1.

[0072] In at least one embodiment, the voltage peak V 2 and V 3 may or may not be equal. In at least one embodiment, V 3 V 4 In at least one embodiment, V 1 From V 3 1. The ramp to may correspond to a voltage gradient selected to compensate for the linear voltage increase across the blocking capacitor due to charge build-up from positive ions bombarding the electrostatic chuck 102 of FIG. 1. In at least one embodiment, the blocking capacitor is not shown in FIG. 1 but may be located between the NSCWV generator 108 and the electrostatic chuck 102. In at least one embodiment, the blocking capacitor may be an insulator 102B between the electrode plate 102A and the substrate 114.

[0073] 6 illustrates a plot 600 of an induced voltage waveform 602 on a surface of a substrate (such as substrate 114 of FIG. 3) according to at least one embodiment. In at least one embodiment, the induced voltage waveform 602 is a result of a superposition of the NSCWV signal 302 and a voltage induced by ions exiting the sheath 202A and impacting the surface of the substrate 114 (FIG. 2). ... 4 During this period, the induced voltage waveform 602 has a substantially constant average voltage and oscillations 604. In at least one embodiment, the oscillations 604 are from a 400 kHz to 4000 kHz signal generated by an NSCWV generator and result from the superposition between the different harmonics discussed above. In at least one embodiment, the NSCWV signal 302 generated by the NSCWV generator is superimposed for comparison. In at least one embodiment, the V 1 From V 3 The ramp to corresponds to a voltage gradient selected to compensate for the linear voltage increase due to charge build-up from positive ions bombarding the electrostatic chuck 102 (FIG. 1).

[0074] FIG. 7 illustrates a method 700 of modifying ion energy and ion angular spread directed at a surface of a substrate during an etching operation, according to at least one embodiment. In at least one embodiment, some or all of the operations of method 700 may be implemented or controlled by hardware, software, or a combination thereof. In at least one embodiment, method 700 begins with operation 710 by placing a substrate on an electrostatic chuck in a plasma chamber. In at least one embodiment, the electrostatic chuck is electrically coupled to an NSCWV generator. In at least one embodiment, method 700 continues with operation 720 by forming a plasma in the plasma chamber, the plasma generating a sheath having a first sheath voltage. In at least one embodiment, method 700 continues with operation 730 by modifying the first sheath voltage to a second sheath voltage by applying a first NSCWV signal to the electrostatic chuck. In at least one embodiment, the first NSCWV signal includes a first periodic function and generates a first voltage response on the wafer substrate. In at least one embodiment, the first voltage response causes a first change in the ion energy spread at the wafer due to a change from the first sheath voltage to the second sheath voltage. In at least one embodiment, as the sheath voltage increases from the first sheath voltage to the second sheath voltage, the ion energy increases. In at least one embodiment, the ion energy distribution decreases and a high etch rate plasma is generated.

[0075] In at least one embodiment, the method 700 ends at operation 740 by changing the second sheath voltage to a third sheath voltage by applying a second NSCWV signal to the electrostatic chuck. In at least one embodiment, the second non-sinusoidal voltage waveform includes a second periodic function and produces a second voltage response on the wafer substrate. In at least one embodiment, the second voltage response produces a second change in the ion energy spread at the wafer due to the change from the second sheath voltage to the third sheath voltage. In at least one embodiment, as the sheath voltage decreases, the ion energy decreases. In at least one embodiment, the ion energy distribution decreases and a lower etch rate plasma is generated.

[0076] In at least one embodiment, and referring again to FIG. 4, a pulsed voltage waveform 300 is applied to the electrostatic chuck 102 (FIG. 1). In at least one embodiment, once a plasma is generated, a first sheath voltage is generated at the plasma boundary at the wafer surface. In at least one embodiment, a first non-sinusoidal voltage waveform, such as NSCWV signal 302, is applied to the electrostatic chuck. In at least one embodiment, this generates a voltage response on the wafer substrate that results in a first change in the spread of ion energy at the wafer. In at least one embodiment, a second sheath voltage is applied for a period T 3 +T 4 is averaged over

[0077] 5, in at least one embodiment, a pulsed voltage waveform 300 is applied to the electrostatic chuck 102 (FIG. 1). In at least one embodiment, the non-sinusoidal voltage waveform is changed from a first periodic function to a second periodic non-sinusoidal voltage waveform, such as the NSCWV signal 304. In at least one embodiment, a lower magnitude base voltage V in the NSCWV signal 304 is applied to the electrostatic chuck 102 (FIG. 1). 2 produces a voltage response on the wafer that results in a second change in the ion energy spread at the wafer. In at least one embodiment, V 1 (Fig. 4) compared to V 2A small magnitude of reduces the ion energy distribution and slows the etch rate, but does not stop the etching process. In at least one embodiment, the third sheath voltage is applied for a period T 7 +T 8 is averaged over

[0078] In at least one embodiment, a pulsed voltage waveform 300 as described in connection with FIG. 3 is applied to an electrostatic chuck to selectively etch high aspect ratio features relative to a mask formed on a wafer mounted on the electrostatic chuck.

[0079] FIG. 8A is a cross-sectional view of a patterned wafer 800 according to at least one embodiment. In at least one embodiment, the patterned wafer 800 includes a substrate 802 and a mask 804 formed on the substrate 802. In at least one embodiment, the substrate 802 may include a single layer or multiple layers. In at least one embodiment, the substrate 802 includes silicon, germanium, III-V, sapphire, or quartz. In at least one embodiment, the substrate 802 includes a dielectric formed on a silicon-containing material. In at least one embodiment, the mask 804 includes a photoresist material that has been patterned by a lithography process. In at least one embodiment, the mask 804 includes a dielectric material that has been previously patterned by a lithography process followed by an etching process. In at least one embodiment, the mask 804 includes a mask having a thickness T M1 In at least one embodiment, to maintain the integrity of the mask 804 during etching. In at least one embodiment, erosion, especially near the edge 805 of the mask, and the degree of isotropic erosion may cause flaring on the sidewalls of the mask 804. In at least one embodiment, depending on the erosion rate of the mask 804 compared to the targeted etch depth, the upper portion of the substrate 802 may be adversely eroded. In at least one embodiment, it is desirable to balance the control of ion energy, ion energy distribution, and directionality to pattern features with high fidelity.

[0080] 8B is a cross-sectional view of the structure of FIG. 8A after a plasma etch process to form a trench in the substrate 802, according to at least one embodiment. In at least one embodiment, a different waveform may be generated by the NSCWV generator while etching the substrate 802. In at least one embodiment, the waveform has the same or substantially the same characteristics as the NSCWV signals 302 and 304 in the pulsed voltage waveform 300 shown in FIG. 3 that is generated by the NSCWV generator 108 (FIG. 1) to etch the substrate 802.

[0081] In at least one embodiment, trench 806 has substantially vertical sidewalls 802A. In at least one embodiment, the substantially vertical sidewalls may enable fabrication of devices having substantially uniform electrical properties. In at least one embodiment, mask 804 is formed with a new thickness T M2 The erosion is essentially uniform up to T M2 is T M1 In at least one embodiment, a balance between a high energy etch and a low energy mask holding operation can be achieved to form trench 806.

[0082] 9A-9D show simulations of ion angular spread as well as ion energy distribution at a wafer surface during processing in an ICP plasma for different applied voltages on an electrostatic chuck according to at least one embodiment, where the vertical axis corresponds to the energy of the ions and the horizontal axis corresponds to the ion angular spread (theta) measured in degrees.

[0083] 9A shows a plot 900 of ion angular spread resulting from an applied voltage of 330 V generated by an RF generator. In at least one embodiment, the RF generator generates a sinusoidal voltage. In at least one embodiment, the sinusoidal voltage is V BIn at least one embodiment, the sinusoidal voltage may be shifted relative to a reference voltage. In at least one embodiment, the magnitude of the peak voltage for one voltage polarity is |V B |+|V shift | and the peak voltage for the opposite polarity is |V B |-|V shift In at least one embodiment, the ion angular spread E A1 is approximately 3.32 degrees for a peak ion energy of 550 eV. In at least one embodiment, the sinusoidal bias voltage V b produces a peak energy of 1.6 to 1.8 Vb eV.

[0084] 9B illustrates a plot 910 of the ion angular spread resulting from an applied voltage of 330V generated by a non-sine continuous wave voltage generator (such as the NCSWV generator 108 of FIG. 1) in accordance with at least one embodiment. In at least one embodiment, the ion angular spread E A2 is approximately 8.1 degrees for a peak applied voltage of 330 V. In at least one embodiment, the non-sinusoidal bias voltage V b-ns is approximately 1V b-ns In at least one embodiment, the peak ion energy is approximately 370 eV.

[0085] 9C illustrates a plot 920 of ion angular spread resulting from a low-to-high level pulsed voltage waveform generated by a non-sine continuous wave voltage generator (such as the NSCWV generator 108 of FIG. 1 ) in accordance with at least one embodiment. In at least one embodiment, the low level voltage is approximately 120V and the high level voltage is approximately 360V. In at least one embodiment, in the pulsed voltage waveform 300 shown in FIG. 3 , the low level voltage of 120V is approximately 360V. 2 (NSCWV signal 304), and the high level voltage of 360V is V 1(NSCWV signal 302). In at least one embodiment, the individual ion angular spread during the period of the NCSWV signal 304 is greater than the individual ion angular spread during the period of the NCSWV signal 302. In at least one embodiment, referring again to FIG. 9C, the average ion angular spread E for the high and low voltage levels A3 is approximately 7.10 degrees. In at least one embodiment, the ion angular spread is less than for the 330 V applied voltage shown in Figure 9B. In at least one embodiment, the peak energy increases and the average angular spread decreases, as expected.

[0086] 9D illustrates a plot 930 of ion angular spread resulting from a low-to-high level pulsed voltage waveform generated by a non-sine continuous wave voltage generator (such as non-sine continuous wave voltage generator 108 of FIG. 1) in accordance with at least one embodiment. In at least one embodiment, the low level voltage is approximately 210V and the high level voltage is approximately 630V. In at least one embodiment, in the pulsed voltage waveform 300 shown in FIG. 3, the low level voltage of 210V is approximately V 2 (NSCWV signal 304) and the high level voltage of 630V is V 1 (NSCWV signal 302). In at least one embodiment, the individual ion angular spread during the period of the NCSWV signal 304 is greater than the individual ion angular spread during the period of the NCSWV signal 302. In at least one embodiment, referring again to FIG. 9D, the average ion angular spread E for the high and low voltage levels A4 is approximately 6.6 degrees. In at least one embodiment, the ion angular spread is less than for the 330 V applied voltage shown in Figure 9B or for the level-to-level applied voltage of Figure 9C. In at least one embodiment, as expected, the average ion angular spread decreases as the peak energy increases.

[0087] In at least one embodiment, the etch profile, relative etch times, and maximum trench width W T10A-10D. In at least one embodiment, simulation results of an etched trench in a substrate are shown corresponding to different pulse voltage waveforms applied to the chuck electrode during etching of the trench. The trench shown in Figures 10A-10D is an embodiment of a trench 806 formed in a substrate 802 using the mask 804 shown in Figure 8B.

[0088] FIG. 10A is a cross-sectional view 1000 of an etch profile of a trench 1002 formed in a silicon substrate 1004 using a mask 804, according to at least one embodiment. In at least one embodiment, the plasma etch process utilized to form the trench 1002 corresponds to the voltage bias conditions on the chuck electrode described in connection with FIG. 9A. In at least one embodiment, the trench 1002 has an initial mask opening of 10 nm. In at least one embodiment, the trench 1002 has a maximum width of 18.3 nm resulting from a peak ion angular spread of 3.32 degrees and an average ion angular spread of 7.7 degrees. In at least one embodiment, the etch time utilized to etch a trench depth of approximately 200 nm is a time t 0 is normalized to

[0089] 10B is a cross-sectional view 1010 of an etch profile of a trench 1012 formed in a silicon substrate 1004 using a mask 804 with the ion angle spread described in connection with FIG. 9B according to at least one embodiment. In at least one embodiment, the trench 1012 has an initial mask opening of 10 nm. In at least one embodiment, the trench 1012 has a maximum width W of 18.8 nm resulting from a peak / average ion energy distribution of 8.1 degrees. T In at least one embodiment, a 1.05t 0 is approximately 5% longer than the etch time used to pattern trench 1002 (FIG. 10A).

[0090] 10C is a cross-sectional view 1020 of an etch profile of a trench 1022 formed in a silicon substrate 1004 using a mask 804 with the ion angle spread described in connection with FIG. 9C according to at least one embodiment. In at least one embodiment, the trench 1022 has an initial mask opening of 10 nm. In at least one embodiment, the trench 1022 has a maximum width of 16.9 nm resulting from a peak ion energy distribution of 7.3 degrees and an average ion angular spread of 7.1 degrees ... 0 is 5% longer than the etch time used to pattern trench 1002 (FIG. 10A).

[0091] In at least one embodiment, the maximum width W T In at least one embodiment, the etch rate is reduced compared to etching trench 1002 (FIG. 10A) and the etch time is increased due to the addition of low voltage level pulses. In at least one embodiment, despite the higher voltage levels, the etch rate is substantially the same as the etch rate for etching trench 1012 (FIG. 10B) due to the addition of additional low voltage level pulses.

[0092] 10D is a cross-sectional view 1030 of an etch profile of a trench 1032 formed in a silicon substrate 1004 using mask 804 with the ion angle spread described in connection with FIG. 9D , according to at least one embodiment. In at least one embodiment, trench 1032 has an initial mask opening of 10 nm. In at least one embodiment, trench 1042 has a maximum width W of 17 nm resulting from a peak ion angle spread of 6.02 degrees and an average ion angle spread of 6.6 degrees. T In at least one embodiment, the 0 is approximately 7% shorter than the etch time used to pattern trench 1002 (FIG. 10A). In at least one embodiment, 0.95t0 This etch time is approximately 11% shorter than the etch time used to pattern trenches 1012 and 1022 (FIGS. 10B and 10C, respectively).

[0093] In at least one embodiment, the etch rate is improved over that for etching trench 1022 (FIG. 10C) because a higher level voltage and an additional "higher" low voltage level pulse are added. T is maintained at approximately 17 nm.

[0094] In at least one embodiment, the etch profile and mask erosion are shown in Figures 10A-10D. In at least one embodiment, the different figures correspond to pulsed voltage waveforms applied to the chuck electrode while etching a trench feature into the substrate. The trench shown in Figures 10A-10D is an embodiment of a trench 806 formed in a substrate 802 using the mask 804 shown in Figure 8B.

[0095] 11A-11D are enlarged cross-sectional views of the masks of FIGS. 10A-10D, according to at least one embodiment. The trenches formed under the respective masks are not shown. Each figure corresponds to a respective pulsed voltage waveform applied to a chuck electrode during etching of a trench feature into a substrate, according to at least one embodiment.

[0096] Figure 11A is a cross-sectional view 1100 of the mask 804 after a process to etch and form the trench 1002 of Figure 10A, in accordance with at least one embodiment. In at least one embodiment, the plasma etch process utilized to form the trench 1002 corresponds to the voltage bias conditions on the chuck electrode described in connection with Figure 9A.

[0097] 11A, dashed line 1101 represents a reference line for the top of mask 804 prior to etching trench 1002. In at least one embodiment, mask 804 is eroded during etching of the trench. In at least one embodiment, mask 804 is eroded by an amount E 1 In at least one embodiment, as shown, E 1 is normalized to 100% erosion.

[0098] Figure 11B is a cross-sectional view 1110 of the mask 804 after a process to etch and form the trench 1012 of Figure 10B, in accordance with at least one embodiment. In at least one embodiment, the plasma etch process utilized to form the trench 1012 corresponds to the voltage bias conditions on the chuck electrode described in connection with Figure 9B.

[0099] 11A, dashed line 1101 represents a reference line for the top of mask 804 prior to etching trench 1012. In at least one embodiment, mask 804 is eroded during etching of the trench. In at least one embodiment, mask 804 is eroded by an amount E 2 As shown, E 2 is approximately 1.04E 1 In at least one embodiment, the greater mask erosion is the result of a narrower energy band, but a wider ion angle spread as compared to the ion angle spread due to the voltage bias condition on the chuck electrode described in connection with FIG.

[0100] Figure 11C is a cross-sectional view 1120 of the mask 804 after a process to etch and form the trench 1022 of Figure 10C, according to at least one embodiment. The plasma etch process utilized to form the trench 1022 corresponds to the voltage bias conditions on the chuck electrode described in connection with Figure 9C.

[0101] 11A, dashed line 1101 represents a reference line for the top of mask 804 prior to etching trench 1022. In at least one embodiment, mask 804 is etched with a quantity E 3 As shown, E 3 is approximately 0.88E 1 In at least one embodiment, the reduced erosion of the mask 804 is a result of the level-to-level pulse voltage waveform (such as the pulse voltage waveform 300 of FIG. 3). In at least one embodiment, the high energy etch is performed prevalently during the high voltage pulse phase. In at least one embodiment, the peak ion energy at the mask 804 is reduced by decreasing the voltage level from a high voltage level to a low voltage level. In at least one embodiment, the ions are slowed down sufficiently to reduce the ion bombardment rate. In at least one embodiment, the duration of the higher and lower ion energy bombardments depends on the duty cycle of the level-to-level pulse voltage waveform. In at least one embodiment, the duty cycle can determine how much respite the mask 804 is provided to the differential ion energy bombardment. In at least one embodiment, the retentiveness of the mask 804 can be increased by decreasing the voltage level from a high voltage level to a low voltage level.

[0102] In at least one embodiment, the peak voltage is approximately 360 V and the ratio between the high and low voltage levels is 3: 1. In at least one embodiment, the ion angle spread corresponding to the higher voltage level is less than 70 percent of the ion angle spread corresponding to the lower voltage level.

[0103] Figure 11D is a cross-sectional view 1130 of mask 804 after a process to etch and form trench 1032 of Figure 10D, in accordance with at least one embodiment. In at least one embodiment, the plasma etch process utilized to form trench 1032 corresponds to the voltage bias conditions on the chuck electrode described in connection with Figure 9D.

[0104] 11D, dashed line 1101 represents a reference line for the top of mask 804 prior to etching trench 1032. In at least one embodiment, mask 804 is etched with a quantity E 4 As shown, E 4 is approximately 0.87E 1 It is.

[0105] In at least one embodiment, the reduced erosion of mask 804 is a result of a level-to-level pulse voltage waveform, whereby mask 804 is provided with respite from ion bombardment during the low voltage phase. In at least one embodiment, the peak voltage may be approximately 630V. In at least one embodiment, this voltage level is higher than the peak voltage implemented in etching trench 1022 (FIG. 10A). In at least one embodiment, the ratio between the high and low voltage levels is maintained at 3:1. In at least one embodiment, the etch rate for forming trench 1032 is substantially different than the etch utilized to form trench 1022 (FIG. 10C). In at least one embodiment, the mask erosion rate is substantially lower than the mask erosion rate observed in FIG. 11C, e.g., E 4 ~E 3 is substantially similar to:

[0106] Referring again to FIG. 11D, in one embodiment, the ion angular spread corresponding to the higher voltage level is less than 70 percent of the ion angular spread corresponding to the lower voltage level.

[0107] In accordance with at least one embodiment, reduced mask erosion can be advantageous if the plasma etching utilized to form trench 1032 (FIG. 10D) is further extended to result in a trench 1032 having a depth greater than the depth of trench 1032.

[0108] 12 illustrates a processor system 1200 with a machine-readable storage medium having instructions that, when executed, cause a processor to improve ion energy and reduce ion energy distribution in an inductively coupled plasma, according to at least one embodiment. In at least one embodiment, the process may be stored in a machine-readable storage medium (e.g., 1203) as computer-executable instructions. In at least one embodiment, the processor system 1200 includes a memory 1201, a processor 1202, a machine-readable storage medium 1203 (also referred to as a tangible machine-readable medium), a communication interface 1204 (e.g., a wireless or wired interface), and a network bus 1205 coupled together as shown.

[0109] In at least one embodiment, the processor 1202 is a digital signal processor (DSP), an application specific integrated circuit (ASIC), a general purpose central processing unit (CPU), or low power logic that implements simple finite state machines for performing the various processes described herein.

[0110] In at least one embodiment, the various logic blocks of the processor system 1200 are coupled together via a network bus 1205. In at least one embodiment, any suitable protocol may be used to implement the network bus 1205. In at least one embodiment, the machine-readable storage medium 1203 includes instructions (also referred to as program software code / instructions) for improving ion energy and reducing ion angular spread in an inductively coupled plasma, as described above.

[0111] In at least one embodiment, the machine-readable storage medium 1203 is a machine-readable storage medium having instructions for improving ion energy and reducing ion angular spread in an inductively coupled plasma. In at least one embodiment, the machine-readable storage medium 1203 has machine-readable instructions that, when executed, cause the processor 1202 to perform the measuring and / or reporting methods described with reference to the various embodiments.

[0112] In at least one embodiment, the program software code / instructions associated with the various embodiments may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other instruction sequence or organization of instruction sequences, referred to as "program software code / instructions," "operating system program software code / instructions," "application program software code / instructions," or simply "software" or firmware embedded in a processor. In at least one embodiment, the program software code / instructions associated with the processes of the various embodiments are executed by processor system 1200.

[0113] In at least one embodiment, program software codes / instructions associated with various embodiments are stored in a computer executable machine readable storage medium 1203 and executed by the processor 1202. Here, the computer executable machine readable storage medium 1203 is a tangible machine readable medium that can be used to store program software codes / instructions and data that, when executed by a computing device, cause one or more processors (e.g., the processor 1202) to perform a process. In at least one embodiment, the process can include controlling a pulse voltage waveform. In at least one embodiment, the process can include controlling a pulse voltage waveform to generate low and high voltage pulses at a predetermined duty cycle. In at least one embodiment, the process can include adjusting the spread of ion energy in a sheath region of the plasma by the pulse voltage waveform. In at least one embodiment, the sheath region is adjacent to a substrate that is placed on an electrostatic chuck during processing. In at least one embodiment, the pulse voltage waveform is a combination of two pulse voltage signals, a first voltage pulse having a higher base voltage amplitude level and a second voltage pulse having a lower base amplitude voltage level. In at least one embodiment, the first voltage pulse comprises a first periodic voltage and the second voltage pulse comprises a second periodic voltage. In at least one embodiment, the first voltage pulse may be applied for a first duration that is longer than, equal to, or shorter than a second duration of the second voltage pulse. In at least one embodiment, the first voltage pulse is an example of a first NCSWV signal and the second voltage pulse is an example of a second NCSWV signal, consistent with NCSWV signals 302 and 304 described in connection with FIGS. 3-5.

[0114] Referring again to FIG. 12, in at least one embodiment, the tangible machine-readable storage medium 1203 may include storage of executable software program code / instructions and data in various tangible locations, including, for example, ROM, volatile RAM, non-volatile memory and / or cache and / or other tangible memory. In at least one embodiment, portions of this program software code / instructions and / or data may be stored in any one of these storage and memory devices. In at least one embodiment, the program software code / instructions may be obtained from other storage, such as, for example, via a centralized server or a peer-to-peer network including the Internet. In at least one embodiment, different portions of the software program code / instructions and data may be obtained at different times and in different communication sessions or in the same communication session.

[0115] In at least one embodiment, the software program code / instructions may be obtained in their entirety prior to executing the respective software program or application. In at least one embodiment, portions of the software program code / instructions and data may be obtained dynamically, e.g., just in time, when needed for execution. In at least one embodiment, some combination of these methods of obtaining the software program code / instructions and data may occur, e.g., for different applications, components, programs, objects, modules, routines, or other instruction sequences or organization of instruction sequences, as examples. In at least one embodiment, the data and instructions may not need to be present in their entirety on the tangible machine-readable medium at any particular time.

[0116] In at least one embodiment, the tangible machine-readable storage media 1203 includes, but is not limited to, recordable and non-recordable types of media, such as volatile and non-volatile memory devices, read-only memories (ROMs), random access memories (RAMs), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., compact disks read-only memories (CDs ROMS), digital versatile disks (DVDs), etc.), among others. In at least one embodiment, the software program code / instructions, while temporarily stored in a digital tangible communication link, can be embodied via electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc., over such tangible communication links.

[0117] Example 1: A method of generating a voltage pulse, the method including: generating a first non-sine continuous wave voltage (NSCWV) signal over a first duration of a clock cycle, the first NSCWV signal including a first base voltage and a first frequency; and performing a first transition, the first transition including changing from the first NSCWV signal to a second NSCWV signal generated over a second duration of the clock cycle, the second NSCWV signal including a second base voltage and a second frequency.

[0118] Example 2: The method of example 1, further comprising performing a second transition, the second transition comprising transitioning from the second NSCWV signal back to the first NSCWV signal.

[0119] Example 3: The method of example 2, further comprising repeating the first transition and the second transition over the clock cycle.

[0120] Example 4: The method of example 1, wherein the magnitude of the first base voltage is greater than the magnitude of the second base voltage.

[0121] Example 5: The method of example 1, wherein the reciprocal of the sum of the first duration and the second duration defines a duty cycle of the voltage pulse, and the duty cycle of the first NSCWV signal is between 50% and 75%.

[0122] Example 6: The method of example 1, wherein the sum of the first duration and the second duration defines a pulse frequency of the voltage pulse, and the pulse frequency is between 1 Hz and 100 kHz.

[0123] Example 7: The method of Example 1, wherein generating the first NSCWV signal further includes performing a first operation including increasing a first magnitude of a voltage level from a reference voltage to the first base voltage over a first time interval, performing a second operation including ramping the voltage level from the first base voltage to a first peak voltage over a second time interval, performing a third operation including decreasing the voltage level from the first peak voltage to the reference voltage over a third time interval, performing a fourth operation including maintaining the voltage level at the reference voltage for a fourth time interval, and repeating the first operation, the second operation, the third operation, and the fourth operation for the first duration.

[0124] Example 8: The method of example 7, wherein the first frequency is equal to one divided by a sum of the first time interval, the second time interval, the third time interval, and the fourth time interval.

[0125] Example 9: The method according to example 8, wherein the first frequency is between 2 Hz and 400 kHz.

[0126] Example 10: The method of example 7, wherein the second time interval is at least 100 times greater than the first time interval or the third time interval, and the fourth time interval is at least 100 times greater than the first time interval or the third time interval.

[0127] Example 11: The method of example 10, wherein a ratio between the second time interval and the fourth time interval is 2:1 or greater.

[0128] Example 12: The method of example 10, wherein the ratio between the second time interval and the fourth time interval is 3:1.

[0129] Example 13: the reference voltage is a first reference voltage and the voltage level is a first voltage level, and generating the second NSCWV signal further includes performing a fifth operation including increasing a second voltage level from a second reference voltage to the second base voltage over a fifth time interval, performing a sixth operation including ramping the second voltage level from the second base voltage to a second peak voltage over a sixth time interval, performing a seventh operation including decreasing the second voltage level from the second peak voltage to the second reference voltage over a seventh time interval, performing an eighth operation including maintaining the second voltage level at the second reference voltage for an eighth time interval, and repeating the fifth operation, the sixth operation, the seventh operation, and the eighth operation for the second duration.

[0130] Example 14: The method of example 13, wherein the second frequency is equal to one divided by the sum of the fifth time interval, the sixth time interval, the seventh time interval, and the eighth time interval.

[0131] Example 15: The method according to example 14, wherein the second frequency is between 2 Hz and 400 kHz.

[0132] Example 16: The method of example 13, wherein the sixth time interval is at least 100 times greater than the fifth time interval or the seventh time interval, and the eighth time interval is at least 100 times greater than the fifth time interval or the seventh time interval.

[0133] Example 17: The method of example 16, wherein the ratio between the sixth time interval and the eighth time interval is 2:1 or greater.

[0134] Example 18: The method of example 16, wherein the ratio between the sixth time interval and the eighth time interval is 3:1.

[0135] Example 19: The method of example 13, wherein a first magnitude of a first difference between the first base voltage and the first reference voltage is greater than a second magnitude of a second difference between the second base voltage and the second reference voltage.

[0136] Example 20: The method of example 13, wherein a third magnitude of the first peak voltage is greater than or less than a fourth magnitude of the second peak voltage.

[0137] Example 21: A method for operating a plasma chamber to increase ion energy and reduce ion angular spread at a surface of a substrate during an etching operation, comprising: placing the substrate on an electrostatic chuck in the plasma chamber, the electrostatic chuck being electrically coupled to a non-sine wave continuous voltage (NSCWV) generator; forming a plasma in the plasma chamber, the plasma generating a sheath that includes a sheath voltage; and modifying the sheath voltage by applying a voltage pulse to the electrostatic chuck using a continuous wave voltage source. and performing a first transition, the first transition comprising changing the first NSCWV signal to a second NSCWV signal generated for a second duration of the clock cycle, the second NSCWV signal comprising a second base voltage and a second frequency.

[0138] Example 22: The method of example 21, further comprising: performing a second transition, the second transition comprising switching the second NSCWV signal back to the first NSCWV signal.

[0139] Example 23: The method of Example 22, further comprising repeating the first transition and the second transition over the clock cycle, wherein applying the voltage pulse results in a change in the spread of ion energies on the surface of the substrate.

[0140] Example 24: The method of example 21, wherein the first NSCWV signal includes a first plurality of harmonics and applying the second NSCWV signal includes a second plurality of harmonics.

[0141] Example 25: The method of example 24, wherein the first plurality of harmonics and the second plurality of harmonics include a fundamental harmonic of 400 kHz and up to a 10th harmonic.

[0142] Example 26: The method of example 21, wherein the voltage pulse further comprises a positive period, a negative period, and a duty cycle from 0 to 100.

[0143] Example 27: The method of example 21, wherein applying the first NSCWV signal further includes a first negative voltage, and a ramp to a second negative voltage, the second negative voltage being 25-50% percent greater than the first negative voltage.

[0144] Example 28: A method for operating a plasma chamber and modifying ion energy and ion angular spread at a surface of a substrate during an etching operation, the method including: placing the substrate on an electrostatic chuck in the plasma chamber, the electrostatic chuck being electrically coupled to a non-sine voltage waveform generator; forming a plasma in the plasma chamber, the plasma generating a sheath having a first sheath voltage; varying the first sheath voltage to a second sheath voltage by applying a first non-sine voltage waveform having a first periodic function to the electrostatic chuck to generate a first voltage response on the electrostatic chuck thereby resulting in a first change in ion energy spread at the substrate; and varying the second sheath voltage to a third sheath voltage by applying a second non-sine voltage waveform having a second periodic function to the electrostatic chuck to generate a second voltage response on the electrostatic chuck thereby resulting in a second change in ion energy spread at the substrate.

[0145] Example 29: The method of example 28, wherein the first non-sinusoidal voltage waveform includes a first base voltage value, and the first non-sinusoidal voltage waveform generates a first ion angular spread at the substrate.

[0146] Example 30: The method of example 29, wherein the second non-sinusoidal voltage waveform includes a second base voltage value, and the second non-sinusoidal voltage waveform results in a second ion angular spread at the substrate.

[0147] Example 31: The method of example 30, wherein the first ion angular spread is less than 70 percent of the second ion angular spread.

[0148] Example 32: The method of example 28, wherein the first ion angular spread produces an etch rate that is twice as high as an etch rate produced by the second non-sinusoidal voltage waveform.

[0149] Example 33: A machine-readable storage medium having machine-executable instructions that, when executed, cause one or more machines to perform a method including controlling a pulse voltage waveform, controlling a periodic voltage, and controlling the spread of ion energy in a sheath region of a plasma by controlling the pulse voltage waveform to generate low voltage pulses and high voltage pulses having a predetermined duty cycle.

[0150] Example 34: The machine-readable storage medium of Example 33, wherein the pulsed voltage waveform has a duty cycle of at least 50% of the high voltage pulses.

[0151] Besides what is described herein, various modifications can be made to the at least one embodiment without departing from the scope thereof, and therefore, the description of the at least one embodiment herein should be construed as an example, and not as a limitation on the scope of the at least one embodiment.

Claims

1. 1. A method for generating a voltage pulse, comprising: generating a first non-sine continuous wave voltage (NSCWV) signal over a first duration of a clock cycle, the first NSCWV signal including a first base voltage and a first frequency; performing a first transition, the first transition including changing from the first NSCWV signal to a second NSCWV signal generated for a second duration of the clock cycle, the second NSCWV signal including a second base voltage and a second frequency; A method comprising:

2. 2. The method of claim 1 , The method, further comprising performing a second transition, the second transition comprising transitioning from the second NSCWV signal back to the first NSCWV signal.

3. 3. The method of claim 2, The method further comprising repeating the first transition and the second transition over the clock cycle.

4. 2. The method of claim 1 , A method, wherein the first base voltage magnitude is greater than the second base voltage magnitude.

5. 2. The method of claim 1 , The reciprocal of the sum of the first duration and the second duration defines a duty cycle of the voltage pulse, and the duty cycle of the first NSCWV signal is between 50% and 75%.

6. 2. The method of claim 1 , The sum of the first duration and the second duration defines a pulse frequency of the voltage pulse, the pulse frequency being between 1 Hz and 100 kHz.

7. 2. The method of claim 1 , Generating the first NSCWV signal includes: performing a first operation including increasing a voltage level a first magnitude from a reference voltage to the first base voltage over a first time interval; performing a second operation including ramping the voltage level from the first base voltage to a first peak voltage over a second time interval; performing a third operation including decreasing the voltage level from the first peak voltage to the reference voltage over a third time interval; performing a fourth action including maintaining the voltage level at the reference voltage for a fourth time interval; repeating the first action, the second action, the third action, and the fourth action for the first duration; and The method further comprising:

8. 8. The method of claim 7, The method of claim 1, wherein the first frequency is equal to one divided by the sum of the first time interval, the second time interval, the third time interval, and the fourth time interval.

9. 9. The method of claim 8, The method of claim 1, wherein the first frequency is between 2 Hz and 400 kHz.

10. 8. The method of claim 7, The method of claim 1, wherein the second time interval is at least 100 times greater than the first time interval or the third time interval, and the fourth time interval is at least 100 times greater than the first time interval or the third time interval.

11. 11. The method of claim 10, A method according to claim 1, wherein a ratio between the second time interval and the fourth time interval is greater than or equal to 2:

1.

12. 11. The method of claim 10, A method according to claim 1, wherein a ratio between the second time interval and the fourth time interval is 3:

1.

13. 8. The method of claim 7, the reference voltage is a first reference voltage, the voltage level is a first voltage level, and generating the second NSCWV signal includes: performing a fifth operation including increasing a second voltage level from a second reference voltage to the second base voltage over a fifth time interval; performing a sixth operation including ramping the second voltage level from the second base voltage to a second peak voltage over a sixth time interval; performing a seventh operation including decreasing the second voltage level from the second peak voltage to the second reference voltage over a seventh time interval; performing an eighth operation including maintaining the second voltage level at the second reference voltage for an eighth time interval; repeating the fifth, sixth, seventh, and eighth actions for the second duration; and The method further comprising:

14. 14. The method of claim 13, The method of claim 1, wherein the second frequency is equal to one divided by the sum of the fifth time interval, the sixth time interval, the seventh time interval, and the eighth time interval.

15. 15. The method of claim 14, The method of claim 1, wherein the second frequency is between 2 Hz and 400 kHz.

16. 14. The method of claim 13, The method of claim 1, wherein the sixth time interval is at least 100 times greater than the fifth time interval or the seventh time interval, and the eighth time interval is at least 100 times greater than the fifth time interval or the seventh time interval.

17. 17. The method of claim 16, A method according to claim 1, wherein a ratio between the sixth time interval and the eighth time interval is greater than or equal to 2:

1.

18. 17. The method of claim 16, A method according to claim 1, wherein a ratio between the sixth time interval and the eighth time interval is 3:

1.

19. 14. The method of claim 13, A first magnitude of a first difference between the first base voltage and the first reference voltage is greater than a second magnitude of a second difference between the second base voltage and the second reference voltage.

20. 14. The method of claim 13, A third magnitude of the first peak voltage is greater than or less than a fourth magnitude of the second peak voltage.

21. 1. A method for operating a plasma chamber to increase ion energy and reduce ion angular spread at a surface of a substrate during an etching operation, comprising: placing the substrate on an electrostatic chuck in the plasma chamber, the electrostatic chuck being electrically coupled to a non-sine continuous wave voltage (NSCWV) generator; forming a plasma in the plasma chamber, the plasma generating a sheath including a sheath voltage; Varying the sheath voltage by applying a voltage pulse to the electrostatic chuck using a continuous wave voltage source, the applying of the voltage pulse comprising: generating a first non-sine continuous wave voltage (NSCWV) signal over a first duration of a clock cycle, the first NSCWV signal including a first base voltage and a first frequency; performing a first transition, the first transition including changing the first NSCWV signal to a second NSCWV signal generated for a second duration of the clock cycle, the second NSCWV signal including a second base voltage and a second frequency; A method comprising:

22. 22. The method of claim 21, The method, further comprising performing a second transition, the second transition comprising changing the second NSCWV signal back to the first NSCWV signal.

23. 23. The method of claim 22, The method further comprising repeating the first transition and the second transition over the clock cycle, wherein applying the voltage pulse effects a change in the spread of ion energies on the surface of the substrate.

24. 22. The method of claim 21, The method of claim 1, wherein the first NSCWV signal includes a first plurality of harmonics and applying the second NSCWV signal includes a second plurality of harmonics.

25. 25. The method of claim 24, The method of claim 1, wherein the first plurality of harmonics and the second plurality of harmonics include a fundamental harmonic and up to a 10th harmonic of 400 kHz.

26. 22. The method of claim 21, The method, wherein the voltage pulse further comprises a positive period, a negative period, and a duty cycle from 0 to 100.

27. 22. The method of claim 21, The method, wherein applying the first NSCWV signal further comprises ramping to a first negative voltage and a second negative voltage, the second negative voltage being 25-50% percent greater than the first negative voltage.

28. 1. A method for operating a plasma chamber and modifying ion energy and ion angular spread at a surface of a substrate during an etching operation, comprising: placing the substrate on an electrostatic chuck in the plasma chamber, the electrostatic chuck being electrically coupled to a non-sinusoidal voltage waveform generator; forming a plasma in the plasma chamber, the plasma generating a sheath having a first sheath voltage; applying a first non-sinusoidal voltage waveform having a first periodic function to the electrostatic chuck to change the first sheath voltage to a second sheath voltage to generate a first voltage response on the electrostatic chuck, thereby causing a first change in ion energy spread at the substrate; modifying the second sheath voltage to a third sheath voltage by applying a second non-sinusoidal voltage waveform comprising a second periodic function to the electrostatic chuck to generate a second voltage response on the electrostatic chuck, thereby causing a second change in ion energy spread at the substrate; A method comprising:

29. 29. The method of claim 28, The method, wherein the first non-sinusoidal voltage waveform includes a first base voltage value, the first non-sinusoidal voltage waveform producing a first ion angular spread at the substrate.

30. 30. The method of claim 29, The method, wherein the second non-sinusoidal voltage waveform includes a second base voltage value, the second non-sinusoidal voltage waveform resulting in a second ion angular spread at the substrate.

31. 31. The method of claim 30, The method of claim 1, wherein the first ion angular spread is less than 70 percent of the second ion angular spread.

32. 30. The method of claim 29, The method of claim 1, wherein the first ion angular spread produces an etch rate that is twice as high as an etch rate produced by the second non-sinusoidal voltage waveform.

33. A machine-readable storage medium having machine-executable instructions that, when executed, cause one or more machines to: Controlling a pulse voltage waveform; Controlling the periodic voltage; controlling the pulse voltage waveform to generate low and high voltage pulses having a predetermined duty cycle, thereby controlling the spread of ion energy within a sheath region of the plasma; A machine-readable storage medium for carrying out a method comprising:

34. 34. The machine-readable storage medium of claim 33, The machine-readable storage medium, wherein the pulsed voltage waveform has a duty cycle of at least 50% of the high voltage pulses.

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