Silicon carbide planar MOSFET device and method for fabricating same

Abstract

The present invention provides a planar silicon carbide MOSFET element and a manufacturing method thereof, which can effectively use the crystal planes of the SiC crystal with high channel mobility, such as the (1120) crystal plane, (1100) crystal plane, or (0338) crystal plane, by providing several shallow trenches while the channel current is still parallel to the (0001) crystal plane of the SiC crystal, and can effectively reduce the channel resistance of the planar silicon carbide MOS element. In addition, the formation of the source region, well region, and channel does not require protection by an additional ion implantation layer (IMP layer), and the process is simplified.

Description

[Technical field]

[0001] The present invention relates to the technical field of semiconductor devices and their manufacture, and in particular to planar silicon carbide MOSFET devices and methods for their manufacture. [Background technology]

[0002] Silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) elements have advantages such as fast switching speed and low on-resistance. In addition, they can achieve a high breakdown voltage level with a small drift layer thickness, which reduces the volume of power switch modules and energy consumption, making them clearly superior in the application fields of power switches, converters, etc.

[0003] Planar SiC-MOSFET devices are widely applied due to the advantages of simple processing, high cell matching, relatively high avalanche energy, etc. However, how to further improve the performance of planar SiC-MOSFET devices has been one of the hot issues being investigated by those skilled in the art. Summary of the Invention

[0004] An object of the present invention is to provide a planar-type silicon carbide MOSFET element and a manufacturing method thereof that can improve the performance of the planar-type SiC-MOSFET element.

[0005] In order to achieve the above object, the present invention provides a silicon carbide drift layer of a first conductivity type having a top surface that is a (0001) crystal plane; a gate oxide layer and a gate electrode sequentially stacked on a top surface of the silicon carbide drift layer; a second conductivity type well region formed in a surface layer of the silicon carbide drift layer on both sides of the gate electrode, and a first conductivity type source region formed in a surface layer of the well region on both sides of the gate electrode; at least one trench is formed in the silicon carbide drift layer at a bottom of the gate electrode and extends toward both sides of the gate electrode to between a boundary of the source region and a boundary of the well region, the trench having a bottom shallower than a bottom of the well region and two sidewall surfaces extending in a width direction of the gate electrode, both of which are crystal planes having a channel mobility higher than a (0001) crystal plane; A planar silicon carbide MOSFET device is provided, wherein the gate oxide layer covers at least an inner surface of the trench and the gate electrode fills the trench.

[0006] Optionally, the crystal plane having a channel mobility higher than that of the (0001) crystal plane includes a (112 0) crystal plane, a (11 00) crystal plane, or a (03 38) crystal plane.

[0007] Optionally, the trenches are arranged in parallel in sequence and spaced apart from one another in the longitudinal direction of the gate electrode, and any two of the trenches are not connected to each other, or at least two of the trenches are connected to each other in corresponding regions.

[0008] Optionally, the bottom depth of the trench is less than the bottom depth of the source region.

[0009] Optionally, the planar silicon carbide MOSFET device further includes a media structure formed in a portion of the trench, the gate oxide layer covering an inner surface of the trench around the periphery of the media structure, and the gate electrode further embedding the media structure.

[0010] Optionally, the top of the media structure is higher than the top of the gate oxide layer around the periphery of the trench, and the gate electrode is contoured over the media structure and has a protruding or flat top.

[0011] Optionally, the planar silicon carbide MOSFET device comprises: source electrodes formed on (0001) crystal faces of the silicon carbide drift layer on both sides of the gate electrode and electrically connected to the source region; a buffer layer of a first conductivity type stacked on a bottom surface of the silicon carbide drift layer; a first conductive type base laminated on a bottom surface of the buffer layer; The semiconductor device further includes a drain electrode laminated on a bottom surface of the base.

[0012] Based on the same inventive concept, the present invention: providing a substrate having a silicon carbide drift layer of a first conductivity type, a top surface of the silicon carbide drift layer being a (0001) crystallographic plane; a step of etching a top surface of the silicon carbide drift layer in a region where a gate electrode is to be formed, to form at least one trench, the trench extending to between a boundary of a source region and a boundary of a well region toward both sides of the gate electrode to be formed, a bottom of the trench being shallower than a bottom of the well region, and two sidewall surfaces of the trench extending in a width direction of the gate electrode to be formed are both crystal planes having a channel mobility higher than that of a (0001) crystal plane; There is further provided a method for manufacturing a planar silicon carbide MOSFET device according to the present invention, comprising the steps of: forming a gate oxide layer and a gate electrode, in that order, on a top surface of the silicon carbide drift layer, wherein the gate oxide layer covers at least an inner surface of the trench and the gate electrode fills the trench.

[0013] Optionally, before forming at least one trench by etching the top surface of the silicon carbide drift layer in a region where a gate electrode is to be formed, first, the well region of the second conductivity type and the source region of the first conductivity type are formed in the top surface of the silicon carbide drift layer, the well regions being formed in a surface layer of the top surface of the silicon carbide drift layer on both sides of the gate electrode, and the source regions being formed in a surface layer of the well regions on both sides of the gate electrode; Alternatively, after forming at least one of the trenches, the well region and the source region are formed in the top surface of the silicon carbide drift layer before or after forming the gate electrode.

[0014] Optionally, the substrate further includes a buffer layer of a first conductivity type and a base of a first conductivity type stacked in sequence on a bottom surface of the silicon carbide drift layer, and the manufacturing method further includes: forming a source electrode on a top surface of the silicon carbide drift layer, the source electrode being electrically connected to the source region; The method further includes forming a drain electrode on a bottom surface of the base.

[0015] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0016] 1. The element is still guaranteed to be a planar silicon carbide MOSFET element, with the (0001) crystal plane of the silicon carbide crystal being the main channel, and the channel current is still parallel to the (0001) crystal plane of the SiC crystal. In addition, by providing several shallow trenches, the crystal planes of the silicon carbide crystal with high channel mobility, such as the (112￣0) crystal plane, (11￣00) crystal plane or (03￣38￣) crystal plane, can be more effectively utilized, and the channel resistance of the planar silicon carbide MOS element can be effectively reduced.

[0017] 2. The bottom depth of the trench is shallower than the source region or well region, so no additional ion implantation layer (IMP layer) protection is required, and the process is simplified.

[0018] 3. The degree of reduction of channel resistance Ron or Rsp is related to the density of trenches, and has a more obvious beneficial effect on planar MOSFET devices applied below 1700V, for example, when the solution of the present invention is applied to a 750V planar silicon carbide MOSFET device, the channel resistance Ron or Rsp can be reduced by 30%. [Brief description of the drawings]

[0019] As can be understood by those skilled in the art, the drawings provided are for a better understanding of the present invention, and are not intended to limit the scope of the present invention in any way. [Figure 1] FIG. 1 is a schematic diagram showing the planar structure of a conventional planar SiC MOSFET element. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line AA′ in FIG. [Diagram 3] FIG. 2 is a schematic diagram of a crystal plane of a SiC crystal. [Figure 4] FIG. 2 is a graph showing the relationship between channel mobility and gate voltage for different crystal planes of a SiC crystal. [Diagram 5] FIG. 1 is a schematic planar structural view of a planar silicon carbide MOSFET element according to one embodiment of the present invention. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line AA′ in FIG. 5. [Figure 7] FIG. 6 is a schematic cross-sectional view taken along line BB' in FIG. 5. [Figure 8] 6 is a schematic cross-sectional view taken along line CC' in FIG. 5. FIG. [Figure 9] FIG. 2 is a schematic cross-sectional view of a planar silicon carbide MOSFET element according to another embodiment of the present invention. [Figure 10] FIG. 2 is a schematic cross-sectional view of a planar silicon carbide MOSFET element according to still another embodiment of the present invention. [Figure 11]FIG. 4 is a schematic planar structural view of a trench in a planar silicon carbide MOSFET element according to still another embodiment of the present invention. [Figure 12] FIG. 4 is a schematic cross-sectional view of a multi-step trench in a planar silicon carbide MOSFET element according to another embodiment of the present invention. [Figure 13] FIG. 4 is a schematic cross-sectional view of a multi-step trench in a planar silicon carbide MOSFET element according to another embodiment of the present invention. [Figure 14] 2 is a flow chart of a method for manufacturing a planar silicon carbide MOSFET device according to a specific embodiment of the present invention. [Figure 15] 1A to 1C are schematic cross-sectional views of a planar silicon carbide MOSFET device according to a specific embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following description, many specific details are provided to make the present invention more clearly understood. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some technical features well known in the art are not described in order to avoid confusing the present invention. It is to be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals represent the same elements throughout. It should be understood that when an element or layer is said to be "on" or "connected" to another element or layer, it may be directly on or connected to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is said to be "directly on" or "connected" to another element or layer, there are no intervening elements or layers. Terms such as first, second, etc. may be used to describe various elements, members, regions, layers, and / or portions, but these elements, members, regions, layers, and / or portions should not be limited to these terms. These terms are only intended to distinguish one element, member, region, layer, or portion from another element, member, region, layer, or portion. Thus, a first element, member, region, layer, or portion discussed below may be referred to as a second element, member, region, layer, or portion without departing from the teachings of the present invention. Spatial relationship terms such as "under," "on the lower surface," "on the lower surface," "on the upper surface," "on the top surface," "on the bottom surface," "on the front surface," "on the back surface," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature depicted in the figures. It should be understood that the spatial relationship terms are intended to further include different orientations of the elements during use and operation other than those depicted in the figures.For example, if an element in a drawing is inverted, an element or feature described as "under", "on the underside", "on the bottom", "on the backside" would be oriented "above" or "on top" or "upper" of the other element or feature. Elements may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context indicates otherwise. It is further understood that the term "comprising" specifies the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0021] The technical solution of the present invention will be described in more detail below with reference to the drawings and specific embodiments. From the following description, the advantages and features of the present invention will become more apparent. It should be noted that the drawings are all very simplified in form and not in exact proportion, and are only used to assist in explaining the embodiments of the present invention easily and clearly.

[0022] 1 and 2, the structure of a conventional planar-type SiC-MOSFET device includes a drain electrode 107, an N++ base 100a, an N+ buffer layer 100b, an N- drift layer 100c, a gate oxide layer 104, and a gate electrode 105, which are stacked in this order from the bottom. The structure further includes a P well 101 formed in the N- drift layer 100c, an N+ source region 102 and a P+ contact region 103 formed in the P well 101 (also called a P base region), and a source electrode 106 formed on the N- drift layer 100c. The source electrode 106 is in electrical contact with the N+ source region 102 and the P+ contact region 103, thereby shorting the N+ source region 102 and the P+ contact region 103.

[0023] In the above planar type SiC-MOSFET device, the channel (not labeled) is located at the bottom of the gate electrode 105, in the region overlapping with the P-well 101. When operating in the forward direction, when the gate voltage is forward biased and above its threshold, an inversion layer is formed, the channel is turned on, and electrons flow from the source electrode 106, in sequence through the N+ source region 102 and the channel, to the depletion region (also called the JFET region, i.e., below the bottom of the gate electrode 105 and in the N-drift layer 100c between the two P-wells 101), downward through the N-drift layer 100c, the N+ buffer layer 100b, and the N++ base 100a, and finally to the drain electrode 107. When the gate electrode 105 and the source electrode 106 are shorted and the drain electrode 107 is forward biased, a reverse bias depletion region is formed by the P well 101 and the N-drift layer 100c, and since the P-type ion doping concentration in the P well 101 is greater than the N-type ion doping concentration in the N-drift layer 100c, the reverse bias depletion region mainly extends to the N-drift layer 100c, resulting in a high breakdown voltage.

[0024] However, the planar SiC-MOSFET element has some drawbacks. Specifically, the conventional planar SiC-MOSFET element is usually manufactured by 4H-SiC crystal, and the distribution diagram of the crystal plane and crystal orientation of the 4H-SiC crystal is as shown in FIG. 3. Due to the influence of the 4H-SiC epitaxial (EPI) crystal orientation, the gate electrode 105 of the planar SiC-MOSFET element is always on the (0001) crystal plane of the SiC crystal. The (0001) crystal plane has many interface states, and as shown in FIG. 4, the channel mobility is only 1 / 3 of that of the (112￣0) crystal plane and the (11￣00) crystal plane. Therefore, the planar SiC-MOSFET element has a high channel resistance. In addition, the stray capacitance of such a structure is also large. The (112￣0) crystal plane and the (11￣00) crystal plane are pyramidal planes perpendicular to the (0001) crystal plane.

[0025] Furthermore, in conventional technology, there are very few wafers on which crystal planes with high channel mobility, such as the (112￣0) crystal plane, (11￣00) crystal plane, and (03￣38) crystal plane, are epitaxially grown. Even if it were possible to epitaxially grow crystal planes with high channel mobility, such as the (112￣0) crystal plane, (11￣00) crystal plane, and (03￣38) crystal plane of a SiC crystal, the epitaxial defects would spread directly across the entire wafer surface, causing the fabricated devices to have large leakage current and degraded electrical performance.

[0026] Therefore, the present invention provides a structure design and a manufacturing method for a novel planar type SiC-MOSFET device, in which the gate electrode is on the (0001) crystal plane of the SiC crystal, and other crystal planes of the SiC crystal with high channel mobility, such as the (1120), (1100), and (0338), are more effectively utilized to reduce the channel resistance and improve the performance of the device, while further reducing the stray capacitance of the device.

[0027] 5 to 8, one embodiment of the present invention provides a planar type silicon carbide MOSFET device including a drain electrode 107, a base 100a, a buffer layer 100b, a silicon carbide drift layer 100c, a gate oxide layer 104, and a gate electrode 105, which are stacked in this order from below (i.e., from the bottom surface to the top surface).

[0028] Here, the base 100a, the buffer layer 100b and the silicon carbide drift layer 100c are all of a first conductivity type (eg, N-type), and the doping concentrations of impurities of the first conductivity type decrease sequentially.

[0029] The SiC crystal in the silicon carbide drift layer 100c is a hexagonal crystal such as 4H-SiC or 6H-SiC, the top surface (which may be called the front surface) of the silicon carbide drift layer 100c is a (0001) crystal plane of the SiC crystal, and well regions 101 of a second conductivity type (e.g., P type) are formed in the surface layer of the top surface of the silicon carbide drift layer 100c on both sides of the gate electrode 105, source regions 102 of a first conductivity type are formed in the surface layer of the top surface of the well regions 101 on each side, and a body contact region 103 of a second conductivity type is formed in the well region 101 on the periphery of the source region 102. The doping concentration of the first conductivity type impurity in the source region 102 and the doping concentration of the second conductivity type impurity in the body contact region 103 are greater than the doping concentration of the second conductivity type impurity in the well region 101, respectively.

[0030] The source electrode 106 is formed on the surface of the source region 102 and the body contact region 103, and electrically connects the body contact region 103 and the source region 102 to make them equipotential. The drain electrode 107 is laminated on the bottom surface of the base 100a (i.e., the back surface of the base 100a). Both the source electrode 106 and the drain electrode 107 may be mainly made of metal, and the material may be selected from Al, AlCu, and AlSiCu.

[0031] In this embodiment, the gate electrode 105, the source region 102, and the well region 101 are arranged to form a parallel stripe structure. The material of the gate electrode 105 may include doped polysilicon, and the conductivity type of the gate electrode 105 may be opposite to that of the silicon carbide drift layer 100c.

[0032] At least one trench 100d is provided in the silicon carbide drift layer 100c below the bottom of the gate electrode 105, and all of these trenches 100d are provided in the cross direction of the channel current (for example, as shown by the dotted arrow in FIG. 6), and when there are multiple trenches 100d, these trenches 100d are formed at intervals in the cross direction of the channel current (for example, as shown by the dotted arrow in FIG. 6). The bottom of each trench 100d is shallower than the bottom of the well region 101, and optionally, the bottom of each trench 100d is shallower than the bottom of the source region 102. For example, the bottom depth of each trench 100d (i.e., the height from the top surface of the silicon carbide drift layer to the bottom surface of the trench 100d) is all less than 1000 Å.

[0033] Each trench 100d may have any suitable shape, such as a rectangle, a trapezoid, etc. Each trench 100d extends to between the boundary of the source region 102 and the boundary of the well region 101 toward both sides of the gate electrode 105, i.e., the length w of the trench 100d in the width direction of the gate electrode (i.e., the AA' direction or the BB' direction in FIG. 5) is between the interval a between the well regions 101 and the interval b between the source regions 102 on both sides of the gate electrode 105, i.e., a <w<bである。

[0034] The crystal planes of the two sidewall surfaces S1 and S2 extending in the width direction of the gate electrode 105 of each trench 100d are both crystal planes in which the channel mobility in the SiC crystal is higher than that of the (0001) crystal plane, such as the (112 0) crystal plane, (11 00) crystal plane, or (03 38 ) crystal plane of the SiC crystal. That is, the sidewall surfaces S1 and S2 are parallel to the (112 0) crystal plane, (11 00) crystal plane, or (03 38 ) crystal plane of the SiC crystal in the silicon carbide drift layer 100c. Here, referring to FIG. 3, the (112 0) crystal plane and (11 00) crystal plane of the SiC crystal are both pyramidal planes perpendicular to the (0001) crystal plane of the SiC crystal, and the channel mobility of the (112 0) crystal plane and the (11 00) crystal plane is about three times that of the (0001) crystal plane. The (03￣38￣) crystal plane of a SiC crystal is a crystal plane that forms an angle of approximately 55° or 54.74° with the (101￣0) crystal plane of a SiC crystal. The (101￣0) crystal plane of a SiC crystal is parallel to the (0001) crystal plane of a SiC crystal.

[0035] It should be understood that the two sidewall surfaces S1, S2 of each trench 100d may be parallel to the width direction AA' of the gate electrode, or may intersect due to process errors, but the angle they form may be limited within a tolerable range. In other words, the angle between the two sidewall surfaces S1, S2 of the trench 100d and the AA' direction may be within 90° as long as it is guaranteed that the crystal planes of the sidewall surfaces S1, S2 are crystal planes with high channel mobility, such as a (112 0) crystal plane, a (11 00) crystal plane, or a (03 38) crystal plane. o It doesn't have to be.

[0036] Optionally, in another embodiment of the present invention, in order to reduce the stray capacitance of the gate electrode 105, referring to Fig. 9, the planar silicon carbide MOSFET device further includes a media structure 108, which is formed in a part of the trench 100d and is used to raise the bottom of the gate electrode 105, the gate oxide layer 104 covers the inner surface of the trench 100d around the media structure 108 and the exposed surface of the source region 102, and the gate electrode 105 further embeds the media structure 108. The media structure 108 is made of an insulating media material, which is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, high-K material, spin-coated dielectric material (such as spin-coated phosphosilicate glass, borophosphosilicate glass or fluorine-doped silica glass), and low-k dielectric material. By providing the above-mentioned medium structure 108, the distance between the gate electrode 105 and the drain electrode 107 is increased, that is, the distance between the two electrodes of the gate-drain capacitance (Cgd) is directly increased, so that Cgd, i.e., feedback capacitance or Miller capacitance, can be effectively reduced and application loss can be reduced. Here, as an example, as shown in FIG. 9, the top of the medium structure 108 is higher than the top of the gate oxide layer 104 on the outer periphery of the trench 100d, the gate electrode 105 covers the medium structure 108 and the gate oxide layer 104 to conform to the shape, and a protrusion (not shown) is further formed. As another example, as shown in FIG. 10, the top of the medium structure 108 is higher than the top of the gate oxide layer 104 on the outer periphery of the trench 100d, the gate electrode 105 further fills the medium structure 108 and has a flat top.

[0037] 5 to 10, in each of the above embodiments, the trenches 100d formed may be arranged in parallel in the length direction of the gate electrode 105, and may be arranged at equal intervals or at unequal intervals, provided that any two trenches 100d are not connected to each other, and in this case, the trenches 100d are formed at intervals in the crossing direction of the channel current. However, the technical solution of the present invention is not limited to this. In another embodiment of the present invention, referring to FIG. 11, the trenches 100d may be arranged in parallel in the length direction of the gate electrode 105, and may be arranged at intervals, provided that at least two trenches 100d are connected to each other in corresponding regions (for example, ends or middle parts). The connected trenches 100d may be adjacent to each other, and there may be at least one trench 100d between them.

[0038] 5 to 10, in the above embodiments, each of the trenches 100d formed is a single-step trench, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, if the overall depth design of the trenches 100d allows, at least one of the trenches 100d may be a two-step trench, a three-step trench, or a more than two-step trench. The cross-sectional structure of the trench 100d which is a two-step trench may have two steps on the sidewall surface including S1 and S2 of the trench 100d as shown in FIG. 12, and the cross-sectional structure of the trench 100d which is a three-step trench may have three steps on the sidewall surface including S1 and S2 of the trench 100d as shown in FIG. 13.

[0039] Based on the same inventive concept, referring to FIG. 14, an embodiment of the present invention further provides a method for manufacturing a planar silicon carbide MOSFET device, which can fabricate the planar silicon carbide MOSFET device of the present invention, and the method specifically includes: A step s11 of providing a substrate having a silicon carbide drift layer of a first conductivity type, the uppermost surface of the silicon carbide drift layer being a (0001) crystal plane; a step s12 of etching the top surface of the silicon carbide drift layer in a region where a gate electrode is to be formed to form at least one trench, the trench extending to between a boundary of a source region and a boundary of a well region toward both sides of the gate electrode to be formed, a bottom of the trench being shallower than a bottom of the well region, and two sidewall surfaces of the trench extending in a width direction of the gate electrode to be formed are both crystal planes having a channel mobility higher than that of a (0001) crystal plane; and step s13 of sequentially forming a gate oxide layer and a gate electrode on a top surface of the silicon carbide drift layer, the gate oxide layer covering at least an inner surface of the trench and the gate electrode filling the trench.

[0040] In step s11, referring to (A) in FIG. 15, a base 100a is prepared, and a first conductivity type buffer layer 100b and a silicon carbide drift layer 100c are successively formed on the base 100a by any appropriate process such as an epitaxial growth process, where the top surface of the silicon carbide drift layer 100c is a (0001) crystal plane, and the thicknesses and doping concentrations of the base 100a, the buffer layer 100b and the silicon carbide drift layer 100c are all designed according to the requirements of the device and are not specifically limited in this embodiment.

[0041] In step s12, referring to (A) in FIG. 15, first, the surface layer of the region in which the channel and depletion region are to be formed in the silicon carbide drift layer 100c is dry etched to form at least one trench 100d, and the two sidewall surfaces extending in the width direction of the gate electrode to be formed in the trench 100d are both crystal planes having a channel mobility higher than that of the (0001) crystal plane.

[0042] Optionally, by an appropriate process such as wet etching or wet etching after oxidation, the crystal plane of the trench 100d is corrected and adjusted to form a crystal plane with high channel mobility such as (112￣0) crystal plane, (11￣00) crystal plane or (03￣38￣) crystal plane, or the trench 100d can be corrected and adjusted from a single-stage trench to a two-stage trench as shown in FIG. 12, a three-stage trench as shown in FIG. 13 or a trench with more stages.

[0043] In an example of this embodiment, referring to (A) in FIG. 15, before executing step s12, that is, before etching the uppermost surface of the silicon carbide drift layer 100c in the region where the gate electrode is to be formed to form at least one trench 100d, first, a second-conductivity-type well region 101 is formed on the uppermost surface of the silicon carbide drift layer 110c by a series of processes such as mask deposition, patterning, and ion implantation. Then, a first-conductivity-type source region 102 and a second-conductivity-type body contact region 103 are formed. The formed trench 100d extends from one well region 101 used as a boundary region of the channel to the other well region 101 used as a boundary region of the channel. The source regions 102 are formed in the surface layers of the well regions 101 on both sides respectively, and there is a gap between the trench 100d and the boundary of the source region 102. That is, as shown in FIGS. 5 and 6, the length w extending in the width direction of the gate electrode of the trench 100d (that is, the AA' direction or the BB' direction in FIG. 5) is between the gap a between the well regions 101 and the gap b between the source regions 102 on both sides of the gate electrode 105, that is, a < w < b. Further, after forming the well region 101, the source region 102, and the body contact region 103, the corresponding mask is removed, and the implanted impurities are activated by a high-temperature annealing process. The bottom depth of the trench 100d is shallower than the bottom depth of the source region 102 or the bottom depth of the well region 101.

[0044] In another example of this embodiment, referring to (A) in FIG. 15, after performing step s12, a series of processes such as mask deposition, patterning and ion implantation are used to first form well regions 101 on the top surface of the silicon carbide drift layer 100c on both sides of the trench 100d, and then form a first conductive type source region 102 and a second conductive type body contact region 103. After forming the well region 101, the source region 102 and the body contact region 103, the corresponding masks are removed, and the implanted impurities are activated by a high-temperature annealing process. The bottom depth of the trench 100d is shallower than the bottom depth of the source region 102 or the bottom depth of the well region 101. Each trench 100d extends to between the boundary of the source region 102 and the boundary of the well region 101 toward both sides of the gate electrode 105. That is, as shown in FIGS. 5 and 6, the length w of the trench 100d in the width direction of the gate electrode (i.e., the AA′ direction or the BB′ direction in FIG. 5) is between the interval a between the well regions 101 and the interval b between the source regions 102 on both sides of the gate electrode 105, that is, a <w<bである。

[0045] In step s13, referring to (D) and (E) in FIG. 15, a gate oxide layer 104 can be formed by a thermal oxidation process or a deposition process, etc., and polysilicon is deposited on the gate oxide layer 104, and then a second conductive type impurity is implanted and activated to form a highly doped polysilicon gate electrode material layer, and then the polysilicon gate electrode material layer and the gate oxide layer 104 are patterned to form a gate electrode 105 and a covered gate oxide layer 104.

[0046] In one example of this embodiment, referring to (B) and (C) in FIG. 15, after performing step s12 and before step s13, first, by a suitable process such as deposition, spin coating, etc., cover the trench 100d, the source region 102, and the body contact region 103 with a medium layer 108', which may have a flat or uneven top surface. The height of the top surface is higher than that of the silicon carbide drift layer 100c, and then, by a process such as resist coating, exposure, and development, a patterned mask 200 is formed, and the medium layer 108' is etched under the masking action of the patterned mask 200 to form a medium structure 108 in the trench 100d. The gate electrode 105 formed in step s13 can cover the medium structure 108 and the gate oxide layer 104 to conform to the shape, and the gate electrode 105 may have a flat or relatively protruding top surface.

[0047] It should be noted that the manufacturing method of this embodiment has a simpler process and is easier to implement because the formation of the source region, well region, and channel does not require protection by an additional ion implantation layer (IMP layer) due to the formation of trench 100d, as compared to the conventional technology.

[0048] 15(E) and (F), after performing step s13, a dulling layer (not shown) may be deposited on the gate electrode 105 and the exposed element surface, and the dulling layer may be etched to form a surface exposing the source region 102 and the body contact region 103, and a source electrode metal may be grown on the source region 102 and the body contact region 103 and annealed to form the source electrode 106, and the source electrode 106 may be electrically connected to the source region 102 and the body contact region 103. Then, a drain electrode metal may be deposited on the bottom surface of the base 100a and annealed to form the drain electrode 107.

[0049] As described above, in the planar silicon carbide MOSFET device and the manufacturing method thereof of the present invention, in addition to the channel current still being parallel to the (0001) crystal plane of the SiC crystal, by providing several shallow trenches, the crystal planes of the SiC crystal with high channel mobility, such as the (112 0) crystal plane, the (11 00) crystal plane, or the (03 38 ) crystal plane, can be more effectively used, and the channel resistance of the planar silicon carbide MOS device can be effectively reduced. In addition, the formation of the source region, the well region, and the channel does not require protection by an additional ion implantation layer (IMP layer), and the process is simplified. In addition, the degree of reduction in the channel resistance Ron or Rsp is related to the density of the trenches, and has a more obvious beneficial effect on the planar MOSFET device applied at 1700V or less. For example, when the solution of the present invention is applied to a 750V planar silicon carbide MOSFET device, the channel resistance Ron or Rsp can be reduced by 30%.

[0050] The above description is merely a description of preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those skilled in the art based on the above disclosure will fall within the scope of protection of the technical solutions of the present invention.

Claims

1. a silicon carbide drift layer of a first conductivity type having a top surface that is a (0001) crystal plane; a gate oxide layer and a gate electrode sequentially stacked on a top surface of the silicon carbide drift layer; a second conductivity type well region formed in a surface layer of the silicon carbide drift layer on both sides of the gate electrode, and a first conductivity type source region formed in a surface layer of the well region on both sides of the gate electrode; at least one trench is formed in the silicon carbide drift layer at a bottom of the gate electrode and extends toward both sides of the gate electrode to between a boundary of the source region and a boundary of the well region, the trench having a bottom shallower than a bottom of the well region and two sidewall surfaces extending in a width direction of the gate electrode, both of which are crystal planes having a channel mobility higher than a (0001) crystal plane; A planar silicon carbide MOSFET device, characterized in that the gate oxide layer covers at least an inner surface of the trench, and the gate electrode fills the trench.

2. 2. The planar silicon carbide MOSFET device according to claim 1, wherein the crystal plane having a channel mobility higher than that of the (0001) crystal plane includes a (112 0) crystal plane, a (11 00) crystal plane, or a (03 38) crystal plane.

3. 2. The planar silicon carbide MOSFET element according to claim 1, wherein the plurality of trenches are arranged in parallel in a longitudinal direction of the gate electrode and spaced apart from each other, and any two of the trenches are not connected to each other, or at least two of the trenches are connected to each other in corresponding regions.

4. 2. The planar silicon carbide MOSFET device of claim 1, wherein the bottom depth of the trench is less than the bottom depth of the source region.

5. 2. The planar silicon carbide MOSFET device of claim 1, further comprising a media structure formed in a portion of the trench, the gate oxide layer covering an inner surface of the trench around the periphery of the media structure, and the gate electrode further embedding the media structure.

6. 8. The planar silicon carbide MOSFET device of claim 7, wherein a top of the media structure is higher than a top of the gate oxide layer around the periphery of the trench, and the gate electrode has a contoured or flat top overlying the media structure.

7. source electrodes formed on (0001) crystal faces of the silicon carbide drift layer on both sides of the gate electrode and electrically connected to the source region; a buffer layer of a first conductivity type laminated on a bottom surface of the silicon carbide drift layer; a first conductivity type base laminated on a bottom surface of the buffer layer; 9. The planar silicon carbide MOSFET device according to claim 1, further comprising: a drain electrode laminated on a bottom surface of the base.

8. providing a substrate having a silicon carbide drift layer of a first conductivity type, a top surface of the silicon carbide drift layer being a (0001) crystallographic plane; a step of etching a top surface of the silicon carbide drift layer in a region where a gate electrode is to be formed, to form at least one trench, the trench extending to between a boundary of a source region and a boundary of a well region toward both sides of the gate electrode to be formed, a bottom of the trench being shallower than a bottom of the well region, and two sidewall surfaces of the trench extending in a width direction of the gate electrode to be formed are both crystal planes having a channel mobility higher than that of a (0001) crystal plane; 8. The method for manufacturing a planar silicon carbide MOSFET device according to claim 1, further comprising the steps of: forming a gate oxide layer and a gate electrode on a top surface of the silicon carbide drift layer in that order, the gate oxide layer covering at least an inner surface of the trench and the gate electrode filling the trench.

9. before forming at least one trench by etching a top surface of the silicon carbide drift layer in a region where a gate electrode is to be formed, first, the well region of a second conductivity type and the source region of a first conductivity type are formed in the top surface of the silicon carbide drift layer, the well region being formed in a surface layer of the top surface of the silicon carbide drift layer on both sides of the gate electrode, and the source region being formed in a surface layer of the well region on both sides of the gate electrode; or forming the well region and the source region in a top surface of the silicon carbide drift layer after forming at least one of the trenches and before or after forming the gate electrode.

10. The substrate further includes a buffer layer of a first conductivity type and a base of a first conductivity type stacked in sequence on a bottom surface of the silicon carbide drift layer, forming a source electrode on a top surface of the silicon carbide drift layer, the source electrode being electrically connected to the source region; The method according to claim 8 or 9, further comprising the step of: forming a drain electrode on a bottom surface of the base.

Images