Package with interconnect die located between substrates - Patents.com

Abstract

1. A package comprising: a first substrate (102), a first integrated device (103) coupled to the first substrate, an interconnect die (110) coupled to the first substrate, a second substrate (104) coupled to the first substrate via the interconnect die, the first integrated device and the interconnect die being located between the first substrate and the second substrate, and an encapsulation layer (106) coupled to the first substrate and the second substrate, the encapsulation layer being located between the first substrate and the second substrate.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 741,998, filed in the United States Patent Office on May 11, 2022, the entire contents of which are incorporated by reference into this specification as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various aspects relate to a package having a substrate and an integrated device. [Background technology]

[0003]

[0003] A package may include a substrate and an integrated device. These components are bonded together to provide a package that can perform various electrical functions. There is a continuing need to provide better performing packages and reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to a package having a substrate and an integrated device.

[0005]

[0005] One embodiment provides a package comprising a first substrate, a first integrated device coupled to the first substrate, an interconnect die coupled to the first substrate, a second substrate coupled to the first substrate via the interconnect die, where the first integrated device and the interconnect die are located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate, where the encapsulation layer is located between the first substrate and the second substrate.

[0006]

[0006] Another embodiment provides a device including a first package including a first substrate, a first integrated device coupled to the first substrate, a means for die interconnection coupled to the first substrate, a second substrate coupled to the first substrate via the means for die interconnection, where the first integrated device and the means for die interconnection are located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate, where the encapsulation layer is located between the first substrate and the second substrate.

[0007]

[0007] Another embodiment provides a method for making a package. The method provides a first substrate having a first surface and a second surface. The method bonds a first integrated device to the second surface of the first substrate. The method bonds an interconnect die to the second surface of the first substrate. The method bonds a second substrate to the first substrate via the interconnect die. The second substrate has a first surface and a second surface. The method forms an encapsulation layer between the first substrate and the second substrate. [Brief description of the drawings]

[0008]

[0008] Various features, properties, and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Figure 1]

[0009] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate and at least one interconnect die. [Diagram 2]

[0010] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate and at least one interconnect die. [Diagram 3]

[0011] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 4]

[0012] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 5A]

[0013] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 5B] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 6A]

[0014] 1A-1C illustrate an exemplary sequence for fabricating an interconnect die. [Figure 6B] 1A-1C illustrate an exemplary sequence for fabricating an interconnect die. [Figure 7]

[0015] 1 illustrates an exemplary flow chart of a method for fabricating an interconnect die. [Figure 8]

[0016] 1 illustrates an exemplary cross-sectional profile view of a package including at least one interconnect die. [Figure 9]

[0017] 1 illustrates an exemplary cross-sectional profile view of a package including at least one interconnect die. [Figure 10A]

[0018] 1 illustrates an exemplary sequence for creating a package that includes a substrate and an interconnect die. [Figure 10B] 1 illustrates an exemplary sequence for creating a package that includes a substrate and an interconnect die. [Figure 11]

[0019] 1 shows an exemplary flow chart of a method for making a package including a substrate and an interconnect die. [Figure 12A]

[0020] 1 illustrates an exemplary sequence for preparing a substrate. [Figure 12B] 1 illustrates an exemplary sequence for preparing a substrate. [Figure 13]

[0021] 1 shows an exemplary flow chart of a method for fabricating a substrate. [Figure 14]

[0022] Illustrated are various electronic devices that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0023] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0010]

[0024] The present disclosure describes a package comprising a first substrate having a first surface and a second surface, a first integrated device coupled to the second surface of the substrate, an interconnect die coupled to the second surface of the substrate, a second substrate having a first surface and a second surface, the second substrate being coupled to the first substrate via the interconnect die, and an encapsulation layer coupled to the second surface of the first substrate and the first surface of the second substrate. A second integrated device may be coupled to the second surface of the second substrate. A second package may be coupled to the second surface of the second substrate. The second package may include a third substrate, a second integrated device coupled to the third substrate, and a second encapsulation layer coupled to the third substrate and the second integrated device. As described further below, the package provides high density interconnects, which helps provide improved package performance while keeping the package small and thin.

[0011] Exemplary Package with Substrate and Interconnect Die

[0025] 1 shows a cross-sectional profile view of a package 100 including a substrate and high density interconnects. The package 100 may include a package on package (PoP). The package 100 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 100 is coupled to a plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0012]

[0026] The package 100 includes at least one interconnect die 101, a substrate 102, a substrate 104, an integrated device 103, an integrated device 105, and an encapsulation layer 106. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 (e.g., a second substrate) is coupled to the substrate 102 (e.g., a first substrate) via the at least one interconnect die 101.

[0013]

[0027] The integrated device 103 (e.g., a first integrated device) is coupled to a second surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 via a plurality of pillar interconnects and / or a plurality of solder interconnects 130. The at least one interconnect die 101 may be coupled to the second surface of the substrate 102 via a plurality of solder interconnects 115. The at least one interconnect die 101 may be coupled to the first surface of the substrate 104 via a plurality of solder interconnects 114. As described further below, the at least one interconnect die 101 may be configured to provide a high density interconnect for the package 100. The encapsulation layer 106 may be coupled to the second surface (e.g., a top surface) of the substrate 102 and the first surface (e.g., a bottom surface) of the substrate 104. The encapsulation layer 106 may encapsulate (e.g., partially or completely) the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may include mold, resin, and / or epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 106 is located between the substrate 102 and the substrate 104. The at least one interconnect die 101 is located between the substrate 102 and the substrate 104. The integrated device 103 is located between the substrate 102 and the substrate 104. The integrated device 103 may include a front side and a back side. The front side of the integrated device 103 may face the substrate 102. The back side of the integrated device 103 may face the substrate 104. The back side of the integrated device 103 may be covered by the encapsulation layer 106. In some implementations, the backside (e.g., backside surface) of the integrated device 103 may remain exposed (e.g., not covered by the encapsulation layer 106). The at least one interconnect die 101 is located laterally of the integrated device 103. The at least one interconnect die 101 may laterally surround the integrated device 103.

[0014]

[0028] At least one interconnect die 101 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 include a pad interconnect 112a (e.g., a pad), a via interconnect 112b (e.g., a via), and a pad interconnect 112c (e.g., a pad). The pad interconnect 112a is coupled to the via interconnect 112b. The via interconnect 112b is coupled to the pad interconnect 112c. The pad interconnect 112a is coupled to a solder interconnect 114a. The solder interconnect 114a is part of a plurality of solder interconnects 114. The plurality of solder interconnects 114 is coupled to the plurality of die interconnects 112. The pad interconnect 112c is coupled to a solder interconnect 115a. The solder interconnect 115a is part of the plurality of solder interconnects 115. The at least one interconnect die 101 may include a dummy die. The at least one interconnect die 101 may not include active components. The at least one interconnect die 101 may not include transistors. The at least one interconnect die 101 may be a means for interconnecting die.

[0015]

[0029] The pitch of the interconnects between the substrate 102 and the substrate 104 may be relatively small. For example, the multiple die interconnects 112 may have a pitch between adjacent die interconnects in the range of about 150-270 micrometers. These dimensions are possible through the use of at least one interconnect die 101, which (i) helps provide a thinner package 100 while still being able to accommodate an integrated device 103 between the two substrates, and (ii) helps provide interconnects with a small pitch (e.g., 150-270 micrometers) within the encapsulation layer, and thus helps provide high density routing (e.g., high density interconnects) within the encapsulation layer. The pad interconnects 112c may have a diameter and / or width of about 30-60 micrometers. The pad interconnects 112b may have a height of about 30-70 micrometers. The pad interconnects 112a may have a diameter and / or width of about 90-220 micrometers. The pad interconnects 112a may have a thickness of about 5-15 micrometers. The encapsulation layer 106 may have a thickness of about 70-150 micrometers. The spacing between the surfaces of the substrates 102 and 104 may be equal to the thickness of the encapsulation layer 106.

[0016]

[0030] The substrate 102 may have a thickness in the range of approximately 90-160 micrometers. The interconnects 122 from the substrate 102 may have a width in the range of approximately 6-8 micrometers. The interconnects 122 from the substrate 102 may have a spacing in the range of approximately 8-10 micrometers. In some implementations, the interconnects 122 from the substrate 102 may have a width and spacing (L / S) of approximately 6 micrometers / 8 micrometers. In some implementations, the interconnects 122 from the substrate 102 may have a width and spacing (L / S) of approximately 8 micrometers / 10 micrometers.

[0017]

[0031] The substrate 104 may have a thickness in the range of approximately 90-160 micrometers. The interconnects 142 from the substrate 104 may have a width in the range of approximately 6-8 micrometers. The interconnects 142 from the substrate 104 may have a spacing in the range of approximately 8-10 micrometers. In some implementations, the interconnects 142 from the substrate 104 may have a width and spacing (L / S) of approximately 6 micrometers / 8 micrometers. In some implementations, the interconnects 122 from the substrate 104 may have a width and spacing (L / S) of approximately 8 micrometers / 10 micrometers.

[0018]

[0032] Note that the above dimensions are exemplary: different implementations may have interconnects with different dimensions and / or configurations.

[0019]

[0033] The integrated device 105 (e.g., a second integrated device) is coupled to a second surface (e.g., a top surface) of the substrate 104 via a plurality of solder interconnects 150. For example, the integrated device 105 may be coupled to the plurality of interconnects 142 of the substrate 104 via a plurality of solder interconnects 150. The integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects and / or a plurality of solder interconnects 150. The integrated device 105 may be configured to be electrically coupled to the integrated device 103 via the plurality of solder interconnects 150, the plurality of interconnects 142, the plurality of solder interconnects 114, at least one interconnect die 101 (the plurality of interconnects 112), the plurality of solder interconnects 115, the plurality of interconnects 122, and / or the plurality of solder interconnects 130.

[0020]

[0034] Figure 2 shows a cross-sectional profile view of package 200 including a substrate and high density interconnects. Package 200 is similar to package 100 of Figure 1 and therefore includes the same or similar components as package 100. Package 200 includes at least one interconnect die 201 that has a different configuration, arrangement, and / or design than at least one interconnect die 101 of Figure 1.

[0021]

[0035] The package 200 is coupled to a board 108 via a number of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a number of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0022]

[0036] The package 200 includes at least one interconnect die 201, a substrate 102, a substrate 104, an integrated device 103, an integrated device 105, and an encapsulation layer 106. The at least one interconnect die 201 is coupled to a second surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 114. The substrate 104 (e.g., a second substrate) is coupled to the substrate 102 (e.g., a first substrate) via the at least one interconnect die 201.

[0023]

[0037] At least one interconnect die 201 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 include via interconnects 112b (e.g., vias). In some implementations, the via interconnects 112b of FIG. 2 may have a width and / or diameter of about 100 micrometers. The solder interconnects 114a are coupled to the solder interconnects 114a. The solder interconnects 114a are part of the plurality of solder interconnects 114. The plurality of solder interconnects 114 are coupled to the plurality of die interconnects 112. The via interconnects 112b are coupled to the solder interconnects 115a. The solder interconnects 115a are part of the plurality of solder interconnects 115. At least one interconnect die 201 may be a dummy die. The at least one interconnect die 201 may not include active components. The at least one interconnect die 201 may not include transistors. One expected difference between the at least one interconnect die 201 and the at least one interconnect die 101 is that the at least one interconnect die 201 does not include the pad interconnects 112a and 112c. One advantage of not having the pad interconnects 112a and / or the pad interconnects 112c is that the at least one interconnect die 201 may be thinner than the at least one interconnect die 101, which may help reduce the overall thickness of the package. The at least one interconnect die 201 may be a means for die interconnection.

[0024]

[0038] The pitch of the interconnects between substrate 102 and substrate 104 may be relatively small. For example, the plurality of die interconnects 112 of at least one interconnect die 201 may have a pitch between adjacent die interconnects in the range of approximately 150-270 micrometers. These dimensions are possible through the use of at least one interconnect die 201, which (i) helps provide a thinner package 200 while still being able to accommodate integrated devices between the substrates, and (ii) helps provide interconnects having a small pitch (e.g., 150-270 micrometers) within the encapsulation layer, thus helping to provide high density routing (e.g., high density interconnects) within the encapsulation layer.

[0025]

[0039] The integrated device 105 may be configured to be electrically coupled to the integrated device 103 via a plurality of solder interconnects 150, a plurality of interconnects 142, a plurality of solder interconnects 114, at least one interconnect die 201 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of interconnects 122, and / or a plurality of solder interconnects 130.

[0026]

[0040] As described further below in at least Figures 8 and 9, in some implementations, another package (e.g., a second package) may be coupled to the package described in Figures 1 and 2. Thus, for example, as described further below, a package having an interconnect die may be a package-on-package (PoP) that includes a first package and a second package on top of the first package.

[0027]

[0041] The integrated device (e.g., 103, 105, 805) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. Chiplets may be fabricated using one or more processes that provide better yields compared to other processes used to fabricate other types of integrated devices, which may lower the overall cost of fabricating the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices). Using several chiplets that perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0028]

[0042] The packages (e.g., 100, 200, 800, 900) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The packages (e.g., 100, 200) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 100, 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The packages (e.g., 100, 200) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0029]

[0043] Having described the various interconnect dies, the sequence for fabricating the interconnect dies will now be described below.

[0030] Exemplary Sequence for Fabricating an Interconnect Die

[0044] In some implementations, fabricating an interconnect die includes several processes. Figure 3 shows an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figure 3 may be used to provide or fabricate an interconnect die 201. However, the process of Figure 3 may be used to fabricate any of the interconnect dies (e.g., 101) described in this disclosure.

[0031]

[0045] It should be noted that the sequence of Figure 3 may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0032]

[0046] Stage 1 illustrates the state after preparing the die substrate 110, as shown in FIG. 3. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0033]

[0047] Stage 2 shows the state after multiple cavities 302 have been formed in the die substrate 110. For example, the multiple cavities 302 may be formed through a first surface of the die substrate 110. The multiple cavities 302 may include grooves. The multiple cavities 302 may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the multiple cavities 302.

[0034]

[0048] Stage 3 shows after a metal layer 305 is formed within the plurality of cavities 302 and / or on the first surface of the die substrate 110. The metal layer 305 may include copper. A plating process may be used to form the metal layer 305.

[0035]

[0049] Stage 4 shows the state after a portion of the metal layer 305 has been removed. For example, the portion of the metal layer 305 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 305 remains in the cavities 302. A polishing process may be used to remove the portion of the metal layer 305. The remaining metal from the metal layer 305 located in the cavities 302 may define the interconnects 112b as described in FIGS. 1 and 2.

[0036]

[0050] Stage 5 shows the state after the die substrate 110 has been thinned. For example, a portion (e.g., the bottom) of the die substrate 110 may be removed such that at least the die substrate 110a remains and exposes the bottom side of the metal layer 305. A grinding process may be used to remove the portion of the die substrate 110.

[0037]

[0051] Stage 6 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. In some implementations, stage 6 may show an implementation of interconnected dies that include interconnects and no additional interconnects are formed in, above, or below the die substrate 110.

[0038] Exemplary Sequence for Fabricating an Interconnect Die

[0052] In some implementations, fabricating an interconnect die includes several processes. Figure 4 shows an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figure 4 may be used to provide or fabricate an interconnect die 201. However, the process of Figure 4 may be used to fabricate any of the interconnect dies (e.g., 101) described in this disclosure.

[0039]

[0053] 4 may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0040]

[0054] Stage 1 illustrates the state after preparing the die substrate 110, as shown in FIG. 4. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0041]

[0055] Stage 2 shows the state after multiple cavities 402 have been formed in the die substrate 110. For example, the multiple cavities 402 may be formed through a first surface of the die substrate 110. The multiple cavities 402 may include grooves. The multiple cavities 402 may extend partially through the thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the multiple cavities 402.

[0042]

[0056] Stage 3 shows after a metal layer 405 is formed in the plurality of cavities 402 and / or on the first surface of the die substrate 110. The metal layer 405 may include copper. A filling process may be used to form the metal layer 405, in which a conductive paste may be used to fill the plurality of cavities 402. An additional metal layer 405 may be located on the die substrate 110.

[0043]

[0057] Stage 4 shows the state after a portion of the metal layer 405 has been removed. For example, the portion of the metal layer 405 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 405 remains in the cavities 402. A polishing process may be used to remove the portion of the metal layer 405. The remaining metal from the metal layer 405 located in the cavities 402 may define the interconnects 112b as described in FIGS. 1 and 2.

[0044]

[0058] Stage 5 shows the state after the die substrate 110 has been thinned. For example, a portion (e.g., the bottom) of the die substrate 110 may be removed such that at least the die substrate 110a remains and exposes the bottom side of the metal layer 405. A grinding process may be used to remove the portion of the die substrate 110.

[0045]

[0059] Stage 6 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. In some implementations, stage 6 may show an implementation of interconnected dies that include interconnects and no additional interconnects are formed in, above, or below the die substrate 110.

[0046] Exemplary Sequence for Fabricating an Interconnect Die

[0060] In some implementations, fabricating an interconnect die includes several processes. Figures 5A-5B show an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figures 5A-5B may be used to provide or fabricate an interconnect die 101. However, the process of Figures 5A-5B may be used to fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0047]

[0061] 5A-5B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0048]

[0062] Stage 1, as shown in FIG. 5A, illustrates a state after preparing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0049]

[0063] Stage 2 shows the state after multiple cavities 302 have been formed in the die substrate 110. For example, the multiple cavities 302 may be formed through a first surface of the die substrate 110. The multiple cavities 302 may include grooves. The multiple cavities 302 may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the multiple cavities 302.

[0050]

[0064] Stage 3 shows after a metal layer 305 is formed within the plurality of cavities 302 and / or on the first surface of the die substrate 110. The metal layer 305 may include copper. A plating process may be used to form the metal layer 305.

[0051]

[0065] Stage 4 shows the state after a portion of the metal layer 305 has been removed. For example, the portion of the metal layer 305 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 305 remains in the cavities 302. A polishing process may be used to remove the portion of the metal layer 305. The remaining metal from the metal layer 305 located in the cavities 302 may define the interconnects 112b as described in FIGS. 1 and 2.

[0052]

[0066] Stage 5, as shown in FIG. 5B, depicts the state after metal layer 307 has been formed on the first surface of die substrate 110. A plating process may be used to form metal layer 307. Metal layer 307 may be bonded to metal layer 305. Metal layer 307 may define a plurality of interconnects 112b as described in FIG. 1 and FIG. 2. Metal layer 307 may represent the front-side interconnects of the interconnect die.

[0053]

[0067] Stage 6 shows the die substrate 110 after thinning. For example, a portion (e.g., bottom) of the die substrate 110 may be removed such that at least die substrate 110a remains and the bottom side of metal layer 305 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least die substrate 110a and die substrate 110b remain. If die substrate 110b is present, the bottom side of metal layer 305 is not exposed. A grinding process may be used to remove a portion (e.g., bottom) of the die substrate 110. In some implementations, stage 6 may show an implementation of an interconnect die that includes interconnects and no additional interconnects are formed in, above, or below the die substrate 110. If no additional interconnects are formed, singulation may occur in a manner similar to that described below in stage 8. As described further below, the interconnect die shown in stage 6 may be used to bond to a substrate.

[0054]

[0068] Stage 7 shows the state after metal layer 309 has been formed on the second surface of die substrate 110. A plating process may be used to form metal layer 309. Metal layer 309 may be bonded to metal layer 305. Metal layer 307 may define a plurality of interconnects 112c as described in Figures 1 and 2. Metal layer 309 may represent the backside interconnects of the interconnect die.

[0055]

[0069] Stage 8 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110.

[0056] Exemplary Sequence for Fabricating an Interconnect Die

[0070] In some implementations, fabricating an interconnect die includes several processes. Figures 6A-6B show an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figures 6A-6B may be used to provide or fabricate an interconnect die 101. However, the process of Figures 6A-6B may be used to fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0057]

[0071] 6A-6B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0058]

[0072] Stage 1, as shown in FIG. 6A, illustrates a state after preparing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0059]

[0073] Stage 2 shows the state after multiple cavities 402 have been formed in the die substrate 110. For example, the multiple cavities 402 may be formed through a first surface of the die substrate 110. The multiple cavities 402 may include grooves. The multiple cavities 402 may extend partially through the thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the multiple cavities 402.

[0060]

[0074] Stage 3 shows after a metal layer 405 is formed in the plurality of cavities 402 and / or on the first surface of the die substrate 110. The metal layer 405 may include copper. A filling process may be used to form the metal layer 405, in which a conductive paste may be used to fill the plurality of cavities 402. The metal layer 405 may be located on the die substrate 110.

[0061]

[0075] Stage 4 shows the state after a portion of the metal layer 405 has been removed. For example, the portion of the metal layer 405 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 405 remains in the cavities 402. A polishing process may be used to remove the portion of the metal layer 405. The remaining metal from the metal layer 405 located in the cavities 402 may define the interconnects 112b as described in FIGS. 1 and 2.

[0062]

[0076] Stage 5, as shown in FIG. 6B, depicts the state after metal layer 407 has been formed on the first surface of die substrate 110. A plating process may be used to form metal layer 407. Metal layer 407 may be bonded to metal layer 405. Metal layer 407 may define a plurality of interconnects 112a as described in FIG. 1 and FIG. 2. Metal layer 407 may represent the front-side interconnects of the interconnect die.

[0063]

[0077] Stage 6 shows the die substrate 110 after thinning. For example, a portion (e.g., bottom) of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 405 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least the die substrate 110a and the die substrate 110b remain. If the die substrate 110b is present, the bottom side of the metal layer 405 is not exposed. A grinding process may be used to remove a portion (e.g., bottom) of the die substrate 110. In some implementations, stage 6 may show an implementation of an interconnect die that includes interconnects and no additional interconnects are formed in, above, or below the die substrate 110. If no additional interconnects are formed, singulation may occur in a manner similar to that described below in stage 8. As described further below, the interconnect die shown in stage 6 may be used to bond to a substrate.

[0064]

[0078] Stage 7 shows the state after metal layer 409 has been formed on the second surface of die substrate 110. A plating process may be used to form metal layer 409. Metal layer 409 may be bonded to metal layer 405. Metal layer 409 may define a plurality of interconnects 112c as described in Figures 1 and 2. Metal layer 409 may represent the backside interconnects of the interconnect die.

[0065]

[0079] Stage 8 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110.

[0066] 1 is an exemplary flow diagram of a method for fabricating an interconnect die;

[0080] In some implementations, fabricating an interconnect die includes several processes. Figure 7 shows an example flow diagram of a method 700 for providing or fabricating an interconnect die. In some implementations, the method 700 of Figure 7 may be used to provide or fabricate the interconnect die 101 described in this disclosure. However, the method 700 may be used to provide or fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0067]

[0081] It should be noted that the method 700 of Figure 7 may combine one or more processes to simplify and / or clarify the method for providing or making an interconnect die. In some implementations, the order of the processes may be changed or modified.

[0068]

[0082] The method provides (at 705) a die substrate (e.g., 110). The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface. Step 1 of FIG. 5A illustrates and describes an example of preparing a die substrate. Step 1 of FIG. 6A illustrates and describes an example of preparing a die substrate.

[0069]

[0083] The method forms (at 710) a plurality of cavities (e.g., 302, 402) in the die substrate 110. For example, the plurality of cavities (e.g., 302, 402) may be formed through a first surface of the die substrate 110. The plurality of cavities (e.g., 302, 402) may include grooves. The plurality of cavities (e.g., 302, 402) may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the plurality of cavities (e.g., 302, 402). Step 2 of FIG. 5A illustrates and describes an example of forming a cavity in the die substrate. Step 2 of FIG. 6A illustrates and describes an example of forming a cavity in the die substrate.

[0070]

[0084] The method forms (at 715) a conductive material (e.g., an electrically conductive material) in the plurality of cavities (e.g., 302, 402) of the die substrate 110. The conductive material may include a metal layer (e.g., 305, 405). The conductive material may be formed on a surface of the die substrate 110. The conductive material may include copper. A plating process may be used to form the conductive material. A filling process may be used to form the conductive material. Stage 3 of FIG. 5A illustrates and describes an example of forming the conductive material in the die substrate. Stage 3 of FIG. 6A illustrates and describes an example of forming the conductive material in the die substrate. In some implementations, forming the conductive material may include removing a portion of the conductive material. A polishing process may be used to remove the portion of the conductive material. Removing the portion of the conductive material may include removing a portion of the conductive material bonded to the first surface of the die substrate 110, leaving the conductive material located in the plurality of cavities (e.g., 302, 402) of the die substrate 110. Step 4 of Figure 5A illustrates and describes an example of removing a portion of the conductive material in the die substrate. Step 4 of Figure 6A illustrates and describes an example of removing a portion of the conductive material in the die substrate.

[0071]

[0085] The method optionally forms (at 720) a plurality of front-side interconnects. The front-side interconnects may be bonded to a top side of the die substrate 110. The plurality of front-side interconnects may be defined by a patterned metal layer (e.g., 307, 407) on the top surface of the die substrate 110. A plating process may be used to form the metal layer (e.g., 307, 407). Metal layer 307 may be bonded to metal layer 305. Metal layer 407 may be bonded to metal layer 405. Metal layer 407 may define a plurality of interconnects 112a as described in Figures 1 and 2. Metal layer 407 may represent the front-side interconnects of the interconnect die. The plurality of interconnects 112a may represent the front-side interconnects of the interconnect die. Step 5 of Figure 5B illustrates and describes one example of forming the front-side interconnects. Step 5 of FIG. 6B illustrates and describes one example of forming a front side interconnect.

[0072]

[0086] The method thins (at 725) the die substrate (e.g., 110). Different implementations may thin the die substrate 110 differently. For example, some implementations may thin the die substrate 110 such that the bottom side of the metal layers (e.g., 305, 405) is exposed. Some implementations may thin the die substrate 110 without exposing the bottom side of the metal layers (e.g., 305, 405). A grinding process may be used to remove a portion (e.g., the bottom) of the die substrate 110. Step 6 of FIG. 5B illustrates and describes an example of thinning the die substrate. Step 6 of FIG. 6B illustrates and describes an example of thinning the die substrate.

[0073]

[0087] The method optionally forms (at 730) a plurality of backside interconnects. The backside interconnects may be bonded to a bottom side of the die substrate 110. The plurality of backside interconnects may be defined by a patterned metal layer (e.g., 309, 409) on the bottom surface of the die substrate 110. A plating process may be used to form the metal layer (e.g., 309, 409). The metal layer 309 may be bonded to the metal layer 305. The metal layer 409 may be bonded to the metal layer 405. The metal layer 409 may define the plurality of interconnects 112c as described in FIG. 1 and FIG. 2. The metal layer 409 may represent the backside interconnects of the interconnect die. The plurality of interconnects 112c may represent the backside interconnects of the interconnect die. Step 7 of FIG. 5B illustrates and describes one example of forming the backside interconnects. Step 7 of FIG. 6B illustrates and describes one example of forming backside interconnects.

[0074]

[0088] The method singulates (at 735) the die substrate 110 to form several interconnected dies (e.g., 101, 201). A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. Step 8 in FIG. 5B illustrates and describes one example of singulation. Step 8 in FIG. 6B illustrates and describes one example of singulation.

[0075] Exemplary Package with Interconnect Dies

[0089] FIG. 8 shows a cross-sectional profile view of a package 800 including high density interconnects. The package 800 may include a package-on-package (PoP). The package 800 includes a package 801 and a package 802. The package 801 may be a first package and the package 802 may be a second package. The package 802 is coupled to the package 801 via a plurality of solder interconnects 860. The package 800 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 800 is coupled to a plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0076]

[0090] The package 801 may be similar to the package 100 of FIG. 1. The package 801 may be configured and / or arranged similarly to that described for the package 100 of FIG. 1. The package 801 includes at least one interconnect die 101, a substrate 102, a substrate 104, an integrated device 103, and an encapsulation layer 106. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 (e.g., a first substrate) includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 (e.g., a second substrate) includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 (e.g., a second substrate) is coupled to the substrate 102 (e.g., a first substrate) via the at least one interconnect die 101.

[0077]

[0091] The package 802 includes a substrate 804, an integrated device 805, a number of wire bonds 850, an adhesive 870, and an encapsulation layer 806. The substrate 804 (e.g., a third substrate) includes at least one dielectric layer 840 and a number of interconnects 842. The integrated device 805 is bonded to the substrate 804 by an adhesive 870. The number of wire bonds 850 are bonded to the integrated device 805 and to the number of interconnects 842 of the substrate 804. The integrated device 805 may include a memory die. In some implementations, there may be several integrated devices 805 stacked on top of each other. The encapsulation layer 806 encapsulates the integrated device 805 and the number of wire bonds 850. The encapsulation layer 806 is bonded to the substrate 804 and the integrated device 805. The encapsulation layer 806 is located above the substrate 804 and the integrated device 805. The encapsulation layer 806 may include a mold, a resin, and / or an epoxy. The encapsulation layer 806 may be a means for encapsulation. The encapsulation layer 806 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 806 may be similar or the same as the encapsulation layer 106.

[0078]

[0092] The integrated device 805 may be configured to be electrically coupled to the integrated device 103 via a plurality of wire bonds 850, a plurality of interconnects 842, a plurality of solder interconnects 860, a plurality of interconnects 142, a plurality of solder interconnects 114, at least one interconnect die 101 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of interconnects 122, and / or a plurality of solder interconnects 130.

[0079]

[0093] FIG. 9 shows a cross-sectional profile view of a package 900 including high density interconnects. The package 900 may include a package-on-package (PoP). The package 800 includes a package 901 and a package 802. The package 901 may be a first package and the package 802 may be a second package. The package 802 is coupled to the package 901 via a plurality of solder interconnects 860. The package 900 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 900 is coupled to a plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0080]

[0094] The package 901 may be similar to the package 200 of FIG. 2. The package 901 may be configured and / or arranged similarly to that described for the package 200 of FIG. 2. The package 901 includes at least one interconnect die 201, a substrate 102, a substrate 104, an integrated device 103, and an encapsulation layer 106. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 (e.g., a first substrate) includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 (e.g., a second substrate) includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface). The substrate 104 (e.g., a second substrate) is coupled to the substrate 102 (e.g., a first substrate) via the at least one interconnect die 101.

[0081]

[0095] The package 802 includes a substrate 804, an integrated device 805, a number of wire bonds 850, an adhesive 870, and an encapsulation layer 806. The substrate 804 (e.g., a third substrate) includes at least one dielectric layer 840 and a number of interconnects 842. The integrated device 805 is bonded to the substrate 804 by an adhesive 870. The number of wire bonds 850 are bonded to the integrated device 805 and to the number of interconnects 842 of the substrate 804. The integrated device 805 may include a memory die. In some implementations, there may be several integrated devices 805 stacked on top of each other. The encapsulation layer 806 encapsulates the integrated device 805 and the number of wire bonds 850. The encapsulation layer 806 is bonded to the substrate 804 and the integrated device 805. The encapsulation layer 806 is located above the substrate 804 and the integrated device 805. The encapsulation layer 806 may include a mold, a resin, and / or an epoxy. The encapsulation layer 806 may be a means for encapsulation. The encapsulation layer 806 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 806 may be similar or the same as the encapsulation layer 106.

[0082]

[0096] The integrated device 805 may be configured to be electrically coupled to the integrated device 103 via a plurality of wire bonds 850, a plurality of interconnects 842, a plurality of solder interconnects 860, a plurality of interconnects 142, a plurality of solder interconnects 114, at least one interconnect die 201 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of interconnects 122, and / or a plurality of solder interconnects 130.

[0083] Exemplary Sequence for Making a Package with a Substrate and Interconnecting Dies

[0097] In some implementations, making a package includes several processes. Figures 10A-10B show an example sequence for providing or making a package. In some implementations, the sequence of Figures 10A-10B may be used to provide or make package 100. However, the process of Figures 10A-10B may be used to make any of the packages described in this disclosure (e.g., 200, 800, 801, 802, 900, 901).

[0084]

[0098] 10A-10B may combine one or more steps to simplify and / or clarify the sequence for providing or making a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0085]

[0099] As shown in FIG. 10A, stage 1 illustrates the state after preparing a substrate 102. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be fabricated using the methods described in FIGS. 12A-12B. In some implementations, a core substrate (e.g., a substrate including a core layer) is prepared.

[0086]

[0100] Stage 2 illustrates a state after the integrated device 103 is bonded to a second surface (e.g., a top surface) of the substrate 102. The integrated device 103 may be bonded to the substrate 102 via a plurality of solder interconnects 130. A solder reflow process may be used to bond the integrated device 103 to the substrate 102. Stage 2 also illustrates a state after at least one interconnect die 101 is bonded to the second surface of the substrate 102. The at least one interconnect die 101 may be bonded to the substrate 102 via a plurality of solder interconnects 115. A solder reflow process may be used to bond the at least one interconnect die 101 to the substrate 102.

[0087]

[0101] Stage 3 shows the state after the substrate 104 is bonded to the at least one interconnect die 101. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 104 may be fabricated using the method described in FIGS. 12A-12B. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided. The at least one interconnect die 101 may be bonded to the substrate 104 via a plurality of solder interconnects 114. A solder reflow process may be used to bond the substrate 104 to the at least one interconnect die 101. The integrated device 103 and the at least one interconnect die 101 may be located between the substrate 102 and the substrate 104. The substrate 104 may be bonded to the substrate 102 via the at least one interconnect die 101.

[0088]

[0102] Stage 4 shows the state after an encapsulation layer 106 is provided between the substrate 102 and the substrate 104. The encapsulation layer 106 may encapsulate the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may be bonded to the second surface of the substrate 102 and the first surface of the substrate 104. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0089]

[0103] 10B, after the plurality of solder interconnects 117 have been bonded to the substrate 102. The plurality of solder interconnects 117 may be bonded to a first surface (e.g., a bottom surface) of the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 117 to the plurality of interconnects 122 of the substrate 102.

[0090]

[0104] Stage 6 shows the state after integrated device 105 has been bonded to the second surface (e.g., top surface) of substrate 104. A solder reflow process may be used to bond the integrated device and / or passive devices to substrate 104. Note that instead of an integrated device, another package, such as package 802, may be bonded to the second surface (e.g., top surface) of substrate 104.

[0091] 1 is an exemplary flow diagram of a method for making a package with a substrate and an interconnect die;

[0105] In some implementations, producing a package includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or producing a package. In some implementations, the method 1100 of Figure 11 can be used to provide or produce the package 100 described in this disclosure. However, the method 1100 can be used to provide or produce any of the packages described in this disclosure (e.g., 200, 800, 801, 802, 900, 901).

[0092]

[0106] It should be noted that the method 1100 of Figure 11 may combine one or more processes to simplify and / or clarify the method for providing or making a package. In some implementations, the order of the processes may be changed or modified.

[0093]

[0107] The method includes (at 1105) preparing a substrate (e.g., 102). The substrate 102 may be a first substrate. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be fabricated using the methods described in Figures 12A-12B. In some implementations, a core substrate (e.g., a substrate including a core layer) is prepared. Step 1 of Figure 10A illustrates and describes one example of preparing a substrate.

[0094]

[0108] The method (at 1110) bonds an integrated device (e.g., 103) and at least one interconnect die (e.g., 101, 201) to a second surface (e.g., top surface) of the substrate 102. The integrated device 103 may be bonded to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be bonded to the substrate 102 via a plurality of pillar interconnects and / or a plurality of solder interconnects 130. A solder reflow process may be used to bond the integrated device 103 to the substrate 102. The at least one interconnect die 101 may be bonded to the substrate 102 via a plurality of solder interconnects 115. A solder reflow process may be used to bond the at least one interconnect die 101 to the substrate 102. Stage 2 of FIG. 10A illustrates and describes one example of bonding an integrated device and an interconnect die to a substrate.

[0095]

[0109] The method includes (at 1115) bonding a substrate (e.g., 104) to a substrate (e.g., 102) via at least one interconnect die (e.g., 101, 201). The substrate 104 may be a second substrate. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 104 may be fabricated using the method described in FIGS. 12A-12B. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided. The substrate 104 may be bonded to the at least one interconnect die 101 via a plurality of solder interconnects 114. The substrate 104 may be bonded to the substrate 102 via the at least one interconnect die 101 such that the at least one interconnect die 101 and the integrated device 103 are located between the substrate 102 and the substrate 104. Step 3 of FIG. 10A illustrates and describes one example of bonding a substrate to another substrate via an interconnect die.

[0096]

[0110] The method forms (at 1120) an encapsulation layer (e.g., 106) between the substrate 102 and the substrate 104. The encapsulation layer 106 may encapsulate the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may be bonded to a second surface of the substrate 102. The encapsulation layer 106 may be bonded to a first surface of the substrate 104. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Step 4 of FIG. 10A illustrates and describes one example of providing an encapsulation layer.

[0097]

[0111] The method bonds (at 1125) a plurality of solder interconnects (e.g., 117) to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 117 to the first surface of the substrate 102. Step 5 of Figure 10B illustrates and describes one example of bonding the solder interconnects to a substrate.

[0098]

[0112] The method then couples (at 1130) an integrated device (e.g., 105) to the second surface (e.g., top surface) of the substrate 104. A solder reflow process may be used to couple the integrated device and / or passive devices to the substrate 104. Note that instead of the integrated device, another package, such as package 802, may be coupled to the second surface (e.g., top surface) of the substrate 104. Step 6 of FIG. 10B illustrates and describes one example of coupling an integrated device to a substrate.

[0099]

[0113] In some implementations, several packages are made simultaneously. In such cases, the method may singulate the packages (e.g., 100, 200, 800, 801, 802, 900, 902).

[0100] Exemplary Sequence for Preparing a Substrate

[0114] In some implementations, fabricating a substrate includes several processes. Figures 12A-12B show an example sequence for providing or fabricating a substrate. In some implementations, the sequence of Figures 12A-12B may be used to provide or fabricate a substrate 102. However, the process of Figures 12A-12B may be used to fabricate any of the substrates described in this disclosure (e.g., 104, 804).

[0101]

[0115] 12A-12B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0102]

[0116] Stage 1 illustrates the state after preparing carrier 1200, as shown in FIG. 12A. A seed layer 1201 and interconnects 1202 may be located on carrier 1200. Interconnects 1202 may be located on seed layer 1201. A plating process and an etching process may be used to form interconnects 1202. In some implementations, carrier 1200 may be provided with seed layer 1201 and a metal layer patterned to form interconnects 1202. Interconnects 1202 may represent at least some of the interconnects from the plurality of interconnects 122.

[0103]

[0117] Stage 2 shows the state after dielectric layer 1220 is formed over carrier 1200, seed layer 1201, and interconnects 1202. A deposition process and / or lamination process may be used to form dielectric layer 1220. Dielectric layer 1220 may include prepreg and / or polyimide. Dielectric layer 1220 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0104]

[0118] Stage 3 shows the state after a number of cavities 1210 have been formed in the dielectric layer 1220. The number of cavities 1210 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0105]

[0119] Stage 4 shows the state after interconnects 1212 have been formed in and on dielectric layer 1220, including in and over multiple cavities 1210. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0106]

[0120] Stage 5 shows the state after dielectric layer 1222 is formed over dielectric layer 1220 and interconnects 1212. A deposition process and / or lamination process may be used to form dielectric layer 1222. Dielectric layer 1222 may include prepreg and / or polyimide. Dielectric layer 1222 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0107]

[0121] 12B, stage 6 shows the state after a number of cavities 1230 have been formed in the dielectric layer 1222. The number of cavities 1230 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0108]

[0122] Stage 7 shows the state after interconnects 1214 have been formed in and on dielectric layer 1222, including in and over multiple cavities 1230. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0109]

[0123] Stage 8 depicts the state after carrier 1200 has been separated (e.g., detached, removed, ground) from at least one dielectric layer 120 and seed layer 1201, and a portion of seed layer 1201 has been removed (e.g., etched away), leaving substrate 102 including at least one dielectric layer 120 and a plurality of interconnects 122. At least one dielectric layer 120 may represent dielectric layer 1220 and / or dielectric layer 1222. A plurality of interconnects 122 may represent interconnects 1202, 1212, and / or 1214.

[0110]

[0124] Different implementations may use different processes to form the metal layer(s) and / or the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0111] 1 is an exemplary flow diagram of a method for fabricating a substrate;

[0125] In some implementations, producing a substrate includes several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or producing a substrate. In some implementations, the method 1300 of Figure 13 can be used to provide or produce a substrate(s) of the present disclosure. For example, the method 1300 of Figure 13 can be used to produce the substrate 102.

[0112]

[0126] It should be noted that the method 1300 of Figure 13 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0113]

[0127] The method provides (at 1305) a carrier (e.g., 1200). Different implementations can use different materials for the carrier 1200. The carrier 1200 can include a seed layer (e.g., 1201). The seed layer 1201 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 12A illustrates and describes one example of a carrier having a seed layer provided thereon.

[0114]

[0128] The method forms and patterns (at 1310) interconnects on the carrier 1200 and the seed layer 1201. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer overlies the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 122). Step 1 of FIG. 12A illustrates and describes one example of forming and patterning interconnects on a seed layer and a carrier.

[0115]

[0129] The method forms / provides (at 1315) a dielectric layer 1220 over the seed layer 1201, the carrier 1200, and the interconnects 1202. A deposition process and / or a lamination process may be used to form the dielectric layer 1220. The dielectric layer 1220 may include prepreg and / or polyimide. The dielectric layer 1220 may include a photoimageable dielectric. Forming the dielectric layer 1220 may also include forming a plurality of cavities (e.g., 1210) in the dielectric layer 1220. The plurality of cavities may be formed using an etching process (e.g., a photoetching process) or a laser process. Steps 2-3 of FIG. 12A illustrate and describe one example of forming a dielectric layer and cavities in the dielectric layer.

[0116]

[0130] The method forms (at 1320) interconnects in and on the dielectric layer. For example, interconnects 1212 may be formed in and on dielectric layer 1220. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 12A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0117]

[0131] The method forms / provides (at 1325) a dielectric layer 1222 over the dielectric layer 1220 and the interconnects 1212. A deposition process and / or lamination process may be used to form the dielectric layer 1222. The dielectric layer 1222 may include prepreg and / or polyimide. The dielectric layer 1222 may include a photoimageable dielectric. Forming the dielectric layer 1222 may also include forming a plurality of cavities (e.g., 1230) in the dielectric layer 1222. The plurality of cavities may be formed using an etching process (e.g., a photoetching process) or a laser process. Steps 5-6 of Figures 12A-12B illustrate and describe one example of forming a dielectric layer and cavities in the dielectric layer.

[0118]

[0132] The method forms (at 1330) interconnects in and on the dielectric layer. For example, interconnects 1214 may be formed in and on dielectric layer 1222. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Forming the interconnects may include forming post interconnects. Step 7 of FIG. 12B illustrates and describes one example of forming interconnects in and on the dielectric layer, including forming post interconnects.

[0119]

[0133] The method separates (at 1335) the carrier (e.g., 1200) from the seed layer (e.g., 1201). The carrier 1200 may be removed and / or ground. The method may also remove (at 1335) a portion of the seed layer (e.g., 1201). An etching process may be used to remove the portion of the seed layer 1201. Step 8 of FIG. 12B illustrates and describes an example of carrier separation and seed layer removal.

[0120]

[0134] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0121] Exemplary Electronic Devices

[0135] FIG. 14 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an autonomous vehicle 1410 may include a device 1400 as described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely examples. Other electronic devices may also be equipped with device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, portable data units such as handheld personal communication system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0122]

[0136] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5B, 6A-6B, 7-9, 10A-10B, 11, 12A-12B, and 13-14 may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It is also noted that Figures 1-4, 5A-5B, 6A-6B, 7-9, 10A-10B, 11, 12A-12B, and 13-14 in this disclosure and their corresponding descriptions are not limited to dies and / or ICs. In some implementations, Figures 1-4, 5A-5B, 6A-6B, 7-9, 10A-10B, 11, 12A-12B, and 13-14 and corresponding descriptions thereof can be used to manufacture, construct, provide, and / or produce a device and / or an integrated device. In some implementations, a device can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0123]

[0137] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0124]

[0138] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even if they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. Use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component "over" a second component can mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be above (e.g., above) a first surface of a second component, and a third component can be above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being above another component, the term "over" as used in this application can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on the second component (e.g., on the surface of the second component), and / or (3) that the first component is present within the second component (e.g., embedded within the second component). A first component that is "in" a second component can be partially located within the second component or completely located within the second component. A value that is about X to XX can mean a value between and including X and XX. The value or values ​​between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0125]

[0139] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form the interconnects.

[0126]

[0140] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0127]

[0141] Further examples are described below to facilitate understanding of the present disclosure.

[0128]

[0142] Aspect 1: A package comprising a first substrate, a first integrated device coupled to the first substrate, an interconnect die coupled to the first substrate, a second substrate coupled to the first substrate via the interconnect die, where the first integrated device and the interconnect die are located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate, where the encapsulation layer is located between the first substrate and the second substrate.

[0129]

[0143] Aspect 2: The package of aspect 1, wherein the interconnected die comprises a die substrate and a plurality of die interconnects.

[0130]

[0144] Example 3: The package of example 2, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0131]

[0145] Aspect 4: The package of aspects 2-3, wherein the interconnect die has a thickness in the range of about 100-200 micrometers.

[0132]

[0146] Aspect 5: The package of Aspects 2-4, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0133]

[0147] Embodiment 6: The package of embodiments 2-5, wherein the die substrate comprises glass and / or silicon.

[0134]

[0148] Aspect 7: The package of aspects 1-6, further comprising a second integrated device coupled to the second substrate, the first integrated device including the first chiplet and the second integrated device including the second chiplet.

[0135]

[0149] Embodiment 8: The package of embodiments 1-7, wherein the interconnect die is located laterally of the first integrated device.

[0136]

[0150] Embodiment 9: The package according to embodiments 1 to 8, wherein the package is a package-on-package (PoP).

[0137]

[0151] Embodiment 10: The package of embodiments 1-9, wherein the interconnect die does not include a transistor.

[0138]

[0152] Aspect 11: A device comprising a first package, the first package comprising: a first substrate, a first integrated device coupled to the first substrate, a means for die interconnection coupled to the first substrate, a second substrate coupled to the first substrate via the means for die interconnection, where the first integrated device and the means for die interconnection are located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate, where the encapsulation layer is located between the first substrate and the second substrate.

[0139]

[0153] Example 12: A device as described in example 11, wherein the means for die interconnection comprises a die substrate and a plurality of die interconnects.

[0140]

[0154] Example 13: The device of example 2, wherein twelve adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0141]

[0155] Embodiment 14: The device of embodiments 12-13, wherein the interconnect die has a thickness in the range of about 100-200 micrometers.

[0142]

[0156] Example 15: A device according to any one of Examples 12 to 14, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

[0143]

[0157] Example 16: The device of Examples 12-15, wherein the die substrate comprises glass and / or silicon.

[0144]

[0158] Embodiment 17: A device according to embodiments 11 to 16, wherein the means for die interconnection is located laterally of the first integrated device.

[0145]

[0159] Aspect 18: The device of aspects 11 to 17, further comprising a second package coupled to the first package via a plurality of solder interconnects, the second package comprising a third substrate, a second integrated device coupled to the third substrate, and a second encapsulation layer coupled to the third substrate and the second integrated device.

[0146]

[0160] Embodiment 19: The device of embodiments 11 to 18, wherein the means for die interconnection does not include a transistor.

[0147]

[0161] Aspect 20: The device described in aspects 11 to 19, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0148]

[0162] Aspect 21: A method of making a package, the method including: preparing a first substrate having a first surface and a second surface; bonding a first integrated device to the second surface of the first substrate; bonding an interconnect die to the second surface of the first substrate; bonding a second substrate to the first substrate via the interconnect die, the second substrate having a first surface and a second surface; and forming an encapsulation layer between the first substrate and the second substrate.

[0149]

[0163] Example 22: The method of example 21, further comprising bonding a second integrated device to a second surface of the second substrate.

[0150]

[0164] Example 23: The method of example 21, further comprising bonding a second package to a second surface of the second substrate via a plurality of solder interconnects, the second package comprising a third substrate, a second integrated device bonded to the third substrate, and a second encapsulation layer bonded to the third substrate and the second integrated device.

[0151]

[0165] Example 24: The method of Examples 21-23, wherein the interconnected die comprises a die substrate and a plurality of die interconnects.

[0152]

[0166] Example 25: The method of example 24, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0153]

[0167] Example 26: The method of example 24-25, wherein the interconnect die has a thickness in the range of about 100-200 micrometers.

[0154]

[0168] Example 27: The method of any one of Examples 24 to 26, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0155]

[0169] Various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. The first substrate and A first integrated device coupled to the first substrate, An interconnect die coupled to the first substrate, wherein the interconnect die is die substrate and Multiple die interconnection sections, The plurality of die interconnection sections include via die interconnection sections and pad die interconnection sections, and A second substrate bonded to the first substrate via the interconnect die, wherein the first integrated device and the interconnect die are located between the first substrate and the second substrate. An encapsulation layer bonded to the first substrate and the second substrate, the encapsulation layer located between the first substrate and the second substrate, A package that includes the following features.

2. The package according to claim 1, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

3. The package according to claim 1, wherein the interconnecting die has a thickness in the range of about 100 to 200 micrometers.

4. The package according to claim 1, wherein the die substrate includes glass and / or silicon.

5. The package according to claim 1, further comprising a second integrated device coupled to the second substrate, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

6. The package according to claim 1, wherein the interconnection die is located laterally to the first integrated device.

7. The package according to claim 1, wherein the package is a package-on-a-package (PoP).

8. The package according to claim 1, wherein the interconnect die does not include a transistor.

9. A method for creating a package, A first substrate having a first surface and a second surface is prepared, The first integrated device is bonded to the second surface of the first substrate, The method involves bonding an interconnecting die to the second surface of the first substrate, wherein the interconnecting die is die substrate and Multiple die interconnection sections and The plurality of die interconnections include via die interconnections and pad die interconnections, and are connected. The method involves bonding the second substrate to the first substrate via the interconnecting die, wherein the second substrate comprises a first surface and a second surface. Forming an encapsulation layer between the first substrate and the second substrate, Methods that include...

10. The method according to claim 9, further comprising bonding a second integrated device to the second surface of the second substrate.

11. The method further includes bonding a second package to the second surface of the second substrate via a plurality of solder interconnections, wherein the second package The third substrate and The second integrated device coupled to the third substrate, The third substrate and the second encapsulation layer coupled to the second integrated device, The method according to claim 9, comprising:

12. The method according to claim 9, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 to 270 micrometers.

13. The method according to claim 9, wherein the interconnecting die has a thickness in the range of about 100 to 200 micrometers.

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