PACKAGE HAVING INTERCONNECT DIE POSITIONED BETWEEN METALLIZATION PORTIONS - Patent application

Abstract

A package comprising a first metallization portion (102), a first integrated device (103), an interconnect die (110), a second metallization portion (104), and an encapsulation layer (106). The first metallization portion (102) includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device (103) is coupled to the first metallization portion. The interconnect die is coupled to the first metallization portion. A second metallization portion coupled to the first metallization portion via the interconnect die, where the first integrated device and the interconnect die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a first plurality of second metallization interconnects. An encapsulation layer coupled to the first metallization portion and the second metallization portion, the encapsulation layer being located between the first metallization portion and the second metallization portion.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 742,001, filed in the United States Patent Office on May 11, 2022, the entire contents of which are incorporated by reference herein as if fully set forth in their entirety below and for all applicable purposes.

[0002] Various features relate to a package having a metallization portion and an integrated device. [Background technology]

[0003] A package may include a substrate and an integrated device. These components are bonded together to provide a package that can perform various electrical functions. There is a continuing need to provide better performing packages and reduce the overall size of the package. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to a package having a metallization portion and an integrated device.

[0005] One embodiment provides a package including a first metallization portion, a first integrated device, an interconnect die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least a first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnect die is coupled to the first metallization portion. A second metallization portion coupled to the first metallization portion via the interconnect die, the first integrated device and the interconnect die being located between the first metallization portion and the second metallization portion. The second metallization portion includes at least a second dielectric layer and a plurality of second metallization interconnects. An encapsulation layer coupled to the first metallization portion and the second metallization portion, the encapsulation layer being located between the first metallization portion and the second metallization portion.

[0006] Another embodiment provides a device including a first package. The first package includes a first metallization portion, a first integrated device, a means for die interconnection, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least a first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The means for die interconnection is coupled to the first metallization portion. A second metallization portion coupled to the first metallization portion via the means for die interconnection, the first integrated device and the means for interconnection being located between the first metallization portion and the second metallization portion. The second metallization portion includes at least a second dielectric layer and a plurality of second metallization interconnects. An encapsulation layer coupled to the first metallization portion and the second metallization portion, the encapsulation layer being located between the first metallization portion and the second metallization portion.

[0007] Another embodiment provides a method for making a package. The method provides a first metallization portion. The method couples a first integrated device to the first metallization portion. The method couples an interconnect die to the first metallization portion. The method forms an encapsulation layer over the first metallization portion, the first integrated device, and the interconnect die. The method forms a second metallization portion over the encapsulation layer such that the second metallization portion is coupled to the first metallization portion through the interconnect die.

[0008] Various features, nature and advantages may become apparent from the following detailed description when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates an exemplary cross-sectional profile view of a package including a metallization portion and at least one interconnect die. [Diagram 2] 1 illustrates an exemplary cross-sectional profile view of a package including a metallization portion and at least one interconnect die. [Diagram 3] 1 illustrates an exemplary cross-sectional profile view of a package including at least one interconnect die. [Figure 4] 1 illustrates an exemplary cross-sectional profile view of a package including at least one interconnect die. [Diagram 5] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 6] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 7A] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 7B] 1 illustrates an exemplary sequence for fabricating an interconnect die. [Figure 8A] 1A-1C illustrate an exemplary sequence for fabricating an interconnect die. [Figure 8B] 1A-1C illustrate an exemplary sequence for fabricating an interconnect die. [Figure 9] 1 illustrates an exemplary flow chart of a method for fabricating an interconnect die. [Figure 10A] 1 illustrates an exemplary sequence for creating a package including metallization and interconnect die. [Figure 10B] 1 illustrates an exemplary sequence for creating a package including metallization and interconnect die. [Figure 11] 1 shows an exemplary flow chart of a method for making a package including a metallization portion and an interconnect die. [Figure 12A] 4 shows an exemplary sequence for fabricating a metallization portion. [Figure 12B]4 shows an exemplary sequence for fabricating a metallization portion. [Figure 13] 1 shows an exemplary flow chart of a method for fabricating a metallization portion. [Figure 14] Illustrated are various electronic devices that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a first metallization portion, a first integrated device, an interconnect die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least a first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnect die is coupled to the first metallization portion. A second metallization portion coupled to the first metallization portion via the interconnect die, the first integrated device and the interconnect die being located between the first metallization portion and the second metallization portion. The second metallization portion includes at least a second dielectric layer and a plurality of second metallization interconnects. An encapsulation layer coupled to the first metallization portion and the second metallization portion, the encapsulation layer being located between the first metallization portion and the second metallization portion. The first metallization portion may include a first redistribution portion comprising a plurality of first redistribution interconnects. The second metallization portion may include a second redistribution portion comprising a plurality of second redistribution interconnects. A second integrated device may be coupled to a first side of the second metallization portion. A second package may be coupled to a first side of the second metallization portion. The second package may include a substrate, a second integrated device coupled to the substrate, and a second encapsulation layer coupled to the substrate and the second integrated device. As described further below, the package provides interconnects having a high aspect ratio and high density interconnects, which helps provide improved package performance while keeping the package small and thin.

[0012] Exemplary Package with Interconnect Dies 1 shows a cross-sectional profile view of a package 100 including metallization and high density interconnects. The package 100 may include a package on package (PoP). The package 100 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 100 is coupled to the plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0013] The package 100 includes at least one interconnect die 101, a metallization portion 102, a metallization portion 104, an integrated device 103, an integrated device 105, and an encapsulation layer 106. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 (e.g., a second metallization portion) is configured to be coupled (e.g., electrically coupled) to the metallization portion 102 (e.g., a first metallization portion) via the at least one interconnect die 101.

[0014] The metallization portion 102 may include a redistribution portion (e.g., a first redistribution portion). The metallization portion 102 may include a first side and a second side. The first side may be a front side and the second side may be a back side. The plurality of metallization interconnects 122 may include a plurality of redistribution interconnects (e.g., a plurality of first redistribution interconnects). The metallization portion 102 may be a front metallization portion (e.g., a front redistribution portion) of the package 100. The metallization portion 102 may be a means for metallization interconnection (e.g., a means for front metallization interconnection).

[0015] The metallization portion 104 may include a redistribution portion (e.g., a second redistribution portion). The metallization portion 104 may include a first side and a second side. The first side may be a front side and the second side may be a back side. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects (e.g., a plurality of second redistribution interconnects). The metallization portion 104 may be a backside metallization portion (e.g., a backside redistribution portion) of the package 100. The metallization portion 104 may be a means for metallization interconnection (e.g., a means for backside metallization interconnection).

[0016] As discussed above, the metallization portions (e.g., 102, 104) may include redistribution portions that include redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The redistribution interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnects and / or redistribution interconnects. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have top and bottom portions. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0017] The integrated device 103 (e.g., a first integrated device) is coupled to a first side (e.g., a front side) of the metallization portion 102 via a plurality of solder interconnects 130. There may or may not be a plurality of pillar interconnects between the integrated device 103 and the plurality of solder interconnects 130. Thus, the integrated device 103 may be coupled to the metallization portion 102 via a plurality of pillar interconnects and a plurality of solder interconnects 130. An underfill 132 may be located between the integrated device 103 and the metallization portion 102. The at least one interconnect die 101 may be coupled to the first side of the metallization portion 102 via a plurality of solder interconnects 115. As described further below, the at least one interconnect die 101 may be configured to provide high aspect ratio interconnects and / or high density interconnects for the package 100. The encapsulation layer 106 may be coupled to a first side (e.g., front side) of the metallization portion 102 and a second side (e.g., back side) of the metallization portion 104. The encapsulation layer 106 may encapsulate (e.g., partially or completely) the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 106 is located between the metallization portion 102 and the metallization portion 104. The at least one interconnect die 101 is located between the metallization portion 102 and the metallization portion 104. The integrated device 103 is located between the metallization portion 102 and the metallization portion 104. The integrated device 103 may include a front side and a back side. The front side of the integrated device 103 may face the metallization portion 102. The back side of the integrated device 103 may face the metallization portion 104. The back side of the integrated device 103 may be covered by an encapsulation layer 106. In some implementations, the back side (e.g., backside surface) of the integrated device 103 may remain exposed (e.g., not covered by the encapsulation layer 106).The at least one interconnect die 101 is located laterally of the integrated device 103. The at least one interconnect die 101 may laterally surround the integrated device 103.

[0018] At least one interconnect die 101 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 include a pad interconnect 112a (e.g., a pad), a via interconnect 112b (e.g., a via), and a pad interconnect 112c (e.g., a pad). The pad interconnect 112a is coupled to the via interconnect 112b. The via interconnect 112b is coupled to the pad interconnect 112c. The pad interconnect 112c is coupled to a solder interconnect 115a. The solder interconnect 115a is part of the plurality of solder interconnects 115.

[0019] The plurality of metallization interconnects 142 from the metallization portion 104 may be coupled to the plurality of die interconnects 112 of at least one interconnect die 101 such that solder interconnects are not required between the interconnect die 101 and the metallization portion 104. That is, the plurality of metallization interconnects 142 may be coupled to the plurality of die interconnects 112 without requiring or using solder interconnects. Thus, the coupling between an interconnect from the plurality of metallization interconnects 142 and a die interconnect (e.g., 112a) from the plurality of die interconnects 112 may be free of solder interconnects.

[0020] At least one interconnect die 101 may include a dummy die. At least one interconnect die 101 may not include active components. At least one interconnect die 101 may not include transistors. At least one interconnect die 101 may be a means for interconnecting die.

[0021] The aspect ratio (e.g., height to width ratio, height to diameter ratio) of the interconnects between metallization portions 102 and 104 can be very high. For example, in some implementations, the die interconnects 112 can have an aspect ratio in the range of about 20:1 to 10:1. In one embodiment, die interconnects 112b can have an aspect ratio in the range of about 20:1 to 10:1. In another embodiment, the combination of die interconnects 112a, die interconnects 112b, and / or die interconnects 112c can have an aspect ratio in the range of about 20:1 to 10:1. The high aspect ratio helps provide high density interconnects when integrated devices are present between metallization portions 102 and 104. Additionally, the pitch of the interconnects between metallization portions 102 and 104 can be relatively small. For example, the multiple die interconnects 112 may have a pitch between adjacent die interconnects in the range of about 80-270 micrometers. These dimensions are possible through the use of at least one interconnect die 101, which (i) helps provide a thinner package 100 while still being able to accommodate an integrated device 103 between two metallization portions, and (ii) helps provide interconnects with a small pitch (e.g., 80-270 micrometers) within the encapsulation layer, and thus helps provide high density routing (e.g., high density interconnects) within the encapsulation layer. The pad interconnects 112c may have a diameter and / or width of about 20-90 micrometers. The pad interconnects 112b may have a height of about 50-500 micrometers. The pad interconnects 112a may have a diameter and / or width of about 20-90 micrometers. The pad interconnects 112a may have a thickness of about 5-15 micrometers. The encapsulation layer 106 may have a thickness of about 70-500 micrometers. The spacing between the surfaces of the metallization portions 102 and 104 may be equal to the thickness of the encapsulation layer 106. Note that the above dimensions are exemplary. Different implementations may have interconnects with different dimensions and / or configurations.The above example dimensions and / or values ​​may be applicable to other packages described in this disclosure.

[0022] The integrated device 105 (e.g., a second integrated device) is coupled to a first side (e.g., a front side) of the metallization portion 104 via a plurality of solder interconnects 150. For example, the integrated device 105 may be coupled to a plurality of metallization interconnects 142 of the metallization portion 104 via a plurality of solder interconnects 150. There may or may not be a plurality of pillar interconnects between the integrated device 105 and the plurality of solder interconnects 150. The integrated device 103 may be coupled to the metallization portion 104 via a plurality of pillar interconnects and / or a plurality of solder interconnects 150. The integrated device 105 may be configured to be electrically coupled to the integrated device 103 via a plurality of solder interconnects 150, a plurality of metallization interconnects 142, at least one interconnect die 101 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of metallization interconnects 122, and / or a plurality of solder interconnects 130.

[0023] 2 illustrates a cross-sectional profile view of package 200 including metallization portions and high density interconnects. Package 200 is similar to package 100 of FIG. 1 and therefore includes the same or similar components as package 100. Package 200 includes at least one interconnect die 201 having a different configuration, arrangement, and / or design than at least one interconnect die 101 of FIG.

[0024] The package 200 is coupled to a board 108 via a number of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a number of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0025] Package 200 includes at least one interconnect die 201, a metallization portion 102, a metallization portion 104, an integrated device 103, an integrated device 105, and an encapsulation layer 106. The at least one interconnect die 201 is coupled to a first side (e.g., the front side) of the metallization portion 102. The metallization portion 104 (e.g., the second metallization portion) is configured to be coupled (e.g., electrically coupled) to the metallization portion 102 (e.g., the first metallization portion) via the at least one interconnect die 201.

[0026] The at least one interconnect die 201 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 includes via interconnects 112b (e.g., vias). In some implementations, the via interconnects 112b of FIG. 2 may have a width and / or diameter of about 100 micrometers. The via interconnects 112b are coupled to solder interconnects 115a. The solder interconnects 115a are part of a plurality of solder interconnects 115.

[0027] A plurality of metallization interconnects 142 from the metallization portion 104 may be coupled to the plurality of die interconnects 112 of the at least one interconnect die 101 such that no solder interconnects are required between the interconnect die 101 and the metallization portion 104. That is, the plurality of metallization interconnects 142 may be coupled to the plurality of die interconnects 112 without requiring or using solder interconnects. Thus, no solder interconnects may be present in the connection between the interconnects from the plurality of metallization interconnects 142 and the die interconnects (e.g., 112b) from the plurality of die interconnects 112.

[0028] The at least one interconnect die 201 may be a dummy die. The at least one interconnect die 201 may not include active components. The at least one interconnect die 201 may not include transistors. One expected difference between the at least one interconnect die 201 and the at least one interconnect die 101 is that the at least one interconnect die 201 does not include the pad interconnects 112a and 112c. One advantage of not having the pad interconnects 112a and / or the pad interconnects 112c is that the at least one interconnect die 201 may be thinner than the at least one interconnect die 101, which may help reduce the overall thickness of the package. The at least one interconnect die 201 may be a means for die interconnection.

[0029] The pitch of the interconnects between metallization portions 102 and 104 may be relatively small. For example, the plurality of die interconnects 112 of at least one interconnect die 201 may have a pitch between adjacent die interconnects in a range of approximately 150-270 micrometers. These dimensions are possible through the use of at least one interconnect die 201, which (i) helps provide a thinner package 200 while still being able to accommodate integrated devices between the metallization portions, and (ii) helps provide interconnects having a small pitch (e.g., 150-270 micrometers) within the encapsulation layer, thus helping to provide high density routing (e.g., high density interconnects) within the encapsulation layer.

[0030] The integrated device 105 may be configured to be electrically coupled to the integrated device 103 via a plurality of solder interconnects 150, a plurality of metallization interconnects 142, at least one interconnect die 201 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of metallization interconnects 122, and / or a plurality of solder interconnects 130.

[0031] As described further below in at least Figures 3 and 4, in some implementations, another package (e.g., a second package) may be coupled to the package described in Figures 1 and 2. Thus, for example, as described further below, a package having an interconnect die may be a package-on-package (PoP) that includes a first package and a second package on top of the first package.

[0032] FIG. 3 shows a cross-sectional profile view of a package 300 including high density interconnects. The package 300 may include a package-on-package (PoP). The package 300 includes a package 301 and a package 302. The package 301 may be a first package and the package 302 may be a second package. The package 302 is coupled to the package 301 via a plurality of solder interconnects 360. The package 300 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 300 is coupled to a plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0033] The package 301 may be similar to the package 100 of FIG. 1. The package 301 may be configured and / or arranged similarly to that described for the package 100 of FIG. 1. The package 301 includes at least one interconnect die 101, a metallization portion 102, a metallization portion 104, an integrated device 103, and an encapsulation layer 106. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization portion 102 (e.g., a first metallization portion) includes a first side (e.g., a front side) and a second side (e.g., a back side). The metallization portion 104 (e.g., a second metallization portion) includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 includes a first side (e.g., a front side) and a second side (e.g., a back side). Metallization portion 104 (eg, a second metallization portion) is coupled to metallization portion 102 (eg, a first metallization portion) through at least one interconnect die 101 .

[0034] The package 302 includes a substrate 304, an integrated device 305, a number of wire bonds 350, an adhesive 370, and an encapsulation layer 306. The substrate 304 includes at least one dielectric layer 340 and a number of interconnects 342. The integrated device 305 is bonded to the substrate 304 by the adhesive 370. The number of wire bonds 350 are bonded to the integrated device 305 and to the number of interconnects 342 of the substrate 304. The integrated device 305 may include a memory die. In some implementations, there may be several integrated devices 305 stacked on top of each other. The encapsulation layer 306 encapsulates the integrated device 305 and the number of wire bonds 350. The encapsulation layer 306 is bonded to the substrate 304 and the integrated device 305. The encapsulation layer 306 is located above the substrate 304 and the integrated device 305. The encapsulation layer 306 may include a mold, a resin, and / or an epoxy. The encapsulation layer 306 can be a means for encapsulation. The encapsulation layer 306 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 306 can be similar or the same as the encapsulation layer 106.

[0035] The integrated device 305 may be configured to be electrically coupled to the integrated device 103 via a plurality of wire bonds 350, a plurality of interconnects 342, a plurality of solder interconnects 360, a plurality of metallization interconnects 142, at least one interconnect die 101 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of metallization interconnects 122, and / or a plurality of solder interconnects 130.

[0036] FIG. 4 shows a cross-sectional profile view of a package 400 including high density interconnects. The package 400 may include a package-on-package (PoP). The package 300 includes a package 401 and a package 302. The package 401 may be a first package and the package 302 may be a second package. The package 302 is coupled to the package 401 via a plurality of solder interconnects 360. The package 400 is coupled to a board 108 via a plurality of solder interconnects 117. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 400 is coupled to a plurality of board interconnects 182 of the board 108 via a plurality of solder interconnects 117.

[0037] The package 401 may be similar to the package 200 of FIG. 2. The package 401 may be configured and / or arranged similarly to that described for the package 200 of FIG. 2. The package 401 includes at least one interconnect die 201, a metallization portion 102, a metallization portion 104, an integrated device 103, and an encapsulation layer 106. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization portion 102 (e.g., a first metallization portion) includes a first side (e.g., a front side) and a second side (e.g., a back side). The metallization portion 104 (e.g., a second metallization portion) includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 includes a first side (e.g., a front side) and a second side (e.g., a back side). Metallization portion 104 (e.g., a second metallization portion) is configured to be coupled (e.g., electrically coupled) to metallization portion 102 (e.g., a first metallization portion) via at least one interconnect die 101.

[0038] The package 302 includes a substrate 304, an integrated device 305, a number of wire bonds 350, an adhesive 370, and an encapsulation layer 306. The substrate 304 includes at least one dielectric layer 340 and a number of interconnects 342. The integrated device 305 is bonded to the substrate 304 by the adhesive 370. The number of wire bonds 350 are bonded to the integrated device 305 and to the number of interconnects 342 of the substrate 304. The integrated device 305 may include a memory die. In some implementations, there may be several integrated devices 305 stacked on top of each other. The encapsulation layer 306 encapsulates the integrated device 305 and the number of wire bonds 350. The encapsulation layer 306 is bonded to the substrate 304 and the integrated device 305. The encapsulation layer 306 is located above the substrate 304 and the integrated device 305. The encapsulation layer 306 may include a mold, a resin, and / or an epoxy. The encapsulation layer 306 can be a means for encapsulation. The encapsulation layer 306 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 306 can be similar or the same as the encapsulation layer 106.

[0039] The integrated device 305 may be configured to be electrically coupled to the integrated device 103 via a plurality of wire bonds 350, a plurality of interconnects 342, a plurality of solder interconnects 360, a plurality of metallization interconnects 142, at least one interconnect die 201 (a plurality of interconnects 112), a plurality of solder interconnects 115, a plurality of metallization interconnects 122, and / or a plurality of solder interconnects 130.

[0040] Metallization interconnects 122 and / or metallization interconnects 142 may have a thickness in the range of approximately 3 to 7 micrometers. For example, one or more redistribution interconnects from metallization interconnects 122 and / or metallization interconnects 142 may have a thickness in the range of approximately 3 to 7 micrometers. In some implementations, one or more trace interconnects (e.g., traces) from interconnects 342 (from substrate 204) may have a thickness in the range of approximately 10 to 15 micrometers.

[0041] The integrated device (e.g., 103, 105, 305) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. Chiplets may be fabricated using processes that provide better yields compared to other processes used to manufacture other types of integrated devices, which may lower the overall cost of fabricating the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices). Using several chiplets that perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0042] The packages (e.g., 100, 200, 300, 400) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The packages (e.g., 100, 200) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 100, 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The packages (e.g., 100, 200) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0043] Having described the various interconnect dies, the sequence for fabricating the interconnect dies will now be described below.

[0044] Exemplary Sequence for Fabricating an Interconnect Die In some implementations, fabricating an interconnect die includes several processes. Figure 5 shows an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figure 5 may be used to provide or fabricate an interconnect die 201. However, the process of Figure 5 may be used to fabricate any of the interconnect dies (e.g., 101) described in this disclosure.

[0045] 5 may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0046] Stage 1, as shown in FIG. 5, illustrates a state after preparing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0047] Stage 2 shows the state after multiple cavities 502 have been formed in the die substrate 110. For example, the multiple cavities 502 may be formed through a first surface of the die substrate 110. The multiple cavities 502 may include grooves. The multiple cavities 502 may extend partially through the thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the multiple cavities 502.

[0048] Stage 3 shows after a metal layer 505 is formed within the plurality of cavities 502 and / or on the first surface of the die substrate 110. The metal layer 505 may include copper. A plating process may be used to form the metal layer 505.

[0049] Stage 4 shows the state after a portion of the metal layer 505 has been removed. For example, the portion of the metal layer 505 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 505 remains in the cavities 502. A polishing process may be used to remove the portion of the metal layer 505. The remaining metal from the metal layer 505 located in the cavities 502 may define the interconnects 112b as described in FIGS. 1 and 2.

[0050] Stage 5 shows the die substrate 110 after it has been thinned. For example, a portion (e.g., a bottom portion) of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 505 is exposed. A grinding process may be used to remove the portion of the die substrate 110. The grinding process may also remove portions of the metal layer 505 located within the plurality of cavities 502.

[0051] Stage 6 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. In some implementations, stage 6 may show an implementation of interconnected dies that include interconnects and no additional interconnects are formed in, above, or below the die substrate 110.

[0052] Exemplary Sequence for Fabricating an Interconnect Die In some implementations, fabricating an interconnect die includes several processes. Figure 6 shows an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figure 6 may be used to provide or fabricate an interconnect die 201. However, the process of Figure 6 may be used to fabricate any of the interconnect dies (e.g., 101) described in this disclosure.

[0053] It should be noted that the sequence of Figure 6 may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0054] Stage 1, as shown in FIG. 6, illustrates a state after preparing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0055] Stage 2 shows the state after cavities 602 have been formed in the die substrate 110. For example, the cavities 602 may be formed through a first surface of the die substrate 110. The cavities 602 may include grooves. The cavities 602 may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the cavities 602.

[0056] Stage 3 shows after a metal layer 605 is formed in the plurality of cavities 602 and / or on the first surface of the die substrate 110. The metal layer 605 may include copper. A filling process may be used to form the metal layer 605, in which a conductive paste may be used to fill the plurality of cavities 602. An additional metal layer 605 may be located on the die substrate 110.

[0057] Stage 4 shows the state after a portion of the metal layer 605 has been removed. For example, the portion of the metal layer 605 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 605 remains in the cavities 602. A polishing process may be used to remove the portion of the metal layer 605. The remaining metal from the metal layer 605 located in the cavities 602 may define the interconnects 112b as described in FIGS. 1 and 2.

[0058] Stage 5 shows the die substrate 110 after it has been thinned. For example, a portion (e.g., a bottom portion) of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 605 is exposed. A grinding process may be used to remove the portion of the die substrate 110. The grinding process may also remove portions of the metal layer 605 located within the plurality of cavities 602.

[0059] Stage 6 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. In some implementations, stage 6 may show an implementation of interconnected dies that include interconnects and no additional interconnects are formed in, above, or below the die substrate 110.

[0060] Exemplary Sequence for Fabricating an Interconnect Die In some implementations, fabricating an interconnect die includes several processes. Figures 7A-7B show an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figures 7A-7B may be used to provide or fabricate an interconnect die 101. However, the process of Figures 7A-7B may be used to fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0061] Note that the sequences of FIGS. 7A-7B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0062] Step 1 shows the state after preparing die substrate 110, as shown in FIG. 7A. Die substrate 110 includes silicon. Die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of die substrate 110 may be the top surface, and the second surface of die substrate 110 may be the bottom surface. In some implementations, the first surface of die substrate 110 may be the bottom surface, and the second surface of die substrate 110 may be the top surface.

[0063] Step 2 shows the state after a plurality of cavities 502 are formed in die substrate 110. For example, the plurality of cavities 502 may be formed through the first surface of die substrate 110. The plurality of cavities 502 may include grooves. The plurality of cavities 502 may extend partially through the thickness of die substrate 110. A laser ablation process and / or an etching process may be used to form the plurality of cavities 502.

[0064] Step 3 shows the state after a metal layer 505 is formed within the plurality of cavities 502 and / or on the first surface of die substrate 110. Metal layer 505 may include copper. A plating process may be used to form metal layer 505.

[0065] Stage 4 shows the state after a portion of the metal layer 505 has been removed. For example, the portion of the metal layer 505 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 505 remains in the cavities 502. A polishing process may be used to remove the portion of the metal layer 505. The remaining metal from the metal layer 505 located in the cavities 502 may define the interconnects 112b as described in FIGS. 1 and 2.

[0066] Stage 5, as shown in FIG. 7B, depicts the state after metal layer 507 has been formed on the first surface of die substrate 110. A plating process may be used to form metal layer 507. Metal layer 507 may be bonded to metal layer 505. Metal layer 507 may define a plurality of interconnects 112b as described in FIGS. 1 and 2. Metal layer 507 may represent the front-side interconnects of the interconnect die.

[0067] Stage 6 shows the die substrate 110 after thinning. For example, a portion (e.g., bottom) of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 505 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least the die substrate 110a and the die substrate 110b remain. If the die substrate 110b is present, the bottom side of the metal layer 505 is not exposed. A grinding process may be used to remove a portion (e.g., bottom) of the die substrate 110. The grinding process may also remove portions of the metal layer 505 located within the cavities 502. In some implementations, stage 6 may show an implementation of an interconnected die that includes interconnects and no additional interconnects are formed in, above, or below the die substrate 110. If no additional interconnects are formed, singulation may occur in a manner similar to that described below in stage 8. As will be further described below, the interconnect die shown in step 6 may be used to bond to a substrate.

[0068] Stage 7 shows the state after metal layer 509 has been formed on the second surface of die substrate 110. A plating process may be used to form metal layer 509. Metal layer 509 may be bonded to metal layer 505. Metal layer 507 may define a plurality of interconnects 112c as described in Figures 1 and 2. Metal layer 509 may represent the backside interconnects of the interconnect die.

[0069] Stage 8 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110.

[0070] Exemplary Sequence for Fabricating an Interconnect Die In some implementations, fabricating an interconnect die includes several processes. Figures 8A-8B show an example sequence for providing or fabricating an interconnect die. In some implementations, the sequence of Figures 8A-8B may be used to provide or fabricate an interconnect die 101. However, the process of Figures 8A-8B may be used to fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0071] 8A-8B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0072] Stage 1, as shown in FIG. 8A, illustrates a state after preparing a die substrate 110. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface.

[0073] Stage 2 shows the state after cavities 602 have been formed in the die substrate 110. For example, the cavities 602 may be formed through a first surface of the die substrate 110. The cavities 602 may include grooves. The cavities 602 may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the cavities 602.

[0074] Stage 3 shows after a metal layer 605 is formed in the plurality of cavities 602 and / or on the first surface of the die substrate 110. The metal layer 605 may include copper. A filling process may be used to form the metal layer 605, in which a conductive paste may be used to fill the plurality of cavities 602. The metal layer 605 may be located on the die substrate 110.

[0075] Stage 4 shows the state after a portion of the metal layer 605 has been removed. For example, the portion of the metal layer 605 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 605 remains in the cavities 602. A polishing process may be used to remove the portion of the metal layer 605. The remaining metal from the metal layer 605 located in the cavities 602 may define the interconnects 112b as described in FIGS. 1 and 2.

[0076] Stage 5, as shown in FIG. 8B, depicts the state after metal layer 607 has been formed on the first surface of die substrate 110. A plating process may be used to form metal layer 607. Metal layer 607 may be bonded to metal layer 605. Metal layer 607 may define a plurality of interconnects 112a as described in FIGS. 1 and 2. Metal layer 607 may represent the front-side interconnects of the interconnect die.

[0077] Stage 6 shows the die substrate 110 after thinning. For example, a portion (e.g., bottom) of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 605 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least the die substrate 110a and the die substrate 110b remain. If the die substrate 110b is present, the bottom side of the metal layer 605 is not exposed. A grinding process may be used to remove a portion (e.g., bottom) of the die substrate 110. The grinding process may also remove portions of the metal layer 605 located within the cavities 602. In some implementations, stage 6 may show an implementation of an interconnected die that includes interconnects and no additional interconnects are formed in, above, or below the die substrate 110. If no additional interconnects are formed, singulation may occur in a manner similar to that described below in stage 8. As will be further described below, the interconnect die shown in step 6 may be used to bond to a substrate.

[0078] Stage 7 shows the state after metal layer 609 has been formed on the second surface of die substrate 110. A plating process may be used to form metal layer 609. Metal layer 609 may be bonded to metal layer 605. Metal layer 609 may define a plurality of interconnects 112c as described in Figures 1 and 2. Metal layer 609 may represent the backside interconnects of the interconnect die.

[0079] Stage 8 shows the state after singulation to form several interconnected dies. A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110.

[0080] 1 is an exemplary flow diagram of a method for fabricating an interconnect die; In some implementations, fabricating an interconnect die includes several processes. Figure 9 shows an example flow diagram of a method 900 for providing or fabricating an interconnect die. In some implementations, the method 900 of Figure 9 may be used to provide or fabricate the interconnect die 101 described in this disclosure. However, the method 900 may be used to provide or fabricate any of the interconnect dies (e.g., 201) described in this disclosure.

[0081] 9 may combine one or more processes to simplify and / or clarify a method for providing or making an interconnect die. In some implementations, the order of the processes may be changed or modified.

[0082] The method provides (at 905) a die substrate (e.g., 110). The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be a top surface and the second surface of the die substrate 110 may be a bottom surface. In some implementations, the first surface of the die substrate 110 may be a bottom surface and the second surface of the die substrate 110 may be a top surface. Step 1 of FIG. 7A illustrates and describes an example of preparing a die substrate. Step 1 of FIG. 8A illustrates and describes an example of preparing a die substrate.

[0083] The method forms (at 910) a plurality of cavities (e.g., 502, 602) in the die substrate 110. For example, the plurality of cavities (e.g., 502, 602) may be formed through a first surface of the die substrate 110. The plurality of cavities (e.g., 502, 602) may include grooves. The plurality of cavities (e.g., 502, 602) may extend partially through a thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the plurality of cavities (e.g., 502, 602). Step 2 of FIG. 7A illustrates and describes an example of forming a cavity in the die substrate. Step 2 of FIG. 8A illustrates and describes an example of forming a cavity in the die substrate.

[0084] The method forms (at 915) a conductive material (e.g., an electrically conductive material) in the plurality of cavities (e.g., 502, 602) of the die substrate 110. The conductive material may include a metal layer (e.g., 505, 605). The conductive material may be formed on a surface of the die substrate 110. The conductive material may include copper. A plating process may be used to form the conductive material. A filling process may be used to form the conductive material. Stage 3 of FIG. 7A illustrates and describes an example of forming the conductive material in the die substrate. Stage 3 of FIG. 8A illustrates and describes an example of forming the conductive material in the die substrate. In some implementations, forming the conductive material may include removing a portion of the conductive material. A polishing process may be used to remove the portion of the conductive material. Removing the portion of the conductive material may include removing a portion of the conductive material bonded to the first surface of the die substrate 110, leaving the conductive material located in the plurality of cavities (e.g., 502, 602) of the die substrate 110. Step 4 of Figure 7A illustrates and describes an example of removing a portion of the conductive material in the die substrate. Step 4 of Figure 8A illustrates and describes an example of removing a portion of the conductive material in the die substrate.

[0085] The method optionally forms (at 920) a plurality of front-side interconnects. The front-side interconnects may be bonded to a top side of the die substrate 110. The plurality of front-side interconnects may be defined by a patterned metal layer (e.g., 507, 607) on the top surface of the die substrate 110. A plating process may be used to form the metal layer (e.g., 507, 607). Metal layer 507 may be bonded to metal layer 505. Metal layer 607 may be bonded to metal layer 605. Metal layer 607 may define a plurality of interconnects 112a as described in FIG. 1 and FIG. 2. Metal layer 607 may represent a front-side interconnect of the interconnect die. The plurality of interconnects 112a may represent a front-side interconnect of the interconnect die. Step 5 of FIG. 7B illustrates and describes one example of forming a front-side interconnect. Step 5 of FIG. 8B illustrates and describes one example of forming front-side interconnects.

[0086] The method thins (at 925) the die substrate (e.g., 110). Different implementations may thin the die substrate 110 differently. For example, some implementations may thin the die substrate 110 such that the bottom side of the metal layer (e.g., 505, 605) is exposed. Some implementations may thin the die substrate 110 without exposing the bottom side of the metal layer (e.g., 505, 605). A grinding process may be used to remove a portion (e.g., bottom) of the die substrate 110. The grinding process may also remove a portion of the metal layer (e.g., 505, 605) located within the cavities (e.g., 502, 602). Step 6 of FIG. 7B illustrates and describes an example of thinning the die substrate. Step 6 of FIG. 8B illustrates and describes an example of thinning the die substrate.

[0087] The method optionally forms (at 930) a plurality of backside interconnects. The backside interconnects may be bonded to a bottom side of the die substrate 110. The plurality of backside interconnects may be defined by a patterned metal layer (e.g., 509, 609) on the bottom surface of the die substrate 110. A plating process may be used to form the metal layer (e.g., 509, 609). The metal layer 509 may be bonded to the metal layer 505. The metal layer 609 may be bonded to the metal layer 605. The metal layer 609 may define the plurality of interconnects 112c as described in FIG. 1 and FIG. 2. The metal layer 609 may represent the backside interconnects of the interconnect die. The plurality of interconnects 112c may represent the backside interconnects of the interconnect die. Step 7 of FIG. 7B illustrates and describes one example of forming the backside interconnects. Step 7 of FIG. 8B illustrates and describes one example of forming backside interconnects.

[0088] The method singulates (at 935) the die substrate 110 to form several interconnected dies (e.g., 101, 201). A mechanical process may be used to singulate the die substrate 110 into several interconnected dies (e.g., 101, 201). A saw may be used to singulate the die substrate 110. Step 8 in FIG. 7B illustrates and describes one example of singulation. Step 8 in FIG. 8B illustrates and describes one example of singulation.

[0089] Exemplary Sequence for Making a Package with Interconnected Dies In some implementations, making a package includes several processes. Figures 10A-10B show an example sequence for providing or making a package. In some implementations, the sequence of Figures 10A-10B may be used to provide or make package 100. However, the process of Figures 10A-10B may be used to make any of the packages described in this disclosure (e.g., 200, 300, 301, 302, 400, 401).

[0090] 10A-10B may combine one or more steps to simplify and / or clarify the sequence for providing or making a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0091] Stage 1, as shown in FIG. 10A, illustrates the state after the metallization portion 102 is provided. The metallization portion 102 may be provided on a carrier 1000. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization portion 102 may include a first side (e.g., a front side) and a second side (e.g., a back side). The metallization portion 102 may include a rewiring portion. The metallization portion 102 may be fabricated using the method described in FIG. 12A-12B.

[0092] Stage 2 illustrates a state after the integrated device 103 is bonded to a first side (e.g., front side) of the metallization portion 102. The integrated device 103 may be bonded to the metallization portion 102 via a plurality of solder interconnects 130. The integrated device 103 may be bonded to the metallization portion 102 via a plurality of pillar interconnects and / or a plurality of solder interconnects 130. A solder reflow process may be used to bond the integrated device 103 to the metallization portion 102. Stage 2 also illustrates a state after at least one interconnect die 101 is bonded to a first side of the metallization portion 102. The at least one interconnect die 101 may be bonded to the metallization portion 102 via a plurality of solder interconnects 115. A solder reflow process may be used to bond the at least one interconnect die 101 to the metallization portion 102.

[0093] Stage 3 shows a state after the encapsulation layer 106 is provided on the metallization portion 102, the integrated device 103, and the at least one interconnect die 101. The encapsulation layer 106 may encapsulate the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may be bonded to a first side of the metallization portion 102. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, a polishing process and / or a grinding process may be performed on the encapsulation layer 106 to planarize at least a surface of the encapsulation layer 106.

[0094] Stage 4 shows a state after the metallization portion 104 is formed on the encapsulation layer 106. The metallization portion 104 may be formed such that at least one dielectric layer 140 and a plurality of metallization interconnects 142 are formed. The metallization portion 104 may be formed such that the metallization portion 104 is coupled (e.g., electrically coupled) to the metallization portion 102 through at least one interconnect die 101. The metallization portion 104 may be formed layer by layer on the encapsulation layer 106 and the interconnect die 101. The metallization portion 104 may include a first side (e.g., front side) and a second side (e.g., back side). The metallization portion 104 may be fabricated using the same and / or similar method as described in FIGS. 12A-12B. Instead of a carrier, the metallization portion 104 is fabricated and / or formed on a surface of the encapsulation layer 106 and / or a surface of the interconnect die 101. At least one interconnect die 101 may be coupled to the metallization portion 104. Because the metallization portion 104 is formed on the at least one interconnect die 101, no solder interconnects are required to couple the metallization portion 104 to the at least one interconnect die 101. Thus, a bond between an interconnect from the plurality of metallization interconnects 142 and a die interconnect (e.g., 112a) from the plurality of die interconnects 112 may be free of solder interconnects. The integrated device 103 and the at least one interconnect die 101 may be located between the metallization portion 102 and the metallization portion 104.

[0095] Stage 5, as shown in Figure 10B, illustrates the state after the carrier 1000 has been removed from the metallization portion 102. A grinding process may be used to remove the carrier 1000 from the metallization portion 102. However, other processes may be used to separate the carrier 1000 from the metallization portion 102.

[0096] Stage 6 shows the condition after the plurality of solder interconnects 117 have been bonded to the metallization portion 102. The plurality of solder interconnects 117 may be bonded to a second side (e.g., backside) of the metallization portion 102. A solder reflow process may be used to bond the plurality of solder interconnects 117 to the plurality of metallization interconnects 122 of the metallization portion 102.

[0097] Stage 7 shows the state after the integrated device 105 is bonded to the first side (e.g., front side) of the metallization portion 104. The integrated device 105 may be bonded to the metallization portion 104 via a plurality of pillar interconnects and / or a plurality of solder interconnects 150. A solder reflow process may be used to bond the integrated device (and / or passive device) to the metallization portion 104 via the plurality of solder interconnects. It should be noted that instead of the integrated device, another package, such as package 302, may be bonded to the first side (e.g., front side) of the metallization portion 104.

[0098] 1 is an exemplary flow diagram of a method for making a package with interconnected dies; In some implementations, producing a package includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or producing a package. In some implementations, the method 1100 of Figure 11 can be used to provide or produce the package 100 described in this disclosure. However, the method 1100 can be used to provide or produce any of the packages described in this disclosure (e.g., 200, 300, 301, 302, 400, 401).

[0099] It should be noted that the method 1100 of Figure 11 may combine one or more processes to simplify and / or clarify the method for providing or making a package. In some implementations, the order of the processes may be changed or modified.

[0100] The method provides (at 1105) a metallization portion (e.g., 102). The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization portion 102 (e.g., a first metallization portion) may include a first side (e.g., a front side) and a second side (e.g., a back side). The metallization portion 102 may be fabricated using the method described in Figures 12A-12B. Step 1 of Figure 10A illustrates and describes one example of providing a metallization portion.

[0101] The method includes (at 1110) bonding an integrated device (e.g., 103) and at least one interconnect die (e.g., 101, 201) to a first side (e.g., front side) of a metallization portion 102. The integrated device 103 may be bonded to the metallization portion 102 via a plurality of pillar interconnects and / or a plurality of solder interconnects 130. A solder reflow process may be used to bond the integrated device 103 to the metallization portion 102. The at least one interconnect die 101 may be bonded to the metallization portion 102 via a plurality of solder interconnects 115. A solder reflow process may be used to bond the at least one interconnect die 101 to the metallization portion 102. Stage 2 of FIG. 10A illustrates and describes one example of bonding an integrated device and an interconnect die to a metallization portion.

[0102] The method forms (at 1115) an encapsulation layer (e.g., 106) over the metallization portion 102, the integrated device 103, and the at least one interconnect die 101. The encapsulation layer 106 may encapsulate the integrated device 103 and the at least one interconnect die 101. The encapsulation layer 106 may be bonded to the front side of the metallization portion 102. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, a polishing process and / or a grinding process may be performed to planarize at least the surface of the encapsulation layer 106. Stage 3 of FIG. 10A illustrates and describes one example of providing an encapsulation layer.

[0103] The method forms (at 1120) a metallization portion (e.g., 104) on the encapsulation layer 106. The metallization portion 104 (e.g., a second metallization portion) may be formed such that the metallization portion 104 is configured to be coupled (e.g., electrically coupled) to a metallization portion (e.g., 102) via at least one interconnect die (e.g., 101, 201). The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may include a first side (e.g., a front side) and a second side (e.g., a back side). The metallization portion 104 may be fabricated using the method described in FIGS. 12A-12B. The metallization portion 104 may be coupled to at least one interconnect die 101. Metallization portion 104 may be formed such that at least one of interconnect die 101 and integrated device 103 is located between metallization portion 102 and metallization portion 104. Step 4 of Figure 10A illustrates and describes one example of forming a metallization portion over an encapsulation layer.

[0104] The method removes (at 1125) the carrier (e.g., 1000) from the metallization portion (e.g., 102). A grinding process may be used to remove the carrier 1000 from the metallization portion 102. However, other processes may be used to separate the carrier 1000 from the metallization portion 102. Step 5 of FIG. 10B illustrates and describes one example of removing the carrier.

[0105] The method bonds (at 1130) a plurality of solder interconnects (e.g., 117) to the metallization portion 102. A solder reflow process may be used to bond the plurality of solder interconnects 117 to the second surface of the metallization portion 102. Step 6 of Figure 10B illustrates and describes one example of bonding the solder interconnects to the metallization portion.

[0106] The method couples (at 1135) an integrated device (e.g., 105) and / or a package (e.g., 302) to the first side (e.g., front side) of the metallization portion 104. The integrated device 105 may be coupled to the metallization portion 104 via a plurality of pillar interconnects and a plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated device(s) (and / or passive devices) to the metallization portion 104. It should be noted that in addition to or instead of the integrated device, another package, such as package 302, may be coupled to the first side (e.g., front side) of the metallization portion 104. Step 7 of FIG. 10B illustrates and describes one example of coupling an integrated device to a metallization portion.

[0107] In some implementations, several packages are made simultaneously. In such cases, the method may singulate the packages (e.g., 100, 200, 300, 301, 302, 400, 402).

[0108] Exemplary sequence for making metallization portions In some implementations, creating the metallization portion includes several processes. Figures 12A-12B show an example sequence for providing or creating the metallization portion. In some implementations, the sequence of Figures 12A-12B can be used to provide or create the metallization portion 102. However, the process of Figures 12A-12B can be used to create any of the metallization portions (e.g., 104) described in this disclosure.

[0109] 12A-12B may combine one or more steps to simplify and / or clarify the sequence for providing or creating the metallization portion. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0110] Stage 1 illustrates the state after preparing the carrier 1200, as shown in FIG. 12A. A seed layer 1201 and interconnects 1202 may be located on the carrier 1200. The interconnects 1202 may be located on the seed layer 1201. A plating process and an etching process may be used to form the interconnects 1202. In some implementations, the carrier 1200 may be provided with the seed layer 1201 and a metal layer that is patterned to form the interconnects 1202. The interconnects 1202 may represent at least some of the metallization interconnects from the plurality of metallization interconnects 122.

[0111] Stage 2 shows the state after dielectric layer 1220 is formed over carrier 1200, seed layer 1201, and interconnects 1202. A deposition process and / or lamination process may be used to form dielectric layer 1220. Dielectric layer 1220 may include prepreg and / or polyimide. Dielectric layer 1220 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0112] Stage 3 shows the state after a number of cavities 1210 have been formed in the dielectric layer 1220. The number of cavities 1210 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0113] Stage 4 shows the state after interconnects 1212 are formed in and on dielectric layer 1220, including in and over multiple cavities 1210. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. Stage 4 shows that some portions of interconnects 1212 may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a rewiring interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0114] Stage 5 shows the state after dielectric layer 1222 is formed over dielectric layer 1220 and interconnects 1212. A deposition process and / or lamination process may be used to form dielectric layer 1222. Dielectric layer 1222 may include prepreg and / or polyimide. Dielectric layer 1222 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0115] 12B, stage 6 shows the state after a number of cavities 1230 have been formed in the dielectric layer 1222. The number of cavities 1230 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0116] Stage 7 shows the state after interconnects 1214 are formed in and on dielectric layer 1222, including in and over multiple cavities 1230. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. Stage 7 shows that some portions of interconnects 1214 may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a rewiring interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0117] Stage 8 illustrates the state after the carrier 1200 has been separated (e.g., detached, removed, ground) from the at least one dielectric layer 120 and the seed layer 1201, and a portion of the seed layer 1201 has been removed (e.g., etched away), leaving behind the at least one dielectric layer 120 and the metallization portion 102 including the plurality of metallization interconnects 122. The at least one dielectric layer 120 may represent the dielectric layer 1220 and / or the dielectric layer 1222. The plurality of metallization interconnects 122 may represent the interconnects 1202, 1212, and / or 1214. As discussed above, the plurality of metallization interconnects 122 may include the plurality of redistribution interconnects. The plurality of metallization interconnects 122 may have a thickness in the range of approximately 3-7 micrometers. For example, one or more redistribution interconnects from the plurality of metallization interconnects 122 may have a thickness in the range of approximately 3 to 7 micrometers that is less than the thickness of the interconnects from the package substrate (e.g., 304). Similar or the same dimensions may be applicable to the plurality of metallization interconnects 142 from the metallization portion 104.

[0118] Different implementations may use different processes to form the metal layer(s) and / or the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0119] 1 is an exemplary flow diagram of a method for fabricating a metallization portion; In some implementations, creating the metallization portion includes several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or creating a metallization portion. In some implementations, the method 1300 of Figure 13 can be used to provide or create the metallization portion(s) of the present disclosure. For example, the method 1300 of Figure 13 can be used to create the metallization portion 102.

[0120] It should be noted that the method 1300 of Figure 13 may combine one or more processes to simplify and / or clarify the method for providing or creating the metallization portion. In some implementations, the order of the processes may be changed or modified.

[0121] The method provides (at 1305) a carrier (e.g., 1200). Different implementations can use different materials for the carrier 1200. The carrier 1200 can include a seed layer (e.g., 1201). The seed layer 1201 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 12A illustrates and describes one example of a carrier having a seed layer provided thereon.

[0122] The method forms and patterns (at 1310) interconnects on the carrier 1200 and the seed layer 1201. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer overlies the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 122). Step 1 of FIG. 12A illustrates and describes one example of forming and patterning interconnects on a seed layer and a carrier.

[0123] The method forms (at 1315) a dielectric layer 1220 over the interconnects 1202, the seed layer 1201, and the carrier 1200. A deposition process and / or a lamination process may be used to form the dielectric layer 1220. The dielectric layer 1220 may include prepreg and / or polyimide. The dielectric layer 1220 may include a photoimageable dielectric. Forming the dielectric layer 1220 may also include forming a plurality of cavities (e.g., 1210) in the dielectric layer 1220. The plurality of cavities may be formed using an etching process (e.g., a photoetching process) or a laser process. Steps 2-3 of FIG. 12A illustrate and describe one example of forming a dielectric layer and cavities in the dielectric layer.

[0124] The method forms (at 1320) an interconnect in and over the dielectric layer. For example, the interconnect 1212 may be formed in and over the dielectric layer 1220. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. A portion of the interconnect formed may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or redistribution interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. A bottom portion of a U-shaped interconnect (or a V-shaped interconnect) may be bonded to a top portion of another U-shaped interconnect (or a V-shaped interconnect). Step 4 of Figure 12A illustrates and describes one example of forming interconnects in and on a dielectric layer.

[0125] The method forms (at 1325) a dielectric layer 1222 over the dielectric layer 1220 and the interconnects 1212. A deposition process and / or lamination process may be used to form the dielectric layer 1222. The dielectric layer 1222 may include prepreg and / or polyimide. The dielectric layer 1222 may include a photoimageable dielectric. Forming the dielectric layer 1222 may also include forming a plurality of cavities (e.g., 1230) in the dielectric layer 1222. The plurality of cavities may be formed using an etching process (e.g., a photoetching process) or a laser process. Steps 5-6 of Figures 12A-12B illustrate and describe one example of forming a dielectric layer and cavities in the dielectric layer.

[0126] The method forms (at 1330) an interconnect in and over the dielectric layer. For example, interconnect 1214 may be formed in and over dielectric layer 1222. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. A portion of the interconnect formed may have a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or redistribution interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. A bottom portion of a U-shaped interconnect (or a V-shaped interconnect) may be bonded to a top portion of another U-shaped interconnect (or a V-shaped interconnect). Step 7 of Figure 12B illustrates and describes one example of forming interconnects in and on a dielectric layer, including forming post interconnects.

[0127] The method separates (at 1335) the carrier (e.g., 1200) from the seed layer (e.g., 1201). The carrier 1200 may be removed and / or ground. The method may also remove (at 1335) a portion of the seed layer (e.g., 1201). An etching process may be used to remove the portion of the seed layer 1201. Step 8 of FIG. 12B illustrates and describes an example of carrier separation and seed layer removal.

[0128] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0129] Exemplary Electronic Devices FIG. 14 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an autonomous vehicle 1410 may include a device 1400 as described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely examples. Other electronic devices may also be equipped with device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, portable data units such as handheld personal communication system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0130] One or more of the components, processes, features, and / or functions shown in Figures 1-6, 7A-7B, 8A-8B, 9, 10A-10B, 11, 12A-12B, and 13-14 may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It is also noted that Figures 1-6, 7A-7B, 8A-8B, 9, 10A-10B, 11, 12A-12B, and 13-14 in this disclosure and corresponding descriptions thereof are not limited to dies and / or ICs. In some implementations, Figures 1-6, 7A-7B, 8A-8B, 9, 10A-10B, 11, 12A-12B, and 13-14 and corresponding descriptions thereof may be used to manufacture, construct, provide, and / or produce a device and / or an integrated device. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0131] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0132] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even if they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. Use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component "over" a second component can mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be above (e.g., above) a first surface of a second component, and a third component can be above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being above another component, the term "over" as used in this application can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on the second component (e.g., on the surface of the second component), and / or (3) that the first component is present within the second component (e.g., embedded within the second component). A first component that is "in" a second component can be partially located within the second component or completely located within the second component. A value that is about X to XX can mean a value between and including X and XX. The value or values ​​between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0133] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form the interconnects.

[0134] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0135] Further examples are described below to facilitate understanding of the present disclosure.

[0136] Aspect 1: A package comprising: a first metallization portion comprising at least one first dielectric layer and a plurality of first metallization interconnects; a first integrated device coupled to the first metallization portion; an interconnect die coupled to the first metallization portion; a second metallization portion coupled to the first metallization portion via the interconnect die, wherein the first integrated device and the interconnect die are located between the first metallization portion and the second metallization portion, the second metallization portion comprising at least one second dielectric layer and a plurality of second metallization interconnects; and an encapsulation layer coupled to the first metallization portion and the second metallization portion, wherein the encapsulation layer is located between the first metallization portion and the second metallization portion.

[0137] Aspect 2: The package of aspect 1, wherein the interconnected die comprises a die substrate and a plurality of die interconnects.

[0138] Aspect 3: The package of aspect 2, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0139] Aspect 4: The package of Aspect 2 or 3, wherein the plurality of die interconnects have an aspect ratio in the range of 20:1 to 10:1.

[0140] Aspect 5: The package of Aspects 2-4, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0141] Embodiment 6: The package of embodiments 2-5, wherein the die substrate comprises glass and / or silicon.

[0142] Aspect 7: The package of Aspects 1-6, further comprising a second integrated device coupled to the second metallization portion, the first integrated device including the first chiplet and the second integrated device including the second chiplet.

[0143] Aspect 8: A package as described in aspects 1-7, wherein the first metallization portion includes a first rewiring portion, the plurality of first metallization interconnect portions includes a plurality of first rewiring interconnect portions, the second metallization portion includes a second rewiring portion, and the plurality of second metallization interconnect portions includes a plurality of second rewiring interconnect portions.

[0144] Aspect 9: The package of aspect 8, wherein a first portion of a first rewiring interconnect from the first plurality of rewiring interconnects includes a side profile having a U-shape or a V-shape, and a second portion of a second rewiring interconnect from the second plurality of rewiring interconnects includes a side profile having a U-shape or a V-shape.

[0145] Embodiment 10: The package of embodiments 1-9, wherein the interconnect die does not include a transistor.

[0146] Aspect 11: A device comprising: a first package comprising: a first metallization portion comprising at least one first dielectric layer and a plurality of first metallization interconnects; a first integrated device coupled to the first metallization portion; a means for die interconnection coupled to the first metallization portion; a second metallization portion coupled to the first metallization portion via the means for die interconnection, wherein the first integrated device and the means for die interconnection are located between the first metallization portion and the second metallization portion, the second metallization portion comprising at least one second dielectric layer and a plurality of second metallization interconnects; and an encapsulation layer coupled to the first metallization portion and the second metallization portion, the encapsulation layer being located between the first metallization portion and the second metallization portion.

[0147] Example 12: A device as described in example 11, wherein the means for die interconnection comprises a die substrate and a plurality of die interconnects.

[0148] Example 13: The device of example 2, wherein twelve adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0149] Example 14: The device of example 12 or 13, wherein the plurality of die interconnects have an aspect ratio in the range of 20:1 to 10:1.

[0150] Example 15: A device according to any one of Examples 12 to 14, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

[0151] Example 16: The device of Examples 12-15, wherein the die substrate comprises glass and / or silicon.

[0152] Aspect 17: A device described in aspects 1 to 16, wherein the eleventh metallization portion includes a first rewiring portion, the plurality of first metallization interconnect portions includes a plurality of first rewiring interconnect portions, the second metallization portion includes a second rewiring portion, and the plurality of second metallization interconnect portions includes a plurality of second rewiring interconnect portions.

[0153] Aspect 18: The device of aspects 11 to 17, further comprising a second package coupled to the first package via a plurality of solder interconnects, the second package comprising a substrate, a second integrated device coupled to the substrate, and a second encapsulation layer coupled to the substrate and the second integrated device.

[0154] Embodiment 19: The device of embodiments 11 to 18, wherein the means for die interconnection does not include a transistor.

[0155] Aspect 20: The device described in aspects 11 to 19, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0156] Aspect 21: A method for making a package, the method including: providing a first metallization portion; bonding a first integrated device to the first metallization portion; bonding an interconnect die to the first metallization portion; forming an encapsulation layer over the first metallization portion, the first integrated device, and the interconnect die; and forming a second metallization portion on the encapsulation layer such that the second metallization portion is bonded to the first metallization portion via the interconnect die.

[0157] Example 22: The method of example 21, further comprising coupling a second integrated device to the second metallization portion.

[0158] Example 23: The method of example 21, further comprising bonding a second package to the metallization portion of example 2 via a plurality of solder interconnects, the second package comprising a substrate, a second integrated device bonded to the substrate, and a second encapsulation layer bonded to the substrate and the second integrated device.

[0159] Example 24: The method of Examples 21-23, wherein the interconnected die comprises a die substrate and a plurality of die interconnects.

[0160] Example 25: The method of example 24, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

[0161] Example 26: The method of example 24 or 25, wherein the plurality of die interconnects have an aspect ratio in the range of 20:1 to 10:1.

[0162] Example 27: The method of any of Examples 21 to 26, wherein the first metallization portion includes a first rewiring portion having a plurality of first rewiring interconnects, and forming the second metallization portion includes forming a second rewiring portion having a plurality of second rewiring interconnects.

[0163] Various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0164] 100, 200, 300, 301, 302, 400 packages 101, 201 Interconnect Die 102, 104 Metallization part 103, 105, 305 Integrated Devices 106, 306 Encapsulation layer 120, 140, 340 Dielectric layer 122, 142 Metallization Interconnects

Claims

1. At least one first dielectric layer, Multiple first metallization interconnection units, A first metallization portion comprising, A first integrated device coupled to the first metallization portion via a plurality of first solder interconnections, An interconnect die coupled to the first metallization portion via a plurality of second solder interconnects, A second metallization portion coupled to the first metallization portion via the interconnecting die and the plurality of second solder interconnects, wherein the first integrated device and the interconnecting die are located between the first metallization portion and the second metallization portion, and the second metallization portion is At least one second dielectric layer, Multiple second metallization interconnection units, A second metallization portion comprising, An encapsulation layer bonded to the first metallization portion and the second metallization portion, the encapsulation layer located between the first metallization portion and the second metallization portion, A package that includes the following features.

2. The aforementioned interconnection die die substrate and Multiple die interconnection sections, The package according to claim 1, comprising:

3. The package according to claim 2, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of 150 to 270 micrometers.

4. The package according to claim 2, wherein the plurality of die interconnection sections have an aspect ratio in the range of 20:1 to 10:

1.

5. The package according to claim 2, wherein the plurality of die interconnects include via die interconnects and pad die interconnects.

6. The package according to claim 2, wherein the die substrate includes glass and / or silicon.

7. The package according to claim 1, further comprising a second integrated device coupled to the second metallization portion, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

8. The first metallization portion includes the first rewiring portion, The plurality of first metallization interconnects include a plurality of first rewiring interconnects, The second metallization portion includes a second rewiring portion, The plurality of second metallization interconnects include a plurality of second rewiring interconnects, The package according to claim 1.

9. The first portion of the first rewiring interconnect from the plurality of first rewiring interconnects includes a side profile having a U-shape or a V-shape, The second portion of the second rewiring interconnect from the plurality of second rewiring interconnects includes a side profile having a U-shape or a V-shape. The package according to claim 8.

10. The package according to claim 1, wherein the interconnect die does not include a transistor.

11. The first package according to any one of claims 1 to 10 A device equipped with the following features.

12. The present invention further comprises a second package coupled to the first package via a plurality of third solder interconnections, wherein the second package is circuit board and A second integrated device coupled to the substrate, The substrate and the second encapsulation layer coupled to the second integrated device, The device according to claim 11, comprising:

13. The device according to claim 11, wherein the device is selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things devices, and devices in an automatic vehicle.

14. A method for creating a package, By providing a first metallization section, The first integrated device is coupled to the first metallization portion via a plurality of first solder interconnections, The interconnect die is connected to the first metallization portion via a plurality of second solder interconnects, Forming an encapsulation layer on the first metallization portion, the first integrated device, and the interconnection die, The second metallization portion is formed on the encapsulation layer such that the second metallization portion is coupled to the first metallization portion via the interconnecting die and the plurality of second solder interconnects, Methods that include...

15. Connecting a second integrated device to the second metallization portion, and / or The second package is joined to the second metallization portion via a plurality of solder interconnections, wherein the second package is circuit board and A second integrated device coupled to the substrate, The substrate and the second encapsulation layer coupled to the second integrated device, to be equipped The method according to claim 14, further comprising:

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