Charge storage structure and method for manufacturing a charge storage structure - Patents.com

Abstract

The present application relates to a charge storage structure and a method for manufacturing the charge storage structure. The charge storage structure according to an embodiment includes a wafer, a first pole region, and a second pole region. The wafer has a first surface having a first texture, and a second surface opposite to the first surface, the second surface having a first portion having a second texture and a second portion connected to the first portion, the first pole region contacts the first portion of the second surface, the second pole region is spaced apart from the first pole region and adjacent to the second portion of the second surface, and the first texture is different from the second texture. The charge storage structure and the method for manufacturing the charge storage structure provided in the present application have the advantages of bringing higher production efficiency with lower manufacturing costs, and can flexibly set the texture of the front surface of the battery and the texture of the opening of the back surface of the battery according to specific needs to meet different product requirements.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application is a national phase application of International Patent Application No. PCT / CN2022 / 141445, filed on December 23, 2022, and claims priority to Chinese Patent Application No. 202211097786.4, filed on September 8, 2022, and Chinese Patent Application No. 202211097547.9, filed on September 8, 2022. The entire disclosures of the above applications are incorporated herein by reference. FIELD OF THE DISCLOSURE Embodiments of the present application relate to the field of charge storage structures, and in particular to charge storage structures and methods of fabricating charge storage structures. [Background technology]

[0002] Solar cells are generally photovoltaic devices that directly convert sunlight into electricity. Interdigital back contact (IBC) solar cells currently in widespread use on the market are usually made of silicon wafers. However, existing IBC solar The manufacturing process of the battery requires many steps and the use of various types of equipment, resulting in high manufacturing costs and unable to meet market needs.

[0003] Therefore, the industry is looking for IBCs with lower manufacturing costs, higher production efficiency, and higher performance. Solar Cell It is also expected to provide a method for fabricating a charge storage structure that can increase production efficiency and reduce manufacturing costs. Summary of the Invention

[0004] An object of the present invention is to provide a charge storage structure and a method for manufacturing the charge storage structure, which can provide higher production efficiency with lower manufacturing costs and can be flexibly designed into various shapes according to different needs.

[0005] A charge storage structure according to one embodiment of the present application comprises a wafer having a first surface with a first texture, a second surface opposite the first surface having a first portion with a second texture and a second portion connected to the first portion, a first pole region in contact with the first portion of the second surface, and a second pole region spaced apart from the first pole region and adjacent to the second portion of the second surface, wherein the first texture is different from the second texture.

[0006] In some embodiments of the present application, the first texture is one of a pyramid texture and an inverted pyramid texture, and the second texture is one of an alkali polished texture, an acid polished texture, a micro polished texture, or a micro polished texture. Rote The texture can be one of the following: texture, pyramid texture, or inverted pyramid texture.

[0007] In some embodiments of the present application, the charge storage structure further comprises an oxide layer covering a second portion of the second surface of the wafer.

[0008] In some embodiments of the present application, the charge storage structure further comprises a semiconductor layer overlying the oxide layer.

[0009] In some embodiments of the present application, the charge storage structure further comprises a first passivation layer covering the first surface, a first portion of the second surface, a third surface of the wafer between the first surface and the second surface, a side of the oxide layer, and a side of the semiconductor layer.

[0010] In some embodiments of the present application, the charge storage structure further comprises a second passivation layer covering the first passivation layer.

[0011] In some embodiments of the present application, the first pole region has a first metal contact and a region connected to the first metal contact.

[0012] In some embodiments of the present application, the region is N + Polar region, or P + It is a polar region.

[0013] In some embodiments of the present application, both the first passivation layer and the second passivation layer located on the first portion of the second surface have a first opening, and the first metal contact of the first pole region passes through the first opening.

[0014] In some embodiments of the present application, the second pole region has a second metal contact connected to the semiconductor layer, the second metal contact being connected to the semiconductor layer without passing through an opening.

[0015] In some embodiments of the present application, the first metal contact is aluminum.

[0016] In some embodiments of the present application, the second metal contact is a silver paste or a silver aluminum paste.

[0017] In some embodiments of the present application, the wafer is a p-type c-Si wafer.

[0018] In some embodiments of the present application, the semiconductor layer comprises a Group IV element.

[0019] In some embodiments of the present application, the semiconductor layer comprises a Group V element.

[0020] In some embodiments of the present application, the semiconductor layer comprises phosphorus.

[0021] In some embodiments of the present application, the second portion of the second surface is a flat surface.

[0022] In some embodiments of the present application, the oxide layer is a tunnel oxide layer.

[0023] In some embodiments of the present application, the inverted pyramid texture has a reflectance between 2% and 15%.

[0024] In some embodiments of the present application, the pyramid texture has a reflectance of about 5% to 20%.

[0025] In some embodiments of the present application, Rote The texture has a reflectivity of approximately 12%.

[0026] According to an embodiment of the present application, a charge storage structure includes a wafer having a first surface with a first texture, a second surface opposite the first surface, the second surface having a first portion with a second texture and a second portion connected to the first portion, a first pole region in contact with the first portion of the second surface, and a second pole region spaced apart from the first pole region and adjacent to the second portion of the second surface, the first texture being selected from the group consisting of an alkali polished texture, an acid polished texture, a micro ... Rote The second texture is one of an alkali polished texture, an acid polished texture, a micro polished texture, and an inverted pyramid texture. Rote texture, or an inverted pyramid texture, where the first texture and the second texture are the same.

[0027] In some embodiments of the present application, the inverted pyramid texture has a reflectance of about 2% to 15%.

[0028] One embodiment of the present application provides a method of fabricating a charge storage structure, comprising the steps of depositing an oxide layer on a backside of a wafer, depositing a semiconductor layer on the oxide layer to cover the oxide layer, depositing a mask layer on the semiconductor layer to cover the semiconductor layer, and depositing a mask layer on the semiconductor layer to cover the semiconductor layer. Ruma and forming a first opening by removing a portion of the mask layer.

[0029] In some embodiments of the present application, the front side of the wafer opposite the back side has a second opening exposed through the mask layer, the semiconductor layer, and the oxide layer.

[0030] In some embodiments of the present application, the method of manufacturing a charge storage structure further comprises performing a surface texturing process on the area where the first opening and the front side of the wafer are located.

[0031] In some embodiments of the present application, the method of fabricating a charge storage structure further comprises depositing an oxide layer on a side surface of the wafer located between the front surface and the back surface.

[0032] In some embodiments of the present application, the method of manufacturing a charge storage structure further comprises removing the mask layer and the semiconductor layer located on the front and side of the wafer before performing the surface texturing process.

[0033] In some embodiments of the present application, the method of fabricating a charge storage structure further comprises removing the oxide layer located on the front and side of the wafer and the mask layer on the back of the wafer.

[0034] In some embodiments of the present application, the method of manufacturing a charge storage structure further includes depositing a first passivation layer on the front and back surfaces, depositing a second passivation layer on the first passivation layer to cover the first passivation layer, and removing a portion of the first passivation layer and a portion of the second passivation layer on the back surface of the wafer from the first opening to form a third opening exposing the wafer.

[0035] In some embodiments of the present application, the method of manufacturing the charge storage structure further includes forming a first contact in the third opening and performing a co-firing process to form a first region adjacent to the first contact and in contact with the wafer.

[0036] In some embodiments of the present application, the method of manufacturing the charge storage structure further includes forming a second contact in an area outside the third opening and performing a co-firing process to enable the second contact to pass through the second passivation layer and the first passivation layer and connect to the semiconductor layer.

[0037] In some embodiments of the present application, the oxide layer is deposited using plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD).

[0038] In some embodiments of the present application, the semiconductor layer is deposited using PECVD or PEALD.

[0039] In some embodiments of the present application, the mask layer is deposited using PECVD or PEALD.

[0040] In some embodiments of the present application, the semiconductor layer comprises a Group IV element.

[0041] In some embodiments of the present application, the semiconductor layer comprises a Group V element.

[0042] In some embodiments of the present application, the semiconductor layer comprises phosphorus.

[0043] In some embodiments of the present application, the mask layer is selected from aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0044] In some embodiments of the present application, the method of manufacturing a charge storage structure further comprises performing an annealing process after depositing the mask layer.

[0045] In some embodiments of the present application, the first opening is formed using a laser process.

[0046] In some embodiments of the present application, a portion of the passivation layer in the first opening is removed using a laser process to form a third opening.

[0047] In some embodiments of the present application, the first passivation layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0048] In some embodiments of the present application, the second passivation layer is deposited using PECVD, ALD, or CVD.

[0049] Compared with the conventional charge storage structure, the charge storage structure provided by the embodiment of the present application provides higher production efficiency with lower production cost, and is excellent in quality and product yield. Moreover, compared with the conventional method for manufacturing the charge storage structure, the method for manufacturing the charge storage structure provided by the embodiment of the present application requires fewer production steps, which reduces the number of required manufacturing equipment, reduces the process difficulty, saves some production materials, and improves product yield. Therefore, it not only effectively improves production efficiency, but also improves quality while lowering production cost.

[0050] In order to facilitate the description of the embodiments of the present application, the accompanying drawings necessary for describing the embodiments of the present application or the prior art are briefly described below. It is clear that the accompanying drawings in the following description only show some embodiments of the present application. Those skilled in the art can obtain drawings of other embodiments based on the structures shown in these accompanying drawings without creative work. In addition, the accompanying drawings disclosed in this specification are for illustrative purposes only and do not show the structures in the embodiments of the present application in exact proportions. [Brief description of the drawings]

[0051] [Figure 1] 1 is a schematic cross-sectional view of a charge storage structure according to an embodiment of the present application; [Diagram 2] 2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Diagram 3] 1 is a schematic cross-sectional view of a charge storage structure according to yet another embodiment of the present application; [Figure 4] 2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Diagram 5] 1 is a schematic cross-sectional view of a charge storage structure according to yet another embodiment of the present application; [Figure 6]2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Figure 7] 1 is a schematic cross-sectional view of a charge storage structure according to yet another embodiment of the present application; [Figure 8] 2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Figure 9] 1 is a schematic cross-sectional view of a charge storage structure according to yet another embodiment of the present application; [Figure 10] 2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Figure 11] 1 is a schematic cross-sectional view of a charge storage structure according to yet another embodiment of the present application; [Figure 12] 1 is a schematic cross-sectional view of a charge storage structure according to the prior art; [Figure 13] 2 is a schematic cross-sectional view of a charge storage structure according to another embodiment of the present application; [Figure 14] 1 is a flow chart of a method for fabricating a charge storage structure according to an embodiment of the present application. [Figure 15A] ~ [Figure 15G] 15A-15C are schematic cross-sectional views of a charge storage structure as shown in FIG. 13 at different stages of manufacture by a method as shown in FIG. 14; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] The embodiments of the present application are described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are indicated by the same reference numerals. The embodiments described in this specification in conjunction with the accompanying drawings are exemplary and illustrated, and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

[0053] As used herein, the terms "about", "substantially" and "essentially" are used to describe and explain minor differences. When used with an event or circumstance, the term may refer to the exact occurrence of the event or circumstance, and to the approximate occurrence of the event or circumstance. For example, when used with a numerical value, the term may refer to a variation range of the numerical value of ±10% or less, such as a variation range of ±5% or less, ±0.5% or less, or ±0.05% or less. For example, two numerical values ​​may be considered to be "substantially" the same if the difference between the two numerical values ​​is ±10% or less of their average value.

[0054] Moreover, for ease of description, terms such as "first," "second," "third," etc. may be used in the specification to distinguish between different elements in a figure or series of figures. "First," "second," "third," etc. are not intended to describe corresponding elements.

[0055] In this application, unless otherwise specified or limited, the terms "dispose," "connect," "couple," "fix," and similar terms are used broadly, and those skilled in the art will understand the terms to mean, depending on the particular context, a fixed, detachably connected, or integrally connected connection. There may also be a mechanical or electrical connection. There may also be a direct connection or an indirect connection through an intermediate structure. There may also be internal communication between two components.

[0056] The present application provides a novel charge storage structure that provides higher quality at lower manufacturing costs.

[0057] FIG. 1 is a schematic cross-sectional view of a charge storage structure 10 according to one embodiment of the present application.

[0058] 1, a charge storage structure 10 according to an embodiment of the present application may include a wafer 101, a pole region 103, a pole region 105, an oxide layer 107, a semiconductor layer 109, a passivation layer 111, and a passivation layer 113. The charge storage structure 10 may be, for example, but not limited to, an interdigital back contact (IBC) solar cell.

[0059] The wafer 101 may have a surface 101a, a surface 101b opposite to the surface 101a, and a surface 101c located between the surfaces 101a and 101b. The wafer 101 may be, for example, but not limited to, a p-type c-Si wafer. The wafer 101 may be any suitable type of wafer. The surface 101a may have a texture. The texture is obtained by performing a texturing process on the surface of the silicon wafer. A good texture structure can reduce solar reflectance, increase light absorption, improve features such as surface passivation and electrode contact, and therefore increase the collection efficiency of charge carriers. The texture of the surface 101a may be a pyramidal texture. The pyramidal texture may have a substantially irregular triangular structure. The large contact area between the pyramidal texture and the metal increases the effective metallization area. However, it is quite difficult to ensure the film uniformity of the deposited passivation layer during the deposition of the passivation layer on the pyramidal texture. The pyramid texture may reflect sunlight twice. Different processes may form pyramid textures with different reflectances. The pyramid texture may have a reflectance of, for example, but not limited to, about 5%-20%, about 5%-10%, about 6%-11%, about 10%-15%, about 15%-20%. The texture of the surface 101a may be a pyramid texture, an alkali polished texture, an acid polished texture, a micro polished texture, or the like. RoteThe alkali polished texture may be one of a pyramid texture, an inverted pyramid texture, and a pyramid texture. The alkali polished texture may exhibit a substantially flat surface. The substantially flat surface of the alkali polished texture is suitable for the deposition of a passivation layer, but not for the formation of metal contacts. The substantially flat alkali polished texture has a smaller contact area with metal than the pyramid texture or the inverted pyramid texture. Furthermore, the flat surface allows for easier diffusion of the metal, resulting in a larger area of ​​final metal contact. The reflectance of the alkali polished texture is greater than about 40%. The acid polished texture may exhibit a surface with multiple continuous curved structures. The acid polished texture may have a reflectance of about 30% to 35%. Micro Rote The texture may be a surface having both an alkali-polished shape and a pyramidal shape. Rote The texture combines the advantages of the pyramidal texture and the alkaline polishing texture, which not only enlarges the effective metallization area but also ensures the film uniformity when depositing the passivation layer. Rote The inverted pyramid texture may have a reflectance of about 10% to 15%. The inverted pyramid texture may exhibit a substantially inverted pyramid shape. The inverted pyramid texture may reflect sunlight three times. The inverted pyramid texture has a higher light trapping ability and carries a higher current than the pyramid texture. The metallized printed inverted pyramids can be designed with smaller line widths and better height to width ratios, which can increase the efficiency of the battery due to better contact with the metal. The inverted pyramid texture may have a reflectance of, for example, but not limited to, about 2% to 15%, about 2% to 10%, about 5% to 10%, about 8% to 10%, about 10% to 12%, about 10% to 15%. The reflectance of the inverted pyramid texture with nanocolumn shape may be low. In order to further reduce the reflectance of sunlight and absorb as much sunlight as possible, the texture of the surface 101a may be preferably a pyramid texture or an inverted pyramid texture.

[0060] The surface 101b may include a first portion 1011b and a second portion 1012b connected to the first portion 1011b. The first portion 1011b may have a texture. The texture of the first portion 1011b may be an alkali polished texture. The texture of the first portion 1011b may be different from the texture of the surface 101a. The texture of the first portion 1011b may be an acid polished texture, a micro polished texture, or a micro polished texture. Rote The texture of the first portion 1011b may be one of an alkali polished texture, an acid polished texture, or an inverted pyramid texture. The second portion 1012b of the surface 101b may be a flat surface. The texture of the first portion 1011b is preferably an alkali polished texture, an acid polished texture, or an inverted pyramid texture. Rote The texture of the first portion 1011b may be the same as the texture of the surface 101a. The texture of the surface 101a and the texture of the first portion 1011b of the surface 101b may be flexibly set according to specific needs to meet different product requirements.

[0061] The pole region 103 may be formed to contact the first portion 1011b of the surface 101b. The pole region 103 may include a metal contact 103a and a region 103b connected to the metal contact 103a. The metal contact 103a may be, for example, but not limited to, aluminum. The metal contact 103a may be set using a conventional screen printing process or any suitable process. The metal contact 103a may be a base contact. In other embodiments of the present application, the metal contact 103a may include any suitable material. The region 103b may be N + Polar region, or P + Region 103b may be a pole region. Region 103b may be formed by performing a co-firing process to treat the portion adjacent to metal contact 103a and in contact with wafer 101. Region 103b may be free of boron.

[0062] The pole region 105 may be spaced apart from the pole region 103 and is formed adjacent the second portion 1012b of the surface 101b. The pole region 105 may include a metal contact 105a. The metal contact 105a may be formed by contacting the passivation layer 102b. 113 , and a passivation layer 111 The metal contact 105a is connected to the semiconductor layer 109 through an opening. The metal contact 105a may be, for example, but not limited to, a silver paste or a silver aluminum paste. The metal contact 105a may be an emitter contact. The metal contact 105a may be set using a conventional screen printing process or any suitable process. In other embodiments of the present application, the metal contact 105a may comprise any suitable material. The metal contact 105a may be connected to the semiconductor layer 109 without passing through an opening. The silver paste or silver aluminum paste is corrosive and may cause the passivation layer to form during co-firing. 113 and passivation layer 111 , and may be connected to the wafer 101. Thus, in order to connect the silver paste or silver-aluminum paste to the wafer 101, the passivation layer 113 and passivation layer 111 It is not necessary to first form an opening in the metal contact 105a. The metal contact 105a and the metal contact 103a may be located on different horizontal planes.

[0063] An oxide layer 107 may cover the second portion 1012b of the surface 101b of the wafer 101. The oxide layer 107 may be, for example, but not limited to, SiO 2 having a thickness of less than 5 nanometers. x The oxide layer 107 may be a tunnel oxide layer. The oxide layer 107 may be any suitable type of oxide layer. The oxide layer 107 may be deposited using plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD). The PEALD process may be performed at a temperature in the range of approximately 100° C. to 500° C. to form the oxide layer 107. The oxide layer 107 may be a tunnel oxide layer.

[0064] A semiconductor layer 109 may cover the oxide layer 107. The semiconductor layer 109 may include a group IV element. The semiconductor layer 109 may include a group V element. The semiconductor layer 109 may include, for example, but not limited to, phosphorus. The semiconductor layer 109 may include, for example, but not limited to, in-situ doped phosphorus. The semiconductor layer 109 may include, for example, but not limited to, phosphine (PH 3 ). Semiconductor layer 109 may be any suitable type of semiconductor layer. Semiconductor layer 109 may be a polysilicon layer. Semiconductor layer 109 may be deposited using PECVD or PEALD. The PECVD process may be performed at a temperature in the range of approximately 100° C. to 500° C. to form semiconductor layer 109.

[0065] The passivation layer 111 may cover the surface 101a of the wafer 101, the first portion 1011b of the surface 101b, the surface 101c between the surfaces 101a and 101b, the side 107a of the oxide layer 107, and the side 109a of the semiconductor layer 109. In another embodiment of the present application, the passivation layer 111 may cover the surface 101a, the first portion 1011b of the surface 101b, the side 107a of the oxide layer 107, and the side 109a of the semiconductor layer 109. The passivation layer 111 located at the first portion 1011b of the surface 101b may have an opening 111a. After the co-firing process is performed, the metal contact 103 The region 103b is formed by connecting the region 103a to the wafer 101 through the opening 111a. The passivation layer 111 may be made of, for example, but is not limited to, AlO x The passivation layer 111 can be, for example, but not limited to, an Al 2 O 3 The passivation layer 111 may be any suitable type of oxide layer. The passivation layer 111 may be SiO x The passivation layer 111 may be a SiO x layer and Al 2 O 3 The layer may be laminated with a SiO xThe layer may be relatively thin, for example, having a thickness of about 2 nm or less. The passivation layer 111 may be deposited using ALD, CVD, or any suitable process. The passivation layer 111 deposited on both sides (i.e., surface 101a and surface 101b) can solve the problem of wrap plating caused by deposition on only one side.

[0066] A passivation layer 113 may cover the passivation layer 111. The passivation layer 113 located on the first portion 1011b of the surface 101b may have an opening 113a. The opening 111a communicates with the opening 113a. The metal contact 103a of the pole region 103 passes through the opening 111a and the opening 113a. The passivation layer 113 may be made of, for example, but not limited to, SiN x layer, SiO x layer, SiON layer, or SiN x layer, SiO x The passivation layer 113 may be any combination of a nitride layer, a SiO 2 layer, and a SiON layer. The passivation layer 113 may be any suitable type of nitride layer. The passivation layer 113 may be deposited using ALD, CVD, PECVD, PEALD, or any suitable process to cover the passivation layer 111. The passivation layer 113 may be an anti-reflective layer. The passivation layer 113 may provide additional hydrogen passivation to the passivation layer 111.

[0067] As shown in Figure 1 of the present application, the charge storage structure 10 does not contain boron, which results in lower manufacturing costs. No high temperature boron diffusion process is used, and no boron diffusion wrap is used. -Around Plating (wrap-around plating) There is no need to perform a wet process to remove the product. Furthermore, the key layers of the device, the oxide layer, the semiconductor layer, and the mask layer, can be deposited sequentially in a process tube without breaking vacuum by using a new tool that combines two deposition techniques, PEALD and PECVD, in one process tube. This reduces the number of manufacturing devices required. SignificantlyIt reduces the heat generation, eases the process difficulty, saves some production materials, reduces the manufacturing cost, and realizes the back cross contact in a very simple way. Meanwhile, since the boron diffusion process is not used, the maximum temperature that the wafer needs to withstand during the whole manufacturing of the charge storage structure (the temperature of the boron diffusion process is about 1000°C to 1200°C) is greatly reduced. This can reduce the problem of the wafer 101 warping due to high temperature, increase the product yield of the charge storage structure 10, and save the energy consumption. Moreover, the oxide layer 107 and the semiconductor layer 109 are manufactured using the PEALD or PECVD process. It can well control the thickness of the oxide layer 107, guarantee the uniformity, reproducibility, and stability of the oxide layer 107, and significantly improve the deposition rate of the semiconductor layer 109. Although the lap plating of the semiconductor layer 109 cannot be completely prevented by depositing the semiconductor layer 109 using the PEALD or PECVD process, it can reduce the extent of the lap plating of the semiconductor layer 109. By limiting the range in which plasma is generated, It can be made smaller to a certain extent, which can increase production efficiency and yield to a certain extent, and reduce technical bottlenecks in low pressure chemical vapor deposition (LPCVD) technology, such as tube breakage that frequently occurs due to polysilicon deposition on the quartz tube wall. Therefore, the charge storage structure 10 shown in FIG. 1 of the present application can bring higher quality and production efficiency with lower manufacturing cost.

[0068] In addition, the texture on the wafer surface 101a of the charge storage structure 10 shown in Figure 1 of the present application can be the same or different from the texture on the wafer surface 101b, which allows those skilled in the art to flexibly design the charge storage structure 10 based on factors such as product performance and manufacturing cost to meet the requirements of different markets.

[0069] 2 is a schematic vertical cross-sectional view of a charge storage structure 20 according to another embodiment of the present application. As shown in FIG 2, the difference between the charge storage structure 20 according to an embodiment of the present application and the charge storage structure 10 shown in FIG 1 is that the texture of the first portion 1011b of the surface 101b of the charge storage structure 20 is an acid polished texture.

[0070] 3 is a schematic vertical cross-sectional view of a charge storage structure 30 according to another embodiment of the present application. As shown in FIG. 3, the difference between the charge storage structure 30 according to an embodiment of the present application and the charge storage structure 10 shown in FIG. 1 is that the texture of the first portion 1011b of the surface 101b in the charge storage structure 30 is a microstructure including a substantially flat portion and a pyramidal portion. Rote It has become a cultural thing.

[0071] 4 is a schematic vertical cross-sectional view of a charge storage structure 40 according to another embodiment of the present application. As shown in FIG 4, the difference between the charge storage structure 40 according to an embodiment of the present application and the charge storage structure 10 shown in FIG 1 is that the texture of the first portion 1011b of the surface 101b of the charge storage structure 40 is an inverted pyramid texture.

[0072] Fig. 5 is a schematic cross-sectional view of a charge storage structure 50 according to another embodiment of the present application. As shown in Fig. 5, the difference between the charge storage structure 50 according to an embodiment of the present application and the charge storage structure 10 shown in Fig. 1 is that the texture of the surface 101a of the charge storage structure 50 is an inverted pyramid texture, and the texture of the first portion 1011b of the surface 101b is an inverted pyramid texture.

[0073] Fig. 6 is a schematic vertical cross-sectional view showing a charge storage structure 60 according to another embodiment of the present application. As shown in Fig. 6, the difference between the charge storage structure 60 according to an embodiment of the present application and the charge storage structure 50 shown in Fig. 5 is that the texture of the first portion 1011b of the surface 101b of the charge storage structure 60 is a pyramidal texture.

[0074] 7 is a schematic vertical cross-sectional view showing a charge storage structure 70 according to another embodiment of the present application. As shown in FIG 7, the difference between the charge storage structure 70 according to an embodiment of the present application and the charge storage structure 50 shown in FIG 5 is that the texture of the first portion 1011b of the surface 101b of the charge storage structure 70 is an alkali polishing texture.

[0075] 8 is a schematic vertical cross-sectional view of a charge storage structure 80 according to another embodiment of the present application. As shown in FIG 8, the difference between the charge storage structure 80 according to an embodiment of the present application and the charge storage structure 50 shown in FIG 5 is that the texture of the first portion 1011b of the surface 101b of the charge storage structure 80 is an acid polished texture.

[0076] 9 is a schematic vertical cross-sectional view of a charge storage structure 90 according to another embodiment of the present application. As shown in FIG. 9, the difference between the charge storage structure 90 according to an embodiment of the present application and the charge storage structure 50 shown in FIG. 5 is that the texture of the first portion 1011b of the surface 101b in the charge storage structure 90 is a microstructure including a substantially flat portion and a pyramidal portion. Rote It has become a cultural thing.

[0077] Fig. 10 is a schematic cross-sectional view of a charge storage structure 1000 according to another embodiment of the present application. As shown in Fig. 10, the difference between the charge storage structure 1000 according to an embodiment of the present application and the charge storage structure 10 shown in Fig. 1 is that the texture of the surface 101a of the charge storage structure 1000 is an acid-polished texture, and the texture of the first portion 1011b of the surface 101b is an acid-polished texture.

[0078] 11 is a schematic vertical cross-sectional view of a charge storage structure 1100 according to another embodiment of the present application. As shown in FIG. 11, the difference between the charge storage structure 1100 according to an embodiment of the present application and the charge storage structure 10 shown in FIG. 1 is that the texture of the surface 101a of the charge storage structure 1100 is a micro-texture. Rote The texture of the first portion 1011b of the surface 101b is Rote It has become a cultural thing.

[0079] The texture of the surface 101a and the texture of the surface 101b of the wafer of the charge storage structure according to the embodiment of the present application can be flexibly set as needed to meet different product requirements.

[0080] Figure 12 shows Prior Art Charge storage structure Construction FIG.

[0081] As shown in FIG. Prior Art Charge storage structure 1200 The figure shows a wafer 201, an n-type region 203 disposed on the front surface 201a of the wafer 201, and a SiN x Layer 205, P disposed on the back surface 201b of wafer 201 + Region 207, N + Area 209, N + Area 209 to P + A surface passivation layer 211, P, which separates the regions 207 + A metal contact 213 connected to region 207, and a N + There may be a metal contact 215 connected to the region 209 .

[0082] P + Region 207 may include a p-type dopant source, such as boron. + During the formation of region 207, a p-type dopant source, such as a printable boron slurry, must be deposited as a strip on the back surface 201b of wafer 201. The wafer 201 is then placed in a diffusion furnace preheated to about 900° C. to 1400° C. to carry out the process of diffusing boron into wafer 201 by facilitating the diffusion of boron through back surface 201b. + Region 207 is formed. In another embodiment, P +Region 207 is formed by depositing a p-type material layer followed by an ion implantation process, after which an annealing process is required for repair.

[0083] N + Region 209 may include an n-type dopant, such as phosphorus. + After the region 207 is formed, N + Region 209 is formed. That is, The temperature of the diffusion furnace is Approximately 850℃~900℃ Entered Then, the phosphorus diffusion process into the wafer 201 is accomplished by switching on the device at a rate that reaches the phosphorus doped profile. + Region 209 is formed by depositing a layer of n-type material followed by an ion implantation process, after which an annealing process is required for repair.

[0084] The charge storage structure shown in FIG. 1200 has a boron diffusion region 207, and equipment that requires a high temperature boron diffusion process during manufacturing and equipment that requires a wet process to remove the wrap plating formed by the boron diffusion.

[0085] The charge storage structure of the present application can bring about higher production efficiency and quality with fewer manufacturing steps and energy consumption, and lower cost, and can meet the requirements for mass production and expand the market potential. In addition, the charge storage structure of the present application can form different textures on the front and back of the wafer, taking into account the product requirements and manufacturing costs. In addition, the present application uses an ALD deposition process to deposit the passivation layer, which can ensure the film uniformity and shape retention when depositing the passivation layer, so that the charge storage structure that can set each texture has high quality.

[0086] The present application provides a novel method for manufacturing a charge storage structure, which can manufacture the charge storage structure more simply and efficiently at low cost, even under the premise that the quality of the charge storage structure is not reduced, but the quality of the charge storage structure is further improved.

[0087] FIG. 13 is a schematic cross-sectional view of a charge storage structure 1300 according to another embodiment of the present application.

[0088] 13, a charge storage structure 1300 according to an embodiment of the present disclosure may include a wafer 301, an oxide layer 303, a semiconductor layer 305, a passivation layer 307, a passivation layer 309, a contact 311, a first region 313, and a contact 315. The charge storage structure 1300 may include, for example, but is not limited to, an IBC solar cell.

[0089] The wafer 301 may have a front surface 301a, a back surface 301b opposite the front surface 301a, and a side surface 301c located between the front surface 301a and the back surface 301b. The wafer 301 may be, for example, but not limited to, a p-type c-Si wafer. The wafer 301 may be any suitable type of wafer. The front surface 301a may include a pyramidal portion. The pyramidal shape may have a substantially irregular triangular structure. The front surface 301a may have an alkali-polished shape (i.e., may have a substantially flat surface), an acid-polished shape (i.e., may have a surface having a plurality of continuous curved structures), a microstructure, or a surface having a plurality of continuous curved structures. Texture The back surface 301b may have any shape. The back surface 301b may have a pyramidal portion 3011b and a flat portion 3011b. 3013b In other embodiments of the present application, the pyramid portion 3011b may include an alkali polished shape, an acid polished shape, a micro polished shape, and a micro polished shape. Texture The shape may be one of a rectangular shape, a rectangular shape, and an inverted pyramid shape.

[0090] The oxide layer 303 is formed on the flat portion 3013 of the back surface 301b of the wafer 301. b The oxide layer 303 may be, for example, but not limited to, SiO 2 having a thickness of less than 5 nanometers. x The oxide layer 303 may be a tunnel oxide layer. The oxide layer 303 may be any suitable type of oxide layer. The oxide layer 303 may be deposited using plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD). The PEALD process may be performed at a temperature in the range of approximately 100° C. to 500° C. to form the oxide layer 303. The oxide layer 303 may be a tunnel oxide layer.

[0091] A semiconductor layer 305 may be disposed on the oxide layer 303. The semiconductor layer 305 may include a group IV element. The semiconductor layer 305 may include a group V element. The semiconductor layer 305 may include, for example, but not limited to, phosphorus. The semiconductor layer 305 may include, for example, but not limited to, in situ doped phosphorus. The semiconductor layer 305 may include, for example, but not limited to, phosphine (PH 3 ). Semiconductor layer 305 may be any suitable type of semiconductor layer. Semiconductor layer 305 may be a polysilicon layer. Semiconductor layer 305 may be deposited using PECVD or PEALD. The PECVD process may be performed at a temperature in the range of approximately 100° C. to 500° C. to form semiconductor layer 305.

[0092] A passivation layer 307 may cover the pyramid portions 3011b, the oxide layer 303, and the semiconductor layer 305 on the front side 301a, the side 301c, and the back side 301b of the wafer 301. The passivation layer 307 may be formed of, for example, but not limited to, AlO x The passivation layer 307 can be, for example, but not limited to, an Al 2 O 3 The passivation layer 307 may be any suitable type of oxide layer. The passivation layer 307 may be SiO x The passivation layer 307 may be a SiOx layer and Al 2 O 3 The layer may be laminated with a SiO x The layer may have a relatively thin thickness, for example, about 2 nm or less. The passivation layer 307 may be deposited using ALD, CVD, or any suitable process. A passivation layer 307 deposited on both sides (i.e., the front side 301a and the back side 301b) can solve the problem of lap plating caused by deposition on only one side.

[0093] A passivation layer 309 may cover the passivation layer 307. The passivation layer 309 may be made of, for example, but not limited to, SiN x layer, SiO x layer, SiON layer, or SiN x layer, SiO x The passivation layer 309 may be any combination of a nitride layer, a SiON layer, and a SiON layer. The passivation layer 309 may be any suitable type of nitride layer. The passivation layer 309 may be deposited using ALD, CVD, PECVD, PEALD, or any suitable process to cover the passivation layer 307. The passivation layer 309 may be an anti-reflective layer. The passivation layer 309 may provide additional hydrogen passivation to the passivation layer 307.

[0094] A contact 311 is connected to the first region 313. The contact 311 may be, for example, but not limited to, aluminum. The contact 311 may be set using a conventional screen printing process or any suitable process. The contact 311 may be a base contact. In other embodiments of the present application, the contact 311 may include any suitable material.

[0095] The first region 313 may be connected to the contact 311. The first region 313 may be formed by performing a co-firing process to treat the portion adjacent to the contact 311 and in contact with the wafer 301. The first region 313 may be formed of P+ The first region 313 may be an N + The first region 313 does not include boron.

[0096] The contact 315 is a passivation layer 309 , and a passivation layer 307 311 to connect to the semiconductor layer 305. The contact 315 may be, for example, but not limited to, a silver paste or a silver aluminum paste. The contact 315 may be an emitter contact. The contact 315 may be set using a conventional screen printing process or any suitable process. In other embodiments of the present application, the contact 315 may comprise any suitable material. The contacts 315 and 311 may be located on different horizontal planes.

[0097] Figure of the present application 13 As shown, the charge storage structure 1300 does not contain boron, so there is no need to use a high temperature boron diffusion process and no need to perform a wet process to remove the boron diffusion wrap plating product. Furthermore, the key layers of the device, the oxide layer, the semiconductor layer, and the mask layer, can be deposited sequentially in a process tube without breaking vacuum by using a new tool that combines two deposition techniques, PEALD and PECVD, in one process tube. This reduces the number of manufacturing devices required. Significantly This reduces the number of steps, eases the process difficulty, saves some production materials, reduces the manufacturing cost, and realizes the back cross contact in a very simple way. On the other hand, since the boron diffusion process is not used, the maximum temperature that the wafer needs to withstand during the entire manufacturing of the charge storage structure (the temperature of the boron diffusion process is about 1000℃~1200℃) is significantly reduced. This can reduce the problem of wafer 301 warping due to high temperature, increase the product yield of charge storage structure 1300, and save energy consumption. Moreover, oxide layer 303 and semiconductor layer 305 are fabricated using PEALD or PECVD process. The thickness of oxide layer 303 can be well controlled, the uniformity, reproducibility and stability of oxide layer 303 can be guaranteed, the deposition rate of semiconductor layer 305 can be significantly improved, and the problem of lap plating can be greatly improved. Although the lap plating of semiconductor layer 305 cannot be completely prevented by depositing semiconductor layer 305 using PEALD or PECVD process, Because the area where plasma is generated is limited, The extent of lap plating of the semiconductor layer 305 can be reduced to a certain extent, which can improve production efficiency and yield to a certain extent and reduce technical bottlenecks in low pressure chemical vapor deposition (LPCVD) technology, such as frequent tube breakage caused by depositing polysilicon on the quartz tube wall. 13 The charge storage structure 1300 shown in Figure 13 results in higher quality and production efficiency at lower manufacturing costs.

[0098] FIG. 14 is a flow chart of a method for fabricating a charge storage structure according to one embodiment of the present application.

[0099] Referring to block 401, a wafer may be provided. The wafer may be subjected to a polishing process. The wafer may be subjected to a cleaning process. The cleaning process on the wafer may be performed after the polishing process.

[0100] Referring to block 402, an oxide layer may be deposited. The oxide layer may be deposited on a surface of the wafer. The oxide layer may be deposited on a front surface of the wafer. The oxide layer may be deposited on a back surface of the wafer opposite the front surface. The oxide layer may be deposited on a side surface of the wafer extending from the front surface to the back surface. The oxide layer may be deposited on the front, back, and side surfaces of the wafer. The oxide layer may be deposited on the back surface of the wafer. The oxide layer deposited on the back surface of the wafer may be lap plated on a portion of the side surface and a portion of the front surface, and the front surface of the wafer may include an opening exposed from the oxide layer. The opening may be in preparation for later texturing the wafer. The oxide layer may be deposited using PECVD or PEALD. The PEALD process may be performed at a temperature in the range of, for example, but not limited to, about 100° C. to 500° C. to form the oxide layer. The oxide layer may be formed of, for example, but not limited to, SiO 2 having a thickness of less than 5 nanometers. x It may be a layer.

[0101] Referring to block 403, a semiconductor layer may be deposited. The semiconductor layer may be deposited over the oxide layer to prepare for subsequent formation of the backside region and connection with the contacts. The semiconductor layer may be deposited using PECVD or PEALD. The PEALD process may be performed at a temperature ranging from, for example, but not limited to, about 100° C. to 500° C. to form the semiconductor layer. The semiconductor layer deposited on the oxide layer on the backside of the wafer may be lap plated onto a portion of the side and a portion of the front. The semiconductor layer may include a group IV element. The semiconductor layer may include a group V element. The semiconductor layer may include, for example, but not limited to, phosphorus. The semiconductor layer may include, for example, but not limited to, in situ doped phosphorus. The semiconductor layer 305 may be doped with, for example, but not limited to, phosphine (PH 3 The semiconductor layer may be any suitable type of semiconductor layer. , S It may be a recon layer.

[0102] Referring to block 404, a mask layer may be deposited. A mask layer may be deposited on the semiconductor layer to cover the semiconductor layer. The mask layer may be deposited using PECVD or PEALD. The mask layer deposited on the semiconductor layer on the back side of the wafer may be lap plated onto a portion of the side and a portion of the front side. The mask layer may be selected from, for example, but not limited to, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0103] Openings in the front side of the wafer may be exposed through the oxide layer, the semiconductor layer, and the mask layer.

[0104] In other embodiments, the oxide layer, the semiconductor layer, and the mask layer may be deposited in sequence over the backside and frontside of the wafer. The oxide layer, the semiconductor layer, and the mask layer can be deposited successively in a process tube without breaking vacuum by using a new tool that combines two deposition techniques, PEALD and PECVD, in one process tube.

[0105] Referring to block 405, an annealing process may be performed. The annealing process changes the crystal structure of the semiconductor layer (such as amorphous silicon or a mixture of amorphous silicon and polysilicon). adjustment An annealing process may be carried out to 3 doping but activation And , semiconductor layer 305 No. The silicon layer may be converted to a polysilicon layer. The phosphorus doped polysilicon layer may then be doped with N + In certain embodiments, an annealing process is performed to Semiconductor layer The crystallinity can be greater than about 80%. In some other embodiments, an annealing process is performed to Semiconductor layer The crystallinity can be from about 88% to about 90%.

[0106] Referring to block 406, an opening may be formed on the back side of the wafer. A portion of the oxide layer, a portion of the semiconductor layer, and a portion of the mask layer on the back side of the wafer may be removed to form the opening on the back side of the wafer. A portion of the oxide layer, a portion of the semiconductor layer, and a portion of the mask layer may be removed using a laser process to form the opening on the back side of the wafer. A portion of the oxide layer, a portion of the semiconductor layer, and a portion of the mask layer may be removed using any suitable process to form the opening on the back side of the wafer. In some embodiments, preferably a portion of the mask layer on the backside of the wafer is removed to form an opening. This opening may be in preparation for later texturing the back side of the wafer.

[0107] Referring to block 407, / inline The semiconductor layers lap-plated on the sides and front can be exposed by removing the front and side mask layers using HF acid in a mold wet process tool.

[0108] The semiconductor layer on the front and sides of the wafer may then be removed. The semiconductor layer may be removed using a suitable chemical reagent. The semiconductor layer on the sides and front may be removed using a suitable chemical reagent. cassette Using a type wet process apparatus, for example, but not limited to, HNO 3 The chemicals may be removed by chemical reagents and additives such as HCl, KOH, or NaOH. Due to the protection of the mask layer, the semiconductor layer on the back side of the wafer is not affected. / inline Mold wet process equipment cassette Through automated connection to mold wet process equipment, the steps of removing the mask layer and removing the semiconductor layer can be completed efficiently and conveniently.

[0109] The oxide layer on the sides and front of the wafer may then be removed. The oxide layer may be removed using any suitable process or suitable chemical reagent.

[0110] Next, surface texturing GupA surface texturing process may be performed on the wafer areas exposed by the openings on both the front and back sides of the wafer simultaneously. After the surface texturing process is performed, the areas of the wafer not covered by the oxide and semiconductor layers on the front and back sides may have a pyramidal shape. In other embodiments, the areas of the wafer not covered by the oxide and semiconductor layers on the front and back sides may have an alkali polished shape, an acid polished shape, a micro polished shape, or a pyramidal shape. Texture The surface texturing process may be performed to repair damage caused by the laser process for forming the openings on the backside of the wafer. S To carry out, a chemical solution (acid or alkali) may be used. For example, in some embodiments, a pyramid texture may be obtained by alkali treatment. For example, in other embodiments, a wormhole-like texture may be obtained by acid treatment. Regardless of the type of texture, the light trapping effect of the wafer (silicon wafer) can be enhanced. In other embodiments, the surface texturing process can be applied to the front and back of the wafer respectively, so that the front of the wafer and the back of the wafer may have different texture shapes. According to actual needs, the surface texturing process may be carried out on the front of the wafer first, or the surface texturing process may be carried out on the back of the wafer first.

[0111] The remaining mask layer on the front side of the wafer may then be removed. The mask layer on the back side of the wafer may then be removed. The mask layer may be: cassette The metal may be removed using HF acid in a wet process tool.

[0112] The order of removing the mask layer, the oxide layer and the semiconductor layer during surface texturing may be flexibly adjusted according to actual needs.

[0113] The surface of the wafer may then be cleaned to provide a high quality and clean sample for subsequent deposition.

[0114] Referring to block 408, a first passivation layer may be deposited. The first passivation layer may be deposited on the front and back sides of the wafer. The first passivation layer may be deposited using ALD, CVD, or any suitable process. The first passivation layer deposited on both sides (i.e., the front and back) can solve the problem of lap plating caused by deposition on only one side. The formed first passivation layer may be deposited on the front, side, and back sides of the wafer. 、 and 、 The pyramids on the back surface, the oxide layer and the semiconductor layer can be covered. The first passivation layer is AlO x The first passivation layer can be, for example, but not limited to, Al 2 O 3 The first passivation layer may be any suitable type of oxide layer. The first passivation layer may be SiO x The first passivation layer may be a SiO x The first passivation layer may be a laminate of a SiO 2 layer and an aluminum oxide layer. The ALD deposition process is used to deposit the first passivation layer, thereby improving the film uniformity during deposition of the first passivation layer, and Conformality Therefore, the charge storage structure capable of setting various textures has high quality.

[0115] A second passivation layer may then be deposited. The second passivation layer may be deposited on the first passivation layer to cover the first passivation layer. The second passivation layer may be deposited using ALD, CVD, PECVD, PEALD, or any suitable process to cover the first passivation layer. The second passivation layer may be, for example, but not limited to, SiN x layer, SiO xlayer, SiON layer, or SiN x layer, SiO x The second passivation layer may be any combination of a nitride layer, a SiOx layer, and a SiON layer. The second passivation layer may be any suitable type of nitride layer. The second passivation layer may be an anti-reflective layer. The second passivation layer may provide additional hydrogen passivation to the first passivation layer.

[0116] Next, referring to block 409, a portion of the textured first passivation layer and a portion of the second passivation layer on the backside of the wafer may be removed to form a third opening. The exposed wafer from the third opening is convenient for forming desired metal contacts in a subsequent step and provides a high quality interface for the subsequent metal contact formation step. A laser process or any suitable process may be used to remove the passivation layers.

[0117] Referring to block 410, contacts may be formed.

[0118] A contact may be formed in the third opening on the back side of the wafer. The contact may be set by a conventional screen printing process or any suitable process. The contact may be, for example, but not limited to, Al. The contact may be a base contact. In other embodiments of the present application, the contact may include any suitable material.

[0119] A co-firing process may be performed to form a first region adjacent to the contact and in contact with the wafer. The first region may be connected to the contact. The first region may be P + The first region may be N + The first region can be boron-free.

[0120] Another contact 2 The passivation layer and the1 A co-firing process may be performed to allow contact through the passivation layer to the semiconductor layer. Another contact may be Ag paste or silver-aluminum paste. Ag paste or silver-aluminum paste is corrosive and may be corroded during co-firing. 2 The passivation layer and the 1 Therefore, in order to connect the Ag paste or silver-aluminum paste to the semiconductor layer, the first 2 The passivation layer and the 1 An opening does not need to be formed in the passivation layer first. The other contact can be an emitter contact. In other embodiments of the present application, the other contact can include any suitable material.

[0121] next, Solar Cell To further increase the efficiency and stability of the FET, an electrical or optical injection process can be performed.

[0122] The method shown in FIG. 14 of the present application can be used to fabricate the charge storage structure more simply and efficiently. In blocks 402-404, PEALD or PECVD process can be used to fabricate the oxide layer, the semiconductor layer, and the mask layer. The same equipment can be used to complete the three layers in the same tube in succession, which greatly reduces the manufacturing complexity, simplifies the process, and facilitates technical mass production. In addition, the oxide layer and the semiconductor layer are deposited using PEALD or PECVD process, rather than LPCVD, so that the thickness of the oxide layer is well controlled, and the uniformity, reproducibility, and stability of the oxide layer that meets the mass production requirements can be guaranteed, and the deposition rate of the semiconductor layer can be greatly improved. In addition, the in-situ doping performed on the semiconductor layer can be performed in a short time. depositionIt does not affect the speed, and can also reduce technical bottlenecks in LPCVD technology, such as frequent tube breakage caused by depositing polysilicon on the quartz tube wall. Furthermore, when using the LPCVD process to deposit oxide and semiconductor layers, it is not possible to directly form a mask layer on the semiconductor layer, and the step of depositing the mask layer needs to be completed by modifying the equipment. However, by using the PEALD or PECVD process, it is possible to directly form a mask layer on the semiconductor layer. Therefore, the method shown in FIG. 14 of the present application can be completed more efficiently, at a lower cost, with less equipment.

[0123] Also, the method shown in FIG. 14 of the present application includes, after the mask layer is deposited, about 1000 without reaching high temperatures of up to 1,200°C (the temperatures required to carry out boron diffusion-related processes) Semiconductor Layer The crystal structure of adjustment On the one hand, the maximum temperature that the wafer must withstand during the fabrication of the entire charge storage structure is significantly reduced, i.e., the wafer can be heated to approximately 1000 s.o.d., thereby reducing the process difficulty, saving some production raw materials, and reducing the manufacturing cost. On the other hand, the maximum temperature that the wafer must withstand during the fabrication of the entire charge storage structure is significantly reduced, i.e., the wafer can be heated to approximately 1000 s.o.d., 1000 Since there is no need to expose the wafer to high temperatures of ℃~1200℃, the wafer is less likely to be warped due to high temperatures, improving the product yield of charge storage structures and reducing energy consumption.

[0124] Furthermore, in the method shown in Figure 14 of the present application, after the backside region is formed, a double-sided texturing process (i.e., front and backside texturing) is performed, which can provide high quality and clean samples for subsequent coating, facilitate the subsequent deposition of another oxide and nitride layer, and improve quality and production efficiency.

[0125] 15A, 15B, 15C, 15D, 15E, 15F, and 15G show a semiconductor device manufactured by the method shown in FIG. 1313A-13C are schematic cross-sectional views of the charge storage structure at different stages of the charge storage structure 1300 as shown in FIG.

[0126] 15A, according to block 401, a wafer 301 may be provided. The wafer 301 may be subjected to conventional polishing and cleaning processes. The wafer 301 has a front surface 301a, a back surface 301b opposite the front surface 301a, and a side surface 301c located between the front surface 301a and the back surface 301b. The wafer 301 may be, for example, but is not limited to, a p-type c-Si wafer. The wafer 301 may be any suitable type of wafer.

[0127] 15B, according to block 402, an oxide layer 303 may be deposited on the backside 301b of the wafer 301. The oxide layer 303 may be deposited using PECVD or PEALD. The oxide layer 303 deposited on the backside 301b of the wafer may be lap plated onto a portion of the side 301c and a portion of the frontside 301a. The frontside 301a of the wafer 301 may have an opening 319 exposed from the oxide layer 303. The oxide layer 303 may be, for example, but not limited to, SiO 2 having a thickness of less than 5 nanometers. x It may be a layer.

[0128] According to block 403, a semiconductor layer 305 is deposited over the oxide layer 303 at the backside 301b to prepare for subsequent formation of a backside region and connection with the contact 315. The semiconductor layer 305 may be deposited using PECVD or PEALD. The semiconductor layer 305 deposited on the backside 301b of the wafer may be overplated onto a portion of the side 301c and a portion of the front side 301a. The semiconductor layer 305 may include a group IV element. The semiconductor layer 305 may include a group V element. The semiconductor layer 305 may include, for example, but not limited to, phosphorus. The semiconductor layer 305 may include, for example, but not limited to, in situ doped phosphorus. The semiconductor layer 305 may be any suitable type of semiconductor material. The semiconductor layer 305 may be deposited using, for example, but not limited to, phosphine (PH 3 ).

[0129] According to block 404, a mask layer 317 may be deposited on the semiconductor layer 305 to cover the semiconductor layer 305 on the back surface 301b. The mask layer 317 may be deposited using PECVD or PEALD. The mask layer 317 deposited on the back surface 301b of the wafer may be lap plated onto a portion of the side surface 301c and a portion of the front surface 301a. The mask layer 317 may be selected from, for example, but not limited to, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0130] An opening 319 in the front side 301 a of the wafer 301 may be exposed through the oxide layer 303 , the semiconductor layer 305 , and the mask layer 317 .

[0131] According to block 405, after the mask layer 317 is deposited, Semiconductor layer Crystal structure (e.g. polysilicon) adjustment In certain embodiments, an annealing process is performed to Semiconductor layerThe crystallinity can be greater than about 80%. In some other embodiments, an annealing process is performed to Semiconductor layer The crystallinity can be about 88% to about 95%. In certain embodiments, an annealing process is performed to remove the PH 3 Simultaneous activation of doping And ,semiconductor Layer It can be converted into a polysilicon layer.

[0132] Referring to FIG. 15C, according to block 406, a portion of the oxide layer 303, a portion of the semiconductor layer 305, and a portion of the mask layer 317 on the back surface 301b of the wafer 301 may be removed using a laser process to form an opening 321.

[0133] Referring to FIG. 15D, / inline The semiconductor layer 305 lap plated on the front and sides may be exposed by removing the mask layer 317 on the front 301a and sides 301c of the wafer 301 using HF acid in a wet process tool.

[0134] The semiconductor layer 305 on the front surface 301a and on the side surfaces of the wafer 301 can be removed. The semiconductor layer 305 can be removed using a suitable chemical reagent. The semiconductor layer 305 on the front surface 301a and on the side surfaces 301c can be removed using a suitable chemical reagent. cassette The oxide layer 303 on the front 301a and sides of the wafer 301 may then be removed by suitable chemical reagents, such as, for example, but not limited to, KOH or NaOH, and additives, using an apparatus of this type.

[0135] Next, a surface texturing is applied to the opening 321 and the area formed on the front surface 301a. GupAfter the surface texturing process is performed, a pyramid portion may be formed on the front surface 301a of the wafer 301, and a pyramid portion 3011b may be formed on the back surface 301b of the wafer 301. That is, the back surface 301b of the wafer 301 may include a pyramid portion 3011b and a flat portion 3013b. 15C Damage caused to the back surface 301b by the laser process used in can be repaired while forming the required pyramidal shape on the back surface 301b.

[0136] The remaining mask layer on the front side of the wafer may then be removed. The mask layer on the back side of the wafer may then be removed. The mask layer may be: cassette The metal can be removed using HF acid in a wet process tool.

[0137] The surface of the wafer 301 may then be cleaned to provide a high quality and clean sample for subsequent deposition.

[0138] The remaining semiconductor layer 305, oxide layer 303, and mask layer 317 may be removed by other suitable process steps.

[0139] 15E, according to block 408, a passivation layer 307 may be deposited on the front surface 301a and the back surface 301b. The passivation layer 307 may be deposited using ALD, CVD, or any suitable process. The passivation layer 307 deposited on both surfaces (i.e., the front surface 301a and the back surface 301b) can solve the problem of lap plating caused by deposition on only one surface. The passivation layer 307 may cover the pyramid portions 3011b, oxide layer 303, and semiconductor layer 305 on the front surface 301a, side surface 301c, and back surface 301b of the wafer 301. The passivation layer 307 may be formed of AlO x The passivation layer 307 can be, for example, but not limited to, an Al 2 O 3The passivation layer 307 may be any suitable type of oxide layer. The passivation layer 307 may be SiO x The passivation layer 307 may be a SiO x layer and Al 2 O 3 It may be a laminate consisting of:

[0140] A passivation layer 309 may be further deposited on the passivation layer 307 to cover the passivation layer 307. The passivation layer 309 may be deposited using ALD, CVD, PECVD, PEALD, or any suitable process to cover the passivation layer 307. The passivation layer 309 may be, for example, but not limited to, SiN x layer, SiO x layer, SiON layer, or SiN x layer, SiO x The passivation layer 309 may be any combination of a nitride layer, a silicon nitride layer, and a SiON layer. The passivation layer 309 may be any suitable type of nitride layer.

[0141] Referring to FIG. 15F, according to block 409, a passivation layer of the pyramid portion 3011b on the back surface 301b of the wafer 301 is 309 and passivation layer 307 A part of the wafer 301 is an opening for exposing the wafer 301. 323 The passivation layer may be removed using a laser process to form 309 and passivation layer 307 The portion may be removed using any suitable process.

[0142] Referring to FIG. 15G, an opening 323A contact 311 may be formed on the semiconductor substrate 310. The contact 311 may be set using a conventional screen printing process or any suitable process. The contact 311 may be, for example, but not limited to, Al. The contact 311 may be a base contact. In other embodiments of the present application, the contact 311 may include any suitable material.

[0143] A co-firing process may then be performed to form region 313 adjacent to contact 311 and in contact with wafer 301. Region 313 is a P + Region 313 may be connected to contact 311. In other embodiments of the present application, region 313 may include N + It may include regions.

[0144] Next, the opening 323 Contacts 315 may be formed in the area outside the passivation layer 312. The contacts 315 may be established using a conventional screen printing process or any suitable process. 309 and passivation layer 307 A co-firing process may be performed to allow a connection through the contact 315 to the semiconductor layer 305. The contact 315 may be Ag. The contact 315 may be an emitter contact. In other embodiments of the present application, the contact 315 may include any suitable material.

[0145] Finally, Fig. 13 The charge storage structure 1300 shown in FIG. 14 of the present application can provide higher production efficiency with less manufacturing steps and energy consumption, and lower cost than the prior art, and the manufactured products have higher quality. Furthermore, the charge storage structure of the present application can form different textures on the front and back sides of the wafer, taking into account product requirements and manufacturing costs.

[0146] The order of the method for fabricating the charge storage structure according to the embodiments of the present application is not limited to the order and steps of the method shown in Fig. 14. Suitable permutations and modifications of the steps and / or order of the method shown in Fig. 14 are also intended to be within the spirit of the embodiments of the present application without departing from the teachings of the foregoing spirit of the embodiments of the present application.

[0147] Although the technical contents and features of the present application have been disclosed above, those skilled in the art will be able to make various substitutions and modifications based on the teachings and disclosures of the present application without departing from the spirit of the present application. Therefore, the scope of the present application is not limited to the contents disclosed in the embodiments, but includes various substitutions and modifications that do not depart from the present application, and is protected by the claims of the present application.

Claims

1. a wafer having a first surface with a first texture and a second surface opposite the first surface having a first portion with a second texture and a second portion connected to the first portion; a first pole region in contact with the first portion of the second surface; a second pole region spaced apart from the first pole region and adjacent the second portion of the second surface, A charge storage structure, wherein the first texture is different from the second texture.

2. 2. The charge storage structure of claim 1, wherein the first texture is one of a pyramid texture and an inverted pyramid texture, and the second texture is one of an alkali polished texture, an acid polished texture, a micro-flocking texture, the pyramid texture, and the inverted pyramid texture.

3. 10. The charge storage structure of claim 1 further comprising an oxide layer covering said second portion of said second surface of said wafer.

4. 4. The charge storage structure of claim 3 further comprising a semiconductor layer overlying said oxide layer.

5. 5. The charge storage structure of claim 4, further comprising a first passivation layer covering the first surface, the first portion of the second surface, a third surface of the wafer between the first surface and the second surface, a side of the oxide layer, and a side of the semiconductor layer.

6. 6. The charge storage structure of claim 5, further comprising a second passivation layer overlying the first passivation layer.

7. 2. The charge storage structure of claim 1, wherein said first pole region includes a first metal contact and a region connected to said first metal contact.

8. The region is N + Polar region, or P + 8. The charge storage structure of claim 7 which is a polar region.

9. 7. The charge storage structure of claim 6, wherein both the first passivation layer and the second passivation layer located on the first portion of the second surface have a first opening, and the first metal contact of the first pole region passes through the first opening.

10. 2. The charge storage structure of claim 1, wherein the second pole region has a second metal contact connected to the semiconductor layer, the second metal contact connecting to the semiconductor layer without passing through an opening.

11. 10. The charge storage structure of claim 9, wherein the first metal contact is aluminum.

12. 11. The charge storage structure of claim 10, wherein the second metal contact is a silver paste or a silver aluminum paste.

13. 2. The charge storage structure of claim 1, wherein the wafer is a p-type c-Si wafer.

14. The method of claim 4 wherein the semiconductor layer comprises a Group IV element.

15. The method of claim 4 wherein the semiconductor layer comprises a Group V element.

16. The method of claim 4 wherein the semiconductor layer comprises phosphorus.

17. The charge storage structure of claim 1 , wherein the second portion of the second surface is a planar surface.

18. The charge storage structure of claim 3 , wherein the oxide layer is a tunnel oxide layer.

19. The charge storage structure of claim 2 , wherein the inverted pyramid texture has a reflectivity between 2% and 15%.

20. The charge storage structure of claim 2 , wherein the pyramid texture has a reflectivity of about 5% to 20%.

21. The charge storage structure of claim 2 , wherein the micro-flocking texture has a reflectivity of about 12%.

22. a wafer having a first surface with a first texture and a second surface opposite the first surface having a first portion with a second texture and a second portion connected to the first portion; a first pole region in contact with the first portion of the second surface; a second pole region spaced apart from the first pole region and adjacent the second portion of the second surface, the first texture is one of an alkali polished texture, an acid polished texture, a microflocking texture, and an inverted pyramid texture; the second texture being one of an alkali polished texture, an acid polished texture, a micro-flocking texture, and an inverted pyramid texture; A charge storage structure, wherein the first texture and the second texture are the same.

23. 20. The charge storage structure of claim 19, wherein the inverted pyramid texture has a reflectivity of about 2% to 15%.

24. 1. A method of manufacturing a charge storage structure, comprising the steps of: depositing an oxide layer on the backside of the wafer; depositing a semiconductor layer on the oxide layer so as to overlie the oxide layer; depositing a mask layer on the semiconductor layer so as to cover the semiconductor layer; forming a first opening by removing a portion of the oxide layer, a portion of the semiconductor layer, and a portion of the mask layer on the back side of the wafer; A method for manufacturing a charge storage structure comprising:

25. 25. The method of fabricating a charge storage structure of claim 24, wherein a front surface of the wafer opposite the back surface has a second opening exposed through the mask layer, the semiconductor layer, and the oxide layer.

26. 26. The method of manufacturing a charge storage structure of claim 25, further comprising the step of performing a surface texturing process on the area where the first opening and the front side of the wafer are located.

27. 25. The method of claim 24, further comprising depositing an oxide layer on a side surface of the wafer located between the front surface and the back surface.

28. 27. The method of claim 26, further comprising removing the mask layer and the semiconductor layer located on the front and side of the wafer before performing the surface texturing process.

29. 27. The method of claim 26, further comprising removing the oxide layer located on the front and side of the wafer and the mask layer on the back of the wafer.

30. depositing a first passivation layer on the front and back surfaces; depositing a second passivation layer on the first passivation layer so as to cover the first passivation layer; 30. The method of claim 29, further comprising the step of removing a portion of the first passivation layer and a portion of the second passivation layer on the back side of the wafer from the first opening to form a third opening exposing the wafer.

31. forming a first contact in the third opening; 31. The method of claim 30, further comprising: performing a co-firing process to form a first region adjacent to the first contact and in contact with the wafer.

32. forming a second contact in a region outside the third opening; 32. The method of fabricating a charge storage structure of claim 31, further comprising: performing the co-firing process to allow the second contact to pass through the second passivation layer and the first passivation layer and connect to the semiconductor layer.

33. 25. The method of claim 24, wherein the oxide layer is deposited using plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD).

34. 25. The method of claim 24, wherein the semiconductor layer is deposited using PECVD or PEALD.

35. 25. The method of claim 24, wherein the mask layer is deposited using PECVD or PEALD.

36. 25. The method of claim 24, wherein the semiconductor layer comprises a Group IV element.

37. 25. The method of claim 24, wherein the semiconductor layer comprises a Group V element.

38. 38. The method of claim 37, wherein the semiconductor layer comprises phosphorus.

39. 25. The method of manufacturing a charge storage structure as recited in claim 24, wherein said mask layer is selected from aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

40. 25. The method of manufacturing a charge storage structure of claim 24, further comprising the step of performing an annealing process after depositing said mask layer.

41. 25. The method of claim 24, wherein the first opening is formed using a laser process.

42. 32. The method of claim 31 , wherein the third opening is formed by removing a portion of the passivation layer in the first opening using a laser process.

43. 31. The method of claim 30, wherein the first passivation layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

44. 31. The method of claim 30, wherein the second passivation layer is deposited using PECVD, ALD, or CVD.

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