A package comprising a substrate configured for a high density interconnect portion and an interconnect die

Abstract

A package comprising a substrate (102) having a first surface and a second surface, a first integrated device (103) coupled to the first surface of the substrate, an interconnect die (110) coupled to the first surface of the substrate, a first encapsulation layer (104) coupled to the first surface of the substrate, the first encapsulation layer encapsulating the first integrated device and the interconnect die, and a second integrated device (105) coupled to the second surface of the substrate.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims priority and benefit to non - provisional application Ser. No. 17 / 741,986, filed May 11, 2022, with the United States Patent and Trademark Office, the entire content of which is hereby incorporated by reference herein in its entirety as if fully set forth below and for all applicable purposes.

[0002]

[0002] Various features relate to a package having a substrate and an integrated device.

Background Art

[0003]

[0003] The package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a continuing need to provide a package that performs better and reduces the overall size of the package.

Summary of the Invention

[0004]

[0004] Various features relate to a package having a substrate and an integrated device.

[0005]

[0005] One embodiment provides a package comprising a substrate having a first surface and a second surface, a first integrated device coupled to the first surface of the substrate, a dummy die coupled to the first surface of the substrate, a first encapsulation layer coupled to the first surface of the substrate that encapsulates the first integrated device and the dummy die, and a second integrated device coupled to the second surface of the substrate.

[0006]

[0006] Another embodiment provides a device comprising a package. The package comprises a substrate having a first surface and a second surface, a first integrated device coupled to the first surface of the substrate, a dummy die coupled to the first surface of the substrate, a first encapsulation layer coupled to the first surface of the substrate and encapsulating the first integrated device and the dummy die, and a second integrated device coupled to the second surface of the substrate.

[0007]

[0007] Another embodiment provides a method for fabricating a package. The method includes providing a substrate having a first surface and a second surface, coupling a first integrated device to the first surface of the substrate, coupling an interconnect die to the first surface of the substrate, coupling a first encapsulation layer to the first surface of the substrate, the first encapsulation layer encapsulating the first integrated device and the interconnect die, and coupling a second integrated device to the second surface of the substrate.

Brief Description of the Drawings

[0008]

[0008] Various features, properties, and advantages may become apparent by reading the following "Detailed Description of the Invention" in conjunction with the drawings that identify corresponding elements throughout with like reference numerals.

Figure 1

[0009] An exemplary cross-sectional profile view of a package including a substrate and at least one interconnect die is shown.

Figure 2

[0010] An exemplary cross-sectional profile view of a package including a substrate and at least one interconnect die is shown.

Figure 3A

[0011] An exemplary sequence for fabricating an interconnect die is shown.

Figure 3B

Figure 4A

[0012] A diagram showing an exemplary sequence for fabricating an interconnect die.

Figure 4B

Figure 5

[0013] An exemplary flowchart of a method for fabricating interconnected dies is shown.

Figure 6A

[0014] An exemplary sequence for fabricating a package including a substrate and interconnected dies is shown.

Figure 6B

Figure 6C

Figure 7

[0015] An exemplary flowchart of a method for fabricating a package including a substrate and interconnected dies is shown.

Figure 8A

[0016] An exemplary sequence for fabricating a package including a substrate and interconnected dies is shown.

Figure 8B

Figure 8C

Figure 9

[0017] An exemplary flowchart of a method for fabricating a package including a substrate and interconnected dies is shown.

Figure 10A

[0018] An exemplary sequence for fabricating a substrate is shown.

Figure 10B

Figure 11

[0019] An exemplary flowchart of a method for fabricating a substrate is shown.

Figure 12

[0020] Described herein are various electronic devices that can integrate dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages.

Best Mode for Carrying Out the Invention

[0009]

[0021] In the following description, specific details are set forth in order to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the present disclosure.

[0010]

[0022] The present disclosure describes a package including a substrate having a first surface and a second surface, a first integrated device coupled to the first surface of the substrate, an interconnect die coupled to the first surface of the substrate, a first encapsulation layer coupled to the first surface of the substrate and encapsulating the first integrated device and the interconnect die, and a second integrated device coupled to the second surface of the substrate. As will be further described below, the package provides high-density interconnects, which helps to provide improved package performance while keeping the package small and thin.

[0011] Exemplary Package Comprising a Substrate and an Interconnect Die

[0023] FIG. 1 shows a cross-sectional profile view of a package 100 including a substrate and high-density interconnects. The package 100 is coupled to a board 108 via a plurality of solder interconnects 115. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0012]

[0024] Package 100 includes at least one interconnect die 101, a substrate 102, integrated devices 103, 105, 107, passive devices 109a, 109b, 109c, encapsulation layers 104, 106, and an outer metal layer 160. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 includes a first surface (e.g., a bottom surface) and a second surface (e.g., a top surface).

[0013]

[0025] The integrated device 103 (e.g., a first integrated device) is coupled to the first surface (e.g., the bottom surface) of the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 may be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. An underfill 132 may be present between the integrated device 103 and the substrate 102. At least one interconnect die 101 may be coupled to the first surface of the substrate 102 via a plurality of solder interconnects 114. As will be further described below, at least one interconnect die 101 may be configured to provide high density interconnects for the package 100. The encapsulation layer 104 may be coupled to the first surface of the substrate 102. The encapsulation layer 104 may encapsulate (e.g., partially or completely) the integrated device 103 and at least one interconnect die 101. The encapsulation layer 104 may include a mold, resin, and / or epoxy. The encapsulation layer 104 may be a means for encapsulation. The encapsulation layer 104 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The integrated device 103 may include a front side and a back side. The front side of the integrated device 103 may face the substrate 102. The back side of the integrated device 103 may face the board 108. The back side of the integrated device 103 may be covered by the encapsulation layer 104. In some implementations, the back side (e.g., the back surface) of the integrated device 103 may remain exposed (e.g., not covered by the encapsulation layer 104). An example of how the back side of the integrated device 103 may be exposed is shown in and described below with reference to FIG. 2.

[0014]

[0026] At least one interconnect die 101 includes a die substrate 110 and a plurality of die interconnect portions 112. The die substrate 110 may include silicon. The plurality of die interconnect portions 112 includes pad interconnect portions 112a (e.g., pads), via interconnect portions 112b (e.g., vias), and pad interconnect portions 112c (e.g., pads). The pad interconnect portion 112a is coupled to the via interconnect portion 112b. The via interconnect portion 112b is coupled to the pad interconnect portion 112c. The pad interconnect portion 112a is coupled to a solder interconnect portion 114a. The solder interconnect portion 114a is part of a plurality of solder interconnect portions 114. The plurality of solder interconnect portions 114 is coupled to the plurality of die interconnect portions 112. The pad interconnect portion 112c is coupled to a solder interconnect portion 115a. The solder interconnect portion 115a is part of a plurality of solder interconnect portions 115. At least one interconnect die 101 may be a dummy die. The interconnect die 101 may not include transistors. At least one interconnect die 101 may not include active components. At least one interconnect die 101 may be means for die interconnect.

[0015]

[0027] The plurality of die interconnects 112 may have a pitch between adjacent die interconnects in the range of about 150 to 270 micrometers. The encapsulation layer 104 may have a thickness (e.g., height) in the range of about 150 to 300 micrometers. The plurality of solder interconnects 115 may have a diameter and / or thickness of about 100 micrometers. The total thickness (e.g., height) of the plurality of solder interconnects 114, at least one interconnect die 101, and the plurality of solder interconnects 115 combined may be in the range of about 250 to 400 micrometers. These dimensions are enabled through the use of at least one interconnect die 101, which (i) helps to provide a thinner package 100 while still being able to accommodate a bottom-side integrated device (e.g., having an appropriate standoff height), and (ii) helps to provide interconnects with a small pitch (e.g., 150 to 270 micrometers) within the encapsulation layer, and thus helps to provide high-density routing (e.g., high-density interconnects) within the encapsulation layer.

[0016]

[0028] The integrated device 105 (e.g., the second integrated device) is coupled to the second surface (e.g., the upper surface) of the substrate 102 via a plurality of solder interconnects 152. For example, the integrated device 105 can be coupled to the plurality of interconnects 122 of the substrate 102 via the plurality of solder interconnects 152. The integrated device 105 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 152. The integrated device 107 (e.g., the third integrated device) is coupled to the second surface of the substrate 102 via a plurality of solder interconnects 172. For example, the integrated device 107 can be coupled to the plurality of interconnects 122 of the substrate 102 via the plurality of solder interconnects 172. The integrated device 107 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and the plurality of solder interconnects 172. The passive device 109a is coupled to the second surface of the substrate 102 via a plurality of solder interconnects 190a. For example, the passive device 109a is coupled to the plurality of interconnects 122 of the substrate 102 via the plurality of solder interconnects 190a. The passive device 109b is coupled to the second surface of the substrate 102 via a plurality of solder interconnects 190b. For example, the passive device 109b is coupled to the plurality of interconnects 122 of the substrate 102 via the plurality of solder interconnects 190b. The passive device 109c is coupled to the second surface of the substrate 102 via a plurality of solder interconnects 190c. For example, the passive device 109c is coupled to the plurality of interconnects 122 of the substrate 102 via the plurality of solder interconnects 190c. The passive devices (e.g., 109a, 109b, 109c) can include capacitors and / or inductors.

[0017]

[0029] The encapsulation layer 106 is coupled to the second surface (e.g., the top surface) of the substrate 102. The encapsulation layer 106 can encapsulate the integrated device 105, the integrated device 107, the passive devices 109a, 109b, and 109c. The encapsulation layer 106 can include a mold, resin, and / or epoxy. The encapsulation layer 106 can be a means for encapsulation. The encapsulation layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0018]

[0030] The outer metal layer 160 can be coupled to the outer surface of the encapsulation layer 106. The outer surface of the encapsulation layer 106 can include a top surface and side surfaces. The outer metal layer 160 can also be coupled to the side surfaces of the substrate 102 and the encapsulation layer 104. The outer metal layer 160 can be configured to be coupled to ground. The outer metal layer 160 can be configured to operate as an electromagnetic interference (EMI) shield for the package 100. The outer metal layer 160 can be configured to be coupled to one or more of the plurality of interconnects 122 of the substrate 102.

[0019]

[0031] FIG. 2 shows a cross-sectional profile view of a package 200 including a substrate and high-density interconnects. The package 200 is similar to the package 100 of FIG. 1 and thus includes the same or similar components as the package 100. The package 200 includes at least one interconnect die 201 having a configuration different from that of at least one of the interconnect dies 101 of FIG. 1.

[0020]

[0032] The package 200 is coupled to the board 108 via a plurality of solder interconnects 115. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 can include a printed circuit board (PCB).

[0021]

[0033] Package 200 includes at least one interconnect die 201, a substrate 102, an integrated device 103, an integrated device 105, an integrated device 107, passive devices 109a, passive devices 109b, passive devices 109c, an encapsulation layer 104, an encapsulation layer 106, and an outer metal layer 160. The at least one interconnect die 201 is coupled to a first surface of the substrate 102 via a plurality of solder interconnects 114.

[0022]

[0034] The at least one interconnect die 201 includes a die substrate 110 and a plurality of die interconnects 112. The die substrate 110 may include silicon. The plurality of die interconnects 112 includes pad interconnects 112a (e.g., pads) and via interconnects 112b (e.g., vias). The pad interconnects 112a are coupled to the via interconnects 112b. The pad interconnects 112a are coupled to solder interconnects 114a. The solder interconnects 114a are part of the plurality of solder interconnects 114. The plurality of solder interconnects 114 are coupled to the plurality of die interconnects 112. The via interconnects 112b are coupled to solder interconnects 115a. The solder interconnects 115a are part of the plurality of solder interconnects 115. The at least one interconnect die 101 may be a dummy die. Thus, one expected difference between the at least one interconnect die 201 and the at least one interconnect die 101 is that the at least one interconnect die 201 does not include pad interconnects 112c. One advantage of not having the pad interconnects 112c is that the at least one interconnect die 201 can be thinner than the at least one interconnect die 101, which can help reduce the overall thickness of the package. The at least one interconnect die 201 may be a dummy die. The interconnect die 201 may not include transistors. The at least one interconnect die 201 may not include active components. The at least one interconnect die 201 may be a means for die interconnect.

[0023]

[0035] The plurality of die interconnect portions 112 of at least one interconnect die 201 may have a pitch between adjacent die interconnect portions in the range of about 150 to 270 micrometers. The encapsulation layer 104 may have a thickness (e.g., height) in the range of about 150 to 300 micrometers. The plurality of solder interconnect portions 115 may have a diameter and / or thickness of about 100 micrometers. The total thickness (e.g., height) of the plurality of solder interconnect portions 114, at least one interconnect die 201, and the plurality of solder interconnect portions 115 combined may be in the range of about 250 to 400 micrometers. These dimensions are made possible through the use of at least one interconnect die 201, which (i) helps to provide a thinner package 200 while still being able to accommodate a bottom-side integrated device (e.g., having an appropriate stand-off height), and (ii) helps to provide interconnect portions with a small pitch (e.g., 150 to 270 micrometers) within the encapsulation layer, and thus helps to provide high-density routing (e.g., high-density interconnects) within the encapsulation layer.

[0024]

[0036] Another difference between package 200 and package 100 is that the back side of the integrated device 103 of package 200 is exposed. As shown in FIG. 2, at least a portion of the back side of the integrated device 103 is not covered by the encapsulation layer 104. This can occur because during the fabrication process of package 200, a portion of the encapsulation layer 104, a portion of the back side of the integrated device 103, and / or a portion of at least one interconnect die 201 may be removed during the grinding and / or polishing process on the bottom side of package 200. However, it should be noted that in some implementation forms of package 200, the back side of the integrated device 103 may be covered by the encapsulation layer 104.

[0025]

[0037] An integrated device (e.g., 103, 105, 107) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103, 105, 107) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a chiplet. The chiplet can be fabricated using a process that provides a better yield compared to the fabrication process for other types of integrated devices, thereby reducing the overall cost of fabricating the chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets can be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects having different widths and / or spacings). In some implementations, a plurality of chiplets can be used to perform the functions of one or more chips (e.g., one or more integrated devices). Using a plurality of chiplets to perform some functions can reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0026]

[0038] Packages (e.g., 100, 200) can be implemented within a radio frequency (RF) package. The RF package can be a radio frequency front end (RFFE) package. The packages (e.g., 100, 200) can be configured to provide Wireless Fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 100, 300) can be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The packages (e.g., 100, 200) can be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0027]

[0039] Although various interconnect dies have been described, the sequence for fabricating the interconnect die will be described below.

[0028] Exemplary sequence for fabricating an interconnect die

[0040] In some implementations, fabricating an interconnect die includes several processes. FIGS. 3A - 3B show an exemplary sequence for providing or fabricating an interconnect die. In some implementations, the sequence of FIGS. 3A - 3B can be used to provide or fabricate the interconnect die 101. However, the processes of FIGS. 3A - 3B can be used to fabricate any of the interconnect dies described in the present disclosure (e.g., 201).

[0029]

[0041] Note that the sequences of FIGS. 3A-3B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnect die. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0030]

[0042] Step 1 shows the state after preparing the die substrate 110, as shown in FIG. 3A. The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be the top surface, and the second surface of the die substrate 110 may be the bottom surface. In some implementations, the first surface of the die substrate 110 may be the bottom surface, and the second surface of the die substrate 110 may be the top surface.

[0031]

[0043] Step 2 shows the state after a plurality of cavities 302 are formed in the die substrate 110. For example, the plurality of cavities 302 may be formed through the first surface of the die substrate 110. The plurality of cavities 302 may include grooves. The plurality of cavities 302 may extend partially through the thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the plurality of cavities 302.

[0032]

[0044] Step 3 shows the state after a metal layer 305 is formed within the plurality of cavities 302 and / or on the first surface of the die substrate 110. The metal layer 305 may include copper. A plating process may be used to form the metal layer 305.

[0033]

[0045] Step 4 shows the state after a portion of the metal layer 305 has been removed. For example, a portion of the metal layer 305 bonded to the first surface of the die substrate 110 may be removed such that the metal layer 305 remains within the plurality of cavities 302. A polishing process may be used to remove a portion of the metal layer 305. The remaining metal from the metal layer 305 located within the plurality of cavities 302 may define a plurality of interconnects 112b as described with respect to FIGS. 1 and 2.

[0034]

[0046] Step 5 shows the state after a metal layer 307 has been formed on the first surface of the die substrate 110 as shown in FIG. 3B. A plating process may be used to form the metal layer 307. The metal layer 307 may be bonded to the metal layer 305. The metal layer 307 may define a plurality of interconnects 112a as described with respect to FIGS. 1 and 2. The metal layer 307 may represent the front-side interconnects of the interconnect die.

[0035]

[0047] Step 6 shows the state after the die substrate 110 has been thinned. For example, a portion of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 305 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least the die substrate 110a and the die substrate 110b remain. If the die substrate 110b is present, the bottom side of the metal layer 305 is not exposed. A grinding process may be used to remove a portion of the die substrate 110. In some implementations, step 6 may show one implementation of an interconnect die that includes interconnects and in which no additional interconnects are formed within, above, or below the die substrate 110. If no further interconnects are formed, singulation may be performed in a manner similar to the method described below with respect to step 8. As further described below, the interconnect die shown in step 6 may be used to bond to a substrate.

[0036]

[0048] Step 7 shows the state after the metal layer 309 is formed on the second surface of the die substrate 110. A plating process may be used to form the metal layer 309. The metal layer 309 may be coupled to the metal layer 305. The metal layer 309 may define a plurality of interconnects 112c, as described with respect to FIGS. 1 and 2. The metal layer 309 may represent the backside interconnects of the interconnected die.

[0037]

[0049] Step 8 shows the state after singulation to form a number of interconnected dies. A mechanical process may be used to singulate the die substrate 110 into a number of interconnected dies (e.g., 101). A saw may be used to singulate the die substrate 110.

[0038] Exemplary sequence for fabricating an interconnected die

[0050] In some implementations, fabricating an interconnected die includes a number of processes. FIGS. 4A-4B illustrate an exemplary sequence for providing or fabricating an interconnected die. In some implementations, the sequence of FIGS. 4A-4B may be used to provide or fabricate the interconnected die 101. However, the processes of FIGS. 4A-4B may be used to fabricate any of the interconnected dies described in this disclosure (e.g., 201).

[0039]

[0051] Note that the sequence of FIGS. 4A-4B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating an interconnected die. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be exchanged or replaced without departing from the scope of this disclosure.

[0040]

[0052] Stage 1 shows the state after the die substrate 110 is prepared, as shown in FIG. 4A. The die substrate 110 contains silicon. The die substrate 110 may include a first surface and a second surface. In some implementation forms, the first surface of the die substrate 110 may be the upper surface, and the second surface of the die substrate 110 may be the bottom surface. In some implementation forms, the first surface of the die substrate 110 may be the bottom surface, and the second surface of the die substrate 110 may be the upper surface.

[0041]

[0053] Stage 2 shows the state after a plurality of cavities 402 are formed in the die substrate 110. For example, the plurality of cavities 402 may be formed through the first surface of the die substrate 110. The plurality of cavities 402 may include grooves. The plurality of cavities 402 may extend partially through the thickness of the die substrate 110. A laser ablation process and / or an etching process may be used to form the plurality of cavities 402.

[0042]

[0054] Stage 3 shows the state after a metal layer 405 is formed in the plurality of cavities 402 and / or on the first surface of the die substrate 110. The metal layer 405 may contain copper. A filling process may be used to form the metal layer 405, and in the filling process, a conductive paste may be used to fill the plurality of cavities 402.

[0043]

[0055] Stage 4 shows the state after a portion of the metal layer 405 is removed. For example, a portion of the metal layer 405 bonded to the first surface of the die substrate 110 may be removed so that the metal layer 405 remains in the plurality of cavities 402. A polishing process may be used to remove a portion of the metal layer 405. The remaining metal from the metal layer 405 located in the plurality of cavities 402 may define a plurality of interconnects 112b as described in FIGS. 1 and 2.

[0044]

[0056] Stage 5 shows the state after the metal layer 407 is formed on the first surface of the die substrate 110, as shown in FIG. 4B. A plating process may be used to form the metal layer 407. The metal layer 407 may be coupled to the metal layer 405. The metal layer 407 may define a plurality of interconnects 112a, as described with respect to FIGS. 1 and 2. The metal layer 407 may represent the front interconnects of the interconnect die.

[0045]

[0057] Stage 6 shows the state after the die substrate 110 is thinned. For example, a portion of the die substrate 110 may be removed such that at least the die substrate 110a remains and the bottom side of the metal layer 405 is exposed. In some implementations, a portion of the die substrate 110 may be removed such that at least the die substrate 110a and the die substrate 110b remain. If the die substrate 110b is present, the bottom side of the metal layer 405 is not exposed. A grinding process may be used to remove a portion of the die substrate 110. In some implementations, stage 6 may show one implementation of an interconnect die that includes interconnects and in which no additional interconnects are formed in, above, or below the die substrate 110. If no further interconnects are formed, singulation may be performed in a manner similar to the method described later in stage 8. As will be further described below, the interconnect die shown in stage 6 may be used to couple to a substrate.

[0046]

[0058] Stage 7 shows the state after the metal layer 409 is formed on the second surface of the die substrate 110. A plating process may be used to form the metal layer 409. The metal layer 409 may be coupled to the metal layer 405. The metal layer 409 may define a plurality of interconnects 112c, as described with respect to FIGS. 1 and 2. The metal layer 409 may represent the backside interconnects of the interconnect die.

[0047]

[0059] Stage 8 shows the state after singulation to form a number of interconnect dies. A mechanical process may be used to singulate the die substrate 110 into a number of interconnect dies (e.g., 101). A saw may be used to singulate the die substrate 110.

[0048] Exemplary Flow Diagram of a Method for Fabricating Interconnected Dies

[0060] In some implementations, fabricating an interconnected die includes several processes. FIG. 5 shows an exemplary flow diagram of a method 500 for providing or fabricating an interconnected die. In some implementations, method 500 of FIG. 5 may be used to provide or fabricate the interconnected die 101 described in this disclosure. However, method 500 may be used to provide or fabricate any of the interconnected dies (e.g., 201) described in this disclosure.

[0049]

[0061] Note that the method 500 of FIG. 5 may combine one or more processes to simplify and / or clarify the method for providing or fabricating an interconnected die. In some implementations, the order of the processes can be changed or modified.

[0050]

[0062] The method prepares a die substrate (e.g., 110) at (505). The die substrate 110 includes silicon. The die substrate 110 may include a first surface and a second surface. In some implementations, the first surface of the die substrate 110 may be the top surface, and the second surface of the die substrate 110 may be the bottom surface. In some implementations, the first surface of the die substrate 110 may be the bottom surface, and the second surface of the die substrate 110 may be the top surface. Step 1 of FIG. 3A illustrates and describes an example of preparing a die substrate. Step 1 of FIG. 4A illustrates and describes an example of preparing a die substrate.

[0051]

[0063] The method forms a plurality of cavities (e.g., 302, 402) in the die substrate 110 (at 510). For example, the plurality of cavities (e.g., 302, 402) can be formed through the first surface of the die substrate 110. The plurality of cavities (e.g., 302, 402) can include grooves. The plurality of cavities (e.g., 302, 402) may extend partially through the thickness of the die substrate 110. To form the plurality of cavities (e.g., 302, 402), a laser ablation process and / or an etching process can be used. Step 2 of FIG. 3A illustrates and describes an example of forming a cavity in the die substrate. Step 2 of FIG. 4A illustrates and describes an example of forming a cavity in the die substrate.

[0052]

[0064] The method forms a conductive material in the plurality of cavities (e.g., 302, 402) of the die substrate 110 (at 515). The conductive material can include a metal layer (e.g., 305, 405). The conductive material can be formed on the surface of the die substrate 110. The conductive material can include copper. To form the conductive material, a plating process can be used. To form the conductive material, a filling process can be used. Step 3 of FIG. 3A illustrates and describes an example of forming a conductive material in the die substrate. Step 3 of FIG. 4A illustrates and describes an example of forming a conductive material in the die substrate. In some implementations, forming the conductive material can include removing a portion of the conductive material. To remove a portion of the conductive material, a polishing process can be used. Removing a portion of the conductive material can include removing a portion of the conductive material bonded to the first surface of the die substrate 110 and leaving the conductive material located in the plurality of cavities (e.g., 302, 402) of the die substrate 110. Step 4 of FIG. 3A illustrates and describes an example of removing a portion of the conductive material in the die substrate. Step 4 of FIG. 4A illustrates and describes an example of removing a portion of the conductive material in the die substrate.

[0053]

[0065] The method forms a plurality of front-side interconnecting portions (at 520). The front-side interconnecting portions can be coupled to the upper side of the die substrate 110. The plurality of front-side interconnecting portions can be defined by a patterned metal layer (e.g., 307, 407) on the upper surface of the die substrate 110. A plating process can be used to form the metal layer (e.g., 307, 407). The metal layer 307 can be coupled to the metal layer 305. The metal layer 407 can be coupled to the metal layer 405. The metal layer 407 can define a plurality of interconnecting portions 112b as described with reference to FIGS. 1 and 2. The metal layer 407 can represent the front-side interconnecting portions of the interconnect die. The plurality of interconnecting portions 112a can represent the plurality of front-side interconnecting portions of the interconnect die. Step 5 in FIG. 3B illustrates and describes an example of forming the front-side interconnecting portions. Step 5 in FIG. 4B illustrates and describes an example of forming the front-side interconnecting portions.

[0054]

[0066] The method thins the die substrate (e.g., 110) (at 525). Different implementation forms may thin the die substrate 110 differently. For example, some implementation forms may thin the die substrate 110 such that the bottom sides of the metal layers (e.g., 305, 405) are exposed. Some implementation forms may thin the die substrate 110 without exposing the bottom sides of the metal layers (e.g., 305, 405). A grinding process can be used to remove a portion of the die substrate 110. Step 6 in FIG. 3B illustrates and describes an example of thinning the die substrate. Step 6 in FIG. 4B illustrates and describes an example of thinning the die substrate.

[0055]

[0067] The method optionally forms (at 530) a plurality of backside interconnects. The backside interconnects can be coupled to the bottom side of the die substrate 110. The plurality of backside interconnects can be defined by a patterned metal layer (e.g., 309, 409) on the top surface of the die substrate 110. A plating process can be used to form the metal layer (e.g., 309, 409). The metal layer 309 can be coupled to the metal layer 305. The metal layer 409 can be coupled to the metal layer 405. The metal layer 409 can define a plurality of interconnects 112c as described with respect to FIGS. 1 and 2. The metal layer 409 can represent the backside interconnects of the interconnect die. The plurality of interconnects 112c can represent the plurality of backside interconnects of the interconnect die. Step 7 of FIG. 3B illustrates and describes an example of forming the backside interconnects. Step 7 of FIG. 4B illustrates and describes an example of forming the backside interconnects.

[0056]

[0068] The method (at 535) fragments the die substrate 110 to form a number of interconnect dies (e.g., 101, 201). A mechanical process can be used to fragment the die substrate 110 into a number of interconnect dies (e.g., 101). A saw can be used to fragment the die substrate 110. Step 8 of FIG. 3B illustrates and describes an example of fragmentation. Step 8 of FIG. 4B illustrates and describes an example of fragmentation.

[0057] Exemplary sequence for fabricating a package comprising a substrate and interconnect dies

[0069] In some implementations, fabricating the package includes a number of processes. FIGS. 6A - 6C show an exemplary sequence for providing or fabricating the package. In some implementations, the sequence of FIGS. 6A - 6C can be used to provide or fabricate the package 100. However, the processes of FIGS. 6A - 6C can be used to fabricate any of the packages described in this disclosure (e.g., 200).

[0058]

[0070] Note that the sequences of FIGS. 6A-6C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0059]

[0071] As shown in FIG. 6A, step 1 shows the state after preparing substrate 102. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 may include a first surface (e.g., top surface) and a second surface (e.g., bottom surface). Substrate 102 can be fabricated using the methods described in FIGS. 10A-10B. In some embodiments, a core substrate (e.g., a substrate including a core layer) is prepared.

[0060]

[0072] Step 2 shows the state after integrated device 103 is coupled to the first surface (e.g., bottom surface) of substrate 102. Integrated device 103 can be coupled to substrate 102 via a plurality of solder interconnects 130. A solder reflow process can be used to couple integrated device 103 to substrate 102. In some implementations, integrated device 103 can be coupled to substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. Step 2 also shows the state after at least one interconnect die 101 is coupled to the first surface of substrate 102. At least one interconnect die 101 can be coupled to substrate 102 via a plurality of solder interconnects 114. A solder reflow process can be used to couple at least one interconnect die 101 to substrate 102. Step 2 also shows underfill 132 provided and / or formed between first integrated device 105 and substrate 102.

[0061]

[0073] Stage 3 shows the state after the encapsulation layer 104 is provided and coupled to the substrate 102. The encapsulation layer 104 can encapsulate the integrated device 103 and at least one interconnect die 101. The encapsulation layer 104 can be coupled to the first surface of the substrate 102. The encapsulation layer 104 can include a mold, resin, and / or epoxy. The encapsulation layer 104 can be a means for encapsulation. The encapsulation layer 104 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0062]

[0074] Stage 4 shows the state after a portion of the encapsulation layer 104 is removed. A grinding process and / or a polishing process can be used to remove a portion of the encapsulation layer 104. In some implementations, a portion of at least one interconnect die 101 and / or a portion of the back side of the integrated device 103 can also be removed.

[0063]

[0075] Stage 5 shows the state after the integrated device 105, the integrated device 107, and the plurality of passive devices 109 (e.g., 109a, 109b, 109c) are coupled to the second surface (e.g., the top surface) of the substrate 102 as shown in FIG. 6B. The integrated device 105 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) can be coupled to the substrate 102 via corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process can be used to couple the integrated device and / or the passive device to the substrate 102.

[0064]

[0076] Step 6 shows the state after the encapsulation layer 106 is provided and coupled to the substrate 102. The encapsulation layer 106 can encapsulate integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 can be coupled to the second surface of the substrate 102. The encapsulation layer 106 can include a mold, resin, and / or epoxy. The encapsulation layer 106 can be a means for encapsulation. The encapsulation layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0065]

[0077] Step 7 shows the state after a plurality of solder interconnects 115 are coupled to at least one interconnect die 101, as shown in FIG. 6C. A solder reflow process can be used to couple the plurality of solder interconnects 115 to at least one interconnect die 101.

[0066]

[0078] Step 8 shows the state after an outer metal layer 160 is formed on the outer surface of the encapsulation layer 106. A sputtering process can be used to form the outer metal layer 160. The outer metal layer 160 can be formed on the top surface of the encapsulation layer 106, the side surface of the encapsulation layer 106, the side surface of the substrate 102, and / or the side surface of the encapsulation layer 104. Step 8 can show the package 100. The package 100 can be fabricated one at a time, or fabricated together as part of one or more wafers and then singulated into individual packages.

[0067] Exemplary flow diagram of a method for fabricating a package comprising a substrate and interconnect dies

[0079] In some implementations, fabricating a package includes several processes. FIG. 7 shows an exemplary flow diagram of a method 700 for providing or fabricating a package. In some implementations, the method 700 of FIG. 7 can be used to provide or fabricate the package 100 described in the present disclosure. However, the method 700 can be used to provide or fabricate any of the packages described in the present disclosure (e.g., 200).

[0068]

[0080] Note that method 700 of FIG. 7 can combine one or more processes to simplify and / or clarify the method for providing or fabricating a package. In some implementations, the order of the processes can be changed or modified.

[0069]

[0081] The method prepares a substrate (e.g., 102) (at 705). Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 can include a first surface (e.g., the top surface) and a second surface (e.g., the bottom surface). Substrate 102 can be fabricated using the method described in FIGS. 10A-10B. In some embodiments, a core substrate (e.g., a substrate including a core layer) is prepared. Step 1 of FIG. 6A illustrates and describes an example of preparing a substrate.

[0070]

[0082] The method couples an integrated device (e.g., 103) and at least one interconnect die (e.g., 101) to a first surface (e.g., the bottom surface) of substrate 102 (at 710). Integrated device 103 can be coupled to substrate 102 via a plurality of solder interconnects 130. A solder reflow process can be used to couple integrated device 103 to substrate 102. At least one interconnect die 101 can be coupled to substrate 102 via a plurality of solder interconnects 114. A solder reflow process can be used to couple at least one interconnect die 101 to substrate 102. Step 2 of FIG. 6A illustrates and describes an example of coupling an integrated device and an interconnect die to a substrate.

[0071]

[0083] The method forms an encapsulation layer (e.g., 104) coupled to a substrate (e.g., 102) at (715). The encapsulation layer 104 (e.g., the first encapsulation layer) can encapsulate the integrated device 103 and at least one interconnect die 101. The encapsulation layer 104 can be coupled to the first surface of the substrate 102. The encapsulation layer 104 can include a mold, resin, and / or epoxy. The encapsulation layer 104 can be a means for encapsulation. The encapsulation layer 104 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, forming the encapsulation layer can include removing a portion of the encapsulation layer 104. A grinding process and / or a polishing process can be used to remove a portion of the encapsulation layer 104. In some implementations, a portion of at least one interconnect die 101 and / or a portion of the back side of the integrated device 103 can also be removed. Stages 3 and 4 of FIG. 6A illustrate and describe an example of providing an encapsulation layer and removing a portion of the encapsulation layer.

[0072]

[0084] The method couples an integrated device (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c) to the second surface (e.g., the top surface) of the substrate 102 at (720). The integrated device 105 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) can be coupled to the substrate 102 via corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process can be used to couple the integrated device and / or the passive devices to the substrate 102. Stage 5 of FIG. 6B illustrates and describes an example of coupling an integrated device and passive devices to a substrate.

[0073]

[0085] The method forms an encapsulation layer (e.g., 106) at (725). The encapsulation layer is coupled to the substrate 102. The encapsulation layer 106 (e.g., the second encapsulation layer) can encapsulate integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 can be coupled to the second surface of the substrate 102. The encapsulation layer 106 can include a mold, resin, and / or epoxy. The encapsulation layer 106 can be a means for encapsulation. The encapsulation layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Step 6 of FIG. 6B illustrates and describes an example of providing an encapsulation layer.

[0074]

[0086] The method couples a plurality of solder interconnects (e.g., 115) to at least one interconnect die 101 at (730). A solder reflow process can be used to couple the plurality of solder interconnects 115 to at least one interconnect die 101. Step 7 of FIG. 6C illustrates and describes an example of coupling a solder interconnect to a substrate.

[0075]

[0087] The method forms an outer metal layer (e.g., 160) on the outer surface of the encapsulation layer 106 at (735). A sputtering process can be used to form the outer metal layer 160. The outer metal layer 160 can be formed on the top surface of the encapsulation layer 106, the side surface of the encapsulation layer 106, the side surface of the substrate 102, and / or the side surface of the encapsulation layer 104. The outer metal layer 160 can be coupled to one of the plurality of interconnects 122 of the substrate 102. The outer metal layer 160 can be configured to operate as an electromagnetic interference (EMI) shield for the package 100. Step 8 of FIG. 6C illustrates and describes an example of forming an outer metal layer.

[0076]

[0088] In some implementations, several packages are fabricated simultaneously. In such a case, the method can singulate the packages (e.g., 100, 200).

[0077] Exemplary sequence for fabricating a package comprising a substrate and an interconnect die

[0089] In some implementations, fabricating a package includes several processes. FIGS. 8A - 8C illustrate an exemplary sequence for providing or fabricating a package. In some implementations, the sequence of FIGS. 8A - 8C can be used to provide or fabricate package 200. However, the processes of FIGS. 8A - 8C can be used to fabricate any of the packages described in the present disclosure (e.g., 100).

[0078]

[0090] Note that the sequence of FIGS. 8A - 8C can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0079]

[0091] As shown in FIG. 8A, step 1 shows the state after preparing substrate 102. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 can include a first surface (e.g., top surface) and a second surface (e.g., bottom surface). Substrate 102 can be fabricated using the methods described in FIGS. 10A - 10B. In some embodiments, a core substrate (e.g., a substrate including a core layer) is prepared.

[0080]

[0092] Stage 2 shows the state after the integrated device 105, the integrated device 107, and the plurality of passive devices 109 (e.g., 109a, 109b, 109c) are coupled to the second surface (e.g., the top surface) of the substrate 102. The integrated device 105 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) can be coupled to the substrate 102 via corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process can be used to couple the integrated device and / or the passive device to the substrate 102.

[0081]

[0093] Stage 3 shows the state after the encapsulation layer 106 is provided and coupled to the substrate 102. The encapsulation layer 106 (e.g., the second encapsulation layer) can encapsulate the integrated devices (e.g., 105, 107) and the passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 can be coupled to the second surface of the substrate 102. The encapsulation layer 106 can include a mold, a resin, and / or an epoxy. The encapsulation layer 106 can be a means for encapsulation. The encapsulation layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0082]

[0094] Stage 4 shows the state after the integrated device 103 is coupled to the first surface (e.g., the bottom surface) of the substrate 102, as shown in FIG. 8B. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. A solder reflow process can be used to couple the integrated device 103 to the substrate 102. Stage 2 also shows the state after at least one interconnect die 201 is coupled to the first surface of the substrate 102. The at least one interconnect die 201 can be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process can be used to couple the at least one interconnect die 201 to the substrate 102. Stage 2 also shows an underfill 132 provided and / or formed between the first integrated device 105 and the substrate 102.

[0083]

[0095] Stage 5 shows the state after the encapsulation layer 104 (e.g., the first encapsulation layer) is provided and coupled to the substrate 102. The encapsulation layer 104 can encapsulate the integrated device 103 and the at least one interconnect die 201. The encapsulation layer 104 can be coupled to the first surface of the substrate 102. The encapsulation layer 104 can include a mold, a resin, and / or an epoxy. The encapsulation layer 104 can be a means for encapsulation. The encapsulation layer 104 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0084]

[0096] Stage 6 shows the state after a portion of the encapsulation layer 104 is removed. A grinding process and / or a polishing process can be used to remove a portion of the encapsulation layer 104. A portion of the at least one interconnect die 201 and / or a portion of the back side of the integrated device 103 can also be removed. By removing a portion of the interconnect die 201, a portion of the die substrate 110 can be removed, thereby exposing the interconnects within the die substrate 110.

[0085]

[0097] Step 7 shows the state after a plurality of solder interconnects 115 are coupled to at least one interconnect die 201, as shown in FIG. 8C. A solder reflow process may be used to couple the plurality of solder interconnects 115 to at least one interconnect die 201.

[0086]

[0098] Step 8 shows the state after an outer metal layer 160 is formed on the outer surface of the encapsulation layer 106. A sputtering process may be used to form the outer metal layer 160. The outer metal layer 160 may be formed on the top surface of the encapsulation layer 106, the side surface of the encapsulation layer 106, the side surface of the substrate 102, and / or the side surface of the encapsulation layer 104. Step 8 may show the package 200. The packages 200 may be fabricated one at a time, or may be fabricated together as part of one or more wafers and then singulated into individual packages.

[0087] Exemplary flow diagram of a method for fabricating a package comprising a substrate and interconnect dies

[0099] In some implementations, fabricating a package includes several processes. FIG. 9 shows an exemplary flow diagram of a method 900 for providing or fabricating a package. In some implementations, the method 900 of FIG. 9 may be used to provide or fabricate the package 200 described in the present disclosure. However, the method 900 may be used to provide or fabricate any of the packages described in the present disclosure (e.g., 100).

[0088]

[0100] Note that the method 900 of FIG. 9 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a package. In some implementations, the order of the processes may be changed or modified.

[0089]

[0101] The method prepares a substrate (e.g., 102) at (905). The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., the top surface) and a second surface (e.g., the bottom surface). The substrate 102 can be fabricated using the method described in FIGS. 10A - 10B. In some embodiments, a core substrate (e.g., a substrate including a core layer) is prepared. Step 1 of FIG. 8A illustrates and describes an example of preparing a substrate.

[0090]

[0102] The method couples integrated devices (e.g., 105, 107) and passive devices (e.g., 109a, 109b, 109c) to a second surface (e.g., the top surface) of the substrate 102 at (910). The integrated device 105 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 152. The integrated device 107 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 172. The plurality of passive devices 109 (e.g., 109a, 109b, 109c) can be coupled to the substrate 102 via corresponding plurality of solder interconnects (e.g., 190a, 190b, 190c). A solder reflow process can be used to couple the integrated devices and / or passive devices to the substrate 102. Step 2 of FIG. 8A illustrates and describes an example of coupling integrated devices and passive devices to a substrate.

[0091]

[0103] The method forms a encapsulation layer (e.g., 106) at (915). The encapsulation layer is coupled to the substrate 102. The encapsulation layer 106 (e.g., the second encapsulation layer) can encapsulate the integrated devices (e.g., 105, 107) and the passive devices (e.g., 109a, 109b, 109c). The encapsulation layer 106 can be coupled to the second surface of the substrate 102. The encapsulation layer 106 can include a mold, resin, and / or epoxy. The encapsulation layer 106 can be a means for encapsulation. The encapsulation layer 106 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Step 3 of FIG. 8A illustrates and describes an example of providing an encapsulation layer.

[0092]

[0104] The method (at 920) couples an integrated device (e.g., 103) and at least one interconnect die (e.g., 101) to a first surface (e.g., the bottom surface) of a substrate 102. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder interconnects 130. The integrated device 103 can be coupled to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 130. A solder reflow process can be used to couple the integrated device 103 to the substrate 102. At least one interconnect die 101 can be coupled to the substrate 102 via a plurality of solder interconnects 114. A solder reflow process can be used to couple at least one interconnect die 101 to the substrate 102. Step 4 of FIG. 8B illustrates and describes an example of coupling an integrated device and an interconnect die to a substrate.

[0093]

[0105] The method (at 925) forms an encapsulation layer (e.g., 104) coupled to a substrate (e.g., 102). The encapsulation layer 104 (e.g., a first encapsulation layer) can encapsulate the integrated device 103 and at least one interconnect die 101. The encapsulation layer 104 can be coupled to the first surface of the substrate 102. The encapsulation layer 104 can include a mold, resin, and / or epoxy. The encapsulation layer 104 can be a means for encapsulation. The encapsulation layer 104 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, forming the encapsulation layer can include removing a portion of the encapsulation layer 104. A grinding process and / or a polishing process can be used to remove a portion of the encapsulation layer 104. In some implementations, a portion of at least one interconnect die 101 and / or a portion of the back side of the integrated device 103 can also be removed. Steps 5 and 6 of FIG. 8B illustrate and describe an example of providing an encapsulation layer and removing a portion of the encapsulation layer.

[0094]

[0106] The method couples (at 930) a plurality of solder interconnects (e.g., 115) to at least one interconnect die 101. A solder reflow process may be used to couple the plurality of solder interconnects 115 to at least one interconnect die 101. Step 7 of FIG. 8C illustrates and describes an example of coupling a solder interconnect to a substrate.

[0095]

[0107] The method forms (at 735) an outer metal layer (e.g., 160) on the outer surface of the encapsulation layer 106. A sputtering process may be used to form the outer metal layer 160. The outer metal layer 160 may be formed on the top surface of the encapsulation layer 106, on the side surface of the encapsulation layer 106, on the side surface of the substrate 102, and / or on the side surface of the encapsulation layer 104. Step 8 of FIG. 8C illustrates and describes an example of forming an outer metal layer.

[0096]

[0108] In some implementations, several packages are fabricated simultaneously. In such cases, the method may singulate the packages (e.g., 100, 200).

[0097] Exemplary sequence for fabricating a substrate

[0109] In some implementations, fabricating a substrate includes several processes. FIGS. 10A - 10B show an exemplary sequence for providing or fabricating a substrate. In some implementations, the sequence of FIGS. 10A - 10B may be used to provide or fabricate the substrate 102. However, the processes of FIGS. 10A - 10B may be used to fabricate any of the substrates described in this disclosure.

[0098]

[0110] Note that the sequence of FIGS. 10A - 10B may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be exchanged or replaced without departing from the scope of this disclosure.

[0099]

[0111] Step 1 shows the state after preparing carrier 1000, as shown in FIG. 10A. Seed layer 1001 and interconnect 1002 can be located on carrier 1000. Interconnect 1002 can be located on seed layer 1001. To form interconnect 1002, a plating process and an etching process can be used. In some implementations, carrier 1000 can be provided with seed layer 1001 and a metal layer patterned to form interconnect 1002. Interconnect 1002 can represent at least some of the interconnects from a plurality of interconnects 142.

[0100]

[0112] Step 2 shows the state after dielectric layer 1020 is formed on carrier 1000, seed layer 1001, and interconnect 1002. To form dielectric layer 1020, a deposition process and / or a lamination process can be used. Dielectric layer 1020 can include a prepreg and / or polyimide. Dielectric layer 1020 can include a photoimageable dielectric. However, different implementations can also use different materials for the dielectric layer.

[0101]

[0113] Step 3 shows the state after a plurality of cavities 1010 are formed in dielectric layer 1020. The plurality of cavities 1010 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0102]

[0114] Step 4 shows the state after interconnects 1012 are formed in and on dielectric layer 1020, including within and on the plurality of cavities 1010. For example, vias, pads, and / or traces can be formed. To form the interconnects, a plating process can be used.

[0103]

[0115] Step 5 shows the state after the dielectric layer 1022 is formed over the dielectric layer 1020 and the interconnect 1012. A deposition process and / or a lamination process may be used to form the dielectric layer 1022. The dielectric layer 1022 may include a prepreg and / or polyimide. The dielectric layer 1022 may include a photoimageable dielectric. However, different implementations may also use different materials for the dielectric layer.

[0104]

[0116] As shown in FIG. 10B, step 6 shows the state after a plurality of cavities 1030 are formed in the dielectric layer 1022. The plurality of cavities 1030 may be formed using an etching process (e.g., a photolithography etching process) or a laser process.

[0105]

[0117] Step 7 shows the state after the interconnect 1014 is formed in and over the dielectric layer 1022, including within and over the plurality of cavities 1030. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnect.

[0106]

[0118] Step 8 shows the state after the carrier 1000 is separated (e.g., removed, detached, ground) from at least one dielectric layer 140 and the seed layer 1001, a portion of the seed layer 1001 is removed (e.g., etched away), leaving the substrate 102 including at least one dielectric layer 120 and a plurality of interconnects 122. The at least one dielectric layer 120 may represent the dielectric layer 1020 and / or the dielectric layer 1022. The plurality of interconnects 122 may represent the interconnects 1002, 1012, and / or 1014.

[0107]

[0119] Different implementation forms can use different processes to form the metal layer(s) and / or interconnects. In some implementation forms, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or an electroplating process can be used to form the metal layer(s).

[0108] Exemplary flow diagram of a method for fabricating a substrate

[0120] In some implementation forms, fabricating a substrate includes several processes. FIG. 11 shows an exemplary flow diagram of a method 1100 for providing or fabricating a substrate. In some implementation forms, the method 1100 of FIG. 11 can be used to provide or fabricate the substrate(s) of the present disclosure. For example, the method 1100 of FIG. 11 can be used to fabricate the substrate 102.

[0109]

[0121] Note that the method 1100 of FIG. 11 can combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate. In some implementation forms, the order of the processes can be changed or modified.

[0110]

[0122] The method prepares a carrier (e.g., 1000) at (1105). Different implementation forms can use different materials for the carrier 1000. The carrier 1000 can include a seed layer (e.g., 1001). The seed layer 1001 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 10A illustrates and describes an example of a carrier provided with a seed layer.

[0111]

[0123] The method forms and patterns interconnects on the carrier 1000 and the seed layer 1001 (at 1110). A metal layer can be patterned to form the interconnects. A plating process can be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer can include a metal layer. The metal layer is located on the seed layer and can be patterned to form interconnects (e.g., 142). Step 1 of FIG. 10A illustrates and describes an example of forming and patterning interconnects on the seed layer and the carrier.

[0112]

[0124] The method forms a dielectric layer 1020 on the seed layer 1001, the carrier 1000, and the interconnects 1002 (at 1115). A deposition process and / or a lamination process can be used to form the dielectric layer 1020. The dielectric layer 1020 can include a prepreg and / or a polyimide. The dielectric layer 1020 can include a photoimageable dielectric. Forming the dielectric layer 1020 can also include forming a plurality of cavities (e.g., 1010) within the dielectric layer 1020. The plurality of cavities can be formed using an etching process (e.g., a photolithography etching process) or a laser process. Steps 2-3 of FIG. 10A illustrate and describe an example of forming the dielectric layer and the cavities within the dielectric layer.

[0113]

[0125] The method forms interconnects within and on the dielectric layer (at 1120). For example, interconnects 1012 can be formed within and on the dielectric layer 1020. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects can also include forming interconnects within the cavities of the dielectric layer. Step 4 of FIG. 10A illustrates and describes an example of forming interconnects within and on the dielectric layer.

[0114]

[0126] The method forms a dielectric layer 1022 (at 1125) over the dielectric layer 1020 and the interconnect 1012. A deposition process and / or a lamination process may be used to form the dielectric layer 1022. The dielectric layer 1022 may include a prepreg and / or a polyimide. The dielectric layer 1022 may include a photoimageable dielectric. Forming the dielectric layer 1022 may also include forming a plurality of cavities (e.g., 1030) within the dielectric layer 1022. The plurality of cavities may be formed using an etching process (e.g., a photolithography etching process) or a laser process. Stages 5 to 6 of FIGS. 10A - 10B illustrate and describe an example of forming a dielectric layer and cavities within the dielectric layer.

[0115]

[0127] The method forms interconnects within and over the dielectric layer (at 1130). For example, an interconnect 1014 may be formed within and over the dielectric layer 1022. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming interconnects within the cavities of the dielectric layer. Forming the interconnects may include forming post - interconnects. Stage 7 of FIG. 10B illustrates and describes an example of forming interconnects within and over the dielectric layer, including forming post - interconnects.

[0116]

[0128] The method separates a carrier (e.g., 1000) from a seed layer (e.g., 1001) (at 1135). The carrier 1000 may be removed and / or ground. The method may also (at 1135) remove a portion of the seed layer (e.g., 1001). An etching process may be used to remove a portion of the seed layer 1001. Stage 8 of FIG. 10B illustrates and describes an example of separating the carrier and removing the seed layer.

[0117]

[0129] Different implementations can use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or an electroplating process can be used to form the metal layer(s).

[0118] Exemplary electronic devices

[0130] FIG. 12 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1202, a laptop computer device 1204, a fixed location terminal device 1206, a wearable device 1208, or an autonomous vehicle 1210 may include a device 1200 as described herein. The device 1200 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1202, 1204, 1206, and 1208, and the vehicle 1210 shown in FIG. 12 are merely examples. Other electronic devices including, but not limited to, a group of devices (e.g., electronic devices) such as mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS)-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented within an autonomous vehicle (e.g., a self-driving vehicle), or any other device that stores or retrieves data or computer instructions, or any combination thereof, may also incorporate the device 1200.

[0119]

[0131] One or more of the components, processes, features, and / or functions shown in FIGS. 1-2, 3A-3B, 4A-4B, 5, 6A-6C, 7, 8A-8C, 9, 10A-10B, and 11-12 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. Note that the FIGS. 1-2, 3A-3B, 4A-4B, 5, 6A-6C, 7, 8A-8C, 9, 10A-10B, and 11-12 in the present disclosure, and their corresponding descriptions, are not limited to dies and / or ICs. In some implementations, FIGS. 1-2, 3A-3B, 4A-4B, 5, 6A-6C, 7, 8A-8C, 9, 10A-10B, and 11-12, and their corresponding descriptions may be used to manufacture, construct, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, a heat dissipation device, and / or an interposer.

[0120]

[0132] Note that the FIGS. in the present disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the FIGS. may not be to an exact scale. In some cases, not all components and / or parts may be shown for clarity purposes. In some cases, the position, location, size, and / or shape of various parts and / or components in the FIGS. may be exemplary. In some implementations, various components and / or parts in the FIGS. may be optional.

[0121]

[0133] The term "exemplary" is used herein to mean "an example, instance, or serving as an illustration." None of the implementation forms or aspects described herein as "exemplary" should be construed as necessarily being more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not necessarily require that all aspects of the present disclosure include the features, advantages, or modes of operation being described. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., a mechanical coupling) between two objects. For example, if object A is physically in contact with object B and object B is in contact with object C, then object A and object C can still be considered to be coupled to each other even if they are not physically in direct contact with each other. Object A coupled to object B can be coupled to at least a part of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., a signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not have an electric current propagating between the two of them. The use of the terms "first", "second", "third", and "fourth" (and / or anything greater than the fourth) is discretionary. Any of the components being described can be the first component, the second component, the third component, or the fourth component. For example, a component referred to as the second component can also be the first component, the second component, the third component, or the fourth component. The terms "enclose", "enclosing", and / or their derivatives mean that an object can partially enclose or completely enclose another object. The terms "upper" and "bottom" are discretionary. A component located in the upper part may be located above a component arranged in the bottom part. In some cases, an upper component may be regarded as a bottom component, and vice versa.As described in this disclosure, a first component positioned “over” a second component can mean that the first component is positioned above or below the second component, depending on how the bottom or top is optionally defined. In another example, the first component may be positioned on (e.g., above) the first surface of the second component, and the third component may be positioned on (e.g., below) the second surface of the second component, where the second surface is on the opposite side of the first surface. In the context of one component being positioned on top of another component, as used in this application, the term “on top of” can be used to mean a component that is present on and / or within another component (e.g., present on the surface of the component or embedded within the component). Therefore, for example, a first component present on top of a second component can mean that (1) the first component is present on top of the second component but not in direct contact with the second component, (2) the first component is present on the second component (e.g., on the surface of the second component), and / or (3) the first component is present within the second component (e.g., embedded within the second component). A first component positioned “in” a second component may be partially positioned within the second component or may be completely positioned within the second component. A value that is about X to XX can mean a value between X and XX, including X and XX. The value(s) between X and XX can be discrete or continuous. As used in this disclosure, the term “about ‘value X’” or “approximately value X” means within a range of 10 percent of “value X”. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0122]

[0134] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, the interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), pillars, metallization layers, redistribution layers, and / or under bump metallization (UBM) layers / interconnects. In some implementations, the interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. The interconnect may include two or more elements or components. The interconnect may be defined by one or more interconnects. The interconnect may include one or more metal layers. The interconnect can be part of a circuit. Different implementations can use different processes and / or sequences to form the interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or an electroplating process may be used to form the interconnect.

[0123]

[0135] Note also that various disclosures included herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. Flowcharts can describe operations as sequential processes, but many of those operations can be performed in parallel or simultaneously. Furthermore, the order of the operations can be rearranged. A process ends when its operations are complete.

[0124]

[0136] Further examples are described below to facilitate understanding of the present disclosure.

[0125]

[0137] Aspect 1: A package comprising a substrate having a first surface and a second surface, a first integrated device coupled to the first surface of the substrate, an interconnect die coupled to the first surface of the substrate, a first encapsulation layer coupled to the first surface of the substrate, the first encapsulation layer encapsulating the first integrated device and the interconnect die, and a second integrated device coupled to the second surface of the substrate.

[0126]

[0138] Aspect 2: The package according to Aspect 1, wherein the interconnect die comprises a die substrate and a plurality of die interconnects.

[0127]

[0139] Aspect 3: The package according to Aspect 2, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 - 270 micrometers.

[0128]

[0140] Aspect 4: The package according to Aspects 1 - 3, wherein the interconnect die has a thickness in the range of about 100 - 200 micrometers.

[0129]

[0141] Aspect 5: The package according to Aspects 2 - 4, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0130]

[0142] Aspect 6: The package according to Aspects 2 - 5, wherein the die substrate includes glass and / or silicon.

[0131]

[0143] Aspect 7: The package according to Aspects 1 - 6, further comprising a second encapsulation layer coupled to the second surface of the substrate.

[0132]

[0144] Aspect 8: The package according to Aspect 7, further comprising an outer metal layer coupled to the second encapsulation layer.

[0133]

[0145] Aspect 9: The package according to Aspects 1 - 8, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0134]

[0146] Aspect 10: The package according to Aspects 1 to 9, wherein the interconnect die is positioned laterally to the first integrated device.

[0135]

[0147] Aspect 11: The package according to Aspects 1 to 10, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0136]

[0148] Aspect 12: A device comprising a package. The package includes a substrate having a first surface and a second surface, a first integrated device coupled to the first surface of the substrate, an interconnect die coupled to the first surface of the substrate, a first encapsulation layer coupled to the first surface of the substrate and encapsulating the first integrated device and the interconnect die, and a second integrated device coupled to the second surface of the substrate.

[0137]

[0149] Aspect 13: The device according to Aspect 12, wherein the interconnect die includes a die substrate and a plurality of die interconnects.

[0138]

[0150] Aspect 14: The device according to Aspect 2, wherein thirteen adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 to 270 micrometers.

[0139]

[0151] Aspect 15: The device according to Aspects 12 to 14, wherein the interconnect die has a thickness in the range of about 100 to 200 micrometers.

[0140]

[0152] Aspect 16: The device according to Aspects 13 to 15, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0141]

[0153] Aspect 17: The device according to Aspects 13 to 16, wherein the die substrate includes glass and / or silicon.

[0142]

[0154] Aspect 18: The device according to any one of Aspects 12 to 17, further comprising a second encapsulation layer bonded to the second surface of the substrate.

[0143]

[0155] Aspect 19: The device according to Aspect 18, further comprising an outer metal layer bonded to the second encapsulation layer.

[0144]

[0156] Aspect 20: The device according to any one of Aspects 12 to 19, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0145]

[0157] Aspect 21: The device according to any one of Aspects 12 to 20, wherein the interconnect die is positioned laterally to the first integrated device.

[0146]

[0158] Aspect 22: The device according to any one of Aspects 12 to 21, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0147]

[0159] Aspect 23: The device according to any one of Aspects 12 to 22, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0148]

[0160] Aspect 24: A method for fabricating a package. The method includes providing a substrate having a first surface and a second surface. The method includes bonding a first integrated device to the first surface of the substrate. The method includes bonding an interconnect die to the first surface of the substrate. The method includes bonding a first encapsulation layer to the first surface of the substrate, the first encapsulation layer encapsulating the first integrated device and the interconnect die. The method includes bonding a second integrated device to the second surface of the substrate.

[0149]

[0161] Aspect 25: The method according to aspect 24, wherein the interconnected die comprises a die substrate and a plurality of die interconnects.

[0150]

[0162] Aspect 26: The method according to aspect 25, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 to 270 micrometers.

[0151]

[0163] Aspect 27: The method according to aspects 24 to 26, wherein the interconnected die has a thickness in the range of about 100 to 200 micrometers.

[0152]

[0164] Aspect 28: The method according to aspects 25 to 27, wherein the plurality of die interconnects includes via die interconnects and pad die interconnects.

[0153]

[0165] Aspect 29: The method according to aspects 25 to 28, wherein the die substrate includes glass and / or silicon.

[0154]

[0166] Aspect 30: The method according to aspects 24 to 29, further comprising bonding a second encapsulation layer to a second surface of the substrate.

[0155]

[0167] The various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Therefore, the present teachings can be readily applied to other types of devices, and many alternative forms, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A substrate having a first surface and a second surface, A first integrated device bonded to the first surface of the substrate, An interconnection die bonded to the first surface of the substrate, A first encapsulation layer bonded to the first surface of the substrate, the first encapsulation layer encapsulating the first integrated device and the interconnection die, A second integrated device bonded to the second surface of the substrate, The interconnection die is provided, die substrate and Multiple die interconnection sections, A package comprising, wherein each of the plurality of die interconnects includes a via die interconnect, a pad die interconnect coupled to the via die interconnect, and a solder interconnect directly coupled to the via die interconnect.

2. The package according to claim 1, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of approximately 150 to 270 micrometers.

3. The package according to claim 1, wherein the interconnecting die has a thickness in the range of about 100 to 200 micrometers.

4. The package according to claim 1, wherein the die substrate includes glass and / or silicon.

5. The package according to claim 1, further comprising a second encapsulation layer bonded to the second surface of the substrate.

6. The package according to claim 5, further comprising an outer metal layer bonded to the second encapsulation layer.

7. The package according to claim 1, wherein the first integrated device includes a first chiplet, and the second integrated device includes a second chiplet.

8. The package according to claim 1, wherein the interconnection die is located laterally to the first integrated device.

9. A device comprising the package according to any one of claims 1 to 8, wherein the device is selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in an automatic vehicle.

10. A method for creating a package, A substrate having a first surface and a second surface is prepared, The first integrated device is bonded to the first surface of the substrate, The interconnection die is bonded to the first surface of the substrate, The first encapsulation layer is bonded to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die. The second integrated device is bonded to the second surface of the substrate, The interconnection die includes, die substrate and Multiple die interconnection sections, A method comprising, wherein each of the plurality of die interconnects includes a via die interconnect, a pad die interconnect coupled to the via die interconnect, and a solder interconnect directly coupled to the via die interconnect.

11. The method according to claim 10, wherein two adjacent die interconnects from the plurality of die interconnects have a pitch in the range of about 150 to 270 micrometers.

12. The method according to claim 10, wherein the interconnecting die has a thickness in the range of about 100 to 200 micrometers.

13. The method according to claim 10, wherein the die substrate includes glass and / or silicon.

14. The method according to claim 10, further comprising bonding a second encapsulation layer to the second surface of the substrate.

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