Sequential complementary FETs incorporating a backside power delivery network via wafer bonding prior to active device formation

Abstract

A semiconductor device includes a backside power rail over a bulk semiconductor material, a first junction dielectric layer over the backside power rail, a first transistor stage over the first junction dielectric layer, a second junction dielectric layer over the first transistor stage, and a second transistor stage over the second junction dielectric layer. The first transistor stage includes a first channel structure having a first epitaxially grown semiconductor material. The second transistor stage includes a second channel structure having a second epitaxially grown semiconductor material. The backside power rail is spaced from the first transistor stage by the first junction dielectric layer. The first transistor stage is spaced from the second transistor stage by the second junction dielectric layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 344,141, filed May 20, 2022, U.S. Provisional Patent Application No. 63 / 344,143, filed May 20, 2022, U.S. Provisional Patent Application No. 63 / 344,144, filed May 20, 2022, U.S. Provisional Patent Application No. 63 / 344,146, filed May 20, 2022, and U.S. Provisional Patent Application No. 63 / 344,148, filed May 20, 2022, which are incorporated by reference in their entireties herein. Aspects of the present disclosure are related to Applicant's U.S. Pat. Nos. 10,586,765 and 10,770,479, as well as Applicant's patent applications entitled "Method to Form Silicon-Germanium Nanosheet Structures," "Method for Wrap-Around Contact Formation Through the Incorporation of Cladding of an Etch-Selective Semiconductor Material," "Method of Forming Confined Growth S / D Contact with Selective Deposition of Inner Spacer for CFET," and "Method to Reduce Parasitic Resistance for CFET Devices Through Single Damascene Processing of Vias," all of which U.S. patents and patent applications are incorporated herein by reference in their entireties.

[0002] FIELD This disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, and to microfabrication methods. [Background technology]

[0003] In the fabrication of semiconductor devices (especially on a microscopic scale), various fabrication processes are performed, such as film formation deposition, etch mask formation, patterning, material etching and removal, and doping processes. These processes are performed repeatedly to form the desired semiconductor device elements on the substrate. Historically, in microfabrication, transistors have been formed in one plane with wiring / metallization formed above the active device plane, and thus characterized as two-dimensional (2D) circuits or 2D fabrication. Although scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, scaling efforts face greater challenges as scaling enters single-digit nanometer semiconductor device fabrication nodes. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of one another. Summary of the Invention

[0004] The present disclosure relates to semiconductor devices and methods of forming semiconductor devices.

[0005] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes bonding a first wafer to a second wafer via a first bonding dielectric layer. The first wafer includes a first bulk semiconductor material. The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed on the second bulk semiconductor material. The second bulk semiconductor material is removed to leave the first stack uncovered. A first transistor stage is formed from the first stack. A third wafer is bonded to the second wafer via a second bonding dielectric layer. The third wafer includes a second stack of alternating layers of epitaxially grown semiconductor layers formed on a third bulk semiconductor material. The third bulk semiconductor material is removed. A second transistor stage is formed from the second stack. The first bulk semiconductor material is removed to leave the first bonding dielectric layer uncovered. A power distribution network is formed in contact with the first bonding dielectric layer, the power distribution network including a backside power rail in contact with a via extending through the first bonding dielectric layer.

[0006] In some embodiments, the backside power rail is formed after forming the first transistor stage and the second transistor stage.

[0007] In some embodiments, local interconnect (LI) structures connected to source / drain (S / D) structures of the first transistor stage are formed before the third wafer is bonded to the second wafer, and at least one via is formed connecting to each LI structure and extending through the first bonding dielectric layer.

[0008] In some embodiments, each backside power rail is formed in contact with at least one via.

[0009] In some embodiments, at least one via opening is formed leaving the first bulk semiconductor material uncovered. The at least one via opening is partially filled with a fill material. LI openings are formed including respective LI openings connecting to the at least one via opening. The fill material is removed. The LI openings and the at least one via opening are filled with a conductive material to form a LI structure and at least one via.

[0010] In some embodiments, after the third wafer is bonded to the second wafer, LI structures connected to the S / D structures of the second transistor stage are formed, and at least one via is formed connecting to each LI structure and extending through the second bonding dielectric layer and the first bonding dielectric layer.

[0011] In some embodiments, each backside power rail is formed in contact with at least one via.

[0012] In some embodiments, at least one via opening is formed leaving the first bulk semiconductor material uncovered. The at least one via opening is partially filled with a fill material. LI openings are formed including respective LI openings connecting to the at least one via opening. The fill material is removed. The LI openings and the at least one via opening are filled with a conductive material to form a LI structure and at least one via.

[0013] In some embodiments, at least one via is formed extending through the second junction dielectric layer and configured to electrically connect a first S / D structure of a first transistor stage to a second S / D structure of a second transistor stage.

[0014] In some embodiments, a signal routing layer is formed above the second transistor stage.

[0015] In some embodiments, vias are formed connecting the signal wiring layer to the first transistor stage and the second transistor stage.

[0016] In some embodiments, the carrier wafer is bonded to a third wafer before the first bulk semiconductor material is removed to leave the first bonding dielectric layer uncovered.

[0017] In some embodiments, after the power delivery network is formed, the carrier wafer is bonded to the backside power rail or a fourth bulk semiconductor material is formed over the backside power rail.

[0018] According to a second aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a backside power rail over a bulk semiconductor material, a first junction dielectric layer over the backside power rail, a first transistor stage over the first junction dielectric layer, a second junction dielectric layer over the first transistor stage, and a second transistor stage over the second junction dielectric layer. The first transistor stage includes a first channel structure having a first epitaxially grown semiconductor material. The second transistor stage includes a second channel structure having a second epitaxially grown semiconductor material. The backside power rail is spaced apart from the first transistor stage by the first junction dielectric layer, and the first transistor stage is spaced apart from the second transistor stage by the second junction dielectric layer.

[0019] In some embodiments, at least one backside power rail overlaps each S / D structure of the first transistor stage along a thickness direction of the bulk semiconductor material.

[0020] In some embodiments, there is no semiconductor material between the backside power rails.

[0021] In some embodiments, there is no semiconductor material between the first transistor stage and the backside power rail.

[0022] In some embodiments, the semiconductor device further includes a signal wiring layer above the second transistor stage.

[0023] In some embodiments, the semiconductor device further includes a first via extending through the first junction dielectric layer and configured to electrically connect a first backside power rail to the respective S / D structures of the first transistor stage, and a second via extending through the first junction dielectric layer and the second junction dielectric layer and configured to electrically connect a second backside power rail to the respective S / D structures of the second transistor stage.

[0024] In some embodiments, the first transistor stage includes a gate-all-around transistor.

[0025] It should be noted that this Summary section does not specify all embodiments and / or inherently novel aspects of the present disclosure or claimed invention. Instead, this Summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For further details and / or anticipated aspects of the invention and embodiments, the reader is directed to the Detailed Description section of this disclosure and corresponding figures, discussed further below. [Brief description of the drawings]

[0026] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, according to standard industry practice, various features are not drawn to scale, and in fact, dimensions of various features may be expanded or reduced for clarity of discussion.

[0027] [Figure 1A] FIG. 2 is a cross-sectional perspective view of a semiconductor device according to some embodiments of the present disclosure, taken orthogonally to a metal interconnect structure. [Figure 1B] FIG. 2 is a cross-sectional perspective view of a semiconductor device according to some embodiments of the present disclosure, the cross-sectional perspective view being orthogonal to a metal gate structure. [Figure 2A]FIG. 2 is a cross-sectional perspective view of a semiconductor device in a related example. [Figure 2B] FIG. 2 is a cross-sectional perspective view of a semiconductor device in a related example. [Figure 2C] FIG. 2 is a cross-sectional perspective view of a semiconductor device in a related example. [Diagram 3] 1 is a flow chart of a process for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 4] 4 is a flow chart of a process for manufacturing a semiconductor device according to another embodiment of the present disclosure. [Diagram 5] 13 is a flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure. [Figure 6] 13 is a flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure. [Figure 7] 13 is a flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure. [Figure 8] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 9] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 10] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 11] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 12] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 12B] FIG. 13 is an enlarged view of box R12 in FIG. 12 according to one embodiment of the present disclosure. [Figure 13]1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 13B] FIG. 14 is an enlarged view of box R13 in FIG. 13 according to one embodiment of the present disclosure. [Figure 14] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 14B] FIG. 15 is an enlarged view of box R14 in FIG. 14 according to one embodiment of the present disclosure. [Figure 15] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 15B] FIG. 16 is an enlarged view of box R15 in FIG. 15 according to one embodiment of the present disclosure. [Figure 16] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 17] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 18] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 19] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 20] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 21] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 22] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 22B] FIG. 23 is an enlarged view of box R22 in FIG. 22 according to one embodiment of the present disclosure. [Figure 23]1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 24] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 25] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 25B] FIG. 26 is a close-up view of box R25 in FIG. 25 according to one embodiment of the present disclosure. [Figure 26] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 27] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 28] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 29] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 30] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 30B] FIG. 31 is a close-up view of box R30 in FIG. 30 according to one embodiment of the present disclosure. [Diagram 31] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 31B] FIG. 32 is a close-up view of box R31 in FIG. 31 according to one embodiment of the present disclosure. [Diagram 32] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 32B] FIG. 33 is a close-up view of box R32 in FIG. 32 according to one embodiment of the present disclosure. [Diagram 33]1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 33B] FIG. 34 is a close-up view of box R33 in FIG. 33 according to one embodiment of the present disclosure. [Diagram 34] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 35] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 36] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 37] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 38] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 39] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 40] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 40B] FIG. 41 is a close-up view of box R40 in FIG. 40 according to one embodiment of the present disclosure. [Diagram 41] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 41B] FIG. 42 is an enlarged view of square R41 in FIG. 41 according to one embodiment of the present disclosure. [Diagram 42] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 43] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 44] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Diagram 45] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 46] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 47] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 48] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 49] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 50] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 51] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 52] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 52B] FIG. 53 is an enlarged view of box R52 in FIG. 52 according to one embodiment of the present disclosure. [Diagram 53] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 54] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 55] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 56]1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 57] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 58] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 59] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 60] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 61] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 62] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 63] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 64] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 65] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 66] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 67] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 68] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 69]1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. [Figure 70] 1A-1D are cross-sectional perspective views of a semiconductor device at various intermediate steps in its manufacture, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The following disclosure provides various embodiments or examples for implementing various features of the presented subject matter. To simplify the disclosure, specific examples of components and configurations are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, a configuration of a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations being discussed. Furthermore, spatially relative terms such as "top", "bottom", "lower", "below", "lower", "lower", "upper", "above" and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures: the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0029] The order of description of the different steps described herein is presented for clarity. In general, the steps can be performed in any suitable order. Moreover, although each of the various features, techniques, configurations, etc. described herein may be described in separate parts of this disclosure, it is understood that each concept can be performed independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0030] 3D integration, or the vertical stacking of multiple devices, aims to overcome the scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. Device stacking has been successfully demonstrated and implemented by the flash memory industry by adopting 3D NAND, but its application to random logic designs is much more difficult in practice. 3D integration for logic chips (CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), SoC (System on Chip)) is being promoted.

[0031] Buried power rail (BPR) technology can be expected to be integrated into new CMOS technology nodes that are expected to be in mass production within the next few years. However, buried power rail technology has several drawbacks, such as: (1) the width of the buried power rail is limited by the presence of residual FINs under the nanosheet stack, (2) the metallization of the buried power rail by filling and recess etching processes introduces significant variations that may adversely affect device performance, (3) it is difficult to incorporate buried signal lines along with the buried power rail due to the presence of the substrate and residual FIN structures under the nanosheet stack, and (4) the wafer backside formation of the buried power rail makes it very difficult to make connections to the interconnects that connect to the source and drain contacts, since any edge placement errors (EPEs) caused by misalignment of critical dimension (CD) variations can easily lead to unintentional shorting of vias to transistors in the above etching process.

[0032] There is a need for a more flexible backside wiring approach that can provide VDD / VSS power through very large structures to provide good IR drop and a larger interface area for connecting vias or dropped interconnect structures to minimize parasitic resistance. There is also a need to be able to incorporate not only backside power but also backside signal wiring that can be used for a variety of applications such as (a) further reducing the standard cell height by incorporating some tracks of M0 on the wafer backside, and (b) incorporating alternative methods to form cross-couples for SRAM devices.

[0033] The techniques disclosed herein include a method for forming a stacked field effect transistor device. The method includes bonding a wafer having a first layer stack of alternating epitaxial layers to another wafer having a dielectric layer through a first bonding dielectric layer to form a composite wafer. A first gate-all-around transistor stage is formed from the first stack. A third wafer is bonded to the composite wafer. The third wafer has a second layer stack of alternating epitaxial layers from which a second gate-all-around transistor stage is formed after wafer bonding, the second gate-all-around transistor stage being complementary to that of the first gate-all-around transistor stage. A power supply network can then be formed in or adjacent to the first bonding dielectric layer to enable wider power rails.

[0034] U.S. Patent No. 10,586,765, entitled "Buried power rails," describes a method in which portions of the power delivery network (PDN) are placed underneath the active devices and transistors of CMOS logic and SRAM to provide significant area scaling, allowing the large VDD and VSS power rails to be removed from the traditional back-end-of-line (BEOL) and thus reducing the height of standard cells by making the power rails accessible through the bottom of the active devices and transistors.

[0035] FIG. 2A shows a diagram of a buried or backside power rail. As used herein, "buried power rail" generally refers to a power rail formed during front-end-of-line (FEOL) integration. As used herein, "backside power rail" generally refers to a power rail formed after the wafer is flipped to expose the wafer backside. For example, power rails 241a and 241b are shown in black and represent high index and high conductivity metals such as ruthenium, tungsten, molybdenum, or other similar metals. These power rails can be used as buried VDD and VSS rails and can be formed either (1) during front-end-of-line (FEOL) integration (where the choice of metal becomes important given the number of high temperature processes incorporated this early in the conventional CMOS device manufacturing process) or (2) alternatively after BEOL processing has been performed (also referred to as backside power rail) (where the wafer is simply flipped to expose the wafer backside where the bulk silicon substrate can be ground down to a point where the backside power rail can be formed). In the latter case, this allows for a larger selection of metals (such as copper) that do not have the high heat treatment limitations and have potentially better electrical conductivity for a given rail size.

[0036] The power rails 241a and 241b must be connected to the source and drain contacts (also called source and drain structures or S / D structures) 213a and 213b of the CMOS devices, which can be achieved by a number of techniques, including but not limited to: (a) extending metal interconnects downward past the shallow trench isolation (STI) 206 to directly contact the buried power rails; (b) incorporating vias 231a and 231b that extend downward from the metal interconnects 219a and 219b past the STI 206 to directly contact the power rails 241a and 241b; (c) or the reverse of (b), where the vias are formed as part of the backside power rail formation process, and the vias are in effect formed to connect the power rails upward to the direct contacts or to the interconnect metal in contact with the source and drain contacts.

[0037] In most applications incorporating buried power rails, the power rails (e.g., 241a or 241b) are effectively limited to trenches transferred into the bulk substrate (e.g., 201). This imposes some limitations on the buried power rails (e.g., 241a or 241b) with respect to their width and, consequently, their IR drop, as well as the amount of space available to connect between VSS / VDD and its corresponding interconnects or source and drain contacts. For any given standard cell height, the width of the buried power rails (e.g., 241a and 241b) will affect what width of nanosheets can be used and the minimum space between NMOS and PMOS. Optimization is performed for a given device to optimize power, performance, and area, but this is a constrained optimization. The reason for these limitations is that the residual FIN structures 209a or 209b used in the nanosheet generation process are still present in the current integration, which prevents any increase in the width of the power rails (e.g., 241a and 241b).

[0038] However, in the backside processing approach to the backside power rails, the bulk substrate (e.g., 201) is ground down to the STI oxide (e.g., 206), so that the residual FIN structures 209a and 209b no longer connect to the bulk (e.g., 201). However, the residual FIN structures, e.g., 209 and 209b, under the nanosheet device remain. The impact of this approach is that the width of the (backside) power rails 241a and 241b can be increased to improve IR drop, but in this case, the (backside) power rails 241a and 241b must be formed below the bottom of the residual silicon FINs 209a and 209b, which means that the vias 231a and 231b that connect to the interconnect metal (e.g., 219a and 219b) now need to be much taller, resulting in higher parasitic resistance. In the case of CFET integration, where NMOS and PMOS devices are stacked on top of each other, this parasitic resistance is already one of the major causes of power and performance impacts, so any increase in the height of these vias is not recommended without a parallel increase in the width of the vias to offset the additional resistance caused by the taller vias.

[0039] The buried or backside power rails may need to be well isolated from the transistors and source and drain contacts that pull up the signal lines in the BEOL. This can be seen in Figures 2B and 2C. In this particular example, power rails 241c and 241d are filled with metal and then recessed down (e.g., through a metal etch process) or run through a bottom-up metal fill process, and then the tops of power rails 241c and 241d are refilled with either oxide or another dielectric, or to form a type of etch-selective dielectric cap (e.g., 202c and 202d) on top of the metallized power rails 241c and 241d.

[0040] Buried power rail technology can be expected to be integrated into new CMOS technology nodes that are expected to be in mass production within the next few years. However, buried power rail technology has several drawbacks, such as: (1) the width of the buried power rail is limited by the presence of residual FINs under the nanosheet stack, (2) the metallization of the buried power rail by filling and recess etching processes introduces significant variations that may adversely affect device performance, (3) it is difficult to incorporate buried signal lines along with the buried power rail due to the presence of the substrate and residual FIN structures under the nanosheet stack, and (4) the wafer backside formation of the buried power rail makes it very difficult to make connections to the interconnects that connect to the source and drain contacts, since any edge placement errors (EPEs) caused by misalignment of critical dimension (CD) variations can easily lead to unintentional shorting of vias to transistors in the above etching process.

[0041] There is a need for a more flexible backside wiring approach that can provide VDD / VSS power through very large structures to provide good IR drop and a larger interface area for connecting vias or dropped interconnect structures to minimize parasitic resistance. There is also a need to be able to incorporate not only backside power but also backside signal wiring that can be used for a variety of applications such as (a) further reducing the standard cell height by incorporating some tracks of M0 on the wafer backside, and (b) incorporating alternative methods to form cross-couples for SRAM devices.

[0042] 1A and 1B show cross-sectional perspective views of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes a backside power rail 141 (e.g., as indicated by 141a, 141b, 141c, and 141d) on a bulk semiconductor material 147. A first junction dielectric layer 105a is disposed on the backside power rail 141. A first transistor stage 110 is disposed on the first junction dielectric layer 105a. A second junction dielectric layer 105b is disposed on the first transistor stage 110. A second transistor stage 120 is disposed on the second junction dielectric layer 105b. A signal wiring layer 107 having a signal line 108 is disposed on the second transistor stage 120.

[0043] Herein, the backside power rail 141 is spaced apart from the first transistor stage 110 by a first bonding dielectric layer 105a, which is spaced apart from the second transistor stage 120 by a second bonding dielectric layer 105b. The backside power rails 141 may be separated from each other by a dielectric material 142. A backside power rail metal liner or barrier 144 may be disposed on the top and sidewalls of the backside power rail 141. In another embodiment, a silicon-on-insulator (SOI) wafer may be used, and the first transistor stage 110 may be made from the top portion of the SOI wafer. Thus, 105a represents the insulator of the SOI wafer. The advantage of the sequential bonding approach to the formation of the backside power distribution network over incorporating SOI wafers is that it allows the incorporation of an etch stop layer (ESL) into the bonding dielectric, which is not feasible with simple SOI wafers. The incorporation of an etch stop layer (ESL) is important for advanced processing where it may be desirable to have the interconnect connect to the backside power supply directly underneath the actual source / drain contacts.

[0044] 1A and 1B, note that in contrast to conventional devices such as semiconductor device 200A in which residual bulk semiconductor material (e.g., 201) and / or residual FIN structures (e.g., 209a and 209b) exist between adjacent buried power rails (e.g., 241a and 241b), no semiconductor material is present between the first transistor stage 110 and the backside power rail 141. In particular, no semiconductor material is present within the first junction dielectric layer 105a disposed between the first transistor stage 110 and the backside power rail 141.

[0045] As a result, the backside power rails 141 herein can be wider in the Y direction than the conventional buried power rails (e.g., 241a and 241b). For example, although not shown, at least one backside power rail (e.g., 141a) can overlap a respective S / D structure (e.g., 113a) in the Z direction. This cannot be achieved in conventional devices such as semiconductor device 200A, where the residual FIN structures 209a and 209b prevent the conventional buried power rails 241a and 242b from overlapping the S / D structures 213a and 213b in the Z direction. In other words, the residual FIN structures 209a and 209b limit the lateral dimensions of the conventional buried power rails 241a and 242b.

[0046] The semiconductor device 100 may also include vias 131 (e.g., as illustrated by 131a, 131b, 131c, 131d, 131e, 131f, 131g, and 131h) configured to electrically connect the transistors to a backside power rail 141 or to a signal wiring layer 107. For example, at least one first via (e.g., 131d) extends through the first bonding dielectric layer 105a and is configured to electrically connect a first backside power rail (e.g., 141c) to each source / drain (S / D) structure (e.g., 113c) of the first transistor stage 110. At least one second via (e.g., 131b and 131e) extends through the first and second bonding dielectric layers 105a and 105b and is configured to electrically connect the second backside power rail (e.g., 141b and 141d) to the respective S / D structures (e.g., 123b and 123c) of the second transistor stage 120. At least one third via (e.g., 131c) extends through the second bonding dielectric layer 105b and is configured to electrically connect the respective S / D structures (e.g., 113b) of the first transistor stage 110 to the signal wiring layer 107. At least one fourth via (e.g., 131a) extends through the second bonding dielectric layer 105b and is configured to electrically connect the respective S / D structures (e.g., 113a) of the first transistor stage 110 to the respective S / D structures (e.g., 123a) of the second transistor stage 120. At least one fifth via (e.g., 131f) extends through the second bonding dielectric layer 105b and is configured to electrically connect the respective gate structures (e.g., 115a) of the first transistor stage 110 to the signal wiring layer 107.

[0047] Semiconductor device 100 may further include local interconnect (LI) structures 119 and 129 (e.g., as indicated by 119a, 129a, and 129c) configured to electrically connect the S / D structures of the transistors to via 131. For example, LI structure 119a is configured to electrically connect S / D structure 113a to via 131a.

[0048] 1A and 1B, the first transistor stage 110 includes a first channel structure 111 (e.g., as indicated by 111a, 111b, and 111c) and a first gate structure 115 (e.g., as indicated by 115a). The first transistor stage 110 may include one or more (e.g., three) first transistors of n-type or p-type arranged in the Y direction. Each of the first transistors may include one or more (e.g., three) first channel structures 111 stacked in the Z direction. As a result, each of the first sets of channels / nanosheets (e.g., 111a) are connected within the same metal gate structure (e.g., 115a). That is, the metal gate metal (e.g., 118a) may be disposed all around the channel structures (e.g., 111a) stacked in the Z direction.

[0049] Similarly, the second transistor stage 120 includes a second channel structure 121 (e.g., as shown by 121a) and a second gate structure 125 (e.g., 125a). The second transistor stage 120 may include one or more (e.g., three) second transistors of n-type or p-type arranged in the Y direction. Each of the second transistors may include one or more (e.g., three) second channel structures 121 stacked in the Z direction. As a result, each of the second sets of channels / nanosheets (e.g., 121a) is connected within the same metal gate structure (e.g., 125a). That is, the metal gate metal (e.g., 128a) may be disposed all around the channel structures (e.g., 121a) stacked in the Z direction.

[0050] Further, it should be understood that the semiconductor device 100 may include any number of transistor stages (eg, 110 and 120) disposed above the bulk semiconductor material 147 in the Z direction.

[0051] It should be noted that the first channel structure 111 may be formed of a first epitaxially grown semiconductor material (e.g., silicon), while the second channel structure 121 may be formed of a second epitaxially grown semiconductor material. As used herein, "epitaxial growth," "epitaxial deposition," "epitaxially grown," "epitaxially formed," or "epitaxy" generally refers to a type of crystal growth or material deposition in which a crystalline layer is formed on a seed layer that is crystalline. The crystalline properties (e.g., crystal orientation) of the crystalline layer are related to or determined by the crystalline properties of the seed layer. In particular, a semiconductor material may also be epitaxially grown on the surface of another semiconductor layer that is crystalline. In some embodiments, epitaxial growth may be selective such that a semiconductor material may only grow epitaxially on another semiconductor surface and not deposit on exposed surfaces of non-semiconductor materials, typically silicon oxide, silicon nitride, etc. Epitaxial growth may be achieved by molecular beam epitaxy, vapor phase epitaxy, liquid phase epitaxy, etc. Si, SiGe, Ge, and other semiconductor materials may be doped (in situ) during epitaxial growth by the addition of dopants. For example, in vapor phase epitaxy, dopant vapor may be added to a gas source.

[0052] In some embodiments, the at least two channel structures may include different chemical compositions from each other. That is, the at least two channel structures may include different semiconductor materials, different dopants, and / or different dopant concentration profiles. For example, the first channel structure 111 may include a different chemical composition from the second channel structure 121. In one example, the first channel structure 111 may include: <100> The second channel structure 121 comprises silicon. <110> In another embodiment, the first channel structure 111 comprises silicon and the second channel structure 121 comprises silicon germanium. Additionally, the first channel structure 111 and the second channel structure 121 can have various shapes or geometries (e.g., nanosheets).

[0053] In some embodiments, each of the first gate structures 115 includes at least one gate dielectric 117 (e.g., as indicated by 117a), such as a high-k dielectric, and at least one gate metal 118 (e.g., as indicated by 118a, 118b, and 118c), such as a work function control metal (WFM). Similarly, each of the second gate structures 125 includes at least one gate dielectric 127 (e.g., as indicated by 127a), such as a high-k dielectric, and at least one gate metal 128 (e.g., as indicated by 128a, 128b, and 128c), such as a WFM. As can be appreciated, depending on the respective channel structures (e.g., 111a and 121a), design requirements (e.g., gate threshold voltage), etc., the gate metals 118 and 128 that function as gate conductors may be the same or different from each other, and the gate dielectrics 117 and 127 may also be the same or different from each other. In this example, at least one gate metal 118 is disposed around the entire periphery of the first channel structure 111, and at least one gate metal 128 is disposed around the entire periphery of the second channel structure 121. Thus, both the first gate structure 115 and the second gate structure 125 may be configured to function as a common gate structure for multiple channel structures. In other examples (not shown), the first gate structure 115 and / or the second gate structure 125 may each be disposed around the entire periphery of a single channel structure. Although both gate metals 118 and 128 are shown with a single material, each of the gate metals 118 and 128 may be made of two or more layers of metals having different work functions. Similarly, each of the gate dielectrics 117 and 127 may be made of two or more layers of dielectric materials.

[0054] In some embodiments, silicide (e.g., as shown by 114a, 114b, 124a, and 124c) may be disposed all around each S / D structure to form a wrap-around S / D contact. In this example, the first S / D structure 113 (e.g., 113a, 113b, and 113c) and the second S / D structure 123 (e.g., 123a, 123b, and 123c) are each configured to electrically connect to one or more (e.g., three) channel structures. In alternative embodiments, the first S / D structure 113 and / or the second S / D structure 123 may directly contact only one respective channel structure. Thus, the semiconductor device 100 may include one or more single-channel transistors.

[0055] In one embodiment, the first bonding dielectric layer 105a is formed by fusion bonding of silicon oxide, or any other suitable bonding dielectric, and may have one or more bonding defects (not shown) at the bonding interface. As will be appreciated by those skilled in the art, such bonding defects at the bonding interface may include, but are not limited to, non-bonded areas, voids (e.g., vacuum or air bubbles), trapped particles, cracks, and the like. Such bonding defects may be characteristic of the semiconductor device 100. In other words, the first bonding dielectric layer 105a may not be a single piece, and thus the bonding interface may differ from a dielectric layer traditionally formed by deposition techniques, as it may differ from the interface between two layers, one layer deposited or formed on top of the other. Such bonding defects may be characterized or detected by known techniques, such as acoustic microimaging, infrared transmission spectroscopy, double cantilever beam testing, (micro)chevron testing, bond strength measurements, white light interferometry, and the like. In another embodiment, no bonding defects are present at the bonding interface. Thus, the first bonding dielectric layer 105a may be a single piece. Similarly, the second bonding dielectric layer 105b may or may not have one or more bonding defects.

[0056] In this embodiment, the first bonding dielectric layer 105a is formed by, for example, fusion bonding of silicon oxide. In another embodiment (not shown), the first bonding dielectric layer 105a may be bonded by another wafer bonding technique, such as surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding, etc. Thus, the first bonding dielectric layer 105a may include one or more different dielectric bonding materials. Similarly, the second bonding dielectric layer 105b may include one or more different dielectric bonding materials.

[0057] In some embodiments, the semiconductor device 100 may include dielectric materials, such as those shown by 103, 105a, 105b, 107, 117, 133, 142, 143, 145, and 146. The dielectric materials may also be referred to as isolation structures, isolation layers, diffusion breaks, inner spacers, gate dielectrics, capping layers, junction dielectrics, contact etch stop layers (CESLs), liners, barriers, etc., depending on their functions. For example, the dielectric material 143 may function as a liner and as an etch stop layer. The dielectric material 133 may function as a capping layer in the LI structures (e.g., 119a and 129a). In addition, some of the dielectric materials may include the same material or different materials. For example, the dielectric materials 142 and 145 may include the same material, such as silicon oxide.

[0058] 1A and 1B, in some embodiments, a shell structure (e.g., 112a) may be disposed entirely around a middle portion of the channel structure (e.g., 111a). This is further described in FIG. 32 and 32B. The shell structure (e.g., 112a) may be formed of a semiconductor material having a lattice mismatch with the first epitaxially grown semiconductor material to form, for example, a strained channel. In addition, the semiconductor device 100 may include an inner spacer (not shown) disposed between each gate structure and each source / drain (S / D) structure. This is shown and further described in FIG. 15 and 15B.

[0059] In a non-limiting example, FIG. 1A shows a cross-sectional perspective view of a substrate segment perpendicular to the nanosheets and parallel along the source and contact planes. FIG. 1A illustrates many embodiments herein, including the absence of residual substrate (e.g., 201 in FIG. 2A) or residual FIN structures (e.g., 209a and 209b in FIG. 2A) under the source and drain contacts (e.g., 113a, 113b, and 113c), relatively (very) wide backside power lines (e.g., 141) that are no longer limited in size based on the presence of residual FIN or residual substrate, confined source and drain epitaxy profiles, wrap-around silicide (e.g., 114a, 124a, and 124c) and metal (e.g., 131a and 119a) around the source and drain contacts, very wide vias (e.g., 131e) connecting the backside power (e.g., 141d) to the source and drain interconnects (e.g., 129c) as a means of reducing parasitic resistance, particularly in complementary FET (CFET) devices, and self-aligned minimum dielectric spacing between the upsized vias and any complementary metal interconnects.

[0060] In a non-limiting example, FIG. 1B shows the completed concept from a cross-sectional view perpendicular to the nanosheets and parallel along the transistor plane. From here, many of the features of the present disclosure can be seen. These features include: Removal of residual substrate or residual FIN structure below the device eliminates the need for a bottom dielectric isolation process (although one is shown in the image). Inter-stage vias (e.g., 131g) connect complementary transistors to form a common NMOS / PMOS gate. Special processing on the PMOS channel enhances hole mobility because the strain effect from the substrate is negated due to the removal of the substrate. Note that in this case, silicon germanium cladding (e.g., 112a) is shown above the PMOS silicon channel (e.g., 111a), but this could be replaced by a pure silicon germanium or even germanium channel as well, and by placement of the PMOS channel on a higher device stage, where the final wafer bond of the PMOS active device stack is composed of a bulk silicon wafer of preferred crystal orientation to promote hole mobility. Here, the vias (e.g., 131f and 131h) connecting the BEOL input signal lines (e.g., 108) to the lower transistor stages (e.g., 110) can be similarly increased in size to improve resistance, and these vias (e.g., 131f and 131h) are patterned in the BEOL incorporating a single damascene process for the original signal lines. Although not shown, it should be understood that the inter-gate vias (e.g., 131g) can similarly extend downward to connect to the backside power supplies (e.g., 141b and / or 141c) to form gate tie-downs, if desired.

[0061] FIG. 3 shows a flow chart of a process 300 for manufacturing a semiconductor device, such as the semiconductor device 100, according to one embodiment of the present disclosure. The process 300 begins in step S310 by bonding a first wafer to a second wafer via a first bonding dielectric layer. The first wafer includes a first bulk semiconductor material. The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed on the second bulk semiconductor material. The second bulk semiconductor material is removed to leave the first stack uncovered. The process 300 then proceeds to step S320, where a first transistor stage is formed from the first stack. In step S330, a third wafer is bonded to the second wafer via a second bonding dielectric layer. The third wafer may include a second stack of alternating layers of epitaxially grown semiconductor layers formed on the third bulk semiconductor material. The third bulk semiconductor material is removed. In step S340, a second transistor stage is formed from the second stack. The first bulk semiconductor material is removed to leave the first bonding dielectric layer uncovered. In step S350, a power distribution network is formed in contact with the first bonding dielectric layer. The power distribution network includes a backside power rail in contact with a via extending through the first bonding dielectric layer.

[0062] FIG. 4 shows a flowchart of a process 400 for manufacturing a semiconductor device, such as the semiconductor device 100, according to another embodiment of the present disclosure. The process 400 begins by forming a first transistor stage and a second transistor stage on the first transistor stage in step S410. The first transistor stage is formed on a first junction dielectric layer on a first bulk semiconductor material. The second transistor stage is formed on the second junction dielectric layer. The second junction dielectric layer separates the first transistor stage from the second transistor stage. The first transistor stage and the second transistor stage have gate-all-around transistors. In step S420, a first via opening is formed that extends through the first transistor stage and the first junction dielectric layer. In step S430, after the first via opening is formed, a first local interconnect (LI) opening is formed that connects with the first via opening. In step S440, a second via opening is formed, the second via opening extending through the second transistor stage, the second junction dielectric layer, the first transistor stage, and the first junction dielectric layer. In step S450, after the second via opening is formed, a second LI opening connecting with the second via opening is formed.

[0063] FIG. 5 shows a flow chart of a process 500 for manufacturing a semiconductor device, such as the semiconductor device 100, according to yet another embodiment of the present disclosure. The process 500 begins in step S510 by forming a stack of epitaxially grown layers of alternating first and second semiconductor materials having etch selectivity to the first semiconductor material. In step S520, a fin structure is formed from the stack. The fin structure includes a channel structure formed of the first semiconductor material. In step S530, source / drain (S / D) structures are formed on both ends of the channel structure by epitaxially growing a third semiconductor material. In step S540, a silicide is formed around the S / D structure.

[0064] FIG. 6 shows a flow chart of a process 600 for fabricating a semiconductor device, such as the semiconductor device 100, according to yet another embodiment of the present disclosure. The process 600 begins in step S610 by forming a stack of epitaxially grown layers of alternating first and second semiconductor materials having etch selectivity to the first semiconductor material. In step S620, a fin structure is formed from the stack. The fin structure includes a channel structure formed of the first semiconductor material. The channel structure has both ends that are uncovered. In step S630, sidewall suppressors are formed at both ends of the channel structure. Each pair of sidewall suppressors laterally bounds a respective source / drain (S / D) region at each end of the channel structure with a respective top opening for accessing the respective S / D region. In step S640, a third semiconductor material is epitaxially grown between each pair of sidewall suppressors to form an S / D structure on both ends of the channel structure.

[0065] FIG. 7 shows a flow chart of a process 700 for fabricating a semiconductor device, such as the semiconductor device 100, according to yet another embodiment of the present disclosure. The process 700 begins in step S710 by forming a stack of epitaxially grown layers of alternating first and second semiconductor materials having etch selectivity to the first semiconductor material. In step S720, a fin structure is formed from the stack. The fin structure includes a channel structure formed of the first semiconductor material. In step S730, the cross section of the channel structure is reduced. In step S740, a third semiconductor material is formed around the entire periphery of the channel structure. The third semiconductor material has a lattice mismatch with the first semiconductor material.

[0066] 8-69 show cross-sectional perspective views of a semiconductor device 800 at various intermediate stages of fabrication according to some embodiments of the present disclosure. For example, although detailed integration may be shown with respect to a sequential CFET device, it should be noted that portions of the present disclosure that relate only to a backside power delivery network may be incorporated into monolithic CFET devices as well as conventional gate-all-around (GAA) devices. It should be noted that the semiconductor device 800 may ultimately become the semiconductor device 100.

[0067] 8, a semiconductor device 800 includes a wafer composite, for example provided by a third party or formed by bonding a first wafer W1 to a second wafer W2 via a first bonding dielectric layer 805a. The first wafer W1 includes a first bulk semiconductor material 801a. The second wafer W2 includes a first stack 851' of alternating layers of epitaxially grown semiconductor layers (e.g., 811 and 853) formed on a second bulk semiconductor material 801b.

[0068] In some embodiments, a silicon substrate (e.g., 801a) is deposited with a suitable bonding dielectric material, such as a liner, which may be comprised of a material such as silicon nitride, or silicon nitride (e.g., 803) with silicon oxide (e.g., 805a), which is the actual bonding dielectric material.

[0069] A second silicon substrate (e.g., 801b) having a gate-all-around nanosheet stack (e.g., 851) (a relatively small stack of layers / sheets for formation into a GAA device) composed of silicon (e.g., 811) and various silicon germanium layers (e.g., 853) is similarly deposited with a suitable liner such as SiCN or silicon nitride (e.g., 803) along with a layer of silicon oxide (e.g., 805a) to be used as a bonding dielectric for bonding to the first wafer (e.g., W1) also having a top surface composed of silicon oxide.

[0070] A second wafer (e.g., W2) is flipped vertically so that the nanosheet active stack (e.g., 851') is facing down, and this wafer (e.g., W2) is then placed on top of the first wafer (e.g., W1) and bonded as shown below.

[0071] In this embodiment, the first wafer W1 and the second wafer W2 are bonded by fusion bonding. In another embodiment (not shown), the first wafer W1 and the second wafer W2 may be bonded by another wafer bonding technique, such as surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding, etc. Thus, the first bonding dielectric layer 105a may include one or more different dielectric bonding materials.

[0072] In an alternative embodiment, as described above, a silicon-on-insulator (SOI) approach is used: instead of wafer bonding, a first stack 851′ of alternating semiconductor layers (e.g., 811 and 853) is epitaxially grown on a SOI wafer that includes a silicon substrate (e.g., 801a), an insulator (e.g., 805a), and a single crystal silicon layer (e.g., 811).

[0073] 9, the second bulk semiconductor material 801b is removed to leave the first stack 851′ uncovered, which is then patterned to form free-standing fin structures 851 (e.g., as shown by 851a, 851b, and 851c). As a result, the fin structure 851 includes a first semiconductor material 811 and a second semiconductor material 853 alternately stacked on top of each other in the Z direction. The first semiconductor material 811 is also referred to as a first channel structure 811.

[0074] In some embodiments, the upper wafer backside silicon substrate (e.g., 801b) may then be removed by a combination of processes including, for example, wafer grinding, polishing, etching, or any combination of the above. Optionally, an epitaxial layer 854 composed of high germanium content silicon germanium, or even germanium, may be used as an etch stop to protect the active stack (e.g., 851) from damage during removal of the bulk substrate (e.g., 801b) from the upper wafer (e.g., W2).

[0075] Next, the nanosheet active stack (e.g., 851') is patterned into a FIN structure (e.g., 851) and the silicon (e.g., 811) / silicon germanium (e.g., 853) FIN is etched to stop either on the liner (e.g., 803) used in the wafer bonding process or on another dielectric layer (e.g., 852) on top of the bonding dielectric liner material (e.g., 803). As an example, in this integration, a level of silicon oxide (e.g., 852) is present on top of the SiCN liner (e.g., 803) that protects the silicon oxide bonding dielectric (e.g., 805a). Now, since the FIN structure (e.g., 851) ends with the dielectric (e.g., 852), there is no longer a residual silicon FIN under the nanosheet stack (e.g., 851) as there is in a conventional gate-all-around (GAA) process. Then, in Figs. 10-35, a first transistor stage 810 can be formed from the first stack 851'.

[0076] 10, a protective film 861 is formed over the fin structure 851. A dummy gate 863 is formed over the protective film 861. A hard mask material 865 is formed over the dummy gate 863. The hard mask material 865 and the dummy gate 863 are then patterned, for example, in a direction perpendicular to the fin structure (e.g., Y direction), with the protective film 861 protecting the fin structure 851.

[0077] In some embodiments, a chemical oxide or thermal oxide liner (e.g., 861) may be formed on the silicon / silicon germanium FIN structure (e.g., 851) to protect the FIN (e.g., 851) from any etching in the dummy gate formation process. After forming the oxide liner (e.g., 861) on the FIN structure (e.g., 851), the dummy gate (e.g., 863) is formed through a process of deposition of a dummy gate material such as amorphous silicon followed by deposition of some type of hard mask material (e.g., 865), which in this example is silicon nitride. The dummy gate (e.g., 863) is patterned orthogonal to the FIN structure (e.g., 851), and then the pattern is transferred through a silicon nitride hard mask (e.g., 865), which in turn becomes the cap material on the dummy gate structure (e.g., 863), which is transferred to the amorphous silicon (e.g., 863) to form the actual dummy gate structure (e.g., 863). The presence of an oxide liner (e.g., 861) on top of the FIN structures (e.g., 851) prevents etching of the silicon / silicon germanium FIN structures (e.g., 851) during pattern transfer of the dummy gate through the amorphous silicon (e.g., 863). These FIN structures (e.g., 851) extend continuously across the dummy gate structures (e.g., 863), allowing a single diffusion break cut process to be used for this integration if desired.

[0078] 11 , a suppression material 867 is formed to cover the fin structure 851. The suppression material 867 includes a top suppression portion 868 that covers the fin structure 851 from above and a sidewall suppression portion 869 that covers the fin structure 851 from the side and defines a future S / D region. In particular, the suppression material 867 may be conformally deposited on the fin structure 851. The exposed portion of the protective film 861 may be removed prior to the formation of the suppression material 867.

[0079] In some embodiments, a first low-k gate spacer material (e.g., 867) is conformally deposited over the dummy gate structure (e.g., 863) and optionally over the surface of the silicon / silicon germanium FIN structure (e.g., 851).

[0080] 12 and 12B, upper restraint portions 868 of restraining material 867 are removed to leave fin structure 851 uncovered in the future S / D regions, with sidewall restraints 869 retained at either end of first channel structure 811. As a result, each pair of sidewall restraints (e.g., 869a) laterally bounds a respective future S / D region at each end of the first channel structure (e.g., 811a).

[0081] In some embodiments, the low-k spacer material (e.g., 867) may be opened to expose the top of the silicon / silicon germanium FIN structure (e.g., 851). Because an anisotropic etching process is used to open the low-k gate spacer material (e.g., 867), no lateral consumption of the low-k gate spacer (e.g., 867) occurs. Thus, the thickness of the low-k spacer is set to maximize overall power / performance / area by reducing capacitance between the metal gate and metal interconnect while minimizing standard cell size and maintaining the required contacted poly pitch (CPP) dimensions for required area scaling.

[0082] 13 and 13B, the exposed portions of the fin structure 851 between each pair of sidewall suppressors (e.g., 869a) are removed to open future S / D regions. In some embodiments, the silicon / silicon germanium FINs (e.g., 851) may be removed by an anisotropic etching process. The etching process should be highly selective to the low-k gate spacer material (e.g., 867) such that the low-k gate spacers (e.g., 867) leave preserved "shoulders" (e.g., 869) that are later used for confined source and drain contact formation.

[0083] In Figures 14 and 14B, recesses are formed in the second semiconductor material 853. For example, if a silicon nanosheet (e.g., 811) is used, the silicon germanium (e.g., 853) can be selectively recessed with high precision to form the physical gate length of the transistor. Note that also disclosed herein is the construction of silicon germanium nanosheets where the initial FIN composition is no longer silicon and silicon germanium, but instead is composed of two silicon germanium materials with significantly different germanium content. Thus, silicon germanium nanosheets with 15-25% germanium can be formed through selective etching of silicon germanium with a much higher germanium content, such as 40% or more. Of course, the limit on the amount of germanium composition in the FIN structure (e.g., 851) may be limited by the pseudo-stress limit at which subsequent epitaxy layers begin to relax, which may be undesirable, so care may be needed to precisely define these stacks based on maintaining strain in the epitaxy stacks, the etch selectivity available in defining the actual nanosheet patterning, and the desired hole mobility required for the PMOS device.

[0084] In Figures 15 and 15B, an inner spacer 862 is recessed. In some embodiments, the recessed silicon germanium (e.g., 853) needs to be filled with an inner spacer dielectric material, which may or may not be the same as the low-k gate spacer material (e.g., 867). Conventional means of cavity-fill deposition may be used here, but may be detrimental to preserving the low-k gate spacer dielectric shoulder (e.g., 869) required for subsequent confined source and drain contact growth. Similarly, cavity-filling of the recessed silicon germanium space may also lead to seam formation in the inner spacer region, which is undesirable. An alternative approach is to incorporate a selective deposition process to form the inner spacer 862. In this example, the inner spacer material is the same as the low-k gate spacer (e.g., 867) (both are SiOC), but multiple materials may be used for both materials if the dielectric constants of the different materials are appropriate.

[0085] In a non-limiting selective deposition process, a native oxide (not shown) can be formed on both the exposed silicon nanosheets (e.g., 811) and the recessed silicon germanium (e.g., 853). From here, the SiGeO is selectively removed without disturbing the native oxide on the silicon nanosheets (e.g., 811). After selectively removing the SiGeO, a self-aligned monolayer (SAM) material is deposited on the bottom that selectively bonds to dielectric materials such as (a) the native oxide on the silicon nanosheets (e.g., 811), (b) the low-k gate spacer material (e.g., 867), and (c) the junction dielectric and junction dielectric liner materials (e.g., 805a and 803). With the SAM in place covering the dielectric surface but not over the removed silicon germanium material (e.g., 853), the inner spacer material can be selectively deposited over the surface of the silicon germanium (e.g., 853) and thus completely surrounding the recessed regions and not over the surfaces of the low-k gate spacers or low-k gate spacer shoulders (e.g., 869) required for confined source and drain growth. It should be understood that other selective deposition processes may also be used herein.

[0086] 16, the end portion 811i (or ends or both ends) of the first channel structure 811 is optionally recessed. For example, after the inner spacer (e.g., 862) is fully formed and the SAM is removed by a thermal process, the silicon nanosheet (e.g., 811) is then slightly recessed into the low-k gate spacer (e.g., 867) or inner spacer (e.g., 862) to form the desired extension area of ​​the device.

[0087] In FIG. 17, a first S / D structure 813 (e.g., as shown by 813a, 813b, and 813c) is formed on an end portion 811i of a first channel structure 811 by epitaxially growing a third semiconductor material between sidewall suppression portions 869 that laterally confine the third semiconductor material.

[0088] For example, if a PMOS device is in a lower device tier, then boron doped silicon germanium source and drain (e.g., 813) can be grown, where the low-k gate spacer dielectric shoulder (e.g., 869) confines the shape of the contact (e.g., 813) to the lateral width of the nanosheet (e.g., 811) itself, thereby allowing large room for placement of complementary vias needed to connect higher tier devices to a backside power source.

[0089] Preferably, the tops of the source and drain contacts (e.g., 813) do not protrude significantly beyond the top of the low-k gate spacer dielectric shoulder (e.g., 869) because they would tend to form a very wide diamond-shaped profile that would take away critical space needed for placement of complementary vias connecting the upper device stages to the backside power supply. Note that some height reduction is seen in the preserved dielectric shoulder (e.g., 869) in the initial low-k gate spacer release process used to expose the initial silicon / silicon germanium FIN structure (e.g., 851) that is later removed by anisotropic etching. A way to avoid the formation of diamond shaped epitaxy on top of the contacts (e.g., 813) is by extending the height of the top silicon germanium film on the top of the initial silicon / silicon germanium FIN structure (e.g., 851) to compensate for the expected vertical erosion of the preserved dielectric shoulder (e.g., 869) so that the epitaxial growth of the contacts (e.g., 813) does not exceed the full height of the shoulder (e.g., 869).

[0090] In FIG. 18, the sidewall suppression portion 869 is removed. In some embodiments, after the lower step source and drain contacts (e.g., 813) are formed, the low-k gate spacer shoulder (e.g., 869) is anisotropically removed. This spacer cannot be isotropically removed because doing so would remove the low-k gate spacer (e.g., 867) that covers the amorphous silicon dummy gate (e.g., 863) that needs to be preserved. The low-k gate spacer shoulder (e.g., 869) may be removed by anisotropic etching, which simultaneously anisotropically removes the same height low-k gate spacer (e.g., 867) from the sidewall of the dummy gate (e.g., 863). Establishing the height of the initial dummy gate hard mask cap (e.g., 865) can ensure that the anisotropic etch used to remove the low-k gate spacer (e.g., 867) does not recess the low-k gate spacer (e.g., 867) below the point where the amorphous silicon dummy gate (e.g., 863) is exposed. Thus, in this example, the selection of the initial silicon nitride cap (e.g., 865) over the dummy gate cap (e.g., 863) is set to a relatively high aspect ratio to ensure that the shoulder (e.g., 869) is removed.

[0091] It could be said that the low-k spacer shoulders (e.g., 869) could be preserved and etched away in a subsequent interconnect trench etch process. However, in this particular example, a novel wrap-around contact process is used. Thus, the shoulders (e.g., 869) are removed and the entire side surface area of ​​the contacts (e.g., 813) is exposed for this process.

[0092] It is worth noting that the selection of the dielectric bonding material (e.g., 805a) and bonding liner (e.g., 803) is also important to this process in order to maintain a good / sufficient dielectric bottom after the low-k spacer shoulder (e.g., 869) is removed. Thus, the selection of the bonding dielectric liner (e.g., 803) is important, and there is the option of having multiple liner stacks to provide whatever etch selectivity is needed to prevent the silicon oxide (e.g., 805a) from being etched in this process.

[0093] 19, a sacrificial film 871 may optionally be formed around the first S / D structure 813 by epitaxially growing a fourth semiconductor material having etch selectivity to the third semiconductor material (e.g., 813). A contact etch stop layer (CESL) film 872 may optionally be formed around the sacrificial film 871.

[0094] In the wraparound contact approach, the exposed source and drain contacts (e.g., 813) may have a semiconductor material selectively deposited thereon, such as by a low temperature CVD epitaxy process, where for example a silicon germanium film (e.g., 871) having a different germanium content than the PMOS boron doped silicon germanium contacts (e.g., 813) may be grown on the surface of the source and drain contacts (e.g., 813). In a CVD epitaxy process, this is inherently selective. In other material choices for this initial sacrificial wraparound film, a selective deposition process may be used in which any native oxide is removed from the contacts and then an etch selective film (e.g., 871) may be selectively deposited on the surface of the contact structure (e.g., 813) prior to deposition of a SAM material that selectively adheres to the dielectric and not to the surface of the contact (e.g., 813) from which the native oxide has been removed.

[0095] After a conformal selective semiconductor liner (e.g., 871) is grown or deposited on the contact structures (e.g., 813), a CESL (e.g., 872) must also be conformally deposited on the contact structures (e.g., 813). This film (e.g., 872) can also be formed using a selective deposition process, but to form a high quality CESL film (e.g., 872) requires plasma and high temperatures that are detrimental to the SAM, which is not preferred.

[0096] 20, an interlayer dielectric (ILD) film 873 is formed and optionally planarized to fill spaces. A via opening 878a is formed in the ILD film 873 leaving the first bulk semiconductor material 801a uncovered. The via opening 878a is partially filled with a fill material 874 to protect at least the first bonding dielectric layer 805a.

[0097] Again, the wrap-around contacts (WAC) (e.g., 871) are optional, although it may be necessary to ensure that the contact resistance is minimized as much as possible to provide maximum power / performance / area scaling, since the interfacial surface area between the contacts (e.g., 813) and the final metal interconnect will be much smaller in a confined contact structure compared to a diamond shaped contact structure.

[0098] Additionally, an advantage of the confined contact structures (e.g., 813) is that the WAC process also allows the interconnect to extend vertically down along the sidewalls of the contact structures (e.g., 813) to maximize the interfacial surface area connection. In contrast, in diamond-shaped contact structures, the connection between the contact and the interconnect metal is limited to only the top of the diamond-shaped contact because the remainder of the contact structure below the maximum lateral width is occluded by the geometry of the diamond-shaped contact.

[0099] After the wrap-around contact (WAC) structure (e.g., 871) is formed, a dielectric film (e.g., 872) may then be deposited to fill the contact area with some type of interlayer dielectric (e.g., 873), such as silicon nitride.

[0100] After formation of the ILD film 873, a hardmask stack 876a is deposited on top of the planarized ILD film (e.g., 873) to store the final interconnect structure. Once the interconnect pattern is stored in the hardmask stack 876a, vias connecting the lower device stages to the backside power are patterned and transferred through the ILD oxide (e.g., 873) selective to the CESL (e.g., 872) and semiconductor liner (e.g., 871) on the contacts (e.g., 813).

[0101] It should be noted that at this point in the integration, one may decide to proceed with the transistor formation first and then return to the silicidation of the source and drain contact structures and the interconnect metal formation. In this example, this process is performed first to show how the source and drain silicidation and interconnect formation and metallization are performed. However, it should be understood that there is an option to continue with the replacement metal gate module first at this point since no metal has yet been introduced into the wafer processing at this point.

[0102] In this integration example, the via opening 878a connects down through the bond dielectric liner (e.g., 803) into the bond dielectric itself (e.g., 805a) to the backside power supply, and the etch terminates on the bottom silicon substrate (bulk silicon) (e.g., 801a). To maintain the integrity of the via structure (e.g., 878a), a gap fill of a spin-on material (e.g., 874) such as spin-on carbon (SoC) is deposited in the formed via opening (e.g., 878a), and the gap fill material (e.g., 874) is recess-etched such that the bottom silicon substrate (e.g., 801a) is completely covered. The sidewalls of the CESL liner (e.g., 872) protecting the contact structure (e.g., 813c) may also be covered by the SoC (e.g., 874).

[0103] 21, local interconnect (LI) openings 879 (e.g., as shown by 879a, 879b, and 879c) are formed in the ILD film 873, leaving the CESL film 872 uncovered. In other words, the interconnect trenches (e.g., 879) can then be transferred to the ILD oxide material (e.g., 873). Note that the LI opening 879c can connect or overlap with the via opening 878a.

[0104] 22 and 22B, the CESL film 872 is removed to uncover the sacrificial film 871, which in turn is removed to uncover the first S / D structure 813. For example, the CESL liner (e.g., 872) covering the contacts (e.g., 813) may be removed to expose the surface of the conformal semiconductor liner (e.g., 871) covering the contact structures (e.g., 813). The semiconductor liner (e.g., 871) covering the contacts (e.g., 813) may then be selectively etched away using an isotropic etching process, such as Tokyo Electron's CERTAS etching process, without damaging the contact structures (e.g., 813) or the surface itself. The isotropic removal of the conformal semiconductor liner (e.g., 871) provides an opening in the subsequent interconnect trench (e.g., 879) having a width of the original conformal semiconductor liner thickness, thus allowing silicide formation and metallization to completely wrap around the entire contact structure (e.g., 813).

[0105] In Figure 23, a silicide material 814 (e.g., as shown by 814a, 814b, and 814c) is formed all around the first S / D structure 813. For example, after the conformal semiconductor liner (e.g., 871) is removed, the source and drain contacts (e.g., 813) are removed, and a suitable silicide material (e.g., 814) is made available to be formed on the exposed surfaces, along with any metal capping material (e.g., 814) such as TiN on the silicide that may be formed by a subsequent plasma termination process. An advantage of sequential or monolithic CFET processing is that the appropriate silicide materials for the NMOS and PMOS source and drain contacts can be selected separately. The initial semiconductor liner material (e.g., 871) encapsulating the source and drain contacts (e.g., 813) is now removed, thereby leaving most of the source and drain contacts (e.g., 813) exposed, leaving a "tunnel" through which silicide formation and subsequent metallization steps can occur.

[0106] 24, the fill material 874 is removed from the via opening 878a. Vias 831d and LI structures 819 (e.g., as shown by 819a, 819b, and 819c) are then formed in the via opening 878a and the LI opening 879.

[0107] For example, the gap fill spin-on carbon film (e.g., 874) may be ashed away prior to interconnect metallization. The SoC (e.g., 874) is maintained during the silicide formation process to prevent any silicide formation on the lower substrate wafer (e.g., 801a). Note that the lower junction dielectric liner material may be selected to also act as a suitable etch stop layer for the initial via pattern transfer through the ILD silicon oxide dielectric (e.g., 873) and the silicon oxide junction dielectric (e.g., 805a).

[0108] The interconnect trenches (e.g., 879a, 879b, and 879c) and elongated vias (e.g., 878a) can then be filled with a highly conductive metal. This process can be done by a conventional metal fill followed by a metal polishing step followed by an etchback recess selective to metal only, or by an underfill metal deposition process that eliminates the need for a metal CMP (chemical mechanical polishing / planarization) processing step. Note that in this example where metallization of the interconnect structures is performed before the replacement metal gate process, there is a recess etch of metal selective to the ILD silicon oxide (e.g., 873) in the high aspect ratio trench. If the replacement metal gate process was performed first, the large silicon nitride cap over the transistor structure would be significantly smaller than depicted here, so the metal recess in this alternative integration requires a very small metal selective recess.

[0109] In Figures 25 and 25B, the LI structure 819 is recessed and a capping layer 833 is formed over the LI structure 819. In this exemplary integration, the metal (e.g., 819) is recessed selectively to exposed dielectric materials such as the ILD silicon oxide (e.g., 863), low-k gate spacers (e.g., 867), and silicon nitride caps (e.g., 865) over the dummy gates (e.g., 873). As discussed above, when this process is performed after the replacement metal gate formation, the high aspect ratio silicon nitride dummy gate caps are replaced by much smaller silicon nitride caps over the actual transistors.

[0110] To allow some type of self-alignment for subsequent processing steps, an etch-selective dielectric capping material (e.g., 833) can be deposited (a) selectively on top of the metal interconnect structure (e.g., 819), or (b) formed by a sequential deposition / polish / recess etch method. For this integration example, the capping material includes a material such as SiCN, whose nitride content is reduced to provide etch selectivity among other dielectric materials present, such as low-k gate spacers (SiOC) (e.g., 867), ILD dielectrics (silicon oxide) (e.g., 873), and dummy gate caps (silicon nitride) (e.g., 865), or, in the case of an alternative integration where replacement metal gate integration is performed first, a metal gate cap (which is also silicon nitride).

[0111] 26, an ILD film 873 is deposited to fill the spaces, after which an etching, polishing, and / or planarization process is performed to remove the hard mask material 865 down to the level of the dummy gate 863. That is, the contact areas may be filled with an ILD dielectric (e.g., 873), such as silicon oxide, and then the wafer (e.g., 800) may be polished down to the dummy gate amorphous silicon (e.g., 863).

[0112] Figures 26 and 27 may show semiconductor device 800 at different cross sections at the same process. For example, Figure 26 may show a perspective view of a cross section along the S / D structure, while Figure 27 may show a perspective view of a cross section along the transistor (e.g., channel structure and gate structure). In Figure 27, an amorphous silicon dummy gate (e.g., 863) is now shown.

[0113] 28, the dummy gate 863 is removed leaving uncovered the protective film 861 covering the fin structure 851. For example, the dummy gate amorphous silicon (e.g., 863) can then be removed with high selectivity to the surrounding dielectric material as well as the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium FIN structure (e.g., 851).

[0114] In FIG. 29, the protective film 861 is removed to leave the fin structure 851 uncovered. For example, after removal of the amorphous silicon (e.g., 863), the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium FIN structure (e.g., 851) may then be removed. Herein, the selection of material for the low-k gate spacer (e.g., 867) is important to have some selectivity to the removal of the chemical oxide liner (e.g., 861) protecting the FIN structure (e.g., 851). In such cases, other suitable low-k dielectric materials with higher selectivity to chemical oxide may be used.

[0115] In Figures 30 and 30B, the second semiconductor material 853 is selectively removed relative to the first channel structure 811. For example, after the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium FIN structure (e.g., 851) is removed, the silicon germanium (e.g., 853) can be etched with high selectivity relative to the silicon (e.g., 811), thus creating the silicon nanosheet structure (e.g., 811). In the case of silicon germanium nanosheet processing, the initial FIN structure (e.g., 851) is composed of two distinct germanium content silicon germanium, and the silicon germanium material with the higher germanium content can be etched with high selectivity relative to the silicon germanium material with the lower content, thus releasing a set of stacked silicon germanium nanosheets.

[0116] 31 and 31B, the first channel structure 811 is shrunk and the rectangular edges of the nanosheet are rounded in the process, for example by an isotropic etching process. In particular, the exposed middle portion 811ii of the first channel structure 811 is shrunk, while the covered end portions 811i of the first channel structure 811 are not etched. As a result, when viewed from the direction of current flow in the first channel structure 811 (e.g., the X-direction), the middle portion 811ii has a smaller circumference than the end portions 811i.

[0117] For example, in the case of PMOS silicon nanosheets, the removal of the bulk substrate (e.g., 801a) directly under the active region significantly reduces strain on the silicon nanosheets (e.g., 811), thus adversely affecting hole mobility in the PMOS silicon channel (e.g., 811). Hole mobility can be enhanced by multiple methods, as discussed in the previous section, such as utilizing different crystal orientations of the bulk silicon wafer for the PMOS device and transistor stage to have a more preferential silicon crystal structure (e.g., 811) along the channel, incorporating a dual silicon germanium FIN structure that can form silicon germanium nanosheets with greater hole mobility compared to silicon, incorporating a silicon germanium cladding process around the trimmed silicon nanosheets, with the advantage being the formation of a binary silicon germanium / silicon channel, as well as providing strain along the channel due to the lattice mismatch between silicon and silicon germanium, etc. Any combination of the above can also be done to incrementally improve hole mobility in PMOS devices. In this example, a silicon germanium cladding process is performed on a silicon channel (e.g., 811) for illustrative purposes. The first step is to isotropically trim the silicon channel (e.g., 811).

[0118] 32 and 32B, a shell structure 812 is formed around the entire periphery of the intermediate portion 811ii of the first channel structure 811. The shell structure 812 is formed of a fifth semiconductor material having a lattice mismatch with the first channel structure 811. For example, after the channel (e.g., 811) is trimmed to a desired width, CVD epitaxy growth of silicon germanium (e.g., 812) can be performed on the silicon surface (e.g., 811) to form a strained PMOS channel.

[0119] 33 and 33B, an intermediate layer 816 of silicon oxide or silicon germanium oxide may optionally be formed around the shell structure 812. At least one gate dielectric 817 may then be formed around the intermediate layer 816. A capping material 875 may optionally be formed around the at least one gate dielectric 817.

[0120] For example, after formation of the PMOS channel, a conventional replacement metal gate process can be performed, in which an intermediate layer 816 of silicon oxide or silicon germanium oxide is grown from the channel (e.g., 811), followed by HfO 2 Such as a conformal or selective deposition of a high-k dielectric film (e.g., 817), followed by deposition of a selective capping material (e.g., 875) such as TiN or amorphous silicon, followed by a given reliability anneal process, followed by removal of the capping material, and finally followed by deposition of a work function controlling metal such as TiN.

[0121] It is important to note that due to the high processing temperatures associated with the reliability anneal, this is actually advantageous for integration where silicide formation around the source and drain contacts and replacement metal gates are performed before metallization of the interconnect.

[0122] It is expected that such reliability anneals may be performed in the future incorporating higher pressure and lower temperature processes, or may be performed using a very rapid anneal step to prevent any phase changes to the formed silicide around the source and drain contacts.

[0123] The advantages of sequential CFET processing over conventional gate-all-around (GAA) integration are seen due to the fact that transistor stacking allows for the use of separate work-function-controlled metallization across both NMOS and PMOS transistors. For conventional GAA HKMG processing, a typical process is (a) deposition of PMOS WFM on both NMOS and PMOS, followed by (b) removal of the PMOS WFM from the NMOS channel, followed by (c) deposition of NMOS work-function-controlled metal on both NMOS and PMOS channels, where the PMOS channel already has the PMOS WFM as the primary metal interfacing with the high-k dielectric. By allowing separate NMOS and PMOS work-function-controlled metal only for the respective channels, this provides a means by which the WFM thickness around the channels can be significantly reduced, while the channels can be placed closer together in a vertical orientation to reduce the height of the metal gate and metal interconnect, thus providing a mechanism for improving device power and performance by reducing the gate-drain capacitance.

[0124] In Figure 34, at least one gate metal 818 is formed around at least one gate dielectric 817. For example, after a PMOS work function controlling metal stack is conformally deposited around the channel, the replacement metal gate is then filled with a highly conductive metal such as tungsten and polished down or recessed etched to form the metal gate.

[0125] In Fig. 35, at least one gate metal 818 is patterned and divided into gate metals 818a, 818b, and 818c separated by dielectric material 877. As a result, gate structures 815 (e.g., as indicated by 815a) are formed to form a first transistor stage 810. In the example of Fig. 35, the first transistor includes a first channel structure 811a, a shell structure 812a, and a gate structure 815a including at least one gate dielectric 817a and at least one gate metal 818a.

[0126] In some embodiments, after the PMOS metal gate (e.g., 818) is formed, a masking process is performed to form cut HKMG that is transferred down into the HKMG stack and then filled with a selected dielectric (e.g., 877), such as silicon nitride or a combination of silicon nitride and silicon oxide, which separates the standard cells from each other in the north-south direction (e.g., Y direction).

[0127] In FIG. 36, a dielectric material 877 is formed over the first transistor stage 810. For example, following formation of the cut HKMG, the replacement metal gate metal stack (e.g., 815) is then recessed vertically down to form a dielectric cap (e.g., 877) over the metal gate (e.g., 815). Typically, such capping material is similar to that used for the cut HKMG, such as silicon nitride. The metal gate cap material (e.g., 877) should be etch selective to both the low-k gate spacer (e.g., 867) and the dielectric cap (e.g., 833) over the metal interconnect (e.g., 819) in the source and drain regions.

[0128] FIG. 37 shows a perspective view along the S / D structure. In FIG. 37, a bonding material 805b' may be formed on top of the first transistor stage 810. For example, the PMOS transistor and source and drain / interconnect are fully formed. A bonding liner (e.g., 803) may be deposited on top of the wafer (e.g., W2) at this point, which may also act as an etch stop layer later during integration. Next, a bonding dielectric (e.g., 805b') is deposited on top of the wafer (e.g., W2) in preparation for the next wafer bonding step where the NMOS active stack is placed on top of the lower transistor / device stage.

[0129] 38, a third wafer W3 is bonded to the second wafer W2 via a second bonding dielectric layer 805b. The third wafer W3 includes a second stack 855' of alternating layers of epitaxially grown semiconductor layers (e.g., 821 and 857) formed on a third bulk semiconductor material 801c.

[0130] For example, the NMOS active stack (e.g., 855') may be grown on a separate wafer (e.g., W3) with deposition of a bond liner (e.g., 803) and a bond dielectric (e.g., 805b') followed by a silicon / silicon germanium device stack. This wafer (e.g., W3) is then flipped on its axis and then bonded to the first wafer (e.g., W1 and W2) having the PMOS transistor (e.g., 810) and devices.

[0131] In FIG. 39, the third bulk semiconductor material 801c is removed to leave the second stack 855′ uncovered, which is then patterned to form an independent fin structure 855 (e.g., as shown by 855a, 855b, and 855c). Thus, the fin structure 855 includes a sixth semiconductor material 821 and a seventh semiconductor material 857 alternately stacked on top of each other in the Z direction. It should be noted that the sixth semiconductor material 821 may be the same or different from the first semiconductor material 811. The seventh semiconductor material 857 may be the same or different from the second semiconductor material 853. The sixth semiconductor material 821 is also referred to as the second channel structure 821.

[0132] In some embodiments, the substrate (e.g., 801c) of the NMOS device stack wafer (e.g., W3) is then ground / polished / etched to expose the NMOS silicon germanium / silicon device stack (e.g., 855'). In other words, the bulk silicon (e.g., 801c) is removed, leaving behind a stack of epitaxially grown layers (nanosheet stacks) (e.g., 855').

[0133] The integration of the previous steps used to form the PMOS devices and transistors (e.g., 810) can be repeated for the upper NMOS transistor and device stages, with a few exceptions: forming interstage connections between source and drain contacts, forming a common gate structure, and also forming a cross-couple between two complementary device stages.

[0134] Similar to the formation of the silicon germanium / silicon FIN structure in the PMOS stage, a similar approach is taken to form the NMOS device stage, where the bond dielectric (e.g., 805b) and liner (e.g., 803) act as suitable etch stops for the termination of the FIN etching process, thus preventing silicon FIN residue from being retained under the upper active devices, and preventing any silicon FIN residue or substrate residue from being retained under the active devices, just as was done for the lower stage (e.g., FIG. 9) when the PMOS active stack was created by a fusion bonding process. This is necessary later in the backside power distribution network formation, where the power lines and any backside signal lines can be formed without interference from any residual FIN structure or residual substrate that would limit the placement of the backside wiring.

[0135] 40 and 40B, the semiconductor device 800 may undergo processes similar to those shown in FIGS. 10, 11, 12, and 12B, such as forming a protective film over the fin structure 855, forming a dummy gate over the protective film, forming a hard mask material over the dummy gate, patterning the hard mask material and the dummy gate, forming a suppression material 867 to cover the fin structure 855, and removing an upper suppression portion 868 of the suppression material 867 to leave the fin structure 855 uncovered in the future S / D region, with sidewall suppression portions 869 retained at both ends of the second channel structure 821. As a result, each pair of sidewall suppression portions (e.g., 869a) laterally bounds a respective future S / D region at each end of the second channel structure (e.g., 821a).

[0136] In some embodiments, the NMOS dummy gate is formed similarly to the previous PMOS dummy gate in the process integration. A similar approach to the low-k gate spacer formation process is performed for the NMOS transistor, and a conformal deposition also covers the protruding silicon / silicon germanium FIN structure (e.g., 855). The low-k gate spacer (e.g., 867) is opened using an anisotropic etching process to expose the protruding silicon / silicon germanium FIN stack (e.g., 855) without causing lateral etching of the low-k gate spacer.

[0137] In Figures 41 and 41B, similar to Figures 13 and 13B, the exposed portions of fin structure 855 between each pair of sidewall restraints (eg, 869a) are removed to open future S / D regions.

[0138] In FIG. 42, similar to FIGS. 14, 14B, 15 and 15B, after the seventh semiconductor material 857 is recessed, inner spacers 862 are formed in the recesses.

[0139] For example, silicon germanium (e.g., 857) may then be laterally recessed to define the physical gate length for the NMOS transistor. The NMOS inner spacer (e.g., 862) is formed similarly to the PMOS inner spacer formation, with the native SiGeO selectively removed relative to the native oxide on the silicon nanosheets, and then a SAM material is deposited that selectively adheres to the dielectric materials (the native oxide on the silicon nanosheets, the low-k gate spacer such as SiOC or SiCBN, and the bond dielectric material such as silicon oxide, and the dielectric liner such as silicon nitride or SiCN). The SAM does not deposit on the silicon germanium surface (e.g., 857), thereby allowing for the direct selective deposition of the inner spacer in the recessed region without causing any disturbance or additional deposition on the low-k gate spacer shoulder (e.g., 869). As with the PMOS device, the inner spacer material (e.g., 862) may be different compared to that of the low-k gate spacer material (e.g., 867), provided that the dielectric constant of the material is within the desired range.

[0140] In FIG. 43, end portions of the second channel structure 821 are optionally recessed, and second S / D structures 823 (e.g., as shown by 823a, 823b, and 823c) are formed on the end portions of the second channel structure 821 by epitaxially growing an eighth semiconductor material between sidewall suppression portions 869 that laterally confine the eighth semiconductor material, similar to FIGS. 16 and 17.

[0141] In some embodiments, the NMOS phosphorus or arsenic doped silicon epitaxy source and drain contacts (e.g., 823) are then grown within the confinement of the low-k gate spacer shoulder (e.g., 869) such that the source and drain width is substantially the same as the nanosheet width, without any diamond shapes growing protruding from either the sides or top of the source and drain contacts (e.g., 823). As was done in the PMOS source and drain contact formation, the top layer of silicon germanium in the initial active FIN structure can be optionally set to a thickness that ensures that the source and drain contacts fully connect to the top layer nanosheet, while not covering the top of the low-k gate spacer shoulder that will be created by CVD epitaxy with larger diamond shapes that would be detrimental to the formation of inter-stage vias that will later be formed to connect the lower stage PMOS devices either to signals above, or the higher stage NMOS devices down to the backside power.

[0142] In FIG. 44, similar to FIGS. 18 and 19, the sidewall suppression portion 869 is removed, a sacrificial film 871 is formed around the second S / D structure 823 by epitaxially growing a ninth semiconductor material having etch selectivity with respect to the eighth semiconductor material, and a contact etch stop layer (CESL) film 872 can be formed around the sacrificial film 871.

[0143] In some embodiments, the low-k gate spacer shoulder (e.g., 869) is removed through an anisotropic etching process in which the lateral width of the low-k gate spacer covering the dummy gate is not etched. The anisotropic etching process will consume the low-k gate spacer vertically, which is why a high aspect ratio silicon nitride cap is placed on top of the amorphous silicon dummy gate structure so that the vertical recess of the low-k gate spacer does not expose any amorphous silicon after the etching process. Similarly, the selection of the bond dielectric liner material is co-optimized with the low-k gate spacer material such that the bond dielectric liner material can be used as a de facto etch stop layer for this process, and the removal of the low-k gate spacer shoulder (e.g., 869) does not damage the bond dielectric material (e.g., 805b) used as isolation between both the complementary device and the transistor.

[0144] Similar to how this was achieved for the PMOS source and drain contacts by growing or depositing an etch-selective semiconductor layer (e.g., 871) over the source and drain contacts (e.g., 823) with the expectation that this conformal semiconductor material (e.g., 871) can later be removed selectively to the source and drain contacts (e.g., 823), wrap-around process integration can also be applied to the NMOS source and drain contacts. A contact etch stop layer (CESL) (e.g., 872) can then be conformally or selectively deposited over the source and drain contacts (e.g., 823).

[0145] In Figure 45, an ILD film 873 is formed and optionally planarized to fill spaces. Via openings 878b and 878c are formed to uncover the first bulk semiconductor material 801a. The via openings 878b and 878c extend through the second junction dielectric layer 805b, the first transistor stage 810, and the first junction dielectric layer 805a.

[0146] At this point in the integration, the priority may be to focus on the replacement metal gate module and build the transistor before forming the metal interconnect for the source and drain contacts. In this exemplary flow, the decision to do the interconnect module first is purely arbitrary and is made for illustration purposes. The module is already accessible in the integration modeling flow. It is important to note that the replacement metal gate (RMG) module may be more likely to start at this stage after the CESL liner is deposited over the contacts.

[0147] This illustrative example continues with local interconnect processing of the upper stage NMOS devices, which looks very similar to what was done for the lower stage PMOS devices, but with some modifications to account for the need for complementary source and drain connections as done for inverters, as well as the need to go through the bond dielectric layers and associated bond dielectric liner material to make the interstage connections.

[0148] In this step, the source and drain regions are filled with an ILD material (e.g., 873) such as silicon oxide, and the expected NMOS interconnect trenches are formed, which are stored in some type of hard mask that is deposited over the ILD (e.g., 873).

[0149] After the upper NMOS interconnect trench pattern is stored in some hardmask material, the via connections connecting the upper NMOS interconnect to the backside power are patterned and then transferred through the ILD oxide (e.g., 873), through the junction dielectric oxide (e.g., 805b) and its associated liner (e.g., 803), through the lower level ILD oxide (e.g., 873), and finally through the lower junction dielectric (e.g., 805a) and its associated liner (e.g., 803). As can be seen in the image below, an etch selective cap (e.g., 833) deposited on top of the lower interconnect metal (e.g., 819) prevents unwanted connections to the lower level PMOS source and drain contacts (e.g., 811) and acts as a self-aligning means to prevent shorts between complementary devices.

[0150] US Patent No. 10,770,479 provides an additional means by which this etch-selective dielectric cap width can be extended through the initial recess of the ILD oxide (e.g., 873) and below the top of the metal interconnect (e.g., 819) so that the conformal or selective deposition of the etch-selective cap effectively partially wraps around the upper portion of the interconnect metal. Thus, the cap width is dependent on the intended thickness of the dielectric cap. The advantage this provides is not only to further maintain proper self-alignment to prevent shorts between complementary devices in a CFET device, but also to define a minimum spacing between vias of individual devices adjacent to that complementary device, thereby preventing potential reliability failures such as TDDB. Additionally, the ability to enforce any minimum spacing between vias and complementary devices also allows the placement of the vias to be optimized to optimize capacitance.

[0151] As with the vias connecting the lower level PMOS interconnect to the backside power supply, the vias connecting the higher level NMOS devices to the backside power supply can be sized much wider to improve parasitic resistance. The self-alignment capabilities of the integration outlined above allow for the increased width of the vias.

[0152] 46, via openings 878b and 878c are filled, for example with fill material 874. Via opening 878d is formed, leaving LI structure 819a uncovered.

[0153] In some embodiments, after the vias (e.g., 878b and 878c) connecting the upper level NMOS interconnects to the backside power supply are formed, they (e.g., 878b and 878c) are then gap filled with a material (e.g., 874) such as spin-on carbon (SoC) that protects the vias (e.g., 878b and 878c) from any additional etching when additional vias (e.g., 878d) are patterned and transferred into the ILD dielectric (e.g., 873).

[0154] In this next case, vias making connections between complementary devices are patterned and transferred through the bonding dielectric (e.g., 805b) and dielectric liner material (e.g., 803) separating the complementary device levels into the upper ILD dielectric (e.g., 873), terminating in an etch-selective dielectric cap (e.g., 833) above the lower PMOS interconnect (e.g., 819a). The etch-selective cap (e.g., 833) can then be opened through a separate etch step selective to the surrounding dielectric material to release the lower level PMOS interconnect metal (e.g., 819a).

[0155] 47, fill material 874 may be formed in via opening 878d and recessed in via openings 878b, 878c, and 878d, for example, to the bonding liner 803 over second bonding dielectric layer 805b, so that second bonding dielectric layer 805b is protected by fill material 874 during subsequent etching and deposition.

[0156] In some embodiments, after formation and transfer of the vias through the ILD (e.g., 873) and the bonding dielectric film (e.g., 805a and 805b), the vias (e.g., 878b, 878c, and 878d) are then filled with a gap fill material (e.g., 874), such as spin-on carbon, to cover the exposed metal surfaces of the opened lower level interconnect metal (e.g., 819a) and to prevent unwanted further etching of the vias in later processing. The gap fill is recessed to a certain extent such that the stored interconnect trench pattern in the storage hardmask film is fully exposed.

[0157] In Figure 48, LI openings 879d, 879e, and 879f are formed to uncover CESL film 872. LI openings 879d, 879e, and 879f connect with via openings 878d, 878b, and 878c, respectively. For example, after the gap fill (e.g., 874) is in place and recessed down to protect the necessary components of the underlying device (e.g., 805b, 819a, and 810), the upper level NMOS interconnect trenches (e.g., 879d, 879e, and 879f) can then be transferred down from the storage hard mask (e.g., 876b) into the ILD oxide (e.g., 873).

[0158] In FIG. 49, the semiconductor device 800 may undergo a process similar to that shown in FIG. 22, FIG. 22B, FIG. 23, FIG. 24, FIG. 25, FIG. 25B, and FIG. 26. For example, the CESL film 872 is removed to uncover the sacrificial film 871, which is then removed to uncover the second S / D structure 823. A silicide material 824 (e.g., as shown by 824a, 824b, and 824c) is formed all around the second S / D structure 823. The fill material 874 is removed. Vias 831a, 831b, and 831e and LI structures 829 (e.g., as shown by 829a, 829b, and 829c) are then formed in the via openings 878d, 878b, and 878c and the LI openings 879d, 879e, and 879f. Vias 831a, 831b, and 831e and LI structures 829 are recessed and a capping layer 833 is formed over LI structures 829. An ILD film 873 is deposited to fill the spaces before an etching, polishing, and / or planarization process is performed to remove the hardmask material down to the level of the dummy gate.

[0159] In some embodiments, the contact etch stop layer (CESL) (e.g., 872) is then removed selectively to the surrounding dielectric material. This is then followed by removal of the conformal semiconductor liner (e.g., 871) to provide the wraparound contacts. Removal of the conformal semiconductor liner material (e.g., 871) leaves tunnels in the ILD dielectric (e.g., 873) that essentially encase the entire source and drain contacts (e.g., 823).

[0160] A silicide (e.g., 824) may then be formed over the exposed NMOS source and drain contacts (e.g., 823). The choice of silicide material in this case may be optimized for the NMOS and need not necessarily be the same as the silicide material (e.g., 814) used for the PMOS contacts (e.g., 813).

[0161] The gap fill material (eg, 874) is then ashed away with high selectivity to the surrounding dielectric material and the silicide (eg, 824) formed over the NMOS source and drain contacts (eg, 823).

[0162] The vias (e.g., 878d, 878b, and 878c) and interconnect trenches (879d, 879e, and 879f) are then metallized with a highly conductive metal such as ruthenium, cobalt, or tungsten. The metal fill process can be by conventional methods such as complete fill with subsequent metal CMP and recess etch, or the metal fill can be done by a bottom-up approach.

[0163] After metallization of the upper level NMOS interconnects (e.g., 829), an etch-selective cap (e.g., 833) is then deposited (conventionally or through a selective deposition process) over the metal interconnects (e.g., 829) to provide some etch selectivity in a subsequent etch process so that connections can be made from either device level to BEOL signal wiring without risk of shorts to complementary devices in the subsequent etch process.

[0164] It should be noted that as the interconnect trenches (879d, 879e, and 879f) are patterned, the intended via structures (e.g., 878d, 878b, and 878c) that will connect between the lower level PMOS interconnects (e.g., 819) and the BEOL signal wiring can be patterned as well. This technique allows for perfect self-alignment and fixed isolation between an individual via of one device and its complementary device, effectively controlling reliability such as TDDB, and allowing for optimization of capacitance between the via and its complementary device. Although not shown here, this technique can be understood by those skilled in the art.

[0165] After deposition of an etch-selective cap (e.g., 833) over the upper level NMOS device, the source and drain regions may be filled with ILD oxide (e.g., 873) and then polished down to the gate cap by CMP.

[0166] 49 and 50 may show the semiconductor device 800 in different cross sections. For example, FIG. 49 may show a perspective view of a cross section along the S / D structure, while FIG. 50 may show a perspective view of a cross section along the gate structure. FIG. 50 shows the dummy gate 863 and the fin structure 855. For example, the wafer (e.g., 800) may be planarized down by CMP to expose the dummy gate amorphous silicon (e.g., 863). If replacement metal gate (RMG) processing / formation is performed prior to the formation of the upper level interconnect (e.g., 829), this CMP step may occur earlier in the process integration.

[0167] In Fig. 51, the semiconductor device 800 may undergo processes similar to those shown in Fig. 28, Fig. 29, Fig. 30, and Fig. 30B. For example, the dummy gate 863 may be removed to uncover the protective film 861 covering the fin structure 855. The protective film 861 is removed to uncover the fin structure 851. The seventh semiconductor material 857 is removed selectively to the second channel structure 821.

[0168] In some embodiments, the amorphous silicon (e.g., 863) is removed from the upper dummy gate region leaving the silicon / silicon germanium FIN stack (e.g., 855) exposed. The silicon germanium (e.g., 857) is then etched selectively to the silicon nanosheets (e.g., 821). The silicon nanosheets (e.g., 821) may optionally be trimmed to round the corners of the nanosheet structures, but need not be trimmed to the extent of the PMOS nanosheets (e.g., 811) if a silicon germanium cladding (e.g., 812) is used to enhance PMOS channel mobility.

[0169] 52 and 52B, an intermediate layer 826 of silicon oxide or silicon germanium oxide may optionally be formed around the second channel structure 821. At least one gate dielectric 827 may then be formed around the intermediate layer 826. A capping material 875 may optionally be formed around the at least one gate dielectric 827.

[0170] In some embodiments, after formation of the NMOS channel (e.g., 821), a conventional replacement metal gate process may be performed, where an intermediate layer of silicon oxide 826 is grown from the channel (e.g., 821), followed by HfO 2 Such as a conformal or selective deposition of a high-k dielectric film (e.g., 827), followed by deposition of some type of capping material (e.g., 875) such as TiN or amorphous silicon, followed by some type of reliability anneal process, followed by removal of the capping material (e.g., 875), and finally followed by deposition of a work function controlling metal such as TiAlN, TiAl, and TiAlC.

[0171] It is important to note that due to the high processing temperatures associated with the reliability anneal, this may actually be advantageous for integration where replacement metal gate (e.g., 863) processing / formation occurs prior to silicide (e.g., 824) formation around the source and drain contacts (e.g., 823) and metallization of the interconnects (e.g., 829).

[0172] It is expected that such reliability anneals may be performed in the future incorporating higher pressure and lower temperature processes, or may be performed using a very rapid anneal step to prevent any phase changes to the formed silicides (e.g., 814 and 824) around the source and drain contacts (e.g., 813 and 823).

[0173] In Fig. 53, similar to Figs. 34 and 35, a second transistor stage 820 is formed. For example, at least one gate metal 828 (e.g., as shown by 828a, 828b, and 828c) may be formed around at least one gate dielectric 827. At least one gate metal 818 may then be patterned and split into gate metals 818a, 818b, and 818c separated by dielectric material 877. As a result, a gate structure 825 (e.g., as shown by 825a) is formed.

[0174] In some embodiments, for example, after an NMOS workfunction controlling metal stack is conformally deposited around the channel (e.g., 821), the replacement metal gate is then filled with a highly conductive metal such as tungsten and polished down or recessed etched to form the metal gate. After the NMOS metal gate (e.g., 825a) is formed, a masking process is performed to form a cut HKMG that is transferred to the HKMG stack and then filled with some type of dielectric (e.g., 877) such as silicon nitride, which separates the standard cells from each other in the north-south direction (e.g., Y direction).

[0175] In Fig. 54, a via opening 878e is formed. In some embodiments, for a common NMOS / PMOS gate connection, some type of inter-gate via (e.g., 878e) needs to be patterned and transferred through the upper transistor metal (e.g., 828), then down through the dielectric junction oxide (e.g., 805b) and its associated liner material (e.g., 803), and finally through the silicon nitride cap (e.g., 877) located above the lower PMOS transistor. To ensure that the inter-gate via is etched only through the transistor area and not into the low-k gate spacer (e.g., 867) or ILD oxide (e.g., 873) in the source and drain regions, a self-aligned gate contact (SAGC) or contact over active gate (COAG) process may be used. What can be done is that the initial ILD film (e.g., 873) in the source and drain contact regions is partially recessed along with the low-k gate spacers (e.g., 867), and this recessed gap is filled with a material that has high etch selectivity to both the metal and the wafer bond dielectric material to ensure that this etching process does not extend into the device regions and does not cause any type of undesirable shorts.

[0176] In Fig. 55, vias 831g are formed. For example, after the inter-gate vias (e.g., 878e) are transferred to form the desired common gate, the vias (e.g., 878e) are metallized with some type of liner material and then filled with a gate metal such as tungsten.

[0177] In Fig. 56, gate metal 828a and 828c are partially removed and filled with dielectric material 877. As a result, gate metal 828a and 828c have a reduced dimension in the Y direction, making more space available for future metal hook-up.

[0178] In some embodiments, after formation and metallization of the inter-gate vias (e.g., 878e), a second HKMG cut process is performed to reduce the size of the upper stage NMOS transistor (e.g., 820) so that the final input connections can be made from the BEOL metal wiring stack to the lower stage PMOS transistor (e.g., 810). This cut structure is also filled with some type of dielectric, such as silicon nitride, with the goal of creating some type of stepped profile in the stacked gate structure, like those present in stacked metal interconnects on the source and drain planes.

[0179] The gate metal and HKMG stack can then be recessed selectively to the surrounding dielectric material to make room for the final upper level gate cap. Once recessing is complete, a dielectric material (e.g., 877) having etch selectivity to the cap (e.g., 833) and low-k gate spacers (e.g., 867) on the upper level NMOS interconnect structure (e.g., 829) is deposited in the recessed region to form the gate cap.

[0180] Figure 57 shows a perspective view along the S / D structure, in which a via opening 878f is formed leaving the LI structure 819b uncovered.

[0181] In some embodiments, vias (e.g., 878f) used to connect BEOL signal wiring to the lower level interconnect (e.g., 819b) are patterned and transferred down through the upper ILD oxide film (e.g., 873), transferred through the junction dielectric (e.g., 805b) and its associated liner film (e.g., 803), and finally open the etch selective cap (e.g., 833) over the lower PMOS metal interconnect (e.g., 819b).

[0182] It is important to note that most of this via (e.g., 878f), which passes through the upper ILD oxide (e.g., 873) and wafer bond dielectric (e.g., 805b), may be formed in a patterning process during the initial upper level interconnect trench etch transfer process (e.g., FIG. 48) to ensure that there is a minimal dielectric difference between any via and its complementary interconnect structure to minimize capacitance and maximize reliability performance. In this particular example, the via (e.g., 878f) is done as a separate patterning step for illustrative purposes.

[0183] It is also important to note that the vias (e.g., 878f) have much wider dimensions relative to the M0 trench pattern, which can be achieved by incorporating a single damascene process in which the vias are formed and metallized before the actual M0 pattern. This allows for larger via widths that connect through multiple device levels (e.g., 810 and 820), which can offset the parasitic resistance penalty that comes from the greater via depth due to the vias having to pass through the junction dielectrics (e.g., 805a and 805b) and associated liner stacks (e.g., 803) that are not required in monolithic implementation of CFETs. The vias (e.g., 878f) that connect the signal wiring to the interconnects (e.g., 819b) can be self-aligned to the contact areas only by the SAGC or COAG processes described above.

[0184] In FIG. 58, via opening 878f may be filled with fill material 874 and via opening 879g is formed leaving IL structure 829a uncovered.

[0185] In some embodiments, after vias (e.g., 878f) are formed connecting the BEOL signal wiring to a lower level PMOS interconnect (e.g., 819b), a gap fill material (e.g., 874) such as spin-on carbon is filled into the formed vias (e.g., 878f) to protect the interconnect metal (e.g., 819b) from any subsequent downstream etching processes associated with the formation of vias connecting to upper level interconnects or transistors.

[0186] FIG. 59 shows a perspective view along the gate structure. In FIG. 59, via openings 878h, 878i, and 878j are formed to leave gate metal 828a, 828b, and 828c uncovered. For example, input vias (e.g., 878h, 878i, and 878j) connecting upper stage NMOS transistors (e.g., 820) can be patterned and transferred through the gate cap material (e.g., 877) to connect to the BEOL. At this point, all of the vias (e.g., 878f and 878g) connecting the BEOL signal wiring to the interconnects (e.g., 819b and 829a) are filled with gap fill spin-on carbon material (e.g., 874) so ​​that they are protected during this etch transfer process.

[0187] In Figure 60, via openings 878h, 878i, and 878j are filled with fill material 874. Via openings 878k and 878l are formed leaving gate metals 818a and 818c uncovered. For example, the patterning of input vias (e.g., 878k and 878l) that connect BEOL signal wiring to lower level PMOS transistors (e.g., 810) must pass through the dielectric staircase created in the replacement gate module. These vias (e.g., 878k and 878l) must similarly pass through the stepped dielectric in the upper gate level (e.g., 825), through the wafer bond dielectric (e.g., 805b) and its associated liner film (e.g., 873), and finally through the gate cap (e.g., 819) of the lower level PMOS gate (e.g., 815), while maintaining selectivity to the surrounding dielectric cap over the ILD oxide (e.g., 803) and interconnect metal (e.g., 877 and 829) provided by the SAGC or COAG processes.

[0188] In Figure 61, the fill material 874 is removed from the via openings 878h, 878i, 878j, 878k, and 878l before the vias 831f, 831h, 832a, 832b, and 832c are formed. For example, the gap fill spin-on carbon material (e.g., 874) can be ashed out from within the via structures (e.g., 878h, 878i, 878j, 878k, and 878l). The input-gate vias (e.g., 832a, 832b, and 832c) and the signal-interconnect (e.g., 831f and 831h) vias can then be simultaneously metallized with a highly conductive metal such as ruthenium, cobalt, tungsten, or other suitable metal.

[0189] Figure 62 shows a perspective view along the S / D structure, in which fill material 874 is removed from via openings 878f and 878g before vias 831c and 832d are formed. For example, Figure 62 may show vias (e.g., 831c and 832d) connecting interconnect metal (e.g., 819b and 829a) to fully metallized BEOL signal wiring.

[0190] It should be noted that Figures 61 and 62 may show semiconductor device 800 at the same processing stage, i.e., fill material 874 may be removed from via openings 878f, 878g, 878h, 878i, 878j, 878k, and 878l by a common etching process. Vias 831c, 832d, 831f, 831h, 832a, 832b, and 832c may be formed simultaneously.

[0191] In Fig. 63, a signal wiring layer 807 is formed over the second transistor stage 820, and a mask layer 809 is formed over the signal wiring layer 807. Note that the signal wiring layer 807 includes a dielectric material in this step, and signal lines 808 may be formed in the signal wiring layer 807 in Fig. 64.

[0192] For example, in a single damascene process, the first BEOL signal wiring layer (e.g., 807) is then patterned and transferred down through the low-k oxide (e.g., 807) to contact the wide gate vias (e.g., 832a, 832b, 832c, 831f, and 831h) and contact vias (e.g., 832d and 831c). An etch-selective cap (e.g., 833) on top of the metal interconnect (e.g., 829) self-aligns the landing of the first metal etch process so that it only lands on the exposed metal (e.g., 832d and 831c) and does not inadvertently short to any devices. The first metal tracks (e.g., 808) are then metallized with a highly conductive material such as ruthenium or cobalt.

[0193] In this example, only a single BEOL metal layer (e.g., 807) is shown, but it should be understood that multiple metal layers (e.g., 16 additional metal layers) may be formed on top of the initial metal layer at the BEOL. A single metal layer (e.g., 807) is shown here for simplicity and illustrative purposes.

[0194] In FIG. 65, a fourth bulk semiconductor material 801d may be formed over the second transistor stage 820.

[0195] In one embodiment, after the final metal (e.g., 808) and / or pads are formed in the BEOL, a dielectric bonding layer (e.g., 805c) and its associated liner (e.g., 803) are deposited on top of the wafer (e.g., W3) and a separate carrier wafer (e.g., W4) containing the fourth bulk semiconductor material 801d. This carrier wafer (W4) is then fusion bonded to the top surface of the existing device wafer (e.g., W3).

[0196] In another embodiment, an etch stop layer (eg, 805c) may be formed over the signal wiring layer 807, and a fourth bulk semiconductor material 801d may be deposited over the etch stop layer (eg, 805c).

[0197] In FIG. 66, the semiconductor device 800 is inverted and the first bulk semiconductor material 801a is removed leaving the first bonding dielectric layer 805a and the via 831 uncovered.

[0198] In some embodiments, the device (e.g., 800) is then flipped on its axis (e.g., along the Z-axis) so that the bottom (e.g., 801a) of the device wafer (e.g., 800) is now exposed. The silicon substrate (e.g., 801a) may be removed by a reverse grinding process, followed by optional CMP and etch removal processes, to expose the bottom dielectric bond liner material (e.g., 803), which may be used as an etch stop layer for the substrate removal process. Removal of this bond dielectric liner (e.g., 803) exposes the wafer bond dielectric (e.g., 805a) itself along with metallized vias (e.g., 831) that connect the interconnects to the backside power delivery network.

[0199] 67 and 68, backside power rails 841 are patterned and formed. The backside power rails are separated from each other by dielectric material 842. A liner or barrier 844 may be disposed on the top and sidewalls of the backside power rails 841.

[0200] In some embodiments, after the exposed metal vias (e.g., 831) are removed, an etch stop layer (e.g., 846) may be deposited over the exposed metal vias (e.g., 831), and then a low-k or silicon oxide film (e.g., 842) may be deposited thereon to enable final etch transfer of the first backside power line (e.g., 841). The backside power lines (e.g., 841), which may also be considered backside VDD and VSS power, may be patterned.

[0201] The advantage of this backside approach is that there are no longer any residual silicon FINs originating from the base of the lower level PMOS source and drain contacts (e.g., 813) that can compete with the sizing and placement of the backside metal lines (e.g., 841). In addition, the lack of residual FINs or residual silicon substrate extending into the wafer backside allows not only the use of backside power lines, but also the inclusion of backside signal lines that can connect directly to the source and drain contacts or even to the gate metal itself. For example, cross-couples can now be formed on the backside of the wafer between intended power lines, or local wiring tracks can also be placed on the wafer backside between power tracks.

[0202] The backside power lines can then be transferred through the silicon oxide or low-k dielectric film (e.g., 842) stopping on the etch stop layer (e.g., 846), which can also be formed of a dielectric material.

[0203] The etch stop layer (e.g., 846) is then opened to expose the vias (e.g., 831) that connect to the backside power supply (e.g., 841). The advantage of this process is that no nano- or micro-TSVs (through silicon vias) are required; the connection is made directly between the vias (e.g., 831) and the first backside metal line (e.g., 841).

[0204] Here, the backside power lines (e.g., 841) have the flexibility to be much wider compared to the original buried power rails described in U.S. Patent No. 10,586,765 based on the absence of residual silicon FIN since the backside power region is created through the wafer fusion bonding process. Thus, the VDD and VSS lines (e.g., 841) can now be metallized with any suitable metal, which could not originally be introduced through the buried power rail concept, which is often formed and metallized in the FEOL, where there are often strict restrictions on what metals can be present before the replacement metal gate (RMG) module.

[0205] In this example, a ruthenium-based barrier (e.g., 844) is formed, which is the same proposed metal as the connecting via 831, followed by plating or filling with copper (e.g., 841). Note that at the wider dimensions used for VDD and VSS in this application, copper actually has a superior IR drop compared to filling these lines with ruthenium or other high refractive index metals, which would be necessary for buried power rail approaches incorporating FEOL integration.

[0206] In Fig. 69, a fifth bulk semiconductor material 847 may be formed over the backside power rail 841. In one embodiment, after all backside power metal layers (e.g., 841) are formed, an additional carrier wafer may be bonded to the backside of the completed wafer via a third bonding dielectric layer 845, optionally with a bonding liner 843, similar to Fig. 65. In another embodiment, a fourth bulk semiconductor material 801d may be deposited over the backside power rail 841.

[0207] In Fig. 70, the semiconductor device 800 is flipped and the fourth bulk semiconductor material 801d is removed. For example, the wafer device (e.g., 800) can then be flipped to expose the BEOL of the entire device wafer. The initial carrier wafer substrate (e.g., 801d) and optionally the dielectric bonding layer 805c can then be removed to expose the entire BEOL (e.g., 808).

[0208] As can be appreciated, various embodiments are contemplated herein. Below are additional exemplary embodiments and advantages.

[0209] 1. A backside power delivery network (BSPDN) formed incorporating a wafer hybrid bonding process before active devices are formed on the wafer. This can be achieved by taking a silicon substrate and depositing a suitable dielectric bonding material thereon, such as silicon oxide, silicon nitride, or other suitable dielectric material. A second silicon substrate wafer is taken and an alternating stack of semiconductor device materials, such as silicon, silicon germanium, germanium, or combinations thereof, is epitaxially grown thereon and a suitable bonding dielectric material is deposited. A second wafer is taken and flipped so that the silicon / silicon germanium / germanium epitaxy stack is now facing down. The second wafer is bonded onto the first wafer such that both dielectric bonding materials interface with each other. The substrate is removed from the backside of the second wafer such that only the intended semiconductor material stack is present after grinding, CMP, and etching processes. An initial FIN structure is formed containing only the semiconductor material from the second wafer, where the bonding dielectric forms the termination of the FIN structure such that there is no residual FIN structure below the intended device. For complementary FET (CFET) devices, the process can be repeated to form additional device stages.

[0210] 2. The embodiment described in #1, where the integration method allows for complete removal of residual silicon substrate or residual silicon FIN structure in the area between the source and drain contacts and the backside power delivery network.

[0211] 3. The embodiment described in #2, in which the lack of residual substrate or residual silicon FIN structure allows for upsizing the dimensions of the initial backside power delivery network to optimize IR drop as well as to allow for placement of any connections made to the source and drain contacts to minimize total resistance that would otherwise be constrained by the presence of residual substrate or residual silicon FIN structure.

[0212] 4. The embodiment described in #2, in which the lack of residual substrate or residual silicon FIN structure not only enables placement of backside power delivery network metal lines, but also enables easy placement of backside signal metal wiring that would otherwise be constrained by the presence of residual substrate or residual silicon FIN structure.

[0213] 5. The embodiment described in #2, in which the lack of residual substrate or residual silicon FIN structure allows connections between the backside power supply and any source and drain contacts to be made without the need to perform micro- or nano-sized through-silicon-via (TSV) processing, and instead the integration allows these connections between the power supply and the source and drain contacts to be made by conventional dielectric etch processes.

[0214] 6. The embodiment described in #3, where the larger available size of the backside power supply lines allows for upsizing of the vias connecting the source and drain contacts to the backside power supply to minimize the total parasitic resistance.

[0215] 7. The embodiment described in #6, in which the upsized vias for 3D complementary FET (CFET) devices can be patterned, formed, and metallized at the same time that the interconnects to the complementary source and drain contacts are formed, thus enabling extremely small and perfectly self-aligned isolation between the complementary metal source and drain interconnect metal and any adjacent metal vias connecting to the complementary device.

[0216] 8. The embodiment described in #6, in which vias can be upsized through confined epitaxy of both the source and drain contacts, which is necessary to reduce the available space within the confined cell height.

[0217] 9. The embodiment described in #8, where the initial bonding dielectric used to form the bottom termination of the initial nanosheet FIN stack can be used as a suitable etch stop layer for the confined source and drain growth process and subsequent removal of the dielectric confinement shoulder.

[0218] 10. The embodiment described in #8, in which contact resistance can be improved by incorporating wrap-around contacts to compensate for the smaller size of the source and drain contacts.

[0219] 11. The embodiment described in #10, wherein the wraparound contacts may be formed by deposition or epitaxial growth of an etch-selective semiconductor material over the formed source and drain contact structures.

[0220] 12. An etch selective process can be used to selectively remove the semiconductor material surrounding the source and drain contacts from the actual contact structures to leave a "tunnel" that wraps around the source and drain contact structures, which can then be exposed to a silicide growth and metallization process that also encapsulates the source and drain contacts. The embodiment described in #10.

[0221] 13. The embodiment described in #1, wherein the semiconductor nanosheet stacks can be replaced by suitable two-dimensional channel materials such as tungsten disulfide, molybdenum disulfide, phosphorene, graphene, or any other suitable 2D channel materials and transition metal dichalcogenides (TMDs).

[0222] 14. The embodiment described in #8, wherein the confined source and drain formation process can be realized in integration where the formed inner spacers are made through selective deposition of inner spacer material onto recessed silicon germanium.

[0223] 15. The embodiment described in #14, wherein the above process is used to prevent removal or any distortion of dielectric sidewall spacers required for formation of confined grown source and drain contacts.

[0224] 16. The embodiment described in #14, wherein the selectively deposited inner spacer material can be of a different composition than the low-k gate spacer, which is also the material used for the dielectric sidewall spacers used to confine the source and drain epitaxy growth.

[0225] 17. The embodiment described in #14, wherein the inner spacer formation process is performed through a selective deposition process in which the native oxide on the recessed silicon germanium surface can be selectively removed relative to the native oxide on the silicon, such that a self-aligned monolayer (SAM) material can selectively adhere to the dielectric, including the native oxide on the silicon, and not to the removed silicon germanium surface, thus allowing deposition of the inner spacer material only on the recessed surface of the silicon germanium.

[0226] 18. The embodiment described in #1, in which bottom dielectric isolation (BDI) integration is no longer required, since the transistor formation in this integration is effectively finished on the junction dielectric and there is no residual substrate or residual FIN structure that would make BDI integration necessary.

[0227] 19. The embodiment described in #1, where a gate tie-down can be easily obtained to the backside power supply, where a via can be formed during the high dielectric constant metal gate (HKMG) processing step where a direct connection can be made between the transistor and a complementary power supply to provide a tie-down of the transistor to the backside power supply.

[0228] 20. The embodiment described in #1, in which removing the bulk substrate has a detrimental strain effect on the PMOS channel that can be compensated for in multiple ways, including (a) incorporation of a silicon germanium channel, (b) silicon germanium cladding around the silicon PMOS channel, and (c) utilizing different crystal orientations of the bulk silicon wafer for silicon or silicon germanium PMOS channels for hole mobility.

[0229] In the above description, specific details have been described, such as the specific geometry of the processing system and a description of the various components and processes used therein. However, it should be understood that the techniques described herein can be implemented in other embodiments that differ from these specific details, and such details are for the purpose of explanation, not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numerical values, materials, and configurations have been shown to provide a sufficient understanding. However, the embodiments can be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and redundant descriptions may be omitted.

[0230] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0231] As used herein, "substrate", "wafer", or "bulk semiconductor material" generally refers to an object that is processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may include, for example, a base substrate structure, such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is intended to include such layers or base structures, as well as any combination of layers and / or base structures. Although the present specification may refer to a particular type of substrate, this is for illustrative purposes only.

[0232] The substrate may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0233] Those skilled in the art will also appreciate that many variations can be made to the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to fall within the scope of the present disclosure. As such, the above description of several embodiments of the present invention is not intended to be limiting. Rather, limitations to the embodiments of the present invention are presented in the following claims.

Claims

1. A method for manufacturing a semiconductor device, wherein the method is Bonding a first wafer to a second wafer via a first bonding dielectric layer, wherein the first wafer comprises a first bulk semiconductor material, and the second wafer comprises a first laminate of alternating layers of epitaxially grown semiconductor layers formed on the second bulk semiconductor material. Removing the second bulk semiconductor material to leave the first laminate uncovered, Forming a first transistor stage from the first laminate, Bonding a third wafer to the second wafer via a second bonding dielectric layer, wherein the third wafer includes a second laminate of alternating layers of epitaxially grown semiconductor layers formed on a third bulk semiconductor material. Removing the third bulk semiconductor material, Forming a second transistor stage from the second laminate, Removing the first bulk semiconductor material and leaving the first junction dielectric layer uncovered, To form a power supply network in contact with the first junction dielectric layer, wherein the power supply network includes a backside power rail in contact with vias extending through the first junction dielectric layer. Methods that include...

2. After forming the first transistor stage and the second transistor stage, the backside power rail is formed. The method according to claim 1, further comprising:

3. Before bonding the third wafer to the second wafer, the method is performed as follows: To form a local interconnect (LI) structure connected to the source / drain (S / D) structure of the first transistor stage, To form at least one via connected to each LI structure and extending through the first junction dielectric layer. The method according to claim 1, further comprising:

4. To form each backside power rail that contacts at least one of the vias. The method according to claim 3, further comprising:

5. Forming at least one via opening such that the first bulk semiconductor material is left uncovered, The at least one via opening is partially filled with a filler material, To form an LI opening that includes each LI opening connected to the at least one via opening, Removing the aforementioned filling material, The LI opening and the at least one via opening are filled with a conductive material to form the LI structure and the at least one via. The method according to claim 3, further comprising:

6. After bonding the third wafer to the second wafer, the method is performed as follows: To form an LI structure connected to the S / D structure of the second transistor stage, To form at least one via connected to each LI structure and extending through the second junction dielectric layer and the first junction dielectric layer. The method according to claim 1, further comprising:

7. To form each backside power rail that contacts at least one of the vias. The method according to claim 6, further comprising:

8. Forming at least one via opening such that the first bulk semiconductor material is left uncovered, The at least one via opening is partially filled with a filler material, To form an LI opening that includes each LI opening connected to the at least one via opening, Removing the aforementioned filling material, The LI opening and the at least one via opening are filled with a conductive material to form the LI structure and the at least one via. The method according to claim 6, further comprising:

9. To form at least one via that extends through the second junction dielectric layer and is configured to electrically connect the first S / D structure of the first transistor stage to the second S / D structure of the second transistor stage. The method according to claim 1, further comprising:

10. Forming a signal wiring layer on the second transistor stage. The method according to claim 1, further comprising:

11. The signal wiring layer is formed to connect vias to the first transistor stage and the second transistor stage. The method according to claim 10, further comprising:

12. Before removing the first bulk semiconductor material and leaving the first junction dielectric layer uncovered, the method is performed as follows: Bonding the carrier wafer to the third wafer. The method according to claim 1, further comprising:

13. After forming the aforementioned power supply network, the method is performed Bonding the carrier wafer to the backside power rail, or forming a fourth bulk semiconductor material so as to cover the backside power rail. The method according to claim 1, further comprising:

Images