Method for patterning a substrate to adjust voltage characteristics - Patents.com

Abstract

A method for adjusting a threshold voltage in a field effect transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure; performing a first patterning process to remove a portion of the diffusion layer deposited in the first region; performing a second patterning process to partially remove a portion of the diffusion barrier layer deposited in the second region; performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region and over the diffusion barrier layer in the second region and the third region; and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.

Description

[Technical field]

[0001] Embodiments of the present disclosure relate to a method for processing a substrate, and more specifically, to adjusting the threshold voltage of a portion of a field effect transistor (FET) device by forming an electrostatic dipole layer and adjusting the thickness of a diffusion barrier layer between the dipole layer and a gate dielectric layer. [Background technology]

[0002] Semiconductor devices such as integrated circuits (ICs) generally have electronic circuit elements, such as transistors, diodes, and resistors, fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit, which may include millions of individual circuit elements. Advances in semiconductor materials and processing technology have led to a reduction in the overall size of ICs and an increase in the number of circuit elements. Further miniaturization is highly desirable for improved IC performance and reduced costs. Control of the threshold voltage (Vt) of transistors is important for use in various devices, including gate modules, and can become more difficult as gate lengths become shorter.

[0003] Therefore, what is needed is a method of forming structures in a FET device to adjust the threshold voltage in various regions of the FET device. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for adjusting a threshold voltage in a field effect transistor (FET) device, the method including performing a deposition process to deposit a diffusion barrier layer on a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer on the gate dielectric layer in the first region and the diffusion barrier layer in the second region and the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.

[0005] An embodiment of the present disclosure provides a method of adjusting a threshold voltage in a field effect transistor (FET) device, the method including forming a diffusion barrier layer in a gate dielectric layer having different thicknesses in a first region, a second region, and a third region of a semiconductor structure, and performing a precision materials engineering (PME) process on an exposed surface of the semiconductor structure.

[0006] An embodiment of the present disclosure provides a method for forming a p-type field effect transistor (PFET) device and an n-type field effect transistor (NFET) device, the method including forming a first n-type dipole layer on a first gate dielectric layer formed on a silicon germanium-containing layer, the first n-type dipole layer having different thicknesses in a first region, a second region, and a third region of the PFET device, forming a second n-type dipole layer on a second gate dielectric layer, the second n-type dipole layer having different thicknesses in the first region, the second region, and a third region of the NFET device, and performing an annealing process to drive dipole dopants from the first n-type dipole layer into the first gate dielectric layer and from the second n-type dipole layer into the second gate dielectric layer.

[0007] To understand the above-described features of the present disclosure in detail, a more detailed description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments and should not be considered as limiting the scope of the present disclosure, as the present disclosure may admit other equally effective embodiments.

Brief Description of the Drawings

[0008] [Figure 1A] A perspective view of a substrate and a cross-sectional view of a transistor disposed on the substrate according to some embodiments are shown. [Figure 1B] A perspective view of a substrate and a cross-sectional view of a transistor disposed on the substrate according to some embodiments are shown. [Figure 1C] A perspective view of a substrate and a cross-sectional view of a transistor disposed on the substrate according to some embodiments are shown. [Diagram 2] A processing system that can be used to perform one or more processes described herein is shown. [Diagram 3] A process flow diagram of a method for processing a substrate according to some embodiments is shown. [Figure 4] A substrate having a plurality of regions according to some embodiments is shown. [Diagram 5] A process flow diagram of a method for processing a substrate according to some embodiments is shown. [Figure 6] A p-type field-effect transistor (PFET) device according to some embodiments is shown. [Figure 7] An n-type field-effect transistor (NFET) device according to some embodiments is shown. [Figure 8] A PFET device according to some embodiments is shown. [Figure 9] A PFET device according to some embodiments is shown. [Figure 10] An NFET device according to some embodiments is shown.

Best Mode for Carrying Out the Invention

[0009] For ease of understanding, the same reference numbers have been used to denote identical elements common to the drawings where possible. It is intended that elements and features of one embodiment can be advantageously incorporated into other embodiments even without further recitation.

[0010] Embodiments of the present disclosure provided herein include processes for forming structures within field effect transistor (FET) devices and tuning the threshold voltage of the structures for various uses. Threshold voltage tuning is achieved by depositing a dipole dopant-containing layer over the gate dielectric layer and driving the dipole dopants into the underlying gate dielectric layer by annealing. The process further includes providing a protective layer, a hard mask, and a compatible etch chemistry to protect regions of the FET device where the threshold voltage is not altered. The processes used herein are suitable for structures having thin individual layers, e.g., layers of about 20 Å or less (e.g., from about 1 Å to about 10 Å).

[0011] Figures 1A, 1B, and 1C show a perspective view of a substrate S and a cross-sectional view of a transistor disposed on the substrate S according to some embodiments. The substrate S includes a die D1. The die D1 includes a first region R1 and a second region R2. A first cross-sectional view SV1 of the first region R1 is shown in FIG. 1B, and a second cross-sectional view SV2 of the second region R2 is shown in FIG. 1C. In some embodiments, the first region R1 is a p-type metal oxide semiconductor field effect transistor (PMOS) device having a gate region GR1, and the second region R2 is an n-type metal oxide semiconductor field effect transistor (NMOS) device having a gate region GR2. The first region R1 may include a transistor including a p-type well region 002A having an active region defined by a separation region 004. The second region R2 is a transistor including an n-type well region 002B having an active region defined by a separation region 004. Each of the first region R1 and the second region R2 may also include a source / drain region disposed within the active region. The source / drain region may include a doped n-type region (e.g., an n-type region) including a lateral portion 006 and a first interlayer dielectric (ILD) layer 018. As shown, the lateral portion 006 of the source / drain region may be laterally adjacent to a semiconductor channel 036 within the well regions 002A, 002B. The first ILD layer 018 may be any suitable dielectric material such as silicon oxide (SiO 2 ), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), etc. The first ILD layer 018 can be deposited by chemical vapor deposition (CVD), furnace chemical vapor deposition (FCVD), or another suitable deposition process.

[0012] The first region R1 includes a gate structure 030, and the gate structure 030 may include a gate region GR1. Similarly, the second region R2 includes a gate structure 030, and the gate structure 030 may include a gate region GR2. Each of the gate structures 030 may include a gate oxide layer 010, a first gate metal layer 012, and optionally, a second gate metal layer 020. In some embodiments, the gate structure 030 includes a spacer 022.

[0013] The first region R1 and the second region R2 may include a metal interconnect structure 034. The second ILD layer 028 may be of a material similar to the first ILD layer 018 and may be deposited on the first ILD layer 018 in the same or a similar manner. The layers used to form the metal interconnect structure 034 may be deposited within recesses formed in the first ILD layer 018 and the second ILD layer 028, such as by the use of CVD, ALD, or physical vapor deposition (PVD). The metal interconnect structure 034 may include a conformal barrier layer 024, such as titanium nitride (TiN), tantalum nitride (TaN), etc., and a metal fill 026 on the barrier layer 024, such as tungsten (W), aluminum (Al), copper (Cu), etc.

[0014] Figures 1A, 1B, and 1C show a configuration including a commonly configured metal oxide semiconductor field effect transistor (MOSFET) device formed within a substrate S, but this configuration is not intended to limit the scope of the disclosure provided herein. This is because other types of formed device structures may benefit from one or more aspects of the disclosure provided herein. The relatively conventional device structure illustrated herein is shown only to simplify the description of the processes performed herein. However, the processes described herein are considered to provide important advantages for configurations such as the following: the device to be formed has a structurally more complex configuration (which may include gate all-around (GAA) FET devices and / or FinFET-type devices), such as a multi-gate device, and due to the gate regions of these multi-gate devices (embedded within many different layers of the device), conventional processing techniques (e.g., implantation) for various gate dielectric materials are not available.

[0015] Figure 2 shows a processing system 202 that can be used to perform one or more of the processes described herein. The processing system 202 disclosed herein may include an Endura® II mainframe or an Endura® III mainframe available from Applied Materials, Inc. of Santa Clara, California. The processing system 202 includes a first transfer module 204a, a second transfer module 204b, and a pass-through module 206 that connects a first transfer chamber 208a of the first transfer module 204a to a second transfer chamber 208b of the second transfer module 204b. The first transfer module 204a includes a first processing chamber 210a, a second processing chamber 210b, a third processing chamber 210c, an ancillary processing chamber 212, and a load lock chamber 213. The second transfer module 204b includes a fourth processing chamber 210d, a fifth processing chamber 210e, a sixth processing chamber 210f, a seventh processing chamber 210g, and an eighth processing chamber 210h.

[0016] Each of the first transfer module 204a and the second transfer module 204b includes a substrate handling robot (not shown) in the first transfer chamber 208a and the second transfer chamber 208b. The substrate handling robot of the first transfer module 204a is operable to transfer substrates between the load lock chamber 213, the first transfer chamber 208a, the processing chambers 210a - 210c, the ancillary processing chamber 212, and the pass - through module 206. The substrate handling robot of the second transfer module 204b is operable to transfer substrates between the pass - through module 206, the second transfer chamber 208b, and the processing chambers 210d - 210h. The processing system 202 includes a load lock chamber 213 coupled to the factory interface 215. The factory interface 215 provides substrates to the processing system 202 separately via one or more factory interface (FI) robots (not shown) and front - opening unified pods (FOUPs) 217.

[0017] Valve 207 is disposed in a load lock chamber 213 having interfaces of processing chambers 210a, 210b, 210c, an auxiliary processing chamber 212, and a first transfer chamber 208a of a first transfer module 204a. Valve 207 is also disposed at an interface of processing chambers 210d, 210e, 210f, 210g, 210h having a second transfer chamber 208b of a second transfer module 204b. In certain embodiments combinable with other embodiments described herein, valve 207 is a slit valve and / or a gate valve. Thus, processing chambers 210a - 210h can be separately isolated from the first transfer chamber 208a and the second transfer chamber 208b. A vacuum pump 219, such as a cryopump, a turbopump, etc., can be connected to the first transfer chamber 208a and the second transfer chamber 208b. The vacuum pump 219 is operable to maintain the vacuum levels of the first transfer chamber 208a and the second transfer chamber 208b. As one or more substrates are transferred between the first transfer chamber 208a and the second transfer chamber 208b, the vacuum levels in each of the first transfer chamber 208a and the second transfer chamber 208b can increase or decrease.

[0018] In this configuration, substrate transfer in the processing system 202 can be completed while the substrate is disposed within a high vacuum environment (e.g., 10 -7 ~10 -9 Torr). This is because the vacuum level in the second transfer chamber 208b is maintained at a base pressure higher than the vacuum level maintained in the first transfer chamber 208a. Typically, as the substrate moves through the first transfer module 204a in the direction from the load lock chamber 213 (e.g., 10 -3 Torr) to the second transfer chamber 208b (e.g., 10 -7 ~10 -8 Torr) and the processing chambers 210d - 210g (e.g., 10 -8 ~10 -9 Torr) within the processing system 202 to the second transfer module 204b, the base pressure or vacuum level (i.e., relatively low pressure) increases.

[0019] The processing chambers 210a to 210h can be any type of processing chamber, such as a deposition chamber. For example, it can be a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, a plasma enhanced chemical vapor deposition (PECVD) chamber, an atomic layer deposition (ALD) chamber, a plasma atomic layer deposition (PEALD), an etching chamber, a degassing chamber, and / or any other type of processing chamber. The types of the processing chambers 210a to 210h are interchangeable within the processing system 202.

[0020] In one embodiment, the processing chambers 210d, 210e, 210f, 210g, 210h are ALD chambers configured to deposit a dipole layer such as a p-type dipole layer. In this configuration, the processing chambers 210b and 210c may include a rapid thermal processing (RTP) chamber configured to heat the substrate to drive a dipole layer including a high-k dielectric layer. One or more of the processing chambers 210a and 212 can be a pre-cleaning chamber, such as an Aktiv (registered trademark) Preclean (“APC”) chamber available from Applied Materials, Inc. in Santa Clara, California. In another embodiment, one or more of the processing chambers 210d, 210e, 210f, 210g, 210h are configured to deposit a diffusion barrier layer by ALD processing.

[0021] The processing system 202 includes a system controller 203 that receives data corresponding to the throughput of each of the processing chambers 210a to 210h. The system controller 203 is operable to apply a prediction model to the data in order to give an instruction according to a processing command directed to processing in the processing chambers 210a to 210h of the processing system 202 and transferring one or more substrates from the processing chambers 210a to 210h of the processing system 202. The system controller 203 may also provide an output corresponding to an optimal combination of a PVD chamber, a CVD chamber, a PECVD chamber, an ALD chamber, a PEALD chamber, an etching chamber, a degassing chamber, or any other type of processing chamber for the processing chambers 210a to 210h of the processing system 202.

[0022] FIG. 3 shows a process flow diagram of a method 300 for changing characteristic values of a gate dielectric layer used in a field effect transistor (FET) device in a semiconductor structure 400 shown in FIG. 4 according to some embodiments. In some embodiments, each layer deposited during the activities performed in method 300 is deposited using an atomic layer deposition (ALD) process.

[0023] As shown in FIG. 4, the semiconductor structure 400 may include a first region 400A, a second region 400B, a third region 400C, and a fourth region 400D. Each of the regions 400A, 400B, 400C, and 400D includes a substrate 402, an interface layer 404 formed on the substrate 402, and a gate dielectric layer 406 formed on the interface layer 404. The substrate 402 may be a silicon-containing substrate (e.g., an n-type Si substrate, a p-type Si substrate). The interface layer 404 may be formed from silicon oxide (SiO 2 )).

[0024] The gate dielectric layer 406 may be formed from a high-k dielectric material. As used herein, the high-k dielectric material is silicon oxide (SiO 2It is a material having a dielectric constant higher than that of (for example, about 3.9). In some embodiments, the gate dielectric layer 406 is formed from a metal oxide. In some embodiments, the high-k dielectric material is a hafnium-containing material, a silicon-containing material, a zirconium-containing material, a titanium-containing material, or a combination thereof. In some embodiments, the high-k dielectric material is a hafnium oxide-containing material (e.g., HfO 2 ) or other suitable materials. The gate dielectric layer 406 is deposited with a thickness of about 20 Å or less, such as from about 5 Å to about 15 Å. The gate dielectric layer 406 is in interfacial contact with the interfacial layer 404. In one example, the gate dielectric layer 406 is formed over the channel region of a metal gate field effect transistor (FET) device, and the gate dielectric layer 406 includes an interfacial layer formed from silicon oxide (SiO 2 ) and a dielectric layer of hafnium oxide (HfO 2 ) formed on the interfacial layer.

[0025] Method 300 begins at activity 302, where a first deposition process is performed to deposit a first diffusion barrier layer 408A over the gate dielectric layer 406 in the first region 400A, the second region 400B, the third region 400C, and the fourth region 400D. The deposited first diffusion barrier layer 408A has a thickness of the first diffusion barrier layer of from about 0 Å to about 15 Å, such as from about 1 Å to 10 Å, or from about 3 Å to about 5 Å. The diffusion barrier layer 408A can be formed from a metal nitride material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W 2 N, WN, WN 2 ), or a combination thereof.

[0026] In Activity 304, a first patterning process is performed to substantially remove a part of the first diffusion barrier layer 408A deposited within the first region 400A. The first patterning process includes many processing steps such as one or more deposition steps, one or more lithography steps, one or more development steps, and one or more etching steps. After the first patterning process is performed, a part of the first diffusion barrier layer 408A deposited within the first region 400A is substantially removed. The second region 400B, the third region 400C, and the fourth region 400D each include a part of the deposited first diffusion barrier layer 408A.

[0027] In Activity 306, a second deposition process is performed to deposit a second diffusion barrier layer 408B on the exposed surface of the semiconductor structure 400 (the gate dielectric layer 406 in the first region 400A and the first diffusion barrier layer 408A in the second region 400B, the third region 400C, and the fourth region 400D). The deposited second diffusion barrier layer 408B has a thickness of a second diffusion barrier layer of about 1 Å to about 10 Å, such as about 3 Å to about 5 Å, or about 0 Å to about 15 Å. In one example, the second diffusion barrier layer 408B is formed of the same material as the first diffusion barrier layer 408A. The second deposition process in Activity 306 can be the same deposition process as the first deposition process in Activity 302.

[0028] In activity 308, a second patterning process is performed to substantially remove a portion of the second diffusion barrier layer 408B deposited in the first region 400A and the second region 400B. The second patterning process includes many processing steps such as one or more deposition steps, one or more lithography steps, one or more development steps, and one or more etching steps. After the second patterning process is performed, a portion of the second diffusion barrier layer 408B deposited within the first region 400A and the second region 400B is substantially removed. The second region 400B includes a portion of the first diffusion barrier layer 408A that has been deposited. Each of the third region 400C and the fourth region 400D includes a portion of the first diffusion barrier layer 408A and a portion of the second diffusion barrier layer 408B.

[0029] An additional region (e.g., the fourth region 400D) can further include a portion of an additional diffusion barrier layer (e.g., the third diffusion barrier layer 408C) having a thickness of the third diffusion barrier layer from about 0 Å to about 15 Å (e.g., from about 1 Å to about 10 Å, from about 3 Å to about 5 Å), and the additional diffusion barrier layer can be formed by deposition and etch-back (e.g., similar to activities 302 and 304) until the semiconductor structure 400 includes regions with various diffusion barrier layers 408 having various diffusion barrier thicknesses. For example, the combined diffusion barrier layer 408 within the second region 400B is the first diffusion barrier layer 408A, and thus has a thickness equal to the thickness of the first diffusion barrier layer. The combined diffusion barrier layer 408 within the third region 400C is a combination of the first diffusion barrier layer 408A and the second diffusion barrier layer 408B, and thus has a thickness equal to the combined thickness of the thickness of the first diffusion barrier layer and the thickness of the second diffusion barrier layer. The combined diffusion barrier layer 408 within the fourth region 400D is a combination of the first diffusion barrier layer 408A, the second diffusion barrier layer 408B, and the third diffusion barrier layer 408C, and thus has a thickness equal to the combined thickness of the thickness of the first diffusion barrier layer, the thickness of the second diffusion barrier layer, and the thickness of the third diffusion barrier layer. In one example, the third diffusion barrier layer 408C is formed from the same material as the first diffusion barrier layer 408A and / or the second diffusion barrier layer 408B.

[0030] In some alternative embodiments, forming diffusion barrier layers 408 with different thicknesses in various regions of the semiconductor structure 400 includes depositing a hard mask over the diffusion barrier layer 408, patterning the hard mask, and etching a portion of the diffusion barrier layer 408 through the openings of the patterned hard mask. For example, after a hard mask is deposited over the diffusion barrier layer 408, an opening in the hard mask is formed within the first region 400A, and then the diffusion barrier layer 408 within the first region 400A is etched. Subsequently, an opening in the hard mask is formed in the second region 400B, and the diffusion barrier layer 408 within the second region 400B is partially etched down to the thickness of the first diffusion barrier layer 408A. Another opening in the hard mask is formed in the third region 400C, and then the diffusion barrier layer 408 within the third region 400C is partially etched down to the combined thickness of the first diffusion barrier layer 408A and the second diffusion barrier layer 408B. In some embodiments, the hard mask is formed from a heat-resistant metal nitride or a heat-resistant metal carbide. The hard mask may be deposited over a protective layer disposed over the diffusion barrier layer 408. The hard mask is deposited to a thickness of from about 10 Å to about 20 Å. Other processes and methods of depositing diffusion barrier layers with different thicknesses across various regions of the semiconductor structure 400 are also envisioned.

[0031] In activity 310, a dipole layer deposition process is performed to deposit a dipole layer 410 over the gate dielectric layer 406 within the first region 400A and over the combined diffusion barrier layer 408 within the second region 400B, the third region 400C, and the fourth region 400D. The dipole layer 410 includes a dipole dopant. Generally, a dipole dopant includes elements that form an electrostatic dipole and, when doped into a dielectric material, is different from a fixed charge type dopant that includes elements that form a positive or negative charge due to electron loss or gain. Without intending to be bound by theory, the presence of a dipole dopant in the dielectric film results in a surface potential at the interface of the gate dielectric layer 406, which is thought to lead to dielectric polarization within the dielectric film. The dielectric polarization resulting from the presence of a desired amount of dipole dopant within the gate dielectric layer 406 can be used to adjust the threshold voltage (Vt) of the FET device. The threshold voltage is the minimum gate-to-source voltage, and for this, it is necessary to create a conduction path between the source terminal and the drain terminal. In some embodiments, it is desirable to dope various regions of the gate dielectric layer (e.g., the metal gate interface surface, the interface surface between the high-k layer and the interfacial dielectric layer, and the channel interface surface) to further adjust the threshold voltage (Vt) of the EFT. The dipole dopant within the dipole layer 410 can be a metal dopant such as aluminum (Al) or lanthanum (La). The dipole layer provides the dipole dopant, which will diffuse into the gate dielectric layer 406 upon subsequent annealing.

[0032] The dipole layer 410 has a dipole layer thickness of from about 3 Å to about 10 Å, such as from about 5 Å to about 8 Å. In some embodiments, the dipole layer 410 is formed from a metal nitride such as titanium nitride that further includes a dipole dopant.

[0033] In some embodiments, the dipole layer 410 has a uniform concentration across the entire thickness of the dipole layer for dipole dopants of about 5% to about 15%, such as about 8% to about 12%, such as about 1% to about 20%. The selection of the dipole dopant concentration in the dipole layer 410 is based on a predetermined final concentration for the dipole dopants diffused into the gate dielectric layer 406. The predetermined concentration of the dipole dopants diffused into the gate dielectric layer 406 is based on a predetermined threshold voltage (Vt) of at least one of the regions (e.g., 400A, 400B, 400C, 400D), or a predetermined difference in the threshold voltage (Vt) of a FET device formed in one of the regions (e.g., 400A, 400B, 400C, 400D) related to a FET device formed in another region (e.g., 400A, 400B, 400C, 400D). In some embodiments, the dipole layer 410 has a substantially uniform concentration for the dipole dopants within the dipole layer.

[0034] In some other embodiments, the dipole layer 410 has a gradient concentration of dipole dopants that varies along the thickness of the dipole layer 410. For example, it has a higher concentration at the surface of the dipole layer 410 closer to the gate dielectric layer 406 and a lower concentration at the opposite surface of the dipole layer 410. In some embodiments, the dipole dopants are formed by an atomic layer deposition (ALD) process. In some embodiments, the gradient concentration of the dipole dopants in the dipole layer 410 is formed by supplying an ALD pulse containing a dipole dopant-containing precursor having a concentration that increases (i.e., a positive gradient) or decreases (i.e., a negative gradient) for each successive layer during the ALD process. In one example, for example, more than about 70 atomic percent, such as more than about 80 percent, more than about 90 percent, etc., of the dipole dopants are disposed in a portion of the dipole layer 410 formed at the surface of the dipole layer 410 closer to the gate dielectric layer 406, and for the remainder of the dipole layer 410 (i.e., the negative gradient), less than 50 percent, such as less than 20 percent, etc., is disposed. In some embodiments, forming the gradient concentration of the dipole dopants includes increasing the exposure time (e.g., pulse time) of the dipole dopants compared to the exposure time of other gases during the ALD process.

[0035] Without being bound by theory, it is believed that by varying the thickness of the diffusion barrier layer 408, the dipole density can be controlled in various regions of the semiconductor structure 400. In some embodiments, the diffusion barrier layer (not shown in FIG. 4) in the first region 400A is less than about 0.3 nm (e.g., 0 nm (thinnest)), and the threshold voltage (Vt) shift is "extremely low". The diffusion barrier layer 408 in the second region 400B is from about 0.3 nm to about 0.6 nm, and the threshold voltage (Vt) is "low" and greater than the threshold voltage (Vt) of the first region 400A. The diffusion barrier layer 408 in the third region 400C is from about 0.6 nm to about 1 nm, and the threshold voltage (Vt) is "standard" and greater than the threshold voltage (Vt) of the second region 400B. The diffusion barrier layer 408 in the fourth region 400D is about 1 nm or greater (thickest), and the threshold voltage (Vt) is "high" and greater than the threshold voltage (Vt) of the third region 400C.

[0036] In activity 312, an annealing process is performed to drive the dipole dopant from the dipole layer 410 to the gate dielectric layer 406. In some embodiments, the annealing process is performed at a temperature of from about 600 °C to about 1100 °C, such as from about 800 °C to about 1000 °C, or from about 700 °C to about 950 °C. In some embodiments, the annealing process is performed for a time of from about 0.5 seconds to about 15 seconds, such as from about 1 second to about 10 seconds. By annealing the semiconductor structure 400, it becomes possible to diffuse the dipole dopant from the dipole layer 410 to the gate dielectric layer 406. Without being bound by theory, in one configuration, the dipole dopant diffused into the gate dielectric layer 406 forms an interface layer 404 (e.g., silicon dioxide (SiO 2 )) formed under it and on the substrate 402, generating a threshold voltage (Vt) shift at the interface. It has been found that by selecting the dopant type and concentration, the threshold voltage (Vt) can be adjusted to be either positive or negative polarity compared to the threshold voltage (Vt) of the undoped dielectric layer, depending on the desired application. In some embodiments, the dipole dopant is a p-type dopant diffused into the gate dielectric layer 406 to cause a negative polarization and a lower threshold voltage (Vt). In some embodiments, it is envisioned that other dopants raise the threshold voltage (Vt). The dipole dopant diffuses from the dipole layer 410 to the lower portion of the gate dielectric layer 406 (e.g., the interface between the gate dielectric layer and the interface layer 404), and it is further contemplated that the oxygen density in the lower portion of the gate dielectric layer 406 (e.g., HfO 2 )) is inhibited compared to the underlying interface layer 404 (e.g., silicon dioxide (SiO 2 ).

[0037] After performing the activity of method 300, additional processes may be performed to form FET devices having different, desirable threshold voltage (Vt) characteristic values. In some embodiments, a first FET having a first threshold voltage (Vt) value is formed. The first FET includes at least a portion of a dielectric layer (e.g., gate region GR1) found within a first region after the semiconductor structure 400 has been subjected to an annealing process. In some embodiments, a second FET having a second threshold voltage (Vt) value is formed. The second FET includes at least a portion of a dielectric layer (e.g., gate region GR2) found within a second region after the semiconductor structure 400 has been subjected to an annealing process. The first threshold voltage (Vt) value is different from the second threshold voltage (Vt) value. Thus, during activity 312, the threshold voltage (Vt) value can be adjusted due to the presence of different thicknesses of the diffusion barrier layer 408 by adjusting the amount of dipole dopants driven into the gate dielectric layer 406. When the first, second, third, and fourth regions form portions of a PMOS device, the first region 400A typically has an ultra-low threshold voltage (Vt), the second region 400B has a low threshold voltage (Vt), the third region 400C has a standard threshold voltage (Vt), and the fourth region 400D has a high threshold voltage (Vt).

[0038] FIG. 5 shows a flow diagram of method 500 for varying the characteristic values of a gate dielectric layer used in a PFET device 600 as shown in FIG. 6 and an NFET device 700 as shown in FIG. 7, according to some embodiments. Method 500 may be used to change the threshold voltage (Vt) within a device that includes a dipole layer between an interface layer and a dielectric layer without forming an additional dipole layer.

[0039] As shown in FIG. 6, the PFET device 600 includes a substrate 602, an interface layer 604 on the substrate 602, a p-type bipolar layer 606 on the interface layer 604, and a gate dielectric layer 608 on the p-type bipolar layer 606. As shown in FIG. 7, the NFET device 700 includes a substrate 702, an interface layer 704 on the substrate 702, an n-type bipolar layer 706 on the interface layer 704, and a gate dielectric layer 708 on the n-type bipolar layer 706. The interface layer 604 and the interface layer 704 can be formed of silicon oxide (SiO 2 ). The p-type bipolar layer 606 may include a p-type bipolar dopant and has a thickness of about 3 Å to about 10 Å, such as about 5 Å to about 8 Å. The n-type bipolar layer 706 may include an n-type bipolar dopant and has a thickness of about 3 Å to about 10 Å, such as about 5 Å to about 8 Å. The gate dielectric layer 608 and the gate dielectric layer 708 may be formed of a high-k dielectric material and may have a thickness of about 5 Å to about 15 Å.

[0040] The first regions 600A of the PFET device 600 and the first regions 700A of the NFET device 700 do not include a diffusion barrier layer. The second regions 600B of the PFET device 600 and the second regions 700B of the NFET device 700 each include a diffusion barrier layer 610 and a diffusion barrier layer 710, respectively. The third regions 600C of the PFET device 600 and the third regions 700C of the NFET device 700 each include a diffusion barrier layer 610 that is thicker than the second region 600B and a diffusion barrier layer 710 that is thicker than the second region 700B. The fourth regions 600D of the PFET device 600 and the fourth regions 700D of the NFET device 700 each include a diffusion barrier layer 610 that is thicker than the third region 600C and a diffusion barrier layer 710 that is thicker than the third region 700C. The diffusion barrier layers 610 and 710 having different thicknesses can be formed by a process similar to the method 300, as described above in connection with FIGS. 3 and 4.

[0041] Method 500 begins at activity 502, where a Precision Material Engineering (PME) process is performed on the exposed surfaces of PFET device 600 (gate dielectric layer 608 within the first region 600A and diffusion barrier layers 610 within the second region 600B, third region 600C, and fourth region 600D) and on the exposed surfaces of NFET device 700 (gate dielectric layer 708 within the first region 700A and diffusion barrier layers 710 within the second region 700B, third region 700C, and fourth region 700D). The PME process includes exposing the exposed surfaces of PFET device 600 and NFET device 700 to nitrogen-containing species such as nitrogen radicals. In some embodiments, the PME process is performed using a separate plasma nitridation (DPN) process available from Applied Materials.

[0042] At activity 504, after the PME process, diffusion barrier layers 610 and 710 are removed.

[0043] Without being bound by theory, for PFET devices having a p-type dipole layer such as p-type dipole layer 606, as the thickness of diffusion barrier layer 610 increases, the threshold voltage (Vt) of the region decreases. In particular, the threshold voltage (Vt) of the first region 600A is higher than that of the second region 600B, in the second region 600B it is higher than that of the third region 600C, and in the third region 600C it is higher than that of the fourth region 600D.

[0044] Without being bound by theory, for NFET devices having an n-type dipole layer such as n-type dipole layer 706, as the thickness of diffusion barrier layer 710 increases, the threshold voltage (Vt) of the region increases. In particular, the threshold voltage (Vt) of the first region 600A is lower than that of the second region 600B, in the second region 600B it is lower than that of the third region 600C, and in the third region 600C it is lower than that of the fourth region 600D.

[0045] In some embodiments, the PME process of method 500 can be used to vary the properties of the gate dielectric layer within PFET device 800 that does not include a dipole layer.

[0046] As shown in FIG. 8, PFET device 800 includes a substrate 802, a silicon germanium-containing layer 804 on substrate 802, an interface layer 806 on silicon germanium-containing layer 804, a gate dielectric layer 808 on interface layer 806, and a diffusion barrier layer 810 on gate dielectric layer 808. A first region 800A of PFET device 800 does not include a diffusion barrier layer. A second region 800B of PFET device 800 includes diffusion barrier layer 810. A third region 800C of PFET device 800 has a thicker diffusion barrier layer 810 compared to second region 800B. A fourth region 800D of PFET device 810 has the thickest diffusion barrier layer 810. Interface layer 806 has a thickness of from about 3 Å to about 8 Å. Silicon germanium-containing layer 804 has a thickness of from about 15 Å to about 25 Å. After performing a PME process (e.g., nitridation process) on the exposed surfaces of PFET device 800 (gate dielectric layer 808 within first region 800A and diffusion barrier layer 810 within second region 800B, third region 800C, and fourth region 800D), the threshold voltage (Vt) value decreases from first region 800A to fourth region 800D.

[0047] In some embodiments, forming an n-type dipole layer having different thicknesses, such as in method 300, can be utilized to vary the characteristic values of the gate dielectric layer used in a PFET device 900 as shown in FIG. 9 and an NFET device 1000 as shown in FIG. 10. The PFET device 900 includes a substrate 902, a silicon germanium-containing layer 904, an interface layer 906, a gate dielectric layer 908, and an n-type dipole layer 910. The NFET device 1000 includes a substrate 1002, an interface layer 1004, a gate dielectric layer 1006, and an n-type dipole layer 1008. The n-type dipole layer 910 and the n-type dipole layer 1008 can be formed from lanthanum oxide. For the PFET device 900, the thicker the formed n-type dipole layer 910, after an annealing process (e.g., RTP process) is performed to drive the dipole dopant from the n-type dipole layer 910 into the gate dielectric layer 908 and from the n-type dipole layer 1008 into the gate dielectric layer 1006, the higher the threshold voltage (Vt) realized by various regions. For the NFET device 1000, the thicker the n-type dipole layer 1008, after a drive-in process is performed, the lower the threshold voltage (Vt) realized by various regions. The different thicknesses (both for PMOS and NMOS) formed in each region can be formed together during the process of forming the respective thicknesses of the n-type dipole layer 910 on the substrate.

[0048] The above description is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method for adjusting a threshold voltage in a field effect transistor (FET) device, comprising: performing a deposition process to deposit a diffusion barrier layer on a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure; performing a first patterning process to remove a portion of the barrier diffusion layer deposited in the first region; performing a second patterning process to partially remove a portion of the diffusion barrier layer deposited in the second region; performing a dipole layer deposition process to deposit a dipole layer on the gate dielectric layer in the first region, within the second region, and on the diffusion barrier layer within the third region; performing an annealing process to drive a dipole dopant from the dipole layer into the gate dielectric layer; A method comprising the above steps.

2. The method according to claim 1, wherein the diffusion barrier layer comprises titanium nitride, tantalum nitride, or tungsten nitride and has a thickness between 0 Å and 15 Å.

3. The method according to claim 1, wherein the gate dielectric layer comprises a high-k dielectric material and has a thickness between 5 Å and 15 Å.

4. The method according to claim 1, wherein the dipole layer comprises a dipole dopant and has a thickness between 3 Å and 10 Å.

5. The method according to claim 4, wherein the dipole layer has a uniform concentration of the dipole dopant between 1% and 20% over the thickness of the dipole layer.

6. The method according to claim 4, wherein the dipole layer has a gradient concentration of the dipole dopant that decreases along the thickness of the dipole layer from a surface of the dipole layer near the gate dielectric layer to an opposite surface of the dipole layer.

7. The method according to claim 1, wherein the deposition process comprises an atomic layer deposition (ALD) process.

8. The method according to claim 1, wherein the annealing process is performed at a temperature between 600 °C and 1100 °C for a time between 0.5 seconds and 15 seconds.

9. The dipole layer is thinnest in the first region and thickest in the third region; The threshold voltage shift is lowest in the first region and highest in the third region compared to an undoped dielectric layer; The method according to claim 1.

10. A method for adjusting a threshold voltage in a field effect transistor (FET) device, comprising: Forming a diffusion barrier layer having different thicknesses in a first region, a second region, and a third region of a semiconductor structure on a gate dielectric layer; Performing precision material engineering (PME) processing on an exposed surface of the semiconductor structure; A method comprising.

11. The method according to claim 10, wherein the gate dielectric layer is formed on a dipole layer having a thickness between 3 Å and 10 Å.

12. The method according to claim 10, wherein the gate dielectric layer is formed on a silicon germanium-containing layer having a thickness between 15 Å and 25 Å.

13. The method according to claim 10, wherein the diffusion barrier layer comprises titanium nitride, tantalum nitride, or tungsten nitride and has a thickness between 0 Å and 15 Å.

14. The method according to claim 10, wherein the gate dielectric layer comprises a high-k dielectric material and has a thickness between 5 Å and 15 Å.

15. The method according to claim 10, wherein the diffusion barrier layer is thinnest in the first region and thickest in the third region.

16. A method of forming a p-type field effect transistor (PFET) device and an n-type field effect transistor (NFET) device, comprising: Forming a first n-type dipole layer in a first gate dielectric layer formed on a silicon germanium-containing layer, the first n-type dipole layer having different thicknesses in a first region, a second region, and a third region of the PFET device; Forming a second n-type dipole layer in a second gate dielectric layer, the second n-type dipole layer having different thicknesses in a first region, a second region, and a third region of the NFET device; Performing an annealing process to drive a dipole dopant from the first n-type dipole layer into the first gate dielectric layer and from the second n-type dipole layer into the second gate dielectric layer; A method comprising.

17. The method according to claim 16, wherein the first n-type dipole layer and the second n-type dipole layer each comprise lanthanum oxide.

18. The method according to claim 16, wherein the first gate dielectric layer and the second gate dielectric layer each comprise a high-k dielectric material and have a thickness between 5 Å and 15 Å.

19. The method according to claim 16, wherein the silicon germanium-containing layer has a thickness between 15 Å and 25 Å.

20. The method according to claim 16, wherein the annealing treatment includes a rapid thermal processing (RTP) treatment.

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