MOSFET device

Abstract

The present invention relates to semiconductor devices and methods including metal-oxide-semiconductor field-effect transistor (MOSFET) devices and methods. Semiconductor devices such as MOFSETs have two source regions, drain regions, two body regions, and a buffer region. Each of the two body regions contacts a different one of the two source regions. The buffer region is located between the two body regions and contacts the two body regions. The doping concentration of the buffer region is lower than the doping concentrations of the two body regions.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to metal oxide semiconductor field effect transistor (MOSFET) devices.

Background Art

[0002] A MOSFET is a type of insulated gate field effect transistor with an intrinsic or parasitic body diode. MOSFET devices have a number of electrical characteristics or parameters. One exemplary characteristic of this MOSFET is the reverse recovery charge (Q RR ). The Q RR of a MOSFET is related to the switching speed in a typical motor drive application, i.e., a DC / DC converter. During the drive commutation of an inductive load, the MOSFET operates in the third quadrant. In this quadrant, the source / drain P-N junction diode turns on and charges are injected into the epitaxial layer. When the device turns off, it is necessary to dissipate the injected charges. That is, when the amount of reverse recovery charge (Q RR ) increases, the turn-off operation of the device becomes slower, the efficiency decreases due to power dissipation, or the device is damaged when the drain voltage becomes high before the charges are removed.

Brief Description of the Drawings

[0003] A more detailed understanding of the present invention can be obtained from the following description which is illustrated with reference to the accompanying drawings.

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[0004] The present invention relates to semiconductor devices such as MOSFET devices and manufacturing methods thereof. Semiconductor devices such as MOSFETs have two source regions, drain regions, two body regions, and a buffer region. Each body region contacts a different one of the two source regions. The buffer region is located between the two body regions and contacts the two body regions. The doping concentration of the buffer region is lower than that of the two body regions. Detailed description

[0005] Some embodiments relate to MOSFETs. The MOSFET has two source regions, drain regions, two body regions, and a buffer region. Each body region contacts a different one of the two source regions. The buffer region is located between the two body regions and contacts the two body regions. The doping concentration of the buffer region is lower than that of the two body regions.

[0006] In some embodiments, the buffer region extends deeper into the epitaxial layer than each of the two body regions. In some embodiments, the two body regions have a p-type material, and each buffer region has a different p-type material with a doping concentration lower than that of the p-type material of the two body regions. In some embodiments, the body diode of the MOSFET has a buffer region. In some embodiments, the body diode of the MOSFET has a P-N junction between the buffer region and the epitaxial layer of the MOSFET. In some embodiments, the P-N junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer when the source region and the drain region are reverse-biased. In some embodiments, the reverse recovery charge in the P-N junction between the buffer region and the epitaxial layer of the MOSFET recombines to form a depletion layer when the source region and the drain region are reverse-biased.

[0007] Some embodiments relate to a method of manufacturing a MOSFET. Doping material is implanted into the die between two body regions to form a buffer region located between these two body regions. The doping concentration of this buffer region is lower than that of the two body regions.

[0008] In some embodiments, the buffer region extends deeper into the epitaxial layer than each of the two body regions. In some embodiments, the two body regions have p-type material, the buffer region has another p-type material, and its doping concentration is lower than that of the p-type material of the two body regions. In some embodiments, the buffer region forms part of the body diode of the MOSFET. In some embodiments, the buffer region forms part of the body diode of the MOSFET that has a P-N junction between this buffer region and the epitaxial layer of the MOSFET. In some embodiments, the P-N junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer when the source region and the drain region of the MOSFET are reverse-biased. In some embodiments, the reverse recovery charge at the P-N junction between the buffer region and the epitaxial layer of the MOSFET recombines to form a depletion layer when the source region and the drain region of the MOSFET are reverse-biased.

[0009] Some embodiments relate to a semiconductor device. This semiconductor device has a source and a drain. The diode of the semiconductor device located between the source and the drain has a buffer region located between two body regions. At least one of these two body regions is in contact with the source. The doping concentration of the buffer region is lower than that of the two body regions.

[0010] In some embodiments, the buffer region extends deeper into the epitaxial layer than each of the two body regions. In some embodiments, the body region has a p-type material doped to a first dopant concentration, and the buffer region has a p-type material doped to a second dopant concentration lower than the first dopant concentration. In some embodiments, the diode has a parasitic diode of the MOSFET. In some embodiments, this diode has a P-N junction between the buffer region and the epitaxial region. In some embodiments, the P-N junction between the buffer region and the epitaxial region forms a depletion layer when the source region and the drain region are reverse-biased.

[0011] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings showing examples. The present invention will be described with reference to these embodiments, but the present invention is not limited to these embodiments. On the contrary, the present invention covers modified embodiments, corrected embodiments, and equivalent embodiments that are included within the spirit and scope of the present invention described in the claims. Further, the following detailed description of the present invention includes a number of specific details for the purpose of providing a complete understanding of the present invention. It should be understood by those skilled in the art that the present invention can be practiced without these specific details. Also, descriptions of known methods, known procedures, known components, and known circuits will be omitted in order to prevent the aspects of the present invention from being unnecessarily obscured.

[0012] In the following description, some technical terms and expressions are used only for the purpose of cost reduction, but are not intended to be limiting. Terms such as "right", "left", "up", and "down" are used to indicate directions in the accompanying drawings. Also, the singular forms used in the claims and the corresponding parts of the specification include one or more of the members mentioned, unless otherwise specified. This singular form includes the specifically described terms, derivatives of these terms, and similar expressions. For example, "at least one" preceding two or more items such as "A, B, or C" may mean A, B, or C alone, or any combination thereof. Note that for some of the drawings, a part is shown in a semi-transparent manner only for the purpose of explanation, illustration, and exemplification, and does not mean that the illustrated elements themselves are transparent in the final manufactured form.

[0013] In this specification, terms such as first, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are used only for the purpose of distinguishing one element from another. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element, without departing from the scope of the present invention. Also, the term "and / or" may mean the listed corresponding items alone, or may also mean the use of one or more of these items in combination.

[0014] Also, when it is described that an element such as a layer, region, substrate, lead, clip, pad or contact exists "on" or "extends over" another element, this represents that it directly exists on or extends over another element. Alternatively, it represents that yet another element is intervening. In contrast, when it is described that an element "directly exists on" or "directly extends over" another element, this represents that no intervening element exists. Also, when it is described that an element is "connected" or "coupled" to another element, this represents that it is directly connected or directly coupled to another element, or that intervening elements may exist. In contrast, when it is described that an element is "directly connected" or "directly coupled" to another element, this represents that no intervening element exists. These terms encompass different orientations of the element in addition to any orientation shown in the drawings.

[0015] Relative terms such as "under", "on", "upper" or "lower", or "horizontal" or "vertical" are used herein to describe the relationship of one element, layer or region to another element, layer or region. These terms encompass different orientations of the element in addition to any orientation shown in the drawings.

[0016] The accompanying drawings are not to scale and illustrate only a part of the structure and only a part of the various layers forming these structures. The accompanying drawings symbolically and schematically show the structure as a whole for facilitating the understanding of the invention and are not intended to reproduce the physical structure in detail. Further, the manufacturing processes and operations can be carried out with the processes and operations disclosed in this specification. That is, there are a number of process operations before, during, and / or after the operations shown and described in this specification. Further, the embodiments according to the present invention can be carried out according to other (possibly normal) processes and operations and do not significantly affect these. Overall, the embodiments according to the present invention can also replace normal process parts and / or can supplement these process parts, and neither significantly affects the surrounding processes and operations.

[0017] Regarding the term “MOSFET,” as a whole, it is synonymous with the term “insulated gate field effect transistor (IGFET)” as many currently used MOSFETs are composed of a non-metal gate and / or a non-oxide gate insulating film. As described in this specification, the term “MOSFET” does not necessarily imply or require an FET having a metal gate and / or an oxide gate insulator. Rather, the term “MOSFET” has a device that is generally known or called as “MOSFET.”

[0018] The term “substantially” in this specification and the claims refers to a design intention rather than a physical result. In the semiconductor field, the ability to measure various aspects of semiconductors accurately has been effectively used. Thus, when measuring with the available accuracy, generally speaking, the physical aspects of semiconductors are not as accurate as at the design time. Further, according to the measurement technology, differences in structures intended to be the same can be easily found. Therefore, terms such as “substantially equal” should be interpreted as being equal at the design time but being susceptible to manufacturing variations and measurement accuracy.

[0019] FIG. 1 is a cross-sectional view showing an exemplary power MOSFET 100. The illustrated MOSFET 100 is an n-channel enhancement mode MOSFET. Note that the embodiments described in this specification are referred to as n-channel enhancement mode MOSFETs for illustrative purposes, but the methods disclosed in this specification are also applicable to p-channel devices. For example, in the case of a p-channel device, the dopants used are of the opposite type to those in an n-channel device. In some embodiments, in the case of a p-channel device, as described in the examples, the regions are the same and the dopant concentrations are also the same, but the types of dopants are reversed (P-region instead of N-region, P-region instead of P+ region, etc.). The techniques described in this specification are also applicable to depletion mode devices that turn off the power MOSFET by applying a gate voltage.

[0020] MOSFT 100 is formed in the wafer 150 by implanting and / or diffusing materials such as dopants into the wafer 150 and depositing materials such as metal and polysilicon in the region 160 on top of the wafer 150. The wafer 150 is a semiconductor wafer made of any suitable material such as silicon, silicon carbide, germanium, gallium nitride, or other semiconductors.

[0021] MOSFT 100 has a source region 102, a drain region 104, a gate region 106, and a body region 108. The source region 102 is an n-doped region in the wafer 150 within the body region 108. The doping concentration of the source region 102 is generally higher than that of other n-type regions of the MOSFET 100 such as the drain region 104. For example, in some embodiments, the region with a high doping concentration has a dopant concentration of 1×10 18 ~5×10 20 atoms / cm 3is within the range. The drain region 104 is a substrate n-doping region with a generally high n-doping concentration, and the purpose is to form a low-resistance current path within the wafer 150 on the side facing the region 160. The N-region 110 is an n-type material deposited on the substrate 104, with a doping concentration slightly lower than that of the substrate (30% less, up to 3 times maximum), but acting as an intermediate layer much higher (at least one order of magnitude higher) than the region 118 within the wafer 150 between the drain region 104 and the n-epitaxial region 118. The general doping concentration range depends on the maximum voltage required for the device, but is approximately a fixed about 1×10 11 / cm 3 ~ about 1×10 17 / cm 3 would be fine. The N-region 110 acts as a barrier, preventing defects from migrating from the drain region 104 to the region 118 and preventing outward diffusion from spreading from the drain region 104 to the n-epitaxial region 118.

[0022] The gate region 106 is a polysilicon material region within the oxide region 112 located on the surface of the wafer 150 within this region 160. The body region 108 is a well of p-type material. Note that polysilicon is an example. For example, in some embodiments, a metal material such as tungsten silicide or aluminum can be used to implement the gate region. The doping concentration of the body region 108 is generally several times higher than the doping level of the epitaxial layer 118, for example, one order of magnitude or more higher within the wafer 150. The source metal 114 can be composed of any suitable conductive material (such as aluminum, copper, gold, and alloys thereof), and is located between the oxide regions 112 within the region 160 on the surface of the wafer 150. The source metal 114 not only forms a contact for the source region 102, but also shorts the source region 102 at the P+ region 116 between the source regions 102 located within the body region 108. The P+ region 116 is a region of p-type material located within the wafer 150 between the source regions 102. The doping concentration of the P+ region 116 is relatively higher than that of the body region 108.

[0023] The body region 108 and the n-epitaxial region 118 share a P-N junction and form an intrinsic (or parasitic) body diode between the source metal 114 and the drain region 104, as indicated by the diode symbol in FIG. 1. In some embodiments, since the P+ region 116 has a relatively high doping concentration, the contact resistance with the metal contact can be reduced, and the emitter of the parasitic bipolar transistor (i.e., the n+ source region 102) can be short-circuited to the p body 108.

[0024] When the source metal 114 and the drain 104 are in the forward bias state and the voltage of the gate 106 is above the threshold voltage (i.e., the minimum gate voltage to turn on the MOSFET for an n-channel device), an n-channel is formed in the body 108 under the gate region 106, and current flows between the source region 102 and the drain region 104 through the inversion layer in the body 108 and through the n-epitaxial layer 118.

[0025] Under the condition that the voltage across the source region 102 and the drain 104 is converted from the forward bias state to the reverse bias state where the voltage is above the reverse breakdown voltage of the P-N junction between the body region 108 and the n-epitaxial region 118, the charge carriers accumulated in the P-N junction recombine, a depletion region is formed in the P-N junction, and the reverse recovery current is blocked (or most of the current is blocked) until the reverse recovery current (I RR ) flows from the drain 104 across the P-N junction between the body region 108 and the n-epitaxial region 118 to the source contact 114. The amount of charge that recombines to block the reverse recovery current (or most of the current) is called the reverse current charge (Q RR ), and the time required to block the reverse recovery current (or most of the current) is called the reverse recovery time (t RR ).

[0026] In some embodiments, the reverse recovery charge (Q RR ) and / or the reverse recovery time (t RR) It is desirable to minimize, optimize, or suppress

[0027] FIG. 2 is a cross-sectional view showing an exemplary power MOSFET 200. The MOSFET 200 illustrated as an n-channel enhancement-mode MOSFET has a buffer region 270 and is substantially the same as the MOSFET 100 described with reference to FIG. 1, except that the body region 208 is divided as shown. The MOSFT 200 is formed in the wafer 250 by implanting and / or diffusing materials such as dopants in the wafer 250 and depositing materials such as metal and polysilicon in the region 260 on the upper surface of the wafer 250. The wafer 150 is a semiconductor wafer composed of any suitable material such as silicon and silicon carbide (silicon carbide).

[0028] The MOSFT 200 has a source region 202, a drain region 204, a gate region 206, and a body region 208. The source region 202 is an n-doping region in the wafer 250 within the body region 208. The doping concentration of the source region 202 is generally higher than that of other n-type regions of the MOSFET 200 such as the drain region 204. The drain region 204 is an n-doping region embedded in the wafer 250 on the side facing the region 260. The N-region 210 is an n-type region in the wafer 250 between the drain region 204 and the n-epitaxial region 218. The doping concentration of the N-region 210 is lower than that of the drain region 204.

[0029] The gate region 206 is a polysilicon material region within an oxide region 212 located on the surface of the wafer 250 within this region 260. The body region 208 is a well of p-type material within the wafer 250. The source metal 214 is located between oxide regions 212 within the region 260 on the surface of the wafer 250. The source metal 214 not only forms a contact to the source region 202, but also shorts the source region 202 with a P+ region 216 between the source regions 202 located within the body region 208. The P+ region 216 is a region of p-type material located within the wafer 250 between the source regions 202. The doping concentration of the P+ region 216 is relatively higher than that of the body region 208.

[0030] The buffer region 270 is a region of p-type material embedded between the body regions 208 and between the P+ region 216 and the n-epitaxial region 218. The doping concentration of the p-type material in the buffer region 270 is considerably lower than that of the P+ region 216, forming a high-low junction between the P+ region 216 and the buffer region 270. The p-type material of the buffer region 270 also has a considerably lower doping concentration than the body region 208. The buffer region 270 and the n-epitaxial region 218 share a P-N junction, forming an intrinsic (or parasitic) body diode between the source metal 214 and the drain region 204, as indicated by the diode symbol in Figure 2.

[0031] The buffer region 270 prevents or suppresses the excessive injection of charges (holes in this case) from the P+ region 216 into the n-epitaxial region 218, forming a high-low junction between the P+ region 216 and the buffer region 270. The charge injection efficiency into the n-epitaxial region 218 of the high-low junction is low. Further, the buffer region 270 prevents the breakdown voltage from occurring prematurely. That is, it prevents premature breakdown between P+216 and N-Epi218.

[0032] Under the condition that the source metal 214 and the drain 204 are in the forward bias state and the voltage of the gate 206 is equal to or higher than the threshold voltage, an n-channel is formed in the body 208 under the gate region 206, and current flows between the source region 202 and the drain region 204 through the inversion layer in the body 208 and through the n-epitaxial layer 218.

[0033] Under the condition that the voltage across the source region 202 and the drain 204 is converted from the forward bias state to the reverse bias state where the voltage is equal to or higher than the reverse breakdown voltage of the P-N junction between the buffer region 270 and the n-epitaxial region 218, the charge carriers accumulated in the P-N junction recombine, a depletion region is formed in the P-N junction, and the reverse recovery current is blocked (or most of the current is blocked) until the reverse recovery current (I RR ) flows from the drain 204 across the P-N junction between the buffer region 270 and the n-epitaxial region 218 to the source contact 214. The amount of charge that recombines to block the reverse recovery current (or block most of the current) is called the reverse current charge (Q RR ), and the time required to block the reverse recovery current (or block most of the current) is called the reverse recovery time (t RR ).

[0034] As described with reference to and shown in FIG. 1, the characteristics of the P-N junction of the body diode of the power MOSFET 200 are different from those of the P-N junction of the body diode of the power MOSFET 100 in that the charge carriers available in the buffer region 270 are less than those in the body region 108. For this reason, the intrinsic body diode of the power MOSFT 200 recombines the reverse recovery charge Q RR in a shorter time than the intrinsic body diode of the power MOSFET 100, and an effect is obtained in which a depletion region is formed and most of the reverse recovery current is blocked in a shorter time than the power MOSFET 100.

[0035] In other words, as shown in and described with reference to FIG. 1, since the doping concentration of the buffer region 270 is much lower than that of the body region 108 of the power MOSFET 100, the reverse recovery charge (Q RR ) is reduced in the power MOSFET 200. Therefore, the reverse recovery time (t RR ) is also shortened in the power MOSFET 200. This leads to the effect of increasing the switching speed of the power MOSFET 200.

[0036] FIG. 3 is a line graph showing the characteristics of the intrinsic body diode of the exemplary power MOSFET 100 shown in and described with reference to FIG. 1. This line graph shows the function I(t) of the intrinsic body diode. That is, it shows the range of the current flowing through the intrinsic body diode in a predetermined time and the time domain (time region) after the switching of the intrinsic body diode from the forward bias state to the reverse bias state.

[0037] At t 0 , the intrinsic body diode is in the forward bias state, and the forward current I F flows through the body diode (from the source 102 to the drain 104) when the bias state of the intrinsic body diode of the power MOSFET 100 switches from forward bias to reverse bias. After t 0 , the forward current I F starts to decrease until it reaches 0 volts in the intrinsic body diode of the power MOSFET 100.

[0038] After the forward current I F reaches zero, the reverse current I R starts to flow through the intrinsic body diode (from the drain 104 to the source 102). This is because the P-N junction of the intrinsic body diode remains in the conductive state, and during this time, the charge carriers in the P-N junction of the intrinsic body diode start to recombine, forming a depletion region. As the charge carriers recombine and the depletion region grows, I R decreases until it reaches the peak I RR called the reverse recovery current I R . The reverse current I R is the reverse recovery current I RRAfter reaching the peak, the reverse current I R decreases, the charges accumulated in the P-N junction recombine to form a depletion region, and the current flowing through the body diode continues to flow through the body diode until the current flowing through the body diode becomes 0 (almost 0 except for the reverse leakage current). Conventionally, from the point in time when the reverse recovery current starts to flow through the body diode until this reverse recovery current reaches I RR and then reaches 10% of the reverse recovery current I RR , the time is called the reverse recovery time (t RR ).

[0039] In some embodiments, this reverse recovery time (t RR ) is calculated based on a different percentage of the peak reverse recovery current I RR or another threshold. The amount of charge that recombines during the formation of the depletion region at the reverse recovery time t RR is called the reverse recovery charge Q RR .

[0040] FIG. 4 is a line graph showing the characteristics of the body diode of the exemplary power MOSFET 200 shown in and described with reference to FIG. 2. This line graph shows the function I(t) of the body diode. That is, it shows the range of the current flowing through the body diode in a predetermined time and time domain after the body diode switches from the forward bias state to the reverse bias state.

[0041] At t 0 , the body diode is in the forward bias state, and the forward current I F flows through the body diode (from the source 202 to the drain 204) when the bias state of the body diode of the power MOSFET 200 switches from forward bias to reverse bias. After t 0 , the forward current I F flowing through the body diode of the power MOSFET 200 begins to decrease until it reaches 0 volts.

[0042] After the forward current I F reaches zero, the reverse current I Rbegins to flow into the intrinsic body diode (from drain 204 to source 202). This is because the P-N junction of the intrinsic body diode remains in a conductive state, during which the charge carriers in the P-N junction of the intrinsic body diode start to recombine, forming a depletion region. As the charge carriers recombine and the depletion region grows, I R decreases until it reaches the reverse recovery current I RR . After the reverse current I R reaches its peak at the reverse recovery current I RR , the reverse current I R decreases, the charges accumulated in the P-N junction recombine to form a depletion region, and the current flowing through the intrinsic body diode continues to flow until the current flowing through the intrinsic body diode becomes 0 (almost 0 except for the reverse leakage current). Conventionally, the reverse recovery time (t RR ) is considered to be the time from when the reverse recovery current starts to flow through the intrinsic body diode until the reverse recovery current reaches 10% of I RR after reaching I RR .

[0043] In some embodiments, this reverse recovery time (t RR ) is calculated based on a different percentage of the peak reverse recovery current I RR or another threshold. The reverse recovery charge Q RR recombines during the formation of the depletion region at the reverse recovery time t RR .

[0044] The amount of reverse recovery charge (Q RR ) accumulated in the P-N junction of the intrinsic body diode of the power MOSFET 200 is less than the amount of reverse recovery charge (Q RR ) accumulated in the P-N junction of the intrinsic body diode of the power MOSFET 100. Therefore, these charge carriers recombine in a shorter time, forming a depletion layer and blocking the reverse current I R in a shorter time than in the case of the power MOSFET 100. In some embodiments, it is possible to achieve the effect of shortening the reverse recovery time (t RR ) compared to the case of the power MOSFET 100, and it is also possible to achieve the effect of shortening the switching time.

[0045] FIG. 5 is a cross-sectional view showing an intermediate structure 500 for manufacturing the power MOSFET 200. This intermediate structure 500 has a wafer 250, a drain region 204, an n-region 210, and an n-epitaxial region 218. In a suitable embodiment, such as a photoresist material or in the case of silicon carbide (silicon carbide), the blocking material 502 is a thick layer of deposited oxide, which is deposited in a region 260 on the upper surface of the wafer 250 and can be called a hard mask (HM). This blocking material 502 is located on the upper surface of the wafer 250 within the region 260 and is a material that selectively blocks the diffusion of doping material into the wafer 250.

[0046] FIG. 6 is a cross-sectional view showing an intermediate structure 600 for manufacturing the power MOSFET 200. This intermediate structure 600 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, and a blocking material 502. As shown by the arrow in FIG. 6, a p-type doping material is implanted into the n-epitaxial region 218 through a gap in the blocking material 502. As shown in the figure, the implanted p-type doping material forms a body region 208 within the intermediate structure 600. Note that other body regions are formed within the wafer 250 as shown in the figure. Such regions, in some embodiments, form part of other devices within the wafer. After the formation of the body region 208 within the intermediate structure 600, in some embodiments, if this blocking material 502 is HM, it does not come off. If the blocking material 502 is a photoresist, it can be removed by using a suitable solvent.

[0047] FIG. 7 is a cross-sectional view showing an intermediate structure 700 for manufacturing the power MOSFET 200. This intermediate structure 700 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, and a body region 208. When an etching process is performed, an oxide spacer (blocking material 702) having an occupied area of a specific dimension remains, and a self-aligned channel region is formed on the upper surface of the wafer 250. Since the blocking material 702 is located on the upper surface of the wafer 250 within the region 260, the diffusion of doping material into the wafer 250 can be selectively blocked.

[0048] FIG. 8 is a cross-sectional view showing an intermediate structure 800 for manufacturing the power MOSFET 200. This intermediate structure 800 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a blocking material 702. As indicated by the arrow in FIG. 8, p-type doping material is embedded into the body region 208 through a gap in the blocking material 702. As shown in the figure, the embedded n-type doping material forms a source region 202 within the intermediate structure 800. Note that other source regions are formed within the wafer 250 as shown. Such regions form part of other devices within the wafer in some embodiments. After the formation of the source region 202 within the intermediate structure 800, the blocking material 702 can be removed, for example, by a suitable solvent.

[0049] FIG. 9 is a cross-sectional view showing an intermediate structure 900 for manufacturing the power MOSFET 200. This intermediate structure 900 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a source region 202. A blocking material 902, such as photoresist, is deposited on a region 260 on the upper surface of the wafer 250. Since the blocking material 902 is located on the upper surface of the wafer 250 within the region 260, the diffusion of the doping material into the wafer 250 can be selectively blocked.

[0050] As indicated by the arrow, the p-type doping material is implanted into the n-epitaxial region 218 between the body regions 208 through the gap in the blocking material 902. In a preferred embodiment, the buffer layer implant overlaps (e.g., slightly) the body layer 208. In some embodiments, when the buffer layer overlaps the body region, the breakdown voltage stability is improved and / or the Qrr decreases as the overlap increases. Also, in some embodiments, when the buffer layer implant overlaps the body region, the overlap is made not to exceed the outer edge of the body region (e.g., the buffer layer 270 does not extend to the right of the right body region 208 in FIG. 11 or does not extend to the left of the left body region 208 in FIG. 11). In some embodiments, this results in the effect that the resistance of the MOSFET does not increase.

[0051] FIG. 10 is a cross-sectional view showing an intermediate structure 1000 for manufacturing the power MOSFET 200. This intermediate structure 1000 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a source region 202. The buffer region 270 is formed by implanting the p-type doping material described with reference to FIG. 9 as shown. The buffer region 270 has a lower p-type doping material concentration than the body region 208 and is preferably 30% deeper than the body region 208. Thus, in some embodiments, the effect that the injection efficiency of the body region is reduced is obtained. This buffer region 270 is shown in more detail in FIGS. 15 and 16 and will be described in more detail with reference to these drawings. In some embodiments, the low doping concentration of the buffer region 270 is opposite to the known region corresponding to the body, and this region is deeper than the body. Therefore, the doping concentration can generally be made as high as possible, malfunction of the parasitic transistor can be prevented, and / or the injection efficiency into the epitaxial layer of the body region can be increased. Also, contrary to the prior art, in some embodiments, since the doping concentration of the buffer region 270 can be lowered, the effect of reducing Qrr can be obtained while alleviating the conventionally observed effects.

[0052] With the blocking material 902 maintained in place, as indicated by the arrow, further p-type material is implanted into the buffer region 270 and the body region 208 through the gap in the blocking material 902.

[0053] FIG. 11 is a cross-sectional view showing an intermediate structure 1100 for manufacturing the power MOSFET 200. This intermediate structure 1100 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, and a P+ region 216 formed by implantation of a p-type doping material as described with reference to FIG. 10. This P+ region 216 has a higher p-type doping concentration than the body region 208 and a higher p-type doping concentration than the buffer 270, but is shallower than the body region 208 and the buffer 270.

[0054] The intermediate structure 1100 can have the blocking material 902 removed by a suitable solvent or the like after the formation of the P+ region 216 as shown in the figure.

[0055] FIG. 12 is a cross-sectional view showing an intermediate structure 1200 for manufacturing the power MOSFET 200. This intermediate structure 1200 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, a P+ region 216, and an oxide layer 212 that forms a thermally grown gate oxide in a region 260 on the upper surface of the wafer 250. In other embodiments, any suitable oxide or other insulator can be used. In this example, the oxide layer 212 has silicon dioxide (SiO 2 )). In this example, the oxide layer 212 is first formed by forming an oxide layer 212A. A gate 206 (preferably a polysilicon material) is deposited on the oxide layer 212A and etched to suitable dimensions. Next, an oxide layer 212B is deposited on the gate 206 and the oxide layer 212A to form the oxide layer 212.

[0056] FIG. 13 is a cross-sectional view showing an intermediate structure 1300 for manufacturing a power MOSFET 200. This intermediate structure 1300 has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, a P+ region 216, and an oxide layer 212.

[0057] The oxide layer 212 is selectively removed from a part of the region 260, for example, by masking and etching or other suitable processes, to expose the P+ region 216 and the source region 202. A source metal 214 is deposited in the gap formed in the oxide layer 212 on the P+ region 216 and the source region 202. The P+ region 216 and the source region 202 are short-circuited together by the source metal 214. The deposition of the source metal 214 is performed by sputtering, evaporation, or other suitable processes.

[0058] By masking and etching or other suitable processes, the gate region 206 grows on the field oxide portion of the oxide 212, and further the oxide 212 grows on the gate region 206. The gate region 206 is composed of a polysilicon material or other suitable materials.

[0059] FIG. 14 is a flowchart showing a method 1400 for manufacturing a power MOSFET such as the power MOSFET 200 shown in FIG. 2 and described with reference to this, in the manner described with reference to FIGS. 5 to 13. Note that in some embodiments, some steps and reordering steps are not used, and / or additional attendant steps are used.

[0060] In step 1402, a blocking material is deposited on the surface of the intermediate structure, patterned to expose the die region for implanting the p-type dopant, and the internal body region of the die is formed to manufacture the power MOSFET.

[0061] In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, and an n-epitaxial region 218 shown in and described with reference to FIG. 5. A blocking material is deposited on the upper surface of the wafer 250 within the region 260 to selectively prevent the doping material from diffusing into the wafer 250 as shown in and described with reference to FIG. 5.

[0062] In a preferred embodiment, the blocking material has silicon dioxide, which is patterned and etched using a photoresist process. The photoresist is removed, leaving the oxide layer as a Hard Mask (HM). In some embodiments, for this purpose, another oxide deposition is added, a self-aligned region is formed for this layer, and the so-called "spacer etching" (which is known) can be performed to achieve the effect of self-aligning two independent implant layers.

[0063] In step 1404, a p-type material is implanted into the exposed region of the intermediate structure to form a body region within the die. After the body region is formed in the intermediate structure, the blocking material (HM) is not removed.

[0064] In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, and a blocking material 502 shown in and described with reference to FIG. 6. As indicated by the arrow in FIG. 6, a p-type doping material is implanted into the n-epitaxial region 218 through a gap in the blocking material 502. As shown in the figure, the implanted p-type material forms a body region 208 within the intermediate structure 600. As also shown in the figure, other body regions are formed within the wafer 250. In some embodiments, this region constitutes part of other devices within the wafer.

[0065] In process 1406, a blocking material, preferably silicon dioxide, is deposited on top of the first HM formed on the surface of the intermediate structure in process 1404, patterned by a spacer etching process, the region of the die is exposed to implant an n-type dopant, and a source region is formed within the die. Note that for this process, in some embodiments, "dry" or plasma etching is performed. Therefore, in some embodiments, since the n-source can be aligned with the body region, the effect of accurately controlling the channel length of the MOSFET can be realized.

[0066] In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, and a body region 208, and as shown in and described with reference to FIG. 7, a blocking material such as an oxide material is deposited on region 260 on the upper surface of the wafer 250. Since the blocking material is located on the upper surface of the wafer 250 and on top of the HM of process 1404, the diffusion of the doping material into the wafer 250 can be selectively prevented.

[0067] In process 1408, an n-type material is implanted into the exposed surface of the intermediate structure to form a source region within the die. After forming the source region in the intermediate structure, the blocking material is removed, for example, by a suitable solvent.

[0068] In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a blocking material 702 shown in and described with reference to FIG. 8. As indicated by the arrow in FIG. 8, an n-type doping material is implanted into the body region 208 through the gap in the blocking material 702. As shown in the figure, the implanted n-type doping material forms a source region 202 within the intermediate structure. Note that as shown in the figure, other source regions are formed within the wafer 250. In some embodiments, this region constitutes part of other devices within the wafer.

[0069] In process 1410, a blocking material is deposited on the surface of the intermediate structure, patterned to expose the die regions for implanting p-type dopants, and a buffer region is formed within the die. In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a source region 202 shown and described with reference to FIG. 9. A blocking material, such as photoresist, is deposited in region 260 on the upper surface of the wafer 250. Since the blocking material is located on the upper surface of the wafer 250 within region 260, the diffusion of the doping material into the wafer 250 can be selectively blocked.

[0070] In process 1412, a p-type doping material is implanted into the exposed regions of the intermediate structure to form a buffer region within the die. In some embodiments, as indicated by the arrows and as shown and described with reference to FIG. 10, the p-type doping material is implanted into the n-epitaxial region 218 between the body regions 208 through the gap in the blocking material 902.

[0071] In process 1414, more p-type material is implanted into the exposed regions of the intermediate structure to form a P+ region within the die, and the blocking material is removed using, for example, a suitable solvent. In some embodiments, as indicated by the arrows and as shown and described with reference to FIG. 10, more p-type material is implanted into the buffer region 270 and the body region 208 through the gap in the blocking material 902, and an intermediate structure is formed as shown and described with reference to FIG. 11.

[0072] In process 1416, an insulator is thermally grown at a high temperature or deposited on the surface of the intermediate structure. In some embodiments, any suitable oxide or other insulator can be used. In this example, the insulator is silicon dioxide (SiO 2) In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, and a P+ region 216, and the insulator is an oxide layer 212 grown within a region 260 on the upper surface of the wafer 250 as shown in and described with reference to FIG. 12. After the thermally deposited oxide, a polysilicon layer is formed and patterned to form the gate of the MOSFET.

[0073] In step 1418, the insulator is patterned and etched to expose the source region and the P+ region, and in step 1420, metal is deposited on the exposed source region and the P+ region to form a source contact and short the source region and the P+ region together. By etching the deposited polysilicon layer, a gate region is formed on the thermally grown or thermally deposited insulator to form the gate of the MOSFET. In some embodiments, the intermediate structure has a wafer 250, a drain region 204, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, a P+ region 216, and an oxide layer 212, and the insulator (such as the oxide layer 212) is selectively removed from a part of the region 260, and the P+ region 216 and the source region 202 are exposed by a masking / etching process or other suitable processes. As a result, a source metal 214 is deposited in a gap formed within the oxide layer 212 on the P+ region 216 and the source region 202. The P+ region 216 and the source region 202 are shorted together by the source metal 214. The deposition of the source metal 214 is performed by sputtering, evaporation, or other suitable processes. Through masking / etching or other suitable processes, a gate region 206 grows on the field oxide portion of the oxide 212, and further oxide 212 grows on the gate region 206. The material for forming the gate region 206 is polysilicon or other suitable materials.

[0074] FIG. 15 is a cross-sectional view showing an exemplary power MOSFET 200 shown in and described with reference to FIG. 2, with the axis denoted by A, and showing the types and concentrations of relative doping for the layers 216, 270, 218, 210, 204. The axis A passes through the layers 216, 270, 218, 210, 204, respectively.

[0075] FIG. 16 is a line graph showing the relative doping concentrations within each region of the MOSFET 200 existing along the axis A of FIG. 15. This line graph shows the relative doping concentrations (on a logarithmic scale) of the respective regions 216, 270, 218, 210, 204. There are transition regions where the doping concentration changes gradually between each region existing along the axis. For example, the segment (interval) W of the line graph indicates the transition region between regions 216 and 270. The segment (interval) X of the line graph indicates the transition region between regions 270 and 218. The segment (interval) Y of the line graph indicates the transition region between regions 218 and 210. The segment (interval) Z of the line graph indicates the transition region between regions 210 and 204. Note that the transition in the doping concentration indicated by the segment (interval) X between the buffer region 270 and the epitaxial region 218 is relatively minimal.

[0076] Due to the minimal transition indicated by the segment (interval) X, the reverse recovery charge (Q RR ) of the power MOSFET 200 is lower compared to power MOSFETs that do not share this characteristic. Therefore, the reverse recovery time (t RR ) is also shorter compared to the MOSFET 200. For this reason, the effect of increasing the switching speed of the power MOSFET 200 can be realized.

[0077] For comparison, FIG. 18 shows a line graph of the relative doping concentrations in the regions of the MOSFET 100 existing along the axis A of FIG. 17. This line graph shows the relative doping concentrations (on a logarithmic scale) of the respective regions 116, 108, 118, 110, 104.

[0078] There is a transition region with a gradually changing doping concentration between each region existing along the axis. For example, the segment (interval) Q of the line graph indicates the transition region between regions 116 and 108. The segment (interval) R of the line graph indicates the transition region between regions 108 and 118. The segment (interval) S of the line graph indicates the transition region between regions 118 and 110. The segment (interval) T of the line graph indicates the transition region between regions 110 and 104. Note that, as shown in FIGS. 15 and 16 and described with reference to these drawings, the transition at the doping concentration indicated by segment (interval) R between the body region 108 and the epitaxial region 118 is relatively large compared to segment (interval) X.

[0079] Due to the relatively large transition indicated by segment (interval) R, the reverse recovery charge (Q RR ) of the power MOSFET 100 becomes larger compared to the power MOSFET 200. Therefore, the reverse recovery time (t RR ) also becomes longer compared to the MOSFET 100. For this reason, in some embodiments, the switching speed of the power MOSFET 100 is slower than that of the MOSFET 200.

[0080] Note that many aspects are possible based on the disclosure of this specification. Although features and elements are used in a specific form, each feature and each element can be used alone, without the need to combine with other features or other elements, or it is also possible to combine with other features and other elements.

Description of Reference Numerals

[0081] 100, 200 Power MOSFET, MOSFET 102 Source region, n+ source region 104 Drain region, substrate 104, 108, 110, 116, 118, 160, 204, 210, 216, 218, 1400 Method 106, 206 Gate region, gate 108 Body region, p body, body 110 N - region 112 Oxide region 114 Source metal 116 P+ region 118 n-epitaxial region, region, epitaxial layer 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, 1418, 1420 Processes 150, 250 Wafers 202 Source region 204, 210, 216, 218, 270 Layers 204 Drain region 208 Body region, body 210 N-region, n-region 212 Oxide 212, 212A, 212B Oxide layers 214 Source metal, source contact 216 P+ region 218 N-Epi, n-epitaxial region 260, 270 Regions 270 Buffer region 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 Intermediate structures 502, 702, 902 Blocking materials Axis A, axis Segments Q, R, S, T, W, X, Y, Z (intervals)

Claims

1. Two source regions, Drain region, two body regions, each contacting a different one of the two source regions; a buffer region located between and in contact with the two body regions, the buffer region being comprised of a region of material of the same dopant type as the two body regions and extending from one of the two body regions to the other; and a material region located between and in contact with the buffer region and at least one of the two source regions; and the doping concentration of the buffer region is lower than the doping concentrations of the two body regions; and the buffer region extends further into the epitaxial layer than each of the two body regions; and 1. A metal-oxide-silicon field-effect transistor (MOSFET), wherein the doping concentration of the material region located between and in contact with the buffer region and at least one of the two source regions is higher than the doping concentration of the two body regions.

2. 2. The MOSFET of claim 1, wherein said two body regions comprise a p-type material and said buffer region comprises another p-type material that is doped to a lower concentration than the p-type material of said two body regions.

3. 2. The MOSFET of claim 1, wherein a body diode of the MOSFET comprises the buffer region.

4. 2. The MOSFET of claim 1, wherein a body diode of the MOSFET comprises a PN junction between a buffer region and an epitaxial layer of the MOSFET.

5. 2. The MOSFET of claim 1, wherein a PN junction between the buffer region and an epitaxial layer of the MOSFET forms a depletion layer when the two source regions and the drain region are reverse biased.

6. 2. The MOSFET of claim 1, wherein reverse recovery charges in a P-N junction between the buffer region and the epitaxial layer of the MOSFET recombine to form a depletion layer when the two source regions and the drain region are reverse biased.

7. implanting a doping material into the die between two body regions to form a buffer region located between the two body regions, the buffer region comprising a region of material of the same dopant type as the two body regions and extending from one of the two body regions to the other; inlaying a material region between and in contact with the buffer region and the source region; The doping concentration of the buffer region is set lower than the doping concentrations of the two body regions; the buffer region extends further into the epitaxial layer than the two body regions; and 1. A method of manufacturing a metal-oxide-silicon field-effect transistor (MOSFET), wherein the material region between and in contact with the buffer region and the source region has a doping concentration greater than the doping concentrations of the two body regions.

8. 8. The method of claim 7, wherein the two body regions comprise a p-type material and the buffer region comprises another p-type material that is doped to a lower concentration than the p-type material of the two body regions.

9. The method of claim 7 , wherein the buffer region comprises a portion of the body diode of the MOSFET.

10. 8. The method of claim 7, wherein the buffer region comprises a portion of a body diode of a MOSFET having a PN junction between the buffer region and an epitaxial layer of the MOSFET.

11. The manufacturing method of claim 7, wherein a PN junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer when the source region and the drain region of the MOSFET are reverse biased.

12. A manufacturing method as described in claim 7, wherein when the source region and the drain region of the MOSFET are reverse biased, reverse recovery charges in the P-N junction between the buffer region and the epitaxial layer of the MOSFET recombine to form a depletion layer.

13. Source, and having a drain, a diode of the semiconductor device located between the source and the drain, the diode having a buffer region located between two body regions, the buffer region being composed of a region of material of the same dopant type as the two body regions and extending from one to the other of the two body regions, at least one of the two body regions contacting the source; the doping concentration of the buffer region is lower than the doping concentrations of the two body regions; and the buffer region extends further into the epitaxial layer than the two body regions; and A semiconductor device, characterized in that a material region located between and in contact with said buffer region and said source has a doping concentration higher than the doping concentrations of said two body regions.

14. 14. The semiconductor device of claim 13, wherein the body region comprises p-type material doped to a first dopant concentration, and the buffer region comprises p-type material doped to a second dopant concentration that is less than the first dopant concentration.

15. 14. The semiconductor device of claim 13, wherein the diode comprises an intrinsic diode of a metal-oxide-silicon field-effect transistor (MOSFET).

16. 14. The semiconductor device of claim 13, wherein the diode comprises a PN junction between the buffer region and the epitaxial layer.

17. 14. The semiconductor device of claim 13, wherein a PN junction between the buffer region and the epitaxial region forms a depletion layer when the source and the drain are reverse biased.

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