Bias level sensor for reciprocal quantum logic

Abstract

A reciprocal quantum logic (RQL) bias level sensor is fabricated on an RQL integrated circuit (IC) and samples an AC or DC bias value provided to an operating RQL circuit on the RQL IC. The bias level sensor or sampler includes a Josephson transmission line (JTL) or logic gate having a bias tap that is enhanced or attenuated compared to a bias tap of a JTL or logic gate within the operating RQL circuit. A sampler JTL or logic gate having an attenuated bias tap to an AC clock resonator may have a lower limit of its operating range located near an optimal bias point that is at the centroid of the operating region of the operating RQL circuit. By stepwise setting the relative strength of the bias taps of the samplers in a population of samplers, the output of a wrapper circuit can indicate whether the supplied bias value is improved or optimized as the supplied bias value varies over a range.

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