Shared Column ADC for In-Memory Computing Macros
JP2025519052AActive Publication Date: 2025-06-24THE TRUSTEES OF PRINCETON UNIV
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Patent Information
- Application Number
- JP2024568086
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-05-16
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2042-05-16
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Figure 2025519052000001_ABST
Abstract
Various embodiments include systems, methods, architectures, mechanisms, devices, and improvements thereto that scale and aggregate a plurality of weighted data representation analog signals supplied by columns of in-memory computing bit cells within an N×M array of bit cells, and perform analog accumulation or aggregation of the weighted data representation analog signals such that the scaled result is supplied for further processing.
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Citation Information
Patent Citations
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