Method for generating a semiconductor device and semiconductor device

Abstract

Method for generating a semiconductor device and semiconductor device According to one embodiment, the method includes providing a semiconductor body (1) having an upper surface (10). A mask (2) is deposited on the upper surface of the semiconductor body, and the mask includes at least one first section (21) and at least one second section (22). The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In a further step, a channel region (11) of a first conductivity type is formed in the semiconductor body (1) within the region of the at least one first section. Forming the channel region includes implanting a dopant of the first type into the semiconductor body through the upper surface. In a further step, an auxiliary layer (3) is deposited on a side surface (22a) of the at least one second section, the side surface facing the at least one first section. Thereby, the lateral extent of the at least one second section is increased and the lateral extent of the at least one first section is decreased. In a further step, a hole is generated in the semiconductor body in the region of the first section with a reduced lateral extent such that the hole extends from the upper surface through the channel region.

Description

Technical Field

[0001] The present disclosure relates to a method for generating a semiconductor device and a semiconductor device.

Background Art

[0002] U.S. Patent Application Publication No. 2012 / 0146090 relates to a transistor device that can be fabricated with an integrated diode using self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulating gate electrodes formed in trenches in the substrate. One or more body regions are formed on top of the substrate adjacent to each gate trench. One or more source regions are formed self-aligned on top of the body regions adjacent to each gate trench. One or more thick insulator portions are formed on top of the gate electrodes on the upper surface of the substrate with a space between adjacent thick insulator portions. Metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the space between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

[0003] U.S. Patent Application Publication No. 2012 / 0164810 relates to a method for manufacturing a silicon carbide semiconductor device. Through a first opening formed in a mask layer, a first impurity region is formed by ion implantation. By depositing a spacer layer on an etch stop layer provided with the mask layer, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. The angle of the second sidewall with respect to the surface is 90° ± 10° over the same height as the second depth. Thereby, the expansion accuracy of the impurity region can be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is an object to provide an improved method for generating a semiconductor device, for example, a method with a reduced number of generation steps and / or a method enabling the generation of smaller structures. A further object is to provide an improved semiconductor device having, for example, smaller structures.

Means for Solving the Problems

[0005] Embodiments of the present disclosure relate to an improved method for generating a semiconductor device and an improved semiconductor device.

[0006] First, a method for generating a semiconductor device is described. According to one embodiment, a method for generating a semiconductor device includes providing a semiconductor body having an upper surface. A mask is deposited on the upper surface of the semiconductor body, and the mask includes at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In a further step, a channel region of a first conductivity type is formed in the semiconductor body within the region of the at least one first section. Forming the channel region includes implanting a dopant of the first type into the semiconductor body through the upper surface. In a further step, an auxiliary layer is deposited on the side surface of the at least one second section, and the side surface faces the at least one first section. Thereby, the lateral extent of the at least one second section increases and the lateral extent of the at least one first section decreases. In a further step, a hole is generated in the semiconductor body in the region of the first section with a reduced lateral extent such that the hole extends from the upper surface through the channel region.

[0007] The excellent properties of wide bandgap semiconductors (WBG), such as high critical electric fields and electron mobility or high-frequency switching, result in much larger figure of merit performance indices compared to commonly used silicon, making them ideal materials for power switches. This enables several applications for energy efficiency and electrical transport.

[0008] Today, most commercially available power SiC-MOSFETs are based on cell designs with a planar channel aligned to the Si face, i.e., the surface of the wafer SiC(0001). However, the boost in current density in such switches is hampered by the junction-FET (JFET) resistance that increases with the downscaling of the injector, and the low inversion channel mobility. On the other hand, trench MOSFETs showing dry-etched U-shaped channels, having no JFET region and high cell density, enable achieving low on-resistance. Especially in the case of SiC channel devices, the trench MOSFET architecture allows for optimizing carrier mobility by designing channels for multiple different crystal planes and enhancing gate dielectric control.

[0009] Nevertheless, the state-of-the-art trench cell designs do not fully exploit the above advantages. Despite using multiple different crystal planes for carrier transport, the trench pitch and width of the cells are still quite large, thus preventing the maximally scaled cell density and hence the high current density of the device.

[0010] The method disclosed herein enables self-aligned channel implantation and trench etching, thus replacing two separate lithography steps. As a result, fewer fabrication steps are required and smaller structures can be fabricated. This method is suitable for the fabrication of various semiconductor devices such as MOSFTs or IGBTs or JFETs or MISFETs.

[0011] The semiconductor body is based on, for example, Si, SiC, GaN, Ga2O3. The semiconductor body may be based on a wide bandgap material. The semiconductor body can comprise a doped substrate and a doped drift layer on the substrate. The upper surface of the semiconductor body may be at least partially formed by the drift layer. For example, the substrate has a higher doping concentration than the drift layer. The substrate and the drift layer may be of the same conductivity type. Both may be either n-doped or p-doped.

[0012] In the step of providing the semiconductor body, the upper surface of the semiconductor body may be a flat surface without breaks or dents or holes.

[0013] The mask may be generated using a lithography process. For example, the mask contains a photoresist. In at least one second section, the mask is thicker than at least one first section. This can mean, for example, that the thickness of the mask in at least one first section is 0 so that the upper surface of the semiconductor body is exposed in the region of at least one first section. Alternatively, the mask may have a thickness of at least one first section that is greater than 0 but less than the thickness of at least one second section. In either case, a step is formed between at least one first section and at least one second section. This step forms the side surface of the second section facing the at least one first section.

[0014] The thickness of the mask is measured in a direction perpendicular to the upper surface. The "thickness" in this specification means the average value of the maximum thickness. For example, the thickness of the mask in at least one second section is at least 2 times or at least 5 times or at least 10 times or at least 100 times greater than the thickness in at least one first section.

[0015] The mask comprises at least one first section, i.e., one or more first sections, and at least one second section, i.e., one or more second sections. All features disclosed herein for one first section are disclosed for all first sections, and similarly, all features disclosed herein for one second section are disclosed for all second sections.

[0016] For simplicity, the expression “at least one” is also referred to herein simply as “the”.

[0017] For example, the mask comprises one second section forming a web and several first sections each within the mesh of the web. Alternatively, the mask may comprise one first section forming a web and several second sections each within the mesh of the web. A further alternative is that the mask comprises several first sections and several second sections, with each first section being laterally between two second sections.

[0018] At least one first section is laterally adjacent to at least one second section. In particular, at least one second section is adjacent to at least one first section laterally. The step between the first section and the second section indicates, for example, the boundary between the first section and the second section. The second section may completely surround at least one first section laterally. Alternatively, the first section may be between two second sections in a first lateral direction. In this specification, the lateral direction is understood as a direction parallel to the upper surface of the semiconductor body and / or parallel to the main extension plane.

[0019] The step of forming the channel region is performed after the step of depositing a mask on the upper surface. Forming the channel region includes implanting a first-type dopant through the upper surface of the semiconductor body. The first-type dopant is either a p-type dopant or an n-type dopant. The second-type dopant is, in this specification, different from the first-type dopant, i.e., either an n-type dopant or a p-type dopant. For example, the first-type dopant is boron and the second-type dopant is arsenic or phosphorus.

[0020] Forming the channel region can further include an annealing step that is performed after implanting the first-type dopant. During the annealing step, the implanted first-type dopant further diffuses within the semiconductor body, and as a result, the channel region spreads into the semiconductor body.

[0021] The channel region is of the first conductivity type. When the first-type dopant is a p-type dopant, the first conductivity type is hole conduction. That is, the channel region is p-doped. When the first-type dopant is an n-type dopant, the first conductivity type is electron conduction, i.e., the channel region is n-doped. The second conductivity type is, in this specification, different from the first conductivity type.

[0022] The channel region is formed within the region of at least one first section, i.e., under at least one first section. During implantation, the dopant can abut the mask over its entire lateral extent, i.e., also in the region of at least one second section. However, since the thickness of the mask in at least one second section is greater, less dopant is implanted into the semiconductor body in the region of the second section. The amount of the first-type dopant implanted into the region of the second section is, for example, not sufficient to form a region of the first conductivity type under the second section.

[0023] The channel region extends, for example, at least 50 nm and / or at most 1 μm from the upper surface into the semiconductor body (depth of the channel region).

[0024] The step of depositing an auxiliary layer on the side surface of at least one second section is performed after forming the channel region. As described above, the side surface of at least one second section may be formed by a step between at least one second section and at least one first section. Thus, the side surface extends obliquely, for example, vertically or substantially vertically, with respect to the upper surface.

[0025] Due to the auxiliary layer, the width or lateral extent of the second section increases, while the width or lateral extent of the first section decreases. In other words, by depositing an auxiliary layer on the side surface of the mask (also referred to as the initial mask), the mask is complemented by the deposited auxiliary layer, and thus is converted into a new mask including the initial mask and the deposited auxiliary layer, having a narrower / smaller first section and a wider / larger second section.

[0026] The thickness of the auxiliary layer on the side surface of at least one second section is, for example, at least 50 nm and at most 1 μm. Thus, the lateral extent of at least one second section increases by at least this thickness, for example, by about twice this thickness, and the lateral extent of at least one first section decreases by at least this thickness, for example, by about twice this thickness.

[0027] The material of the auxiliary layer is, for example, different from the material of the initial mask. For example, the auxiliary layer includes or consists of SiO2 or SiN or polysilicon.

[0028] The step of generating holes in the semiconductor body is performed after deposition of the auxiliary layer. The holes are generated in the region of the first section with a reduced lateral extent. During generation of the holes, the semiconductor body under the second section with an increased lateral extent may be protected by the second section with an increased lateral extent, and as a result, the holes are actually formed only in the region of the first section with a reduced lateral extent.

[0029] Due to the reduced lateral extent of the first section, the generated holes have a smaller lateral extent or width than the previously formed channel region. Thus, the holes are formed through the channel region. For example, the holes are laterally adjacent to the channel region. For example, the holes are either completely surrounded by the channel region laterally, or the channel region is adjacent to the holes on both sides with respect to the first lateral direction.

[0030] For example, the generated holes protrude deeper into the semiconductor body than the channel region, for example at least 1.5 times deeper. By way of example, the depth of the holes is at least 500 nm and / or at most 2 μm.

[0031] According to a further embodiment, after forming the channel region and before depositing the auxiliary layer, a further auxiliary layer that increases the lateral extent of at least one second section and decreases the lateral extent of at least one first section is deposited on the side surfaces of at least one second section. Since the further auxiliary layer is deposited before the auxiliary layer, the further auxiliary layer is also referred to herein as the first auxiliary layer, and thus the auxiliary layer is also referred to herein as the second auxiliary layer.

[0032] Thus, during this method, the lateral extent of the second section of the mask may be doubled, and the lateral extent of the first section of the mask may be halved. In other words, the initial mask is converted twice into each new mask such that each time the first section becomes narrower / smaller and the second section becomes wider / larger.

[0033] The thickness of the further auxiliary layer on the side surfaces of at least one second section may be within the same range as the thickness of the auxiliary layer on the side surfaces. The further auxiliary layer may be a material different from the auxiliary layer and / or the mask. For example, the further auxiliary layer comprises or consists of SiO2 or SiN or polysilicon.

[0034] According to a further embodiment, after depositing a further auxiliary layer and before depositing the auxiliary layer, a contact region of a second conductivity type is formed in the semiconductor body within the region of the first compartment. The contact region is formed to be between the channel region and the upper surface of the semiconductor body. The formation of the contact region includes implanting a dopant of the second type into the semiconductor body through the upper surface.

[0035] The formation of the contact region may include an annealing process after implanting the dopant of the second type. In the annealing process, the dopant of the second type further diffuses within the semiconductor body, and as a result, the contact region further spreads into the semiconductor body.

[0036] The contact region is at least partially formed from the previously formed channel region. Thus, the amount of the dopant of the second type to be implanted is sufficient to convert a part of the channel region of the first conductivity type to the second conductivity type.

[0037] During the implantation of the dopant of the second type, the lateral extent of the first compartment is reduced compared to the lateral extent of the first compartment during the implantation of the dopant of the first type, so the contact region has a smaller lateral extent than the channel region. Thus, in the lateral direction, the contact region is surrounded by the channel region or the channel region is adjacent on both sides with respect to the first lateral direction.

[0038] The depth of the contact region is smaller than the depth of the channel region, for example, such that the contact region is between the channel region and the upper surface. In other words, in the vertical direction perpendicular to the upper surface, the contact region is disposed between the channel region and the upper surface.

[0039] According to a further embodiment, the hole is formed through the contact region. For example, the hole is laterally adjacent to the contact region. Since the lateral extent of the first section during the formation of the hole is smaller than the lateral extent of the first section during the implantation of the second type of dopant, the lateral extent of the hole is smaller than the lateral extent of the contact region. For example, the hole is completely surrounded laterally by the contact region, or the contact region is adjacent to the hole on both sides with respect to a first lateral direction. For example, in the first lateral direction, the contact region is arranged between the hole and the channel region.

[0040] By forming the hole, the channel region and / or the contact region formed in the region of at least one first section can be divided into two channel regions and / or contact regions. All features disclosed herein and below with respect to one channel region or one contact region within the region of at least one first section are also disclosed for two contact regions or two channel regions within the region of at least one first section.

[0041] According to a further embodiment, the auxiliary layer is deposited by a conformal, i.e., non-directional deposition process. As a result, the side surfaces of at least one second section, the upper surface of at least one second section, and the region of the first section are covered by the auxiliary layer. For example, within the region of the first section, the upper surface of the semiconductor body is covered by the auxiliary layer. The auxiliary layer may be deposited, for example, by chemical vapor deposition, abbreviated as CVD.

[0042] According to a further embodiment, after the deposition of the auxiliary layer, a directional material removal process is applied in which more of the auxiliary layer is removed on the region of the first section and the upper surface of the second section than on the side surfaces of at least one second section. The removal process may be an etching process, such as a dry etching process like a plasma etching process. The directional material removal process is also known as an anisotropic material removal process.

[0043] After the material removal process, the side surfaces of at least one second compartment are still covered at least by the remaining portions of the previously deposited auxiliary layer. However, here, the region of at least one first compartment having a reduced lateral extent and / or the upper surface of at least one second compartment may be exposed after the directional material removal process. The holes are formed, for example, after performing the directional material removal process. For example, the specified thickness of the auxiliary layer on the side surface relates to the thickness after the material removal process.

[0044] The same is disclosed for the auxiliary layer with respect to the conformal deposition process, and the subsequent directional material removal process may also be performed for additional auxiliary layers. The implantation of the second type of dopant is performed, for example, after the directional material removal process applied to the additional auxiliary layer.

[0045] According to at least one embodiment, the protective layer is deposited on the semiconductor body at least in the region of at least one first compartment before depositing the auxiliary layer and / or before depositing an additional auxiliary layer. The protective layer is configured to protect the semiconductor body when removing the (additional) auxiliary layer by the directional material removal process. For example, the protective layer is an etch stop layer that prevents the etchant from reaching the semiconductor body.

[0046] According to a further embodiment, before applying the mask, the semiconductor body is of the second conductivity type at least on the upper surface. For example, the entire upper surface is of the second conductivity type. In particular, the drift layer of the semiconductor body may be of the second conductivity type. The substrate may also be of the second conductivity type.

[0047] According to a further embodiment, during the implantation of the first type of dopant, at least one second section protects the underlying semiconductor body from the first type of dopant such that the semiconductor body remains of the second conductivity type at the upper surface within the region of the at least one second section. In other words, the amount of the first type of dopant reaching the semiconductor body in the region of the at least one second section is not sufficient to convert the conductivity type of the semiconductor body.

[0048] According to a further embodiment, the method further comprises forming an electrically insulating layer on the surface of the holes. The insulating layer is, for example, SiO2. The formation of the insulating layer may be performed by filling the holes with an electrically insulating material or by oxidizing the surface of the holes. The surface of the holes is in particular the side and / or bottom surface formed by the semiconductor body and defining the holes.

[0049] According to a further embodiment, the method further comprises forming a gate electrode over and / or in at least one of the holes such that the gate electrode is electrically insulated from the semiconductor body by the electrically insulating layer. The gate electrode may comprise or consist of at least one of a metal such as Cu, Al, Au, Ag or an alloy thereof, or highly doped polysilicon.

[0050] The formation of the electrically insulating layer and / or the gate electrode may be performed with the mask still on the upper surface of the semiconductor body.

[0051] According to a further embodiment, the method comprises removing the mask. During the removal of the mask, the auxiliary layer and / or a further auxiliary layer may be removed together with the initial mask.

[0052] According to a further embodiment, the method includes forming a main electrode on the top surface such that the main electrode is adjacent to and electrically connected to the semiconductor body in a region where the main electrode is adjacent to at least one hole in the lateral direction. In particular, this step is performed after removing the mask such that the main electrode is adjacent to the top surface of the semiconductor body in a region where at least one second section of the mask previously covered the top surface.

[0053] The main electrode is a metal such as, for example, Cu, Al, Au, Ag, or an alloy thereof. For example, the main electrode is electrically insulated from the gate electrode, for example by an electrically insulating layer. The main electrode may be adjacent to and in electrical contact with the contact region and the channel region. For example, an ohmic contact is formed between the main electrode and the contact region and / or the channel region.

[0054] According to a further embodiment, the main electrode is adjacent to at least one diode region of the semiconductor body on the top surface. The diode region is of a second conductivity type. For example, the diode region is a region of the semiconductor body that was previously covered and thus protected by at least one second section of the mask. The diode region may be formed by a drift layer. For example, the diode region and the main electrode together form a Schottky diode, which is also referred to as a JBS diode. Thereby, a Schottky contact is formed between the main electrode and the diode region.

[0055] In a first lateral direction, the contact region and the channel region may be arranged between the hole and the diode region. The diode region may be adjacent to the channel region in the first lateral direction.

[0056] According to a further embodiment, a further mask is deposited on the top surface of the semiconductor body before depositing the mask. The further mask may also include a photoresist and may be formed by lithography.

[0057] According to a further embodiment, at least one plug region of a first conductivity type is formed in the semiconductor body by using a further mask. Forming at least one plug region may also include implanting a dopant of a first type into the semiconductor body through the top surface. After implantation, an annealing process may be performed so that the plug region further spreads within the semiconductor body.

[0058] According to a further embodiment, at least one plug region is at least partially formed in a region adjacent to the top surface and then covered by at least one second section of the mask.

[0059] The plug region may also be disposed within the region of the first section of the mask to be subsequently deposited. For example, during implantation of a dopant of a second type, the plug region within the region of the first section of the mask is converted to a second conductivity type and thus becomes part of the contact region.

[0060] According to a further embodiment, the doping concentration within at least one plug region is greater than that within the channel region. When referring to the doping concentrations of different regions, in each case, the average or maximum doping concentration of the region is intended.

[0061] For example, at least one plug region has a doping concentration that is at least one order of magnitude greater than the doping concentration of the channel region. The doping concentration of the plug region is, for example, 10 18 cm -3 ~10 19 cm -3 . The doping concentration of the channel region is, for example, 10 16 cm -3 ~10 18 cm -3 .

[0062] The doping concentration of the contact region is, for example, at least one order of magnitude greater than, for example, the doping concentration of the drift layer and / or the diode region and / or the channel region. The doping concentration of the contact region is, for example, 1018 cm -3 ~10 19 cm -3 is. The doping concentration of the drift layer and / or the diode region is, for example, 10 15 cm -3 ~10 17 cm -3 is.

[0063] According to a further embodiment, the mask includes a plurality of strip-shaped first sections and a plurality of strip-shaped second sections. For example, the first section is formed between every two second sections. Similarly, the second section may be formed between every two first sections. For example, the first section and the second section are alternately arranged side by side in a first lateral direction.

[0064] The first section and the second section are strip-shaped, that is, elongated. For example, the second section is formed as a rib. The main extending directions of the first section and the second section may extend parallel to each other. For example, each of the first section and the second section extends in a second lateral direction perpendicular to the first lateral direction.

[0065] According to a further embodiment, channel regions and holes are formed in some or each region of the first section. Each channel region may be formed in a strip shape, and each hole may be formed as a trench. The strip-shaped channel regions and trenches may all extend in the second lateral direction. When forming the trench, each strip-shaped channel region is separated from each other in the first lateral direction and divided into two strip-shaped channel regions.

[0066] Similarly, strip-shaped contact regions may be formed in the region of each first section. The strip-shaped contact regions extend, for example, in the second lateral direction. When forming the trench, each strip-shaped contact region is separated from each other in the first lateral direction and divided into two strip-shaped contact regions.

[0067] All features disclosed so far and below regarding the formation of channel regions and / or contact regions and / or holes within the region of at least one first section are also disclosed for the formation of all other channel regions and / or contact regions and / or holes within the further first section of the mask.

[0068] According to a further embodiment, a plurality of plug regions are formed. All features disclosed in relation to at least one plug region are also disclosed for all other plug regions.

[0069] According to a further embodiment, each plug region is formed in a stripe shape, i.e., elongated.

[0070] According to a further embodiment, the plug region extends obliquely with respect to the channel region. For example, the plug region extends perpendicular to the channel region. The plug region may extend in a first lateral direction and may be spaced apart from each other in a second lateral direction. For example, all plug regions extend parallel to each other.

[0071] Next, a semiconductor device is described. The semiconductor device may be produced using the method according to any one of the embodiments disclosed herein. Thus, all features disclosed for the method are also disclosed for the semiconductor device, and vice versa.

[0072] According to one embodiment, a semiconductor device comprises a semiconductor body having an upper surface. At least one hole extends from the upper surface into the semiconductor body. The at least one hole defines an active region of the semiconductor body in a first lateral direction parallel to the upper surface. The active region includes at least one channel region of a first conductivity type and at least one contact region of a second conductivity type. The at least one channel region and the at least one contact region are adjacent to the at least one hole in the first lateral direction. The at least one contact region is embedded in the at least one channel region such that in a vertical direction perpendicular to the upper surface, the at least one contact region is disposed between the upper surface and the at least one channel region and the at least one contact region is adjacent to the upper surface in the vertical direction. The width of the active region measured in the first lateral direction is at most three times the depth of the at least one hole measured in the vertical direction.

[0073] An active region having such an aspect ratio (width / depth) can be generated using the methods described herein. For example, the width of the active region is at most twice the depth of the at least one hole or at most the depth of the at least one hole.

[0074] The active region of the semiconductor device is the region in which charge carriers are transported during operation. For example, the active region is formed between two holes and is defined by the two holes in the first lateral direction. The active region is, for example, a continuous region of the semiconductor body.

[0075] The semiconductor device can comprise several active regions that are laterally spaced apart from each other by one or more holes. All features disclosed for one active region are also disclosed for all other active regions.

[0076] According to a further embodiment, the width of the active region is at most 3 μm or at most 2.5 μm or at most 2 μm or at most 1.5 μm or at most 1 μm.

[0077] According to a further embodiment, the semiconductor device further comprises a main electrode on the upper surface within the active region.

[0078] According to a further embodiment, the active part includes at least a diode region, and the at least one diode region is of a second conductivity type. The at least one diode region may be adjacent to the upper surface of the semiconductor body in the vertical direction.

[0079] According to a further embodiment, the main electrode is adjacent to and in electrical contact with at least one contact region. Additionally, the main electrode may be adjacent to and in electrical contact with at least one diode region and / or at least one channel region.

[0080] According to a further embodiment, the surface of at least one hole is at least partially covered by an electrically insulating layer. The surface of the hole is formed by the semiconductor body. For example, the side and bottom surfaces of the hole are covered by the electrically insulating layer.

[0081] According to a further embodiment, a gate electrode is formed over and / or within at least one hole and is electrically insulated from the semiconductor body by an insulating layer.

[0082] According to a further embodiment, the active region includes at least one plug region, the at least one plug region is of a first conductivity type, and is adjacent to the upper surface. For example, the at least one plug region has a higher doping concentration than at least one channel region.

[0083] According to a further embodiment, the semiconductor device is a power semiconductor device. The semiconductor device is, for example, a MOSFET or an IGBT or a JFET or a MISFET. A further main electrode may be applied to the bottom surface of the semiconductor body, which is opposite to the upper surface. The power semiconductor device may be configured such that the voltage difference between the main electrode and the further main electrode is at least 1 kV, for example at least 1.2 kV or at least 3.3 kV.

[0084] In the case of a MISFET, JFET or MOSFET, the contact region is also referred to as the source region. In the case of an IGBT, the contact region is also referred to as the emitter region.

[0085] According to a further embodiment, the semiconductor device comprises a plurality of holes, each formed as a trench. The trenches are spaced apart from each other in a first lateral direction. Each trench extends in a second lateral direction. The first lateral direction and the second lateral direction are, for example, orthogonal to each other.

[0086] According to a further embodiment, the semiconductor device comprises a plurality of active regions, each active region being arranged between a pair of trenches. Thus, in the first lateral direction, one active region is formed between each pair of trenches.

[0087] According to a further embodiment, each active region includes at least two elongated channel regions, for example strip-shaped channel regions. The channel regions extend in the second lateral direction. Furthermore, each active region includes at least two elongated contact regions, for example strip-shaped contact regions. Each contact region extends in the second lateral direction. The contact regions may be spaced apart from each other in the first lateral direction. Similarly, the channel regions may be spaced apart from each other in the first lateral direction.

[0088] The lengths of the trenches, contact regions, and / or channel regions measured along the second lateral direction may all be the same.

[0089] According to a further embodiment, the channel region and the contact region of each active region are each adjacent to the trench defining the active region. Thus, in each active region, one contact region and one channel region are adjacent to the trench defining the active region on one side with respect to a first lateral direction, and a further channel region and a further contact region are adjacent to the trench defining the active region on the other side with respect to the first lateral direction.

[0090] According to a further embodiment, the width of the active region is the distance between two trenches defining the active region in a first lateral direction.

[0091] Hereinafter, based on exemplary embodiments, a method for generating a semiconductor device and a semiconductor device will be described in more detail with reference to the drawings. The accompanying drawings are included to provide a further understanding. In the drawings, elements having the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. The description of each of the following figures will not be repeated as long as the elements or components correspond to each other with respect to their functions in different figures. For clarity, elements may not be denoted by corresponding reference numerals in all figures.

Brief Description of the Drawings

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Figure 19

[0093] FIG. 1 shows a flowchart of a first exemplary embodiment of a method for generating a semiconductor device. In step S1, a semiconductor body having an upper surface is provided. Next, in a second step S2, a mask is deposited on the upper surface, the mask including at least one first section and at least one second section laterally adjacent to the at least one first section. The mask is thicker in at least one second section than in at least one first section. In step S3, at least one channel region of a first conductivity type is formed in the semiconductor body in the region of the at least one first section, forming the channel region including implanting a dopant of the first type into the semiconductor body through the upper surface. In step S4, an auxiliary layer is deposited on a side surface of the at least one second section facing the at least one first section, the auxiliary layer increasing a lateral extent of the at least one second section and decreasing a lateral extent of the at least one first section. In step S5, a hole is formed in the semiconductor body in the region of the at least one first section having a reduced lateral extent such that at least one hole extends from the upper surface through the channel region.

[0094] FIG. 2 shows a flowchart of a second exemplary embodiment of a method for generating a semiconductor device. Steps S1 to S5 are the same as those of the first exemplary embodiment. After step S1, step S6 of depositing an additional mask on the upper surface of the semiconductor body is performed. In step S7, at least one plug region of the first conductivity type is formed in the semiconductor body by using the additional mask. Subsequently, the additional mask is removed, and steps S2 and S3 are performed. After step S3 in which the channel region is formed, step S8 of depositing an additional auxiliary layer on the side surface of at least one second section of the mask to increase the lateral extent of at least one second section and decrease the lateral extent of at least one first section is performed. Thereafter, in step S9, a contact region of the second conductivity type is formed in the semiconductor body in the region of the first section such that the contact region is between the channel region and the upper surface of the semiconductor body. Forming the contact region includes implanting a dopant of the second type through the upper surface. The contact region is of the second conductivity type. Subsequently, steps S4 and S5 are performed. After step S5 in which holes are formed, in step S10, an electrically insulating layer is formed on the surface of at least one hole. Then, in step S11, a gate electrode is formed over and / or in at least one hole, and the gate electrode is electrically insulated from the semiconductor body by the electrically insulating layer. In step S12, the mask is removed, and in step S13, a main electrode is formed on the upper surface of the semiconductor body.

[0095] Here, FIGS. 3 to 18 show exemplary embodiments of a method for generating a semiconductor device based on various positions during the method. In this exemplary embodiment, the dopant of the first type is a p-type dopant, and thus, the first conductivity type is hole conduction. The dopant of the second type is an n-type dopant, and thus, the second conductivity type is electron conduction. However, the method can also be implemented with the dopant of the first type being an n-type dopant and the dopant of the second type being a p-type dopant.

[0096] In FIG. 3, a semiconductor body 1 is provided. The semiconductor body 1 is based on a wide bandgap material such as, for example, SiC. The semiconductor body 1 comprises an n-doped substrate 19 and an n-doped drift layer 18 on the substrate 19. The doping concentration in the substrate 19 is greater than the doping concentration in the drift layer 18. For example, in the drift layer 18, the doping concentration is 10 15 cm -3 ~10 17 cm -3 . The drift layer 18 forms the upper surface 10 of the semiconductor body 1.

[0097] FIG. 3 also shows a plurality of different directions used in this specification. In this specification, the lateral direction is defined as the direction parallel to the upper surface 10 or the main extension plane of the semiconductor body 1. In FIG. 3, a first lateral direction Q is perpendicular to the plane of the paper, and a second lateral direction L is parallel to the plane of the paper. The vertical direction V is the direction perpendicular to the upper surface 10 or the main extension plane and is also parallel to the plane of the paper in FIG. 3.

[0098] FIG. 4 shows the position in the method where a first mask 8, which is also referred to as a further mask 8 in this specification, is deposited on the upper surface 10 of the semiconductor body 1. The mask 8 comprises a first section 81 where the upper surface 10 is exposed and a second section 82 where the upper surface 10 is covered by a mask material. For example, the mask 8 is generated by using photolithography. The mask material of the first mask 8 may be a photoresist.

[0099] FIG. 5 shows the position where a first type of dopant, i.e., a p-type dopant such as boron, is implanted into the semiconductor body 1 through the upper surface 10. Thereby, a plug region 14 is generated within the region of the first section 81 of the first mask 8. Therefore, the plug region 14 is a p-doped region. Therefore, the amount of the p-type dopant implanted is very large so that the previously n-doped semiconductor material under the first section 81 of the first mask 8 is converted into a p-doped semiconductor material.

[0100] An amount of p-type dopant may reach through the second section 82 of the first mask 8 and may be received within the semiconductor body 1 below the second section 82. However, the shielding or protection by the second section 82 is efficient enough that the amount of p-type dopant reaching the semiconductor body 1 is not sufficient to convert the n-doped semiconductor material to p-doped material. As a result, the plug region 14 is formed only within the region of the first section 81 of the first mask 8. In the region of the second section 82, the semiconductor body 1 remains n-doped.

[0101] The formation of the plug region 14 can include an annealing process after or during the implantation process, such that the implanted p-type dopant further drifts within the semiconductor body 1, and as a result, the plug region 14 further expands. The doping concentration of the plug region 14 after annealing is, for example, 10 18 cm -3 ~10 19 cm -3 is.

[0102] In contrast to what is shown in FIG. 5, the plug region 14 may also be formed within a trench. For this purpose, a trench may be formed within the semiconductor body 1 in the region of the first section 81, and then a p-type dopant may be implanted within the semiconductor body 1 in the region of the trench. In this way, it is achieved that the plug region 14 extends deeper within the semiconductor body 1.

[0103] In FIG. 6, the semiconductor body 1 after removal of the first mask 8 is shown in a plan view with respect to the top surface 10. As can be seen here, the plug region 14 is an elongated stripe-shaped region each extending in a first lateral direction Q and spaced apart from each other in a second lateral direction L.

[0104] Figure 7 shows a further position of the method. Again, a plan view of the upper surface 10 of the semiconductor body 1 is shown. In Figure 7, a second mask 2, which is also simply referred to as mask 2 in this specification, is applied to the upper surface 10 of the semiconductor body 1. The second mask 2 comprises a first section 21 and a second section 22. In the first section 21, the upper surface 10 of the semiconductor body 1 is exposed. However, in the second section 22, the upper surface 10 is covered by a mask material. The second mask 2 may also be produced here by photolithography. The mask material may be a photoresist.

[0105] The first section 21 and the second section 22 are each an elongated stripe-shaped structure extending along the second lateral direction L. In the first lateral direction Q, the first section and the second section 22 are arranged alternately.

[0106] Figure 8 shows the semiconductor body 1 again in a sectional view, but here in a rotated view compared to Figures 3 to 5, with the second lateral direction L perpendicular to the plane of the paper and the first lateral direction Q parallel to the plane of the paper.

[0107] Figure 8 shows the positions where a first type of dopant, i.e., a p-type dopant, is implanted through the upper surface 10. In the first section 21, the semiconductor body 1 is not protected by the mask 2. For this reason, the amount of p-type dopant implanted into the semiconductor body 1 is greater in the region of the first section 21 than in the region of the second section 22. As a result, a channel region 11 is formed within the region of the first section 21. The channel region 11 has a first conductivity type, i.e., hole conduction or p-doped. In other words, the amount of p-type dopant implanted is sufficient to convert the previously n-doped semiconductor material in the region of the first section 21 into p-doped semiconductor material. In the region of the second section 22, the amount of p-type dopant implanted is not sufficient to change the doping type. The formation of the channel region 11 may also include an additional annealing process here.

[0108] FIG. 9 shows the position of the method in which a first auxiliary layer 4, also referred to herein as a further auxiliary layer, is deposited on the initial mask 2. Thereby, the first auxiliary layer 4 also covers the upper surface of the semiconductor body 1 in the region of the first section 21, the upper surface of the initial mask 2 in the region of the second section 22, and also the side surface 22a of the second section 22. The side surface 22a extends perpendicular to the upper surface 10 and is respectively formed by the step between the first section 21 and the second section 22 of the initial mask 2. To deposit the first auxiliary layer 4, a conformal or non-directional deposition process such as CVD is used. The first auxiliary layer 4 comprises or consists of, for example, SiN or SiO2.

[0109] FIG. 10 shows a further position of the method in which a directional material removal process such as dry etching is used to remove the material of the first auxiliary layer 4 within the region of the first section 21 and on the upper surface of the second section 22. The directional material removal process does not remove or does not completely remove the material of the first auxiliary layer 4 on the side surface 22a of the second section 22. As a result, at least a part of the first auxiliary layer 4 remains on the side surface 22a of the second section 22. Thus, the second section 22 effectively becomes wider, that is, their lateral extension range in the first lateral direction Q increases, and the first section 21 becomes less effective, that is, their lateral extension range in the first lateral direction Q decreases. The thickness of the remaining part of the first auxiliary layer 4 on the side surface 22a of the second section 22 is, for example, at least 100 nm and at most 1 μm. Thus, the width of each of the second sections 22 increases by twice this thickness, and the width of each of the first sections decreases by twice this thickness.

[0110] Before depositing the further auxiliary layer 4, a protective layer (not shown), for example an etch stop layer, may be deposited on the upper surface 10 of the semiconductor body 1. This protective layer can protect the semiconductor body 1 within the region of the first section from attack during the directional material removal process.

[0111] FIG. 11 shows the position of the method in which a second type of dopant, i.e., an n-type dopant, is implanted into the semiconductor body 1 through the upper surface 10. Thereby, the contact region 12 is formed within the region of the first section 21 with a reduced lateral extent. Compared with the embodiment of the first type of dopant for forming the channel region 11, due to the reduced lateral extent of the first section 21, the contact region 12 is narrower than the channel region 11, i.e., the lateral extent in the first lateral direction Q is smaller. Here too, the formation of the contact region 12 may further include an annealing step (not shown).

[0112] The contact region 12 is formed from a part of the previously formed channel region 11 and is of the second conductivity type, i.e., electron conduction or n-doped. Thus, the amount of n-type dopant implanted is sufficient to convert each part of the channel region 11 from p-doped to n-doped. For example, the doping concentration of the contact region 12 is 10 18 cm -3 ~10 19 cm -3 is.

[0113] As further seen in FIG. 11, the depth of the contact region 12 is smaller than the depth of the channel region 11, and the depth is measured in the vertical direction V. Thus, the contact region 12 is formed between the upper surface 10 and the channel region 11 in the vertical direction V.

[0114] FIG. 12 shows the position of the method in which a second auxiliary layer 3, also referred to herein simply as the auxiliary layer 3, is deposited on the upper surface 10 of the semiconductor body 1 by a conformal deposition method. The auxiliary layer 3 covers the upper surface 10 of the region of the first section 21, the upper surface of the second section 22, and the side surface 22a of the second section 22. The second auxiliary layer 3 may be of a different material from the first auxiliary layer 4. The second auxiliary layer 3 is formed, for example, from SiN or SiO2.

[0115] At the position shown in FIG. 13, a directional material removal process such as dry etching is used to remove the material of the second auxiliary layer 3 within the region of the first section 21 and on the upper surface of the second section 22. Due to the directional method, the remainder of the second auxiliary layer 3 remains on the side surface 22a of the second section 22, and as a result, the width of the second section 22 effectively increases here as well, and the width of the first section 21 effectively decreases here as well. The remaining thickness of the second auxiliary layer 3 on the side surface 22a may be within the same region as the first auxiliary layer 4.

[0116] At the position of FIG. 14, holes 5 in the form of trenches are etched into the semiconductor body 1 in the region of the first section 21 with a reduced width. The etchant used for etching is preferably selected such that the etching rate of the semiconductor material of the semiconductor body 1 is greater than the etching rates of the mask material and / or the material of the first auxiliary layer 4 and / or the material of the second auxiliary layer 3.

[0117] The trenches 5 extend from the upper surface 10 through the contact region 12 and the channel region 11 and are deeper than the channel region 11. Each of the trenches 5 divides the previously continuous contact region 12 and channel region 11 into two contact regions 12 and two channel regions 11 adjacent to the respective trenches 5 on both sides with respect to the first lateral direction Q. As an example, the depth of the etched trenches 5 is 1 μm or less.

[0118] FIG. 15 shows the position of the method in which an electrically insulating layer 51 is formed on the surface of the trenches 5. The electrically insulating layer 51 is formed, for example, by oxidizing the surface of the trenches 5. Additionally, a gate electrode 7 is formed within the trenches 5.

[0119] At the position of FIG. 16, the second mask 2 and the remaining auxiliary layers 3, 4 on the side surface 22a of the second section 22 are removed. As a result, in the region between the trenches 5, the upper surface 10 of the semiconductor body 1 is exposed. Between each pair of trenches 5, the upper surface 10 is partially formed by two contact regions 12, two channel regions 11, and a diode region 13. Thereby, the contact region 12 is embedded in the channel region 11. As a result, the contact region 12 and the channel region 11 are adjacent to the trench 5, but are electrically insulated from the gate electrode 7 in the trench 5 by the electrical insulation layer 51. The diode region 13 is formed by the drift layer 18 and is thus n-doped.

[0120] Due to the method described herein, there is only one lithography step necessary to generate the channel region 11, the contact region 12, and the trench 5. Such a self-alignment process enables the generation of very small structures. The distance between two adjacent trenches 5 measured in the first lateral direction Q is, for example, at most three times the depth of the trench 5. For example, the distance is at most 3 μm. The width of each of the contact regions 12 measured in the first lateral direction Q is, for example, at most 1 μm or at most 500 nm.

[0121] FIG. 17 shows the semiconductor body 1 of FIG. 16 in a perspective view so that the positions of the trenches 5, the contact regions 12, the channel regions 11, the diode regions 13, and the plug regions 14 relative to each other can be seen. The plug region 14 extends obliquely with respect to the trench 5 and is adjacent to the upper surface 10 of the region previously covered by the second section 22 of the mask 2.

[0122] At the position of FIG. 18, the first main electrode 6 is deposited on the upper surface 10 of the semiconductor body 1. The main electrode 6 is adjacent to the semiconductor body 1 in the region between the trenches 5 and is in direct contact with the contact region 12, the channel region 11, and the diode region 13. The first main electrode 6 is formed of, for example, a metal. This is electrically insulated from the gate electrode 7 by the electrical insulation layer 51.

[0123] FIG. 19 shows the final semiconductor device 100. The semiconductor device 100 is a power semiconductor device such as, for example, a power MOSFET. On the bottom surface opposite to the top surface 10 of the semiconductor body 1, a second main electrode 9 is deposited. The first main electrode 6 is a source electrode, and the second main electrode 9 is a drain electrode.

[0124] The plug region 14 is used, for example, to make electrical contact with the channel region 11. Due to the high doping concentration of the plug region 14, an ohmic contact can be formed between the plug region 14 and the first main electrode 6. On the other hand, the plug region 14 is electrically connected to the channel region 11, and as a result, at the end, the channel region 11 is electrically well connected to the first main electrode 6.

[0125] During operation, a voltage difference greater than, for example, 1 kV is applied between the first main electrode 6 and the second main electrode 9. In the forward operation of the MOSFET, the current flowing between the main electrodes 6 and 9 is controlled by the gate electrode 7. In the conduction mode, electrons are injected from the first main electrode 6 into the contact region 12. From there, the electrons pass through the channel region 11, travel along the trench 5, enter the drift layer 18, and flow from there to the second main electrode 9. The diode region 13, together with the first main electrode 6, forms a Schottky diode that blocks in the conduction mode.

[0126] Therefore, the flow of charge carriers mainly occurs in the region between the trenches 5, and for this reason, this region is called the active region A in this specification. By the method described in this specification, a very small structure of the active region A can be generated.

[0127] The embodiments shown in FIGS. 1 to 19 above represent an improved method for generating a semiconductor device and exemplary embodiments of a semiconductor device. Accordingly, they do not constitute a complete list of all embodiments by the improved method and the improved semiconductor device. The actual method and device may differ from the embodiments shown with respect to elements, the order of method steps, etc.

Description of Reference Numerals

[0128] Reference numeral 1 Semiconductor body 2 (Second) mask 3 (Second) auxiliary layer 4 First / further auxiliary layer 5 Hole 6 (First) main electrode 7 Gate electrode 8 First mask / further mask 9 Second main electrode 10 Upper surface 11 Channel region 12 Contact region 13 Diode region 14 Plug region 18 Drift layer 19 Substrate 21 First compartment 22 Second compartment 22a Side surface of the second compartment 22 51 Electric insulation layer 81 First compartment of mask 8 82 Second compartment of mask 8 100 Semiconductor device Si Method step Q First lateral direction L Second lateral direction V Vertical direction

Claims

1. A semiconductor device (100), comprising: a semiconductor body (1) having an upper surface (10); at least one hole (5) extending from the upper surface (10) into the semiconductor body (1); the at least one hole (5) defining an active region (A) of the semiconductor body (1) in a first lateral direction (Q); the active region (A) including at least one channel region (11) of a first conductivity type and at least one contact region (12) of a second conductivity type; the at least one channel region (11) and the at least one contact region (12) being adjacent to the at least one hole (5) in the first lateral direction (Q); the at least one contact region (12) being embedded in the at least one channel region (11) such that the at least one contact region (12) is disposed between the upper surface (10) and the at least one channel region (11) in a vertical direction (V) perpendicular to the upper surface (10) and such that the at least one contact region (12) is adjacent to the upper surface (10); a width of the active region (17) measured in the first lateral direction (Q) being at most three times a depth of the at least one hole (5) measured in the vertical direction (V); the active region (A) being of the first conductivity type and comprising at least one plug region (14) adjacent to the upper surface (10); the at least one plug region (14) having a higher doping concentration than the at least one channel region (11), the semiconductor device (100).

2. comprising channel regions (11) formed in several stripes, several trench-forming holes (5), and plug regions (14) formed in several stripes, the plug regions (14) extending obliquely with respect to the channel regions (11), the semiconductor device (100) according to claim 1.

3. a width of the active region (A) being at most 3 μm, the semiconductor device (100) according to claim 1 or 2.

4. further comprising a main electrode (6) on the upper surface (10) within the active region (A), the active region (A) including at least one diode region (13) of the second conductivity type, the at least one diode region (13) being adjacent to the upper surface (10), The main electrode (6) is adjacent to and in electrical contact with the at least one contact region (12) and the at least one diode region (13). The semiconductor device (100) according to any one of the preceding claims. **Claim 5** The surface of the at least one hole (5) is at least partially covered by an electrically insulating layer (51). A gate electrode (7) is formed on and / or in the at least one hole (5) and is electrically insulated from the semiconductor body (1) by the insulating layer (51). The semiconductor device (100) according to any one of the preceding claims. **Claim 6** The semiconductor device (100) is a power semiconductor device. The semiconductor device (100) comprises a plurality of holes (5) each formed as a trench, the trenches (5) being spaced apart from each other in the first lateral direction (Q), and each trench (5) extending in a second lateral direction (L). The semiconductor device (100) comprises a plurality of active regions (A) each disposed between a pair of trenches (5). Each active region (A) includes at least two elongated channel regions (11) extending in the second lateral direction (L) and at least two elongated contact regions (12) extending in the second lateral direction (L). The channel region (11) and the contact region (12) of each active region (A) are each adjacent to the trench (5) defining the active region (A). The width of the active region (A) is the distance between the two trenches (5) defining the active region (A) in the first lateral direction (Q). The semiconductor device (100) according to any one of the preceding claims. **Claim 7** A method for generating a semiconductor device, comprising: providing a semiconductor body (1) having an upper surface (10); applying a mask (2) to the upper surface (10), wherein the mask (2) comprises at least one first section (21) and at least one second section (22) laterally adjacent to the at least one first section (21), and applying the mask (2) which is thicker in the at least one second section (22) than in the at least one first section (21). Forming a channel region (11) of a first conductivity type in the semiconductor body (1) in the region of the at least one first section (21), forming the channel region (11), which includes implanting a dopant of a first type into the semiconductor body (1) through the top surface (10), depositing an auxiliary layer (3) on a side surface (22a) of the at least one second section (22) facing the at least one first section (21), the auxiliary layer (3) increasing a lateral extent of the at least one second section (22) and decreasing a lateral extent of the at least one first section (21), generating a hole (5) in the semiconductor body (1) in the region of the at least one first section (21) with a reduced lateral extent such that the hole (5) extends from the top surface (10) through the channel region (11), comprising, before depositing the mask (2), a further mask (8) is deposited on the top surface (10) of the semiconductor body (1), at least one plug region (14) of the first conductivity type is formed in the semiconductor body (1) by using the further mask (8), the at least one plug region (14) is adjacent to the top surface (10), is at least partially formed in a region of the top surface (10) that is subsequently covered by the at least one second section (22) of the mask (2), and a doping concentration in the at least one plug region (14) is greater than a doping concentration in the channel region (11). Method.

8. After forming the channel region (11) and before depositing the auxiliary layer (3), a further auxiliary layer (4) is deposited on the side surface (22a) of the at least one second section (22), the further auxiliary layer (4) increasing a lateral extent of the at least one second section (22) and decreasing a lateral extent of the at least one first section (21). After depositing the further auxiliary layer (4) and before depositing the auxiliary layer (3), a contact region (12) of a second conductivity type is formed in the semiconductor body (1) in the region of the first section (21), such that the contact region (12) is between the channel region (11) and the upper surface (10), and the formation of the contact region (12) includes implanting a dopant of a second type into the semiconductor body (1) through the upper surface (10). The hole (5) is formed through the contact region (12). The method according to claim 7.

9. The auxiliary layer (3) is deposited by a conformal deposition process such that the side surface (22a) of the at least one second section (22), the upper surface of the at least one second section (22), and the region of the first section (21) are covered by the auxiliary layer (3). Subsequently, a directional material removal process is applied in which more of the auxiliary layer (3) is removed on the region of the first section (21) and the upper surface of the second section (22) than on the side surface (22a) of the second section (22). The method according to claim 7 or 8.

10. Before applying the mask (2), the semiconductor body (1) is of the second conductivity type at least on the upper surface (10). During implantation of the dopant of the first type, the at least one second section (22) protects the semiconductor body (1) below from the dopant of the first type such that the semiconductor body (1) remains of the second conductivity type on the upper surface (10) within the region of the at least one second section (22). The method according to any one of claims 7 to 9.

11. Forming an electrically insulating layer (51) on the surface of the hole (5); Forming the gate electrode (7) on and / or in the at least one hole (5) such that the gate electrode (7) is electrically insulated from the semiconductor body (1) by the electrically insulating layer (51); Removing the mask (2); Forming a main electrode (6) on the upper surface (10) such that the main electrode (6) is electrically connected adjacent to the semiconductor body (1) in the region laterally adjacent to the at least one hole (5). The method according to any one of claims 7 to 10.

12. The main electrode (6) is adjacent to at least one diode region (13) of the semiconductor body (1) of the second conductivity type on the upper surface (10). The method according to claim 11, which depends on claim 10. Claim 13 The mask (2) comprises a plurality of strip-shaped first sections (21) and a plurality of strip-shaped second sections (22). A channel region (11) and a hole (5) are formed in the region of some of the first sections (21), each channel region (11) is formed in a strip shape, and each hole (5) is formed as a trench. The method according to any one of claims 7 to 12. Claim 14 A plurality of plug regions (14) are formed. Each plug region (14) is formed in a strip shape. The plug region (14) extends obliquely with respect to the channel region (11). The method according to claim 13.

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