Encoded Data Dependency Matrix for Power Efficiency Scheduling

Abstract

The disclosed system may include a processor configured to encode dependencies indicating that child instructions represented in a dependency matrix depend on parent instructions represented in the dependency matrix, using an encoding scheme that reduces the number of bits required to represent one or more instructions from a set of instructions in an instruction buffer represented by the dependency matrix. The processor may be configured to store the encoded dependencies in the dependency matrix and dispatch instructions into the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

Description

Background Art

[0001] A computing device may include a processor for executing instructions from program code such as firmware, an operating system, an application, etc. The processor may read instructions from the program code as macro instructions. To execute a macro instruction, the processor may first decode each macro instruction into micro-operations (μops or uops) that can form processor-level operations for the macro instruction. For example, an ADD macro instruction may be decoded into micro-operations that can cause the processor to execute specific parts of an ADD operation such as data acquisition / loading, addition of data, storage of the addition result, etc. The processor may execute each micro-operation to execute the corresponding macro instruction.

[0002] The processor may execute micro-operations in order (e.g., in the order based on the decoding of macro instructions), but some processors may improve processing efficiency by executing micro-operations out of order. Executing micro-operations out of order can reduce the latency associated with waiting for a particular micro-operation (which may be waiting for a particular resource) by executing different micro-operations instead of waiting. For example, the processor may execute a ready micro-operation (e.g., a micro-operation waiting for no resources) before an old micro-operation that may not be ready.

[0003] The processor may include a scheduler that facilitates scheduling of which micro-operations are dispatched (e.g., sent to execution units within the processor for execution). The decoded micro-operations may be transferred to the scheduler to be queued in a buffer. When an execution unit is available for executing a micro-operation, the scheduler can select a ready micro-operation for transmission to the available execution unit.

[0004] Micro-operations can depend on other micro-operations with respect to resources. In the example of ADD, an additional micro-operation (e.g., a consumer operation in this example) can depend on a previous load / store micro-operation (e.g., a producer operation in this example) to complete the loading of the data to be added to a register (e.g., fast local storage on a processor). In other words, the consumer operation may be ready when all of its producer operations are complete. To facilitate the determination of whether the dependencies of micro-operations are resolved, the scheduler can use a dependency matrix to track which micro-operations depend on which other micro-operations. The dependency matrix can track which micro-operations in the scheduler's buffer depend on which other micro-operations in the scheduler's buffer.

[0005] The accompanying drawings, which are a part of this specification, illustrate several exemplary embodiments. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

[0006]

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Best Mode for Carrying Out the Invention

[0007] Throughout the drawings, the same reference numerals and descriptions, while not necessarily being the same, indicate similar elements. The exemplary embodiments described herein are capable of various modifications and alternative forms, but specific embodiments are shown by way of example in the drawings and are described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the specific forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternative forms falling within the scope of the appended claims.

[0008] As will be described in more detail below, the present disclosure describes a system and method for encoding a dependency matrix for more efficient scheduling of processor instructions. In one example, a method for encoding a dependency matrix may include using an encoding scheme to encode a dependency indicating that a newly allocated instruction in an instruction buffer represented by the dependency matrix depends on another instruction in the instruction buffer. The method may also include storing the encoded dependency in the dependency matrix. The method may further include dispatching an instruction into the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instruction. Dispatching may further be based on identifying the readiness of each of the decoded dependencies.

[0009] In one example, a method for encoding a dependency matrix may include using an encoding scheme to encode a first dependency indicating that a first instruction represented in the dependency matrix depends on a second instruction represented in the dependency matrix. The method may also include storing the encoded first dependency in the dependency matrix. The method may further include dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix for the first instruction. In some examples, dispatching may further be based on identifying the readiness of each of the decoded dependencies.

[0010] In some examples, the encoding scheme may correspond to a partial encoding scheme that divides a set of instructions represented by a dependency matrix into groups and represents the source instructions of the dependencies using a group value that may correspond to the group containing the source instruction and an index value that may correspond to the source instruction within the group. In some examples, decoding the dependencies may include using the group value to identify the group containing the source instruction and using the index value to identify which instruction within the identified group corresponds to the source instruction.

[0011] In some examples, the encoding scheme may correspond to a full encoding scheme that represents the source instructions of the dependencies using a location value that may correspond to the index location of the source instruction in the dependency matrix. In some examples, decoding the dependencies may include using the location value to identify the source instruction.

[0012] In some examples, the method may include encoding a second dependency that may indicate that a newly allocated instruction in the instruction buffer depends on two instructions represented in the dependency matrix. In some examples, the method may include encoding a second dependency that may indicate that a first instruction depends on a third instruction represented in the dependency matrix. The method may further include storing the encoded second dependency in the dependency matrix. The second dependency may be encoded using a second encoding scheme different from the encoding scheme. In some examples, the encoding scheme may include a special value indicating no dependency.

[0013] In one example, a method for encoding a dependency matrix may include storing a newly allocated instruction in a buffer for queuing instructions. The newly allocated instruction may depend on another instruction in the buffer. The method may also include encoding a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix, using an encoding scheme that reduces the number of bits required to represent one or more instructions from a set of instructions in the buffer. The method may further include storing the encoded dependency in the dependency matrix. Additionally, the method may include dispatching an instruction into an instruction buffer, at least based on decoding one or more dependencies stored in the dependency matrix for the instruction. Dispatching may further be based on identifying the readiness of each of the decoded dependencies. In some examples, an index location within the dependency matrix may correspond to a buffer location within the buffer.

[0014] In one example, a method for encoding a dependency matrix may include storing a first instruction in a buffer for queuing instructions. The first instruction may depend on a second instruction in the buffer. The method may also include encoding a first dependency indicating that the first instruction depends on the second instruction, using an encoding scheme that reduces the number of bits required to represent one or more instructions from a set of instructions in the buffer. The method may further include storing the encoded first dependency in the dependency matrix. Additionally, the method may further include dispatching the first instruction, at least based on decoding one or more dependencies stored in the dependency matrix for the first instruction. In some examples, dispatching may further be based on identifying the readiness of each of the decoded dependencies. In some examples, an index location within the dependency matrix may correspond to a buffer location within the buffer.

[0015] In some examples, the encoding scheme may correspond to a partial encoding scheme that divides a set of instructions into groups and represents a source instruction with a dependency using a group value corresponding to the group containing the source instruction and an index value corresponding to the source instruction within the group. In some examples, decoding a dependency may include using the group value to identify the group containing the source instruction and using the index value to identify which instruction within the identified group corresponds to the source instruction.

[0016] In some examples, the encoding scheme may correspond to a full encoding scheme that represents a source instruction with a dependency using a location value corresponding to the buffer location of the source instruction in a buffer. In some examples, decoding a dependency may include using the location value to identify the source instruction.

[0017] In one example, a system for encoding a dependency matrix may include physical memory and at least one physical processor. The physical processor may include a buffer for queuing instructions, a dependency matrix for tracking dependencies between instructions in the buffer, and a control circuit for identifying instructions in the buffer that are ready using the dependency matrix. In some examples, the control circuit may be configured to encode dependencies indicating that a new instruction allocated and / or written to the buffer depends on another instruction indicated by the dependency matrix in the buffer using an encoding scheme that reduces the number of bits required to represent one or more instructions from a set of instructions in the buffer. Also, the control circuit may be configured to store dependencies encoded in the dependency matrix at an index location corresponding to the buffer location of a first instruction in the buffer. The control circuit may be further configured to dispatch instructions into the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions.

[0018] In one example, a system for encoding a dependency matrix may include physical memory and at least one physical processor. The physical processor may include a buffer for queuing instructions, a dependency matrix for tracking dependencies between instructions in the buffer, and a control circuit for identifying instructions in the buffer that are ready using the dependency matrix. In some examples, the control circuit may be configured to encode a first dependency indicating that a first instruction in the buffer depends on a second instruction in the buffer using an encoding scheme that reduces the number of bits required to represent one or more instructions from a set of instructions in the buffer. Also, the control circuit may be configured to store the first dependency encoded in the dependency matrix at an index location corresponding to the buffer location of the first instruction in the buffer. The control circuit may be further configured to dispatch the first instruction based at least on decoding one or more dependencies stored in the dependency matrix for the first instruction. In some examples, dispatching may be further based on identifying the readiness of each of the decoded dependencies.

[0019] Any of the features of the above-described embodiments can be used in combination with each other according to the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and the claims.

[0020] This disclosure generally relates to an encoded dependency matrix. Increasing the size of a scheduler's buffer can provide certain performance benefits, but the corresponding dependency matrix can increase in size accordingly. Since the dependency matrix can be implemented using physical circuitry, there can be additional considerations such as power, heat, and area on the die for larger dependency matrices. As will be described in more detail below, embodiments of this disclosure can encode dependencies using an encoding scheme. A dependency can indicate that a child instruction represented in a dependency matrix depends on a parent instruction represented in the dependency matrix. The encoding scheme can reduce the number of bits required to represent one or more instructions from a set of instructions represented by the dependency matrix. The encoded dependencies can be stored in the dependency matrix. To determine whether an instruction is ready for dispatch, embodiments of this disclosure can decode one or more dependencies stored in the dependency matrix for a given instruction and identify the readiness of each of the decoded dependencies.

[0021] Features from any of the embodiments described herein can be used in combination with one another according to the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and the claims.

[0022] In the following, with reference to FIGS. 1-5, a detailed description of various embodiments of an encoding scheme for a dependency matrix is provided. A detailed description of an exemplary system for encoding a dependency matrix is provided in connection with FIG. 1. A detailed description of various encoding schemes for a dependency matrix, including descriptions of a partial encoding scheme (e.g., FIG. 3) and a complete encoding scheme (e.g., FIG. 4), is provided in connection with FIGS. 2-4. A detailed description of an exemplary method for encoding a dependency matrix is provided in connection with FIG. 5.

[0023] FIG. 1 is a block diagram of an exemplary system 100 of an encoded dependency matrix. System 100 may correspond to a computing device such as a desktop computer, laptop computer, server, tablet device, mobile device, smartphone, wearable device, augmented reality device, virtual reality device, network device, and / or an electronic device. As shown in FIG. 1, system 100 includes one or more memory devices such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drive (HDD), Solid-State Drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, and / or any other suitable storage memory.

[0024] As shown in FIG. 1, an exemplary system 100 includes one or more physical processors such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 may access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) that implement soft-core processors, application-specific integrated circuits (ASICs), systems on chip (SoCs), one or more portions of these, one or more variations or combinations of these, and / or any other suitable physical processor, but are not limited thereto.

[0025] In some embodiments, the term "instructions" may refer to computer code that can be read and executed by a processor. Examples of instructions may include macro instructions (e.g., program code that may require a processor to decode into processor instructions that the processor can directly execute) and micro-operations (e.g., low-level processor instructions that are decoded from macro instructions and form part of the macro instructions), but are not limited thereto.

[0026] As further shown in FIG. 1, the processor 110 includes a control circuit 112, a buffer 114, and a dependency matrix 116. The control circuit 112 may correspond to a scheduler and include circuits and / or instructions for scheduling instructions for dispatch. The buffer 114 may correspond to local storage of the processor 110 that queues instructions prior to dispatch and may have a buffer size N (e.g., the buffer 114 may queue up to N instructions). The dependency matrix 116 may correspond to a dependency matrix that tracks which instructions in the buffer 114 depend on which other instructions in the buffer 114.

[0027] In some examples, the processor 110 (and / or its functional units) can read program instructions from the memory 120 and decode the read program instructions into micro-operations. The processor 110 (and / or its functional units) can transfer the newly decoded micro-operations to the control circuit 112. The control circuit 112 can store the decoded micro-operations in the buffer 114 and update the dependency matrix 116 to reflect the newly queued micro-operations and dependencies. When an execution unit of the processor 110 is available to execute a micro-operation (which in some examples can be broadcast in an N-wide format indicating the updated status of N instructions in the buffer 114), the control circuit 112 can select the micro-operation prepared from the buffer 114 and dispatch it to the available execution unit. To determine whether a micro-operation in the buffer 114 is ready, the control circuit 112 can identify the dependencies of the micro-operation and access the dependency matrix 116 to determine whether these dependencies have been resolved (e.g., whether the corresponding micro-operation has completed). If the dependencies are resolved, the control circuit 112 can select the micro-operation for dispatch and update the buffer 114 and the dependency matrix 116 accordingly (e.g., by removing or otherwise flushing the associated entry).

[0028] FIG. 2 shows a dependency matrix 200 (which may correspond to dependency matrix 116) that tracks dependencies between instructions. An instruction (e.g., a consumer) may depend on a second instruction (e.g., a producer) if the instruction uses a value that is not known until the second instruction completes. For example, an instruction may perform an operation on the result of a second instruction. More specifically, an instruction may perform an operation using a value in a register updated by a second instruction. Since a consumer depends on the value from its producer, the consumer may not be ready to be dispatched until its producer has finished execution. Thus, the dependency matrix 200 can track dependencies between instructions and facilitate tracking when an instruction is ready.

[0029] The dependency matrix 200 can track dependencies between instructions stored in a buffer (e.g., buffer 114) or other similar queue structures that can queue instructions for out-of-order execution as described herein. In some examples, the dependency matrix 200 can follow the indexing of the buffer. For example, row 1 of the dependency matrix 200 may refer to instruction 1 in the buffer. Thus, the number of rows of the dependency matrix 200 may correspond to the size of the buffer.

[0030] In FIG. 2, each column of the dependency matrix 200 can also correspond to each instruction in the buffer following the same indexing. Thus, each row of the dependency matrix 200 can indicate the dependencies of the corresponding instruction (e.g., a consumer) by marking the appropriate column (e.g., a producer). For example, in FIG. 2, row 1 has marks in columns 5 and 8 to indicate that instruction 1 (in the buffer) depends on instructions 5 and 8. As seen in FIG. 2, an instruction can depend on any number of other instructions, such as 0, 1, 2, 3, etc.

[0031] In some examples, the dependency matrix 200 can be implemented using a physical circuit that can maintain the value of each matrix element (e.g., a bit based on a stored charge). FIG. 2 shows a dependency matrix 200 for a buffer size N of eight instructions. Due to the one-to-one correspondence between rows and the buffer size, and between columns and the buffer size, the dependency matrix 200 can have an N×N size (e.g., 8×8). As the buffer size increases, the dependency matrix 200 can increase quadratically or exponentially accordingly. Since the dependency matrix 200 can be implemented in a circuit, the size of the dependency matrix 200 can become prohibitively large considering the area required for the dependency matrix 200 within the processor, the timing required to update the dependency matrix 200, and the power consumption and heat dissipation required to operate the dependency matrix 200.

[0032] The present disclosure provides various encoding schemes that can reduce the size of the dependency matrix. As described above, the dependency matrix can have an N×N size for N instructions. Instructions typically depend on at most a few other instructions (e.g., often three or less and may be less than N) such that each row in the dependency matrix can be mostly empty. Thus, the dependency matrix may be a sparse matrix and may be suitable for efficient encoding or other similar compression. To maintain the one-to-one relationship with the instruction buffer, the number of rows in the dependency matrix can remain unchanged. Thus, reducing the size of the dependency matrix can include reducing the number of columns according to the partial and / or full encoding schemes described herein. Further, although the present disclosure refers to rows and columns of the dependency matrix, in other examples, the matrix dimensions can be swapped (e.g., reducing the number of rows while maintaining the number of columns, referring to instructions using columns instead of rows, etc.).

[0033] FIG. 3 shows a dependency matrix 300 that can correspond to the dependency matrix 116 using a partial encoding scheme. Similar to the dependency matrix 200, the dependency matrix 300 can include the number of rows (e.g., 8) corresponding to the number of instructions that can be stored in the buffer. The entire set of instructions can be divided into groups that can be identified via a group value 310. Within each group, a particular instruction can be identified via an index value 320.

[0034] For example, in FIG. 3, eight instructions can be divided into two groups (e.g., "rows 1-4" and "rows 5-8"). The group value 310 can identify a particular group based on bits corresponding to each group (e.g., the first bit for "rows 1-4" and the second bit for "rows 5-8"), or can identify a particular group based on an identification value (e.g., using a predetermined number of bits to store a binary number or vector, where each group is associated with a different numerical value). The index value 320 can identify a particular instruction within a group, for example, by using bits corresponding to each index position, although in other examples, this index value can also use an encoded value.

[0035] As shown in FIG. 3, instruction 1 (e.g., row 1) can have two dependencies. The first dependency can correspond to an instruction from "rows 5-8" as indicated by the first group value 310. The first index value 320 indicates the first instruction from the group that is row 5. The second dependency identifies row 8 (e.g., the fourth instruction within "rows 5-8"). Thus, instruction 1 depends on instruction 5 and instruction 8.

[0036] In some examples, a special value or default value can indicate no dependencies. For example, row 5 can use a default value for the group value 310 (e.g., default to "rows 5 - 8") and a special value for the index value 320 (e.g., a blank value). In other examples, other special values can be used, such as a value where all bits are empty, a value where all bits are filled, etc.

[0037] Figure 3 shows a simple example of eight instructions divided into two groups to illustrate the partial decoding scheme. The specific example shown in Figure 3 may not necessarily reduce the number of columns from the number of columns in the dependency matrix 200, but the number of columns can be further reduced by increasing the number of groups. Additionally, the reduction in columns can become more significant as the number of instructions increases. For example, in the case of a buffer that can hold 100 instructions, when using the scheme shown in Figure 2, a 100×100 dependency matrix may be required. However, dividing the instructions into four groups of 25 instructions can use 4 bits for the group value 310 (e.g., 1 bit per group) and 25 bits for the index value 320 (e.g., 1 bit per instruction within the group) so that each dependency can be encoded in 29 bits. If there are two dependencies, the dependency matrix size can be 100×58. The matrix size can be further adjusted by adjusting the number of groups and by further encoding the group value 310 and / or the index value 320.

[0038] Figure 4 shows a dependency matrix 400 (which may correspond to the dependency matrix 116) using the full encoding scheme. Similar to the dependency matrix 200 and the dependency matrix 300, the dependency matrix 400 can include the number of rows (e.g., 8) corresponding to the number of instructions that can be stored in the buffer. Each instruction can be identified by encoding its index or buffer location within the buffer into the location value 410.

[0039] For example, in FIG. 4, each dependency can be stored in a vector or a series of bits that can include, for example, a binary number that can uniquely identify each instruction in the buffer. Row 1 (e.g., instruction 1) depends on rows 5 and 8, as indicated by the corresponding location value 410. As seen in FIG. 4, the dependencies may not be indicated by a special value.

[0040] FIG. 4 shows a simple example of eight instructions to illustrate the full decoding scheme. The number of columns can be reduced from the number of columns of the dependency matrix 200 (and in some examples, the dependency matrix 300) if the number of bits required for the two location values 410 is less than the total number of instructions. Additionally, the column reduction can become more pronounced as the number of instructions increases. For example, in the case of a buffer that can hold 100 instructions and using the scheme shown in FIG. 2, a 100×100 dependency matrix may be required. However, encoding 100 index locations may require at least a 7-bit vector (e.g., 2^7 = 128 to guarantee a unique value for each index location). If there are two dependencies, the dependency matrix size can be 100×14.

[0041] Furthermore, in some examples, a hybrid encoding scheme can be used, in which a partial encoding scheme can incorporate aspects of the full encoding scheme and / or vice versa. In still other examples, some dependency entries (e.g., the first dependency) can be encoded in one encoding scheme and other dependency entries (e.g., the second dependency) can be encoded in a different encoding scheme.

[0042] FIG. 5 is a flowchart of an exemplary computer-executable method 500 for encoding a dependency matrix. The steps shown in FIG. 5 can be executed by any suitable computer-executable code and / or computing system, including the system shown in FIG. 1. In one example, each of the steps shown in FIG. 5 can represent an algorithm whose structure includes a plurality of sub-steps and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0043] As shown in FIG. 5, at step 502, one or more of the systems described herein can encode a first dependency indicating that a first instruction represented in the dependency matrix depends on a second instruction represented in the dependency matrix using an encoding scheme that reduces the number of bits required to represent one or more instructions from the set of instructions represented by the dependency matrix. For example, the control circuit 112 can encode the first dependency using the encoding scheme described herein.

[0044] The systems described herein can execute step 502 in various ways. In one example, the control circuit 112 can store the newly received instruction in the buffer 114 and then determine that this instruction depends on at least a second instruction (e.g., a source instruction) within the buffer 114. The control circuit 112 can then encode this dependency using, for example, the partial encoding scheme (see FIG. 3) and / or the complete encoding scheme (see FIG. 4) described herein.

[0045] As described herein, a partial encoding scheme can include dividing a set of instructions into groups and representing source instructions of dependencies using group values and index values. The group value can correspond to the group containing the source instruction, and the index value can correspond to the source instruction within the group. As described herein, a full encoding scheme can include representing source instructions of dependencies using location values that can correspond to the index locations of the source instructions within a dependency matrix.

[0046] In some examples, a first instruction can depend on a third instruction in buffer 114 such that the first instruction can depend on two instructions (e.g., a second instruction and a third instruction). Control circuit 112 can encode a second dependency of the instructions using the same or a different encoding scheme as that used to encode the first dependency. For example, as shown in FIGS. 3 and 4, row 1 (e.g., instruction 1) depends on rows 5 and 8. In some examples, the second dependency can be an update and / or a portion of the first dependency.

[0047] Returning to method 500, at step 504, one or more of the systems described herein can store the encoded first dependency in a dependency matrix. For example, control circuit 112 can store the encoded first dependency in dependency matrix 116.

[0048] The systems described herein can perform step 504 in various ways. In one example, control circuit 112 can store the encoded first dependency in dependency matrix 116 as part of the final step of encoding. In some examples, control circuit 112 can also store the encoded second dependency in dependency matrix 116. In such examples, control circuit 112 stores both dependencies in dependency matrix 116 as part of a process for encoding and / or storing all dependencies for an instruction.

[0049] In step 506, one or more of the systems described herein may dispatch a first instruction based at least on decoding one or more dependencies stored in a dependency matrix for the first instruction. For example, control circuit 112 may dispatch the first instruction based on decoding the dependencies within dependency matrix 116.

[0050] The systems described herein may perform step 506 in various ways. In some examples, control circuit 112 may dispatch the first instruction based on identifying the readiness of each of the decoded dependencies. The decoded dependencies may be ready, for example, when the corresponding instruction has completed loading data into an appropriate register. In some examples, control circuit 112 may decode the encoded dependencies in a partial encoding scheme by using a group value to identify a group that includes a source instruction and an index value to identify which instruction within the identified group corresponds to the source instruction. In some examples, control circuit 112 may decode the encoded dependencies in a full encoding scheme by using a location value to identify the source instruction within buffer 114.

[0051] The systems and methods described herein provide an encoding scheme that can reduce the size of a dependency matrix associated with a processor's instruction buffer. Reducing the size of the dependency matrix can reduce the area, as well as the storage and wiring to storage that may be required to implement the dependency matrix. In some examples, the reduced-size dependency matrix may be able to increase the size of the instruction buffer without using up the available space within the processor. Additionally, the encoding scheme may be selected based on timing considerations. Certain operations may broadcast a signal to wake up child operations upon completion. In some examples, a child operation may not necessarily wake up a grandchild operation. A full encoding scheme may be suitable for such examples. In other examples, operations (e.g., address generation operations, memory operations, etc.) may not require a broadcast to wake up child operations. Timing may be important in such examples such that a partial encoding scheme may be more appropriate. Additionally, the encoding scheme may be applicable to other matrices that a processor may implement, particularly sparse matrices.

[0052] As described above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those included within the modules described herein. In their most basic configuration, each of these computing devices may include at least one memory device and at least one physical processor.

[0053] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile memory device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device may store, load, and / or maintain one or more of the modules described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, or any other suitable storage memory.

[0054] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor may access and / or modify one or more of the modules stored in the memory device described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs) that implement softcore processors, application specific integrated circuits (ASICs), system on chips (SoCs), one or more portions of these, one or more variations or combinations thereof, or any other suitable physical processor.

[0055] Additionally, one or more of the elements described herein may transform data, physical devices, and / or representations of physical devices from one form to another. For example, one or more of the units described herein may receive instruction data to be transformed, transform the instruction data, output the result of the transformation to a queue instruction, determine dependencies using the result of the transformation, and store the result of the transformation to track dependencies between instructions. Additionally or alternatively, one or more of the modules enumerated herein may transform a processor, volatile memory, non-volatile memory, and / or any other part of a physical computing device from one form to another by executing on a computing device, storing data on a computing device, and / or otherwise interacting with a computing device.

[0056] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include transmission-type media such as carrier waves, as well as non-transitory media such as magnetic storage media (e.g., hard disk drives, tape drives, floppy (registered trademark) disks), optical storage media (e.g., Compact Disk (CD), Digital Video Disk (DVD), BLU-RAY (registered trademark) disks), electronic storage media (e.g., solid state drives and flash media), and other delivery systems, but are not limited thereto.

[0057] The process parameters and the order of steps described and / or illustrated in this specification are provided by way of example only and can be changed as desired. For example, although those illustrated and / or described in this specification can be shown or discussed in a particular order, these steps do not necessarily have to be performed in the order shown or discussed. Various exemplary methods described and / or illustrated in this specification may omit one or more of those described or illustrated in this specification, or may include additional steps in addition to those disclosed.

[0058] The above description is provided to enable those skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed in this specification. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed in this specification are to be considered in all respects as illustrative and not restrictive. When determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0059] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and the claims should be construed to allow both direct and indirect (i.e., via other elements or components) connections. Further, the term "a" or "an" as used in this specification and the claims should be construed to mean "at least one of". Finally, for ease of use, the terms "including" and "having" (and their derivatives) are interchangeable with the term "comprising" and have the same meaning when used in this specification and the claims.

Claims

1. It is a method, Using an encoding scheme that encodes index locations into values, a first dependency is encoded to indicate that a first instruction represented in a dependency matrix depends on a second instruction represented in the dependency matrix, The encoded first dependency is stored in the dependency matrix, Dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix for the first instruction, method.

2. The encoding scheme corresponds to a partial encoding scheme that includes dividing the set of instructions represented by the dependency matrix into groups, and representing the dependency source instructions using a group value corresponding to the group containing the source instructions and an index value corresponding to the source instructions within the group. The method according to claim 1.

3. In the aforementioned partial coding scheme, decoding is performed as follows: Using the group value, identify the group containing the source instruction, This includes using the aforementioned index value to identify which instruction within the identified group corresponds to the source instruction, The method according to claim 2.

4. The encoding scheme corresponds to a complete encoding scheme that includes representing the source instructions of a dependency using location values ​​corresponding to the index locations of the source instructions in the dependency matrix. The method according to claim 1.

5. In the complete encoding scheme, the decoding includes identifying the source instruction using the location value. The method according to claim 4.

6. Encoding a second dependency that indicates the first instruction depends on a third instruction represented in the dependency matrix, The method includes storing the encoded second dependency in the dependency matrix, The method according to claim 1.

7. The second dependency is encoded using a second encoding scheme different from the encoding scheme. The method according to claim 6.

8. The aforementioned encoding scheme includes a special value indicating no dependency, The method according to claim 1.

9. Dispatching the first instruction is based on identifying the readiness state of each of the decoded dependencies. The method according to claim 1.

10. It is a method, The first instruction is stored in a buffer for queuing instructions, wherein the first instruction depends on a second instruction in the buffer. Encoding a first dependency indicating that the first instruction depends on the second instruction, using an encoding scheme that reduces the number of bits required to represent one or more instructions from the set of instructions in the buffer by encoding the index location of the buffer into a value, The encoded first dependency is stored in a dependency matrix, Dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix for the first instruction, method.

11. The encoding scheme corresponds to a partial encoding scheme that includes dividing the set of instructions into groups and representing dependent source instructions using a group value corresponding to the group containing the source instructions and an index value corresponding to the source instructions within the group. The method of claim 10.

12. In the aforementioned partial coding scheme, decoding is performed as follows: Using the group value, identify the group containing the source instruction, This includes using the aforementioned index value to identify which instruction within the identified group corresponds to the source instruction, The method according to claim 11.

13. The encoding scheme corresponds to a complete encoding scheme that includes representing the dependency source instruction using a location value corresponding to the buffer location of the source instruction in the buffer, The method of claim 10.

14. In the complete encoding scheme, the decoding includes identifying the source instruction using the location value. The method according to claim 13.

15. Encoding a second dependency indicating that the first instruction depends on a third instruction in the buffer, The method includes storing the encoded second dependency in the dependency matrix, The method of claim 10.

16. The aforementioned encoding scheme includes a special value indicating no dependency, The method of claim 10.

17. The index location in the dependency matrix corresponds to the buffer location in the buffer, The method of claim 10.

18. It is a system, Physical memory and It comprises at least one physical processor, The aforementioned physical processor is A buffer for queuing instructions, A dependency matrix that tracks the dependencies between instructions in the buffer, The system includes a control circuit that identifies ready instructions in the buffer using the dependency matrix, The aforementioned control circuit is Encoding a first dependency indicating that a first instruction in the buffer depends on a second instruction in the buffer, using an encoding scheme that reduces the number of bits required to represent one or more instructions from the set of instructions in the buffer by encoding the index location of the buffer into a value, The encoded first dependency is stored in the dependency matrix in an index location corresponding to the buffer location of the first instruction in the buffer, Dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix for the first instruction, It is configured to do, system.

19. The encoding scheme corresponds to a partial encoding scheme that includes dividing the set of instructions into groups and representing dependent source instructions using a group value corresponding to the group containing the source instructions and an index value corresponding to the source instructions within the group. In the aforementioned partial coding scheme, decoding is performed as follows: Using the group value, identify the group containing the source instruction, This includes using the aforementioned index value to identify which instruction within the identified group corresponds to the source instruction, The system according to claim 18.

20. The encoding scheme corresponds to a complete encoding scheme that includes representing the dependency source instruction using a location value corresponding to the buffer location of the source instruction in the buffer, In the complete encoding scheme, the decoding includes identifying the source instruction using the location value. The system according to claim 18.

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