Split register list for renaming

Abstract

The disclosed system may include a processor configured to detect that a data unit size of an instruction is smaller than a register. The processor may allocate a first portion of the register to an instruction while leaving a second portion of the register available for allocation to additional instructions. Further, the processor may track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

Description

Background Art

[0001] Modern processor architectures can incorporate various features to improve performance. For example, a processor may be able to execute instructions such as processor-level micro-operations (micro-operation, uop or μop) decoded from program code non-sequentially or out of order. Instructions can access registers (e.g., high-speed local storage within the processor that can hold data for operating the instruction), more specifically, architectural registers (e.g., registers defined by an instruction architecture that may be visible to software but can be abstracted from physical registers within the processor) to perform operations.

[0002] Since instructions may be executed out of order, instructions may change architectural registers in a way that can modify another instruction. For example, while a first instruction may require the result of a second instruction stored in an architectural register, another instruction may load a value into the architectural register. When the value is loaded into the architectural register, it may prevent the first instruction from operating correctly with the correct value. To prevent such scenarios, a processor may map architectural registers or other logical registers (e.g., registers abstracted from physical registers) to different physical registers during the renaming phase of the processor's instruction pipeline. The processor may include more physical registers than the number of architectural registers defined in the instruction architecture.

[0003] During the renaming phase, the processor can select an available physical register for mapping. Thus, the processor can track which of its physical registers are available. In some architectures, the processor can support instructions of different register sizes. For example, some instructions can use architecture registers that each correspond to two physical registers, while other instructions can use architecture registers that each correspond to one physical register. To simplify register management, the processor can manage physical registers based on the largest architecture register size supported.

[0004] The accompanying drawings illustrate some exemplary embodiments and form a part of this specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

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[0006] Throughout the drawings, the same reference numerals and descriptions, while not necessarily identical, indicate similar elements. The exemplary embodiments described herein are capable of various modifications and alternative forms, but a particular embodiment is shown by way of example in the drawings and described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternative forms falling within the scope of the appended claims.

[0007] As will be described in more detail below, the present disclosure describes various systems and methods for managing split registers within a split register for renaming. To simplify register management, a processor can manage physical registers based on the maximum architectural register size supported. However, in such a manner, for example, when supporting instructions of a smaller size, physical registers may not be used. Thus, in one example, a method for managing split registers for renaming can include detecting that the data unit size of an instruction is smaller than the register, and allocating the first part of the register to the instruction while leaving the second part of the register available for allocation to additional instructions. The method can also include tracking the register as a split register.

[0008] In some examples, tracking a register may include marking the register in a split register list. The split register list may track split registers such that a corresponding second portion has an address value that is the other of even or odd based on one of even or odd address values. In some examples, the method may further include unmarking a register in the split register list when the first and second portions are available.

[0009] In some examples, the method may include selecting a register from a free register list. Each of the free registers can be tracked in the free register list as a pair of register portions. Additionally, the method may include tracking a second portion of the register within a list of free register portions.

[0010] In some examples, the method may include marking the first portion as available when the instruction is complete. In some examples, the method may include allocating the second portion to a second instruction. In some examples, the data unit size may correspond to the instruction width of the instruction. In some examples, the size of the register may correspond to the width of a wide instruction.

[0011] In one example, a method for managing split registers for renaming may include detecting that an instruction's data unit size is smaller than a register size, and for the instruction, selecting a free register having the register size from a free register list. The method may also include allocating the first portion of the selected register to the instruction and keeping the second portion of the selected register available for allocation to an additional instruction, and tracking the selected register as a split register in a split register list.

[0012] In one embodiment, a system for managing split registers for renaming may include at least one physical processor including a physical memory, a plurality of registers, and a control circuit for managing the allocation of registers for instructions. The control circuit is configured to select an available register from the list of available registers for an instruction having a data unit size smaller than that of the registers. The control circuit may further be configured to allocate a first portion of the selected register to the instruction and keep the second portion of the selected register available for allocation to additional instructions, and to track the selected register as a split register within the split register list.

[0013] Features from any of the above-described embodiments can be used in combination with each other according to the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and the claims.

[0014] The present disclosure generally relates to splitting registers during the rename phase of a processor's instruction pipeline. As will be described in more detail below, the present disclosure provides a system and method for splitting and tracking registers that can be a combination of physical registers. Instead of tracking individual physical registers, the processor tracks combinations of physical registers (as registers) and may split the combination if the instruction does not require the combined registers. The processor can use a bit vector to track whether a register is a split register, avoiding the need for significant changes to the processor's renaming scheme.

[0015] For example, embodiments of the present disclosure may detect that the data unit size of an instruction is smaller than a register. In response, embodiments of the present disclosure may allocate a first portion of the register to an instruction while leaving a second portion of the register available for allocation to additional instructions. The register may be tracked as a split register.

[0016] Features from any of the embodiments described herein can be used in combination with one another in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and the claims.

[0017] Details of various embodiments of split register renaming are provided below with reference to FIGS. 1-6. A detailed description of an exemplary system for managing split registers is provided in connection with FIG. 1. A detailed description of an exemplary renaming workflow is provided in connection with FIG. 2. Detailed descriptions of registers and split register lists are provided in connection with FIGS. 3 and 4. A detailed description of an exemplary method for managing split registers for renaming is provided in connection with FIG. 6.

[0018] FIG. 1 is a block diagram of an exemplary system 100 for managing split registers for renaming. System 100 may correspond to a computing device such as a desktop computer, laptop computer, server, tablet device, mobile device, smartphone, wearable device, augmented reality device, virtual reality device, network device, and / or electronic device. As shown in FIG. 1, system 100 may include one or more memory devices such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, one or more variations or combinations of these, and / or any other suitable storage memory.

[0019] As shown in FIG. 1, an exemplary system 100 can include one or more physical processors such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 can access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems on chip (SoCs), one or more portions of these, one or more variations or combinations of these, and / or any other suitable physical processor.

[0020] In some embodiments, the term "instructions" can refer to computer code that can be read and executed by a processor. Examples of instructions can include, but are not limited to, macroinstructions (e.g., program code that can require a processor to decode into processor instructions that the processor can directly execute) and micro-operations (e.g., low-level processor instructions that are decoded from a macroinstruction and form part of the macroinstruction).

[0021] As further shown in FIG. 1, the processor 110 can include a control circuit 112, a register 130, a register list 140, and a split register list 150. The control circuit 112 can correspond to a rename unit or other similar control unit and can include circuits and / or instructions for allocating and / or assigning registers to instructions. The register 130 can correspond to one or more registers of the processor 110. The register list 140 can correspond to a free list that can track which of the registers 130 are free (e.g., not in use) and / or which of the registers 130 are not available. The split register list 150 can correspond to one or more lists that can track which of the registers 130 are split into register portions.

[0022] In some embodiments, the term "register" can refer to the processor's fast local storage that can be used to hold data for operations. Examples of registers can include, but are not limited to, physical registers (e.g., physical storage units within the processor), logical registers (e.g., registers referenced by instructions and dynamically mapped to physical registers), and architectural registers (e.g., registers defined by the architecture that are visible to software and dynamically mapped to physical registers). In some examples, a register (e.g., a pair register) can refer to two or more physical registers. In some examples, the size or number of bits of a physical register can be defined by the processor's hardware architecture.

[0023] Figure 2 shows an exemplary pipeline 200 for a processor, such as processor 110 (and / or its functional units), to execute instructions. During the fetch stage 202, processor 110 can read program instructions from memory 120. Processor 110 can fetch based on an active thread or other criteria. In the decode stage 204, processor 110 may decode the read program instructions into micro-operations. Processor 110 (and / or its functional units) may transfer the newly decoded micro-operations to a scheduler, which may queue the micro-operations until they are ready for dispatch. In the dispatch stage 206, the scheduler can dispatch one or more micro-operations that are ready for dispatch. A micro-operation can be ready for dispatch when its dependencies (e.g., resources that may depend on other instructions to complete execution) are resolved. In some examples, the scheduler may select ready micro-operations upon receiving that an execution unit of processor 110 has become available.

[0024] In the rename stage 208, control circuit 112 can allocate registers to dispatched micro-operations as needed. Control circuit 112 can access one or more of register file 230 (which may correspond to and / or represent register 130), free list 240 (which may correspond to register list 140), and split register list 250 (which may correspond to split register list 150). Register file 230 may correspond to an array of registers of processor 110. Figure 3 shows register file 330 (which may correspond to register file 230).

[0025] As shown in FIG. 3, the register file 330 can include a pair register 332, a pair register 334, and a pair register 336. In some examples, the processor 110 implements an architecture that can support wide instructions that can operate on data unit sizes larger than the register size of a physical register. For example, a wide instruction or a special instruction can operate on a data unit size that is twice the physical register size. The data unit size can correspond to the bit size of the data unit operated on by an instruction. In some examples, the data unit size corresponds to the instruction width (e.g., the bit size of an instruction). To support wide instructions, the processor 110 manages registers and physical register pairs such that the pair register size can be twice the physical register size. Thus, as shown in FIG. 3, the pair register 332 includes a physical register 333A (having address “00”) and a physical register 333B (having address “01”), the pair register 334 includes a physical register 335A (having address “02”) and a physical register 335B (having address “03”), and the pair register 336 includes a physical register 337A (having address “04”) and a physical register 337B (having address “05”). The pair registers described herein include pairs of physical registers, but in other embodiments, a pair register may include a different number of physical registers, such as three, four, etc.

[0026] The physical registers for each register can be consecutive such that a register can include two consecutive physical registers, but in other examples, the physical registers may not be consecutive. As seen in FIG. 3, since each pair register includes a pair of consecutive physical registers, each pair register is associated with an even address value. For example, the pair register 332 has an address of 00 (since address 01 is considered part of the pair register 332). Similarly, the pair register 334 has an address of 02, and the pair register 336 has an address of 04. In other embodiments, a register can have an odd address value and the associated second physical register can have an even address value.

[0027] During rename stage 208, processor 110 may allocate any one of pair register 332, pair register 334, or pair register 336 based on availability. In other words, processor 110 can allocate two physical registers to an instruction. However, in some examples, an instruction may have a data unit size and / or instruction width that is smaller than the pair register size. An instruction may not require two physical registers. The systems and methods described herein enable splitting a pair register into portions that can correspond to physical registers.

[0028] FIG. 4 shows register list 440, split register list 450 (which may correspond to split register list 150 and / or split register list 250), derived pair register list 460, and derived single register list 461 (which may correspond to free list 240 and / or register list 140). In some examples, register list 440 includes register list 442A and register list 442B. Register list 442A tracks the availability of physical registers corresponding to the first portion of a pair register, and register list 442B tracks the availability of physical registers corresponding to the second portion of a pair register. In some examples, register list 442A may track even physical registers (e.g., physical registers with even addresses), and register list 442B may track odd physical registers (e.g., physical registers with odd addresses). The availability of pair and single registers is tracked using vectors including derived pair register list 460 and derived single register list 461 so that a rename table or other complex structure may not be required.

[0029] The sizes of the various register lists shown in FIG. 4 may be N / L, where N is the maximum or total number of single physical registers available in the processor. In the examples described herein, N is 384 (e.g., 384 physical registers). L corresponds to the number of physical registers that can be combined, such as two physical registers combined into a pair register as described herein. Also, L corresponds to the number of lists, and N is a multiple of L. In the examples described herein, L is 2, corresponding to two register lists (e.g., register list 442A and register list 442B), and further corresponding to a pair register that includes two physical registers (e.g., an even register and an odd register). Each of the lists (e.g., register list 442A, register list 442B, split register list 450, derived pair register list 460, and / or derived single register list 461) is indexed between [0...N / L - 1], and each holds data corresponding to registers in different manners. For example, register list 442A is implemented as a 192-bit vector (e.g., 384 / 2) that holds information regarding even addressable registers, while register list 442B is implemented as a 192-bit vector that holds information regarding odd addressable registers. In other examples, L may be a different value. In one particular example, if the physical registers are 128-bit sized registers, it may be desirable to allocate one physical register to a 128-bit uop, two physical registers to a 256-bit uop, and four physical registers to a 512-bit uop, and as a result, in this particular example, L can be 4.

[0030] Since the pair registers are managed as pairs of physical registers (e.g., L = 2), each pair register has an address with an even value (e.g., corresponding to a physical register number or PRN), as further shown in FIG. 3. The derived pair register list 460 corresponds to a free pair list (indicating which pair registers are free), and the derived single register list 461 corresponds to a free single register list (indicating which single registers are free). The derived pair register list 460 (which is also stored in a register) is a list derived from the AND combination of register list 442A and register list 442B. The derived single register list 461 (which is also stored in a register) is a list derived from the XOR combination of register list 442A and register list 442B. FIG. 5 shows an exemplary simplified circuit 500 for deriving the pair register list and the single register list.

[0031] FIG. 5 includes an even list 542A that may correspond to the register list 442A, an odd list 542B that may correspond to the register list 442B, a split vector 550 that may correspond to the split register list 150, an AND gate 544, an XOR gate 546, a pair list 560 that may correspond to the derived pair register list 460, a single list 561 that may correspond to the derived single register list 461, and a rename block 582 that may correspond to the rename stage 208. Each of the split vector 550, the even list 542A, and the odd list 542B has the same size N / 2 (e.g., 384 / 2 = 192-bit vector). Each marked bit in the even list 542A and the odd list 542B indicates an empty portion of a pair register (e.g., a physical register). Thus, both the empty even and odd portions indicate an empty pair register, while only one of the empty even and odd portions indicates an empty single register. Accordingly, the pair list 560 is derived using the AND gate 544, and the single list 561 is derived using the XOR gate 546. For each index value, if both the even list 542A and the odd list 542B have a marked bit, the AND gate 544 marks the corresponding bit in the pair list 560. In addition, for each index value, if a bit (but not both bits) in either the even list 542A or the odd list 542B is marked, the XOR gate 546 marks the corresponding bit in the single list 561.

[0032] Returning to FIG. 4, the derived pair register list 460 and the derived single register list 461 are, in some examples, composed of 192-bit vectors. In the example shown in FIG. 4, a pair register (e.g., a partial pair) is identified by an even address value such that the derived pair register list 460 tracks even address values. Thus, the pair registers from the derived pair register list 460 have even address values and include two consecutive empty portions (e.g., the PRN of an even address and the next odd address PRN). Also, the derived single register list 461 tracks even address values that include the most significant bit (MSB) data of the address value, but may not have the least significant bit (LSB) information of the address value. To specifically identify whether the even or odd portion of a pair register is empty, the LSB data can be queried against one of the register lists 442A and / or 442B to determine the LSB data. For example, query the register list 442B (e.g., odd address) to determine the LSB status. For an index marked as empty within the derived single register list 461, if the corresponding index within the register list 442B is empty, the LSB data indicates that its odd portion is empty. Otherwise, if the corresponding index within the register list 442B is not empty, the LSB data indicates that its even portion is empty. As described herein, the derived single register list 461 is derived by an XOR operation. Also, a marked bit indicates that one portion of the corresponding pair register is not empty within the register list 442A or the register list 442B.

[0033] If a new pair register is formed (e.g., both parts of the pair register are freed), the corresponding addresses / bits in register lists 442A and 442B are marked and propagated to the derived pair register list 460. If only one of the addresses / bits in register lists 442A and 442B is set (e.g., only one part of the pair register is free), the corresponding even address value is set in the derived single register list 461 to store the MSB data of the address value. Optionally, in some examples, a new pair need not be tracked (e.g., update / derive the derived pair register list 460) unless the number of free pairs in the derived pair register list 460 becomes less than a threshold number of free pair registers required for the renaming iteration, such as to reduce power consumption.

[0034] In some examples, the split register list 450 tracks which registers are split. The split register list 450 is implemented as a 192 - bit vector. For example, as shown in FIG. 4, the split register list 450 can track the physical registers with even addresses. The marked bit in the split register list 450 for a register (indexed based on the even address value) indicates that the corresponding pair register is split.

[0035] Returning to FIG. 2, in some examples, during the rename stage 208, the control circuit 112 selects an available pair register (e.g., a physical register pair) for the instruction from the derived pair register list 460. If the instruction has a data unit width that matches the pair register size, or if the instruction has other architecture signals (such as whether the instruction is a special instruction, the type of operation, etc.), the control circuit 112 allocates all of the selected pair register (e.g., both parts) to the instruction and indicates that the corresponding entry is not available within the derived pair register list 460 (e.g., by unmarking the corresponding bits in the register lists 442A and 442B and updating the derived pair register list 460 as described herein).

[0036] If the command has a data unit width smaller than the register size and there are no other architecture signals (such as whether the command is a special command, the type of operation, etc.), the control circuit 112 proceeds to allocate only the free portion of the selected pair of registers (e.g., a free single physical register) to the command. If the selected pair of registers has not yet been split, the control circuit 112 allocates the even portion of the selected pair of registers to the command and unmarks the corresponding bit in the register list 442A. The control circuit 112 splits the selected pair of registers (makes the odd portion available) by marking the appropriate bits in the split register list 450 (e.g., by marking the even address entries as split) and by unmarking the appropriate bits in the derived pair register list 460 (e.g., by updating / deriving the derived register list 460 as described herein). Thus, the even portion of the selected pair of registers is allocated to the command and the odd portion is available to be allocated later. Additionally, in some examples, the control circuit 112 may actively mark the appropriate bits of a single free register portion as free if the command was previously allocated earlier due to overwriting of architecture signals in the register list 442A and / or the register list 442B (such as registers allocated in an earlier stage of the pipeline).

[0037] If the selected pair register has been previously split (e.g., if the derived single register list 461 provides free registers and / or the list 460 of derived pair registers has not been updated / derived), the control circuit 112 allocates an even address value to the instruction if available, or an odd address value corresponding thereto if available, and accordingly updates the entry in the register list 440 as not available (e.g., in either the register list 442A or the register list 442B, and in the derived single register list 461). In some examples, if the instruction has a data unit width smaller than the register size, the control circuit 112 may first check the derived single register list 461 for the free register portion before selecting and splitting another free pair register.

[0038] In some examples, the rename stage 208 may obtain only a particular (e.g., P = 6, S = 6) selected register list of either pair registers or single registers. In some examples, the rename stage 208 may preemptively update the entries in the register list 440 and / or the derived pair register list 460 as not available, rather than marking the entries as available or not available later when the selected register list is transferred to the rename stage 208. These selected register lists may be designated as not available when provided from the free list block to the rename stage 208. P pair selected register lists may be designated as not available from the derived pair register list 460. S single selected register lists may be designated as not available from the derived single register list 461 and within the register list 442A or the register list 442B, depending on the selected LSB bit.

[0039] After the command is completed, or when a physical register retires or is otherwise returned due to any other situation (such as flash, etc.), the control circuit 112 updates the relevant list (for example, one or more of the register list 140, split register list 150, free list 240, split register list 250, split register list 450, etc.) accordingly. For example, if the returned physical register has an even address value, the control circuit 112 identifies whether it is a split register (by checking the split register list 450). If the returned even physical register corresponds to a split register, the control circuit 112 marks the corresponding entry in the register list 442A as free. If the control circuit 112 determines that the returned even physical register is not the split register marked in the split register list 450, the control circuit 112 marks the appropriate entries in both the register list 442A and the register list 442B as free for the appropriate address. If the returned physical register has an odd address value, the control circuit 112 marks the corresponding entry in the register list 442B as free.

[0040] In some examples, the control circuit 112 generates / derives a new pair register list and / or a new single register list (for example, by updating / deriving as described herein) and writes them to the derived pair register list 460 and the derived single register list 461. The control circuit 112 unmarks the appropriate bits of the newly generated pair registers in the split register list 450. In some examples, the control circuit 112 can complement the derived pair register list 460 with a new pair list, while the control circuit 112 can write all the bits in the bit vector of the derived single register list 461.

[0041] Returning to FIG. 2, in the issue / execute stage 210, the processor 110 and / or its execution units execute the dispatched micro-operations. Although FIG. 2 shows a basic exemplary pipeline 200, in other examples, the processor 110 can execute the stages in various orders, repeat iterations, and / or execute the stages in parallel.

[0042] FIG. 6 is a flowchart of an exemplary computer-executable method 600 for managing split registers for renaming. The steps shown in FIG. 6 may be performed by any suitable computer-executable code and / or computing system, including the system shown in FIG. 1. In one example, each of the steps shown in FIG. 6 can represent an algorithm whose structure includes a plurality of sub-steps and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0043] As shown in FIG. 6, in step 602, one or more of the systems described herein can detect that the data unit size of an instruction is smaller than a pair register. For example, the control circuit 112 detects that the data unit size of an instruction is smaller than the pair register selected by the control circuit 112.

[0044] The systems described herein can perform step 602 in various ways. As described herein, the data unit size corresponds to the instruction width of an instruction, and the size of a pair register can correspond to the width of a wide instruction (e.g., a physical register pair). In some examples, the control circuit 112 can detect the data unit size from the instruction width of an instruction or other architecture signals (such as whether the instruction is a special instruction, the type of operation, etc.).

[0045] As further described herein, each free register is tracked within the free register list as a pair of register portions, or as a single portion free list. For example, register list 140 tracks free registers as pairs of physical registers. In some examples, derived pair register list 460 tracks available pair registers and derived single register list 461 tracks available single registers. In some examples, control circuit 112 selects a pair register from the free register list (e.g., from register list 140, derived pair register list 460, and / or derived single register list 461). When the selected register is provided to the rename block, the corresponding bit of the selected register is marked as not free in derived pair register list 460 or derived single register list 461.

[0046] In step 604, one or more of the systems described herein can allocate the first portion of a pair register to an instruction while leaving the second portion of the pair register available (in a manner that leaves it available) for allocation to an additional instruction. For example, after selecting a free register for an instruction, control circuit 112 splits the selected pair register as described herein to allocate the first portion of the pair register to the instruction while leaving the second portion of the pair register available (in a manner that leaves it available) for allocation to an additional instruction.

[0047] The system described in this specification can perform step 604 in various ways. In one example, control circuit 112 divides the selected pair register (which has an even address value, although in other embodiments it may have an odd address value) by marking the corresponding entry as divided within split register list 450. Control circuit 112 allocates the second portion of the split register to another instruction within this cycle. If the second portion cannot be allocated to another instruction, control circuit 112 holds the second portion in a register within the rename block. This held register prevents the second portion from being returned to the free list. Also, control circuit 112 can determine to allocate a previously held second portion register (e.g., from a previous cycle) to an appropriate new instruction in this cycle (e.g., an instruction that is not a wide instruction and meets the condition of having no other architecture signals that should be prioritized). Control circuit 112 may then proceed to clear the hold register within the rename block.

[0048] As described above, if the selected register is already divided, control circuit 112 can allocate the first portion to an instruction. In another iteration, control circuit 112 can then allocate the second portion to a second instruction, if necessary.

[0049] Returning to method 600, at step 606, one or more of the systems described in this specification can track a pair register as a split register. For example, control circuit 112 tracks a pair register as a split register by updating a relevant list (e.g., one or more of register list 140, split register list 150, free list 240, split register list 250, split register list 450, etc.).

[0050] The system described in this specification can perform step 606 in various ways. In one example, tracking a register includes marking the register in a split register list (e.g., split register list 250 and / or split register list 450). The split register list tracks split registers such that, based on one of an even or odd address value, the corresponding second part has the other of the even or odd address values. In some examples, control circuit 112 further tracks the second part of the register within a list of free register parts (e.g., register list 442B and / or derived register list 461).

[0051] In some examples, control circuit 112 marks the first part as free when the instruction is complete (e.g., by updating register list 442A). In some instances, control circuit 112 marks the second part as free when the corresponding instruction is complete (e.g., by updating register list 442B). In some examples, control circuit 112 marks the first and second parts as free when the corresponding instruction is complete (e.g., by updating register lists 442A and 442B, which may further update / derive derived paired register list 460 and / or derived single register list 461 in some examples). Also, control circuit 112 may unmark the register in the split register list (e.g., split register list 450) when the first and second parts are free to indicate that the first and second parts have reformed a paired register.

[0052] Figure 7 shows a simplified top-level diagram of the split register naming process 700 described herein. Flash block 772, rename block 774, and retire block 776 return physical register numbers at 778 to update the free list 741 (which may correspond to register list 440), which may include updating one or more of free register list 742A (which may correspond to register list 442A), free register list 742B (which may correspond to register list 442B), split register list 750 (which may correspond to split register list 450), pair list 760 (which may correspond to derived pair register list 460), and single list 761 (which may correspond to derived single register list 461). From the updated free list 741, additional PRNs (e.g., six, although other numbers of PRNs may be used in other examples) are read at 780 for rename block 782.

[0053] Figure 8 shows a simplified flowchart of the return process 800 with reference to Figure 7, as performed, for example, at 778. At 802, the free list (e.g., free list 741) receives the returned PRN, e.g., the address returned for freeing. At 804, it is evaluated whether the given address of each PRN is even or odd. If it is odd, this indicates in some examples that a single PRN has been freed, and at 808, the corresponding bit in free register list 742B is marked as free.

[0054] At 804, if the address is even, in some examples, this indicates that a pair of registers is freed, and at 806, the corresponding bit in the free register list 742A is marked. At 810, the bits in the split vector (e.g., split register list 750) are checked to see if they are marked as pair registers. If the bit is not marked as a pair register, at 814, the process completes the current iteration. If the bit is marked as a pair register, at 812, the corresponding bit in the free register list 742B is marked as free, indicating that both the even and odd parts of the pair register are free.

[0055] In an example of returning a PRN, such as address 04 corresponding to index 2 as shown in FIG. 4 for register list 442A, the register list 442A is updated at index 2 and marks PRN04 as free. The split register list 450 is checked to determine if index 2 is split or a pair register. If the split register list 450 indicates a pair register, the register list 442B is also updated as free at index 2, indicating that the pair register (e.g., both parts) is free. The register list 442B may not need to be updated if the returned PRN is not a pair register. In another example, for an odd address such as 01, the register list 442B is updated at index 0.

[0056] FIG. 9 shows a simplified flowchart of a list update process 900 with reference to FIG. 7, for example, after returning a PRN and in some examples, after process 800. At 902, the pair list 760 is evaluated to determine if the number of available pair registers is low (e.g., below the threshold number of pair registers for the current iteration), which indicates that the pair list 760 needs to be updated. If the number of available pair registers is not low, process 900 completes the current iteration at 904.

[0057] If the number of paired registers at 902 is small, process 900 proceeds to 906 to update paired list 760 and single list 761. The free register list 742A is combined with the free register list 742B using an AND operation (see also FIG. 5) to derive the next paired list. The free register list 742A is combined with the free register list 742B using an XOR operation (see also FIG. 5) to derive the next XOR list.

[0058] At 908, the next paired list is written to paired list 760 for update, and the next XOR list is written to single list 761 for update. Additionally, at 910, the next paired list is unmarked within split register list 750 to indicate that the newly derived pairs are not split. Similarly, at 912, the next paired list is unmarked within free register list 742A and free register list 742B.

[0059] The bits set within single list 761 are derived from either free register list 742A or free register list 742B (as a single register) using an XOR operation, and the resulting bit is marked if the corresponding bit is marked within free register list 742A (e.g., even address) or free register list 742B (e.g., odd address), but not both. Thus, the next XOR list (and single list 761) does not know or notice whether it contains an even or odd PRN address value. The bits read from single list 761 are used to determine all bits of the PRN address value except the LSB, but further queried or referenced against free register list 742B to determine whether the single PRN is odd (indicated by the corresponding marked bit within free register list 742B) or even.

[0060] In an example of generating a pair register, referring to FIG. 4, PRN04 and PRN05 are empty (within register lists 442A and 442B respectively). If the number of free pairs (e.g., pair free list counter) does not meet the threshold number of free pairs (e.g., is less than or equal to the threshold number of free pairs such as 24), a new pair is generated from the available free space. PRN04 is empty, and as a result, the derived pair register list 460 is updated accordingly (e.g., index 2 can be marked as empty). PRN04 is marked as not empty within register list 442A (e.g., at index 2), and PRN05 is marked as not empty within register list 442B (e.g., at index 2). The split register list 450 is marked as a pair or not split (e.g., at index 2).

[0061] In an example of making a single register available, PRN04 is empty and PRN05 is not empty. If the pair free list counter does not meet the threshold number of free pairs (e.g., is less than or equal to the threshold number of free pairs which can be, for example, 24), a new pair is needed. By performing an XOR operation on PRN04 and PRN05, it can be determined whether index 2 corresponds to a single register. The derived single register list 461 is updated accordingly at index 2 and marked as empty. In some examples, if the pair free list counter meets the threshold number of free pairs (e.g., the number of free pairs is greater than the threshold number of free pairs), a new pair is not needed.

[0062] Figures 10A and 10B show simplified flow diagrams of various selection processes with reference to FIG. 7. FIG. 10A shows a process 1000 for selecting a single PRN. At 1002, a single list 761 is provided and / or updated. At 1004, the single list 761 is examined to determine whether the single list 761 has six available PRNs (in other examples, other numbers of PRNs may be required), and whether stage P0 (e.g., PRN0) is invalid (e.g., a floating-point register is required). If neither condition is met, at 1006, the current iteration of process 1000 ends. Otherwise, at 1008, six PRNs are read and written to the stage P0 flip-flop at 1010. Using an appropriate method or way, stage P0 is invalidated during rename read and simultaneously written to the stage P1 (e.g., PRN1) flip-flop.

[0063] Proceeding to 1012, the free register list 742B (e.g., odd-address PRNs) is checked to determine whether the stage P0 address is marked. If not marked in the free register list 742B, at 1014, it is determined that the LSB is 0. Otherwise, at 1016, it is determined that the LSB is 1. Additionally, at 1020, the address or PRN is written to the stage P1 flip-flop during rename read (e.g., a new uop is in the pipeline and the rename read is asserted to indicate that the PRN is required for the operation) and given to the rename block.

[0064] In an example of selecting a single PRN, with further reference to FIG. 4, after selecting a single PRN (using, for example, the logic to find the first N), the corresponding entry in the derived single register list 461 is marked as not available. The address of the selected PRN is checked against the register list 442B to determine whether the address is odd. If the selected PRN is found in the register list 442B, it is marked as not available in the register list 442B and confirmed to be odd. If the selected PRN is not found in the register list 442B, it is marked as not available in the register list 442A and confirmed to be even.

[0065] For example, for PRN04 (having index 2 in register list 442A), index 2 of the derived single register list 461 may be marked as not available. If index 2 of register list 442B is marked as available, PRN = {2, 1'b1} = PRN05. Otherwise, PRN = {2, 1'b0} = PRN04. For PRN05, index 2 of register list 442B is marked as not available. For PRN04, index 2 of register list 442A is marked as not available.

[0066] Figure 10B shows a process 1001 for selecting a pair register. At 1030, a pair list 760 is provided and / or updated. At 1032, the pair list 760 is examined to determine whether it has six available PRNs (in other examples, other numbers of PRNs may be required), and whether stage P0 is invalid (e.g., a floating-point register is required). If these conditions are not met, at 1034, the current iteration of process 1001 ends. Otherwise, proceed to 1036, where six PRNs are read from the pair list 760 for renaming. At 1038, the address is written to the stage P0 flip-flop. Using a certain method or way, stage P0 is invalidated during rename read at the same time as it is written to the stage P1 flip-flop.

[0067] Process 1001 continues at 1048 by writing the address or PRN to the stage P1 flip-flop during rename read. Process 1001 ends the current iteration at 1050 by providing a PRN to the rename block.

[0068] In an example of selecting a pair PRN, with further reference to FIG. 4, after selecting a pair PRN such as PRN04 (having index 2 in register list 442A) (e.g., using logic to find the first N), this PRN is marked as not available in the derived pair register list 460. The rename stage can then use and / or allocate this pair PRN to the uop.

[0069] Figures 11A and 11B are simplified flow diagrams of an exemplary renaming process 1100 in conjunction with the systems and methods described herein. At 1102, the following two conditions are evaluated: (1) whether the current uop size is less than 512 (e.g., whether the current instruction is smaller than the wide instruction size), and (2) whether there is no SSE merge (e.g., in some examples, a merge type operation for Streaming SIMD Extension (SSE), corresponding to the architecture signal of an instruction that requires a register of wide instruction size, Streaming SIMD Extension (SIMD)). If either condition is evaluated as false, at 1104, a pair PRN is allocated. If it is determined that the uop is 512 or the SSE merge is set, a pair PRN is allocated.

[0070] If both conditions are true (indicating that a register of wide instruction size is not required), at 1104, it can be evaluated that the last stored odd single PRN is valid. If the last stored odd single PRN is valid (indicating that a single PRN is available), at 1106, an odd single PRN is allocated, and at 1108, the stored odd single PRN is marked as invalid (e.g., neither free nor occupied).

[0071] At 1104, if the last stored odd single PRN is not valid, at 1110, it can be determined whether there is a valid second part of the pair PRN. If there is a valid second part of the pair PRN, at 1112, this second part is allocated to the current uop.

[0072] At 1110, if there is no valid second part, at 1114, the pair PRN is split and the first part is allocated to the current uop. At 1118, it can be determined whether the second part of the pair PRN (split at 1114) is used by another uop in the current cycle. If the second part is not used by another uop in this cycle, at 1120, the second part is stored in the odd single PRN of the uop in the next cycle (e.g., the iteration of the next cycle of 1104). If the second part is used by another uop in this cycle, at 1122, this second part is allocated to another uop in this cycle instead of storing the second part and avoiding splitting of the new pair PRN in the current iteration of process 1100.

[0073] In addition, after splitting the pair PRN at 1114, at 1116, an update to the split vector (e.g., split register list 150, split register list 450, split register list 750, etc.) is sent to indicate that this pair PRN has been split. Process 1100 follows process 1101 shown in FIG. 11B. At 1124, the architectural override is checked so that the uop may not need a PRN already owned by it and allocated to the uop from the free list (e.g., the PRN allocated to the uop from the PRN load / store (LS) / execute (EX) first-in-first-out (FIFO) in the previous pipeline stage). If there is no architectural override, at 1126, the PRN allocated by the renaming process is used. Otherwise, at 1128, the PRN allocated by the renaming process is returned to the free list and the PRN allocated by the LS or EX FIFO is used instead.

[0074] In an example of allocating a PRN during renaming, with further reference to FIG. 4, PRN04 can be a paired PRN. For the current uop read from dispatch, if the uop size is less than 512 and there is no SSE merge, during renaming, the availability of the stored split PRN is checked. If there is a stored split PRN that is available and not yet allocated, this stored split PRN is allocated to the current uop. If the stored split PRN is available but allocated to another uop, the availability of the corresponding second part (which may be split in this cycle) is checked. If the second part is available, it is allocated to the current uop. Otherwise, PRN04 is split and its first part is allocated to the current uop. After splitting PRN04, PRN05 may be allocated to another uop in this cycle or stored for use in the next cycle. If there is an SSE merge, the current uop may be an SSE merge operation, or otherwise, an instruction of size 512 such that a paired PRN can be allocated. Alternatively, if PRN04 is a single PRN and the current uop is not an SSE merge operation (or a 512-bit instruction), PRN04 can be allocated to the current uop.

[0075] The systems and methods described herein provide flexibility in allocating free registers during the rename stage of a processor's instruction pipeline. In one example, a processor architecture can support 512-bit instructions that require 512-bit registers. The processor can have 384 physical registers, each 256 bits, organized into 192 pairs of physical registers such that each pair of physical registers meets the 512-bit size. To simplify register management, the processor can track 512-bit registers as 256-bit shadow (physical) registers for renaming and paired 256-bit physical registers, and 384 single physical registers for maintaining a complete list of returned physical register numbers.

[0076] The processor can further support smaller instructions such as 256-bit instructions, 128-bit instructions, etc. 512-bit registers may be used for smaller instructions, but shadow registers may not be used for smaller instructions. Enabling the use of shadow registers can increase the performance of the number of instructions per cycle of the processor. The shadow registers can be used by changing the renaming scheme to map each physical register of a pair as a high or low logical register number. For example, one 512uop that requires one 512-bit physical register can be converted into two 256uop that require two 256-bit physical registers. However, such mapping can add unduly complexity and overhead to the renaming stage. Such changes may require effectively doubling the queue size. For example, two uops may need to track the high and low logical register numbers mapped to two physical registers. Therefore, instead of one instruction being held in the retirement queue, scheduler queue, and other queues, two or more instructions need to be held, effectively degrading processor performance.

[0077] The systems and methods described herein can advantageously reduce the overhead for managing shadow registers. Instead of managing each physical register individually, the systems and methods described herein can manage physical register pairs (e.g., manage pairs using the derived pair register list 460 and manage 192 single registers using the derived single register list 461). For example, a processor can manage 192 register pairs. Since the registers can be split as needed, the normal renaming queue may not need to be doubled. Split registers can be tracked based on their original register pairs using a bit vector indicating whether the register has been split and another bit vector indicating whether the split parts are free. In some examples, the control circuit 112 can allocate single registers that are free for a uop. Thus, the systems and methods described herein can enable efficient use of shadow registers and / or all registers. This approach can be extended within a processor to enable only the allocation of appropriate physical registers to an appropriate instruction width without doubling queues, doubling renaming, efficiently using all registers, and supporting wide instructions.

[0078] As described above, the computing devices and systems described and / or shown herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those included within the modules described herein. In their most basic configuration, each of these computing devices(s) can include at least one memory device and at least one physical processor.

[0079] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile memory device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device can store, load, and / or maintain one or more of the modules described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), optical disk drive, cache, variations or combinations of one or more of these, or any other suitable storage memory.

[0080] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor can access and / or modify one or more of the modules stored in the memory device described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field programmable gate arrays (FPGAs) implementing softcore processors, application specific integrated circuits (ASICs), system on chips (SOCs), portions of one or more of these, variations or combinations of one or more of these, or any other suitable physical processor.

[0081] Although shown as individual elements, the modules described and / or shown herein may represent a single module or portion of an application. Additionally, in certain embodiments, one or more of these modules, when executed by a computing device, may represent one or more software applications or programs that can cause the computing device to perform one or more tasks. For example, one or more of the modules described and / or shown herein may represent modules that are stored and configured to operate on one or more of the computing devices or systems described and / or shown herein. Also, one or more of these modules may represent all or part of one or more dedicated computers configured to perform one or more tasks.

[0082] Additionally, one or more of the modules described herein may transform data, physical devices, and / or representations of physical devices from one form to another. For example, one or more of the units described herein may receive instruction data to be transformed, transform the instruction data, output the result of the transformation to determine whether to split a register, use the result of the transformation to split a register, and store the result of the transformation to manage the split register. Additionally or alternatively, one or more of the modules enumerated herein may transform a processor, volatile memory, non-volatile memory, and / or any other portion of a physical computing device from one form to another by executing on the computing device, storing data on the computing device, and / or otherwise interacting with the computing device.

[0083] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, as well as non-transitory-type media such as magnetic storage media (e.g., hard disk drives, tape drives, and floppy (registered trademark) disks), optical storage media (e.g., Compact Disk (CD), Digital Video Disk (DVD), and BLU-RAY (registered trademark) disks), electronic storage media (e.g., solid state drives and flash media), and other delivery systems.

[0084] The process parameters and the order of steps described and / or illustrated herein are provided as examples only and can be changed as desired. For example, the steps illustrated and / or described herein can be depicted or considered in a particular order, but these steps do not necessarily have to be executed in the order illustrated or described. The various exemplary methods described and / or illustrated herein can also omit one or more of the steps described or illustrated herein, or can include additional steps in addition to the disclosed steps.

[0085] The foregoing description is provided to enable those skilled in the art to make the best use of the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as exemplary and not restrictive. When determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0086] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and the claims are to be construed to permit both direct and indirect (i.e., via other elements or components) connections. Additionally, the term "a" or "an" as used in this specification and the claims is to be construed to mean "at least one of". Finally, for ease of use, the terms "including" and "having" (and their derivatives), when used in this specification and the claims, are interchangeable with the word "comprising" and have the same meaning.

Claims

1. It is a method, Detecting that the data unit size of an instruction is smaller than that of a pair of registers, Allocating the first portion of the pair register to the instruction, such that the second portion of the pair register remains available for allocation to an additional instruction, This includes marking a pair of registers as a divided register using a divided register list that tracks which pair of registers has been divided into a first part and a second part, method.

2. Detecting that the data unit size of the instruction is smaller than that of a pair register includes detecting the data unit size from at least one of the instruction width and architecture signals of the instruction. The method according to claim 1.

3. Marking the pair registers includes setting the bits of the pair registers in the partitioned register list. The method according to claim 1.

4. The partitioned register list traces the partitioned registers such that, based on an even or odd address value, the corresponding second portion has the other even or odd address value. The method according to claim 3.

5. If the first and second portions are empty, the process includes unmarking the pair registers in the partitioned register list. The method according to claim 3.

6. This includes selecting a first or second portion of the pair register from an available register list. The method according to claim 1.

7. The process includes marking the first portion as empty when the aforementioned instruction is completed. The method according to claim 1.

8. The process includes marking the second portion as empty when the aforementioned instruction is completed. The method according to claim 7.

9. The process includes marking the first and second portions as empty once the aforementioned instructions are completed. The method according to claim 1.

10. The data unit size corresponds to the instruction width of the instruction, The method according to claim 1.

11. The size of the pair register corresponds to the width of a wide instruction. The method according to claim 1.

12. The size of the register portion corresponds to half the width of the wide instruction. The method according to claim 11.

13. It is a method, Detecting the data unit size from the instruction's architecture signal, The detection of the data unit size of the aforementioned instruction being smaller than the register size, The above instruction involves selecting an empty register having the above-mentioned register size from the list of empty registers, Allocating the first portion of the selected register to the instruction, such that the second portion of the selected register remains available for allocation to an additional instruction, This includes marking the selected register as a partitioned register in a partitioned register list that tracks which pair of registers were partitioned into a first part and a second part, method.

14. The partitioned register list traces the partitioned registers such that, based on an even or odd address value, the corresponding second portion has the other even or odd address value. The method according to claim 13.

15. If the first and second portions are empty, the selected registers in the partitioned register list are unmarked. The method according to claim 13.

16. Each of the free registers is tracked as a pair of register parts within the free register list. The method according to claim 13.

17. The process includes marking the first portion as empty when the aforementioned instruction is completed. The method according to claim 13.

18. It is a system, Physical memory and It comprises at least one physical processor, The at least one physical processor is Multiple registers, It includes a control circuit for managing the allocation of registers for instructions, The aforementioned control circuit is For instructions with a data unit size smaller than that of a register, an available register is selected from the list of available registers among the multiple registers. Allocating the first portion of the selected register to the instruction, such that the second portion of the selected register remains available for allocation to an additional instruction, The selected registers are marked as partitioned registers in a partitioned register list that tracks which pair of registers were partitioned into a first part and a second part, It is configured to do, system.

19. Each of the free registers is tracked as a pair of register parts within the free register list. The system according to claim 18.

20. The first and second portions of the selected register are tracked within the list of available register portions. The system according to claim 18.

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