Gate trench power semiconductor device having a trench shield pattern formed during well injection and related methods

Abstract

A wide-bandgap semiconductor layer structure is provided, which includes a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided on the upper surface of the wide-bandgap semiconductor layer structure. A dopant of a second conductivity type is implanted into the wide-bandgap semiconductor layer structure such that a well region directly below the source region and a trench shield region directly below the trench are simultaneously formed, and the well region and the trench shield region each have the second conductivity type.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority of U.S. Patent Application No. 17 / 845,120, filed on June 21, 2022, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices, and more particularly, to power semiconductor devices having gate trenches and methods of manufacturing such devices.

Background Art

[0003] A metal - insulating - semiconductor field - effect transistor (MISFET) is a well - known type of semiconductor transistor that may be used as a switching device. The MISFET is a three - terminal device having a gate terminal, a drain terminal, a source terminal, and a semiconductor body. The source region and the drain region are formed in the semiconductor body and are separated by a channel region, and the gate electrode (which may function as the gate terminal or may be electrically connected to the gate terminal) is disposed adjacent to the channel region. The MISFET can be turned on or off by setting the bias voltage applied to the gate electrode above or below a threshold value. When the MISFET is turned on (i.e., when the MISFET is in the "on state"), current flows through the channel region of the MISFET between the source region and the drain region. When the bias voltage is below the threshold level, current stops flowing through the channel region.

[0004] An n-type MISFET has a source region and a drain region with n-type (electron) conductivity, and a channel with p-type (hole) conductivity. Thus, an n-type MISFET has an "n-p-n" design. An n-type MISFET turns on when a gate bias voltage sufficient to form a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source region and drain region is applied to the gate electrode, thereby enabling majority carriers to flow between the source region and the drain region. A p-type MISFET has a "p-n-p" design and turns on when a gate bias voltage sufficient to form a conductive p-type inversion layer in the n-type channel region that electrically connects the p-type source region and drain region is applied to the gate electrode. In this specification, the terms "first conductivity type" and "second conductivity type" are used to indicate either n-type or p-type, and the first conductivity type and the second conductivity type are different. Thus, when a first region of a device has a first conductivity type and a second region of the device has a second conductivity type, this means that the first region has n-type conductivity and the second region has p-type conductivity, or the first region has p-type conductivity and the second region has n-type conductivity.

[0005] The gate electrode of a MISFET is separated from the channel region by a thin dielectric layer called a gate dielectric layer. Typically, a power MISFET implements a thin gate dielectric layer using an oxide layer such as a silicon oxide layer. A MISFET including an oxide gate dielectric layer is called a metal oxide semiconductor field effect transistor (MOSFET), and the gate dielectric layer is called a gate oxide layer. Since the oxide gate dielectric layer is almost always used due to its excellent properties, the description in this specification focuses on MOSFET rather than MISFET, but it should be understood that the techniques according to the embodiments of the invention described herein are equally applicable to devices having a gate dielectric layer formed of a material other than oxide.

[0006] Since the gate electrode of a MOSFET is insulated from the channel region by a gate oxide layer, a minimal gate current is required to keep the MOSFET in the on state or to switch the MOSFET between the on state and the off state. The gate current can be kept small during switching because the gate forms a capacitor with the channel region. Therefore, only a minimal charging and discharging current is required during switching, which can reduce the complexity of the gate drive circuit and increase the switching speed. A MOSFET may be a stand-alone device or may be combined with other circuit devices. For example, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) is a semiconductor device that includes both a MOSFET and a bipolar junction transistor (BJT: Bipolar Junction Transistor), and combines the high-impedance gate electrode of the MOSFET with the low on-state conduction loss that the BJT can provide. The IGBT may be implemented, for example, as a Darlington pair that includes a high-voltage n-channel MOSFET at the input and a BJT at the output. Since the base current of the BJT is supplied through the channel of the MOSFET, the external drive circuit can be simplified (because the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0007] In some applications, a MOSFET may need to conduct a large current and / or may need to be able to block a high voltage. Such MOSFETs are often referred to as "power" MOSFETs. Power MOSFETs are often manufactured from wide-bandgap semiconductor materials such as silicon carbide (referred to herein as the "wide-bandgap semiconductor" term encompasses any semiconductor having a bandgap of at least 1.4 eV), and silicon carbide has many advantageous properties including, for example, a high electric field breakdown strength, a high thermal conductivity, a high electron mobility, a high melting point, and a high saturated electron drift velocity.

[0008] Power semiconductor devices such as power MOSFETs can have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain terminal, gate terminal, and source terminal of a power MOSFET) are on the same major surface (i.e., the top surface or the bottom surface) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include a substrate such as a growth substrate. In this specification, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0009] The semiconductor layer structure of a power semiconductor device typically includes an "active region" having one or more functional semiconductor devices with junctions such as p-n junctions. The active region functions as the main junction for blocking voltage during reverse bias operation and supplying current during forward bias operation. The power semiconductor device may have an edge termination in the termination region of the semiconductor layer structure adjacent to the active region. Typically, a plurality of power semiconductor devices are formed within / on a common semiconductor layer structure, and each power semiconductor device typically has its own edge termination. After the semiconductor layer structure is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices. Each power semiconductor device can have a unit cell structure in which the active regions of each power semiconductor device include a plurality of individual "unit cell" devices that are electrically connected in parallel and function together as a single power semiconductor device.

[0010] A vertical power semiconductor device including a MOSFET transistor can have a standard gate electrode design in which the gate electrode of the transistor is formed at the top of the semiconductor layer structure, or alternatively, the gate electrode may be embedded in a trench within the semiconductor layer structure. A MOSFET having an embedded gate electrode is typically referred to as a gate-trench MOSFET. In a standard gate electrode design, the channel region of each unit cell transistor is disposed horizontally directly beneath the gate electrode. In contrast, in a gate-trench MOSFET design, the channel is disposed vertically. Gate-trench MOSFETs can offer high performance but typically require a more complex manufacturing process.

[0011] One of the failure mechanisms of a power MOSFET is the so-called "dielectric breakdown" of the gate oxide layer. When the power MOSFET is in the conducting or "on" state, the gate oxide layer is exposed to a high electric field. Due to the stress generated in the gate oxide layer by these electric fields, defects that accumulate over time are generated in the oxide material. When the concentration of defects reaches a critical value, a so-called "percolation path" may be generated through the gate oxide layer, which electrically connects the gate electrode to the source region or the drain region, thereby generating a short circuit that may destroy the device. The "lifetime" of the gate oxide layer (i.e., how long the device can operate before dielectric breakdown occurs) is a function of, among other things, the magnitude of the electric field to which the gate oxide layer is exposed and the length of time the electric field is applied. FIG. 1 is a schematic graph showing the relationship between the operating time until dielectric breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This graph assumes that the same electric field is always applied (which is not necessarily the case) and that the gate oxide layer has a certain thickness. As shown in FIG. 1, this relationship may be approximately linear in some cases when the gate oxide lifetime is plotted on a logarithmic scale. An important point obtained from FIG. 1 is that as the electric field level increases, the lifetime of the gate oxide layer decreases exponentially. Although the lifetime of the gate oxide layer can be extended by increasing its thickness, various performance parameters of the MOSFET may be functions of the thickness of the gate oxide layer, and therefore, increasing the thickness of the gate oxide layer is typically not accepted as a way to extend the lifetime of the gate oxide layer. SUMMARY OF THE INVENTION

[0012] According to some embodiments of the present invention, a method of manufacturing a semiconductor device is provided. According to these methods, a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type and a source region having the first conductivity type on the drift region is provided, and the wide-bandgap semiconductor layer structure includes a trench therein. A dopant of a second conductivity type is implanted into the wide-bandgap semiconductor layer structure such that both a well region directly under the source region and a trench shield region directly under the trench are formed simultaneously, and the well region and the trench shield region each have the second conductivity type.

[0013] In some embodiments, the trench may extend into the drift region through the source region.

[0014] In some embodiments, the dopant of the second conductivity type may be implanted into the drift region through the source region.

[0015] In some embodiments, the well region may be formed by converting a part of the drift region having the first conductivity type into a well region having the second conductivity type.

[0016] In some embodiments, the well region can separate the source region from the drift region.

[0017] In some embodiments, the source region can form the upper parts of both the first sidewall and the second sidewall of the trench, the drift region can form the lower parts of the first sidewall and the second sidewall, and the first sidewall faces the second sidewall.

[0018] In some embodiments, when the dopant of the second conductivity type is implanted into the wide-bandgap semiconductor layer structure, the first sidewall of the trench may be exposed.

[0019] In some embodiments, the method may further include performing an oxidation process to convert at least first and second sidewalls and a bottom of the trench into an oxide material, and removing the oxide material to convert the trench into an enlarged trench.

[0020] In some embodiments, the wide-bandgap semiconductor layer structure may extend in a length direction, a width direction, and a depth direction that are perpendicular to each other, and a lower surface of the wide-bandgap semiconductor layer structure may extend in the length direction and the width direction.

[0021] In some embodiments, the source region may extend a first distance in the depth direction, the shield region may extend a second distance in the depth direction, and the second distance may exceed the first distance.

[0022] In some embodiments, the second distance may be at least 1.5 times or at least 2 times the first distance.

[0023] In some embodiments, a part of the well region extending to the upper surface of the wide-bandgap semiconductor layer structure may extend a third distance in the depth direction, and the third distance may be substantially the same as the second distance.

[0024] In some embodiments, the concentration of the dopant of the second conductivity type in the source region is at least 5×10 15 / cm 3 It may be.

[0025] In some embodiments, the doping profile of the dopant of the second conductivity type in a part of the well region directly below the source region varies by less than 15% from the doping profile of the dopant of the second conductivity type in the lower part of the shield region extending longitudinally directly below the center of the bottom of the trench.

[0026] In some embodiments, the method can further include injecting a dopant of a second conductivity type into the wide bandgap semiconductor layer structure directly below the trench.

[0027] In some embodiments, the dopant of the second conductivity type and the additional dopant of the second conductivity type may be injected using the same ion implantation mask. In some embodiments, the additional dopant of the second conductivity type may be injected before the dopant of the second conductivity type is injected.

[0028] In some embodiments, the method can further include forming a mask on the sidewalls of the trench before injecting the additional dopant of the second conductivity type into the wide bandgap semiconductor layer structure.

[0029] In some embodiments, the upper surface of the source region may be exposed when the additional dopant of the second conductivity type is injected into the wide bandgap semiconductor layer structure.

[0030] In some embodiments, the method further includes injecting an additional dopant of a second conductivity type into the wide bandgap semiconductor layer structure directly below the trench. In some embodiments, the additional dopant of the second conductivity type may be injected before an oxidation process that converts at least the first and second sidewalls and the bottom of the trench to an oxide material is performed.

[0031] In some embodiments, the upper surface of the source region may be exposed when the dopant of the second conductivity type is injected into the wide bandgap semiconductor layer structure.

[0032] In some embodiments, the step of providing a wide-bandgap semiconductor layer structure includes forming a drift region on the upper surface of a wide-bandgap semiconductor substrate having a first conductivity type, and forming a source region by implanting dopant ions of the first conductivity type on the upper surface of the drift region, wherein the source region has a higher concentration of dopant of the first conductivity type than the drift region, and forming a trench on the upper surface of the wide-bandgap semiconductor layer structure.

[0033] In some embodiments, the method may further include implanting a dopant of a second conductivity type into the semiconductor layer structure to form first and second support shields in the semiconductor layer structure on each of the first and second sides of the trench.

[0034] In some embodiments, the method may further include sequentially forming a gate oxide layer and a gate electrode in the trench.

[0035] In some embodiments, the method may further include forming a trench shield region connection region that electrically connects the trench shield region to the well region.

[0036] According to a further embodiment of the present invention, a semiconductor device including a wide-bandgap semiconductor layer structure is provided, the wide-bandgap semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region having a first conductivity type on the well region, a gate electrode in the trench, and a shield region having a second conductivity type directly below the gate trench, wherein the doping profile of the dopant of the second conductivity type in a part of the well region directly below the source region varies by less than 15% from the doping profile of the dopant of the second conductivity type in the lower part of the shield region extending longitudinally directly below the center of the bottom of the trench.

[0037] In some embodiments, the well region may be between the drift region and the source region, and the trench may extend into the drift region through the source region and the well region.

[0038] In some embodiments, the semiconductor layer structure may extend in a length direction, a width direction, and a depth direction that are perpendicular to each other, and the lower surface of the semiconductor layer structure may extend in the length direction and the width direction.

[0039] In some embodiments, the source region may extend a first distance in the depth direction, the shield region may extend a second distance in the depth direction, and the second distance may exceed the first distance.

[0040] In some embodiments, the second distance may be at least 1.5 times or at least 2 times the first distance.

[0041] In some embodiments, the semiconductor device may further include first and second support shields having a second conductivity type within the wide-bandgap semiconductor layer structures on each of the first and second sides of the trench, and the first and second support shields extend closer to the bottom surface of the wide-bandgap semiconductor layer structure than the shield region.

[0042] In some embodiments, the concentration of the dopant of the second conductivity type in the upper part of the shield region may exceed the concentration of the dopant of the second conductivity type in the source region.

[0043] In some embodiments, the average concentration of the dopant of the second conductivity type in the upper half of the shield region may exceed the average concentration of the dopant of the second conductivity type in the lower half of the shield region.

[0044] In some embodiments, the drift region, the well region, the source region, and the shield region include silicon carbide.

[0045] According to a further embodiment of the present invention, a semiconductor device is provided with a wide-bandgap semiconductor layer structure, the wide-bandgap semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region having a first conductivity type on the well region, a gate electrode in a trench, and a shield region having a second conductivity type directly below the trench, the shield region extending downward by a first distance from the bottom of the trench into the semiconductor layer structure, the well region extending downward by a second distance from the upper surface of the semiconductor layer structure into the semiconductor layer structure, and the first distance being within + / - 10% of the second distance.

[0046] In some embodiments, the well region may be between the drift region and the source region, and the trench may extend through the source region and the well region into the drift region.

[0047] In some embodiments, the source region may extend downward by a third distance from the upper surface of the semiconductor layer structure into the semiconductor layer structure, and the first distance exceeds the third distance.

[0048] In some embodiments, the first distance is at least 1.5 times or at least 2 times the third distance.

[0049] In some embodiments, the semiconductor device may further include first and second support shields having a second conductivity type within the wide-bandgap semiconductor layer structure on each of the first and second sides of the trench, and the first and second support shields extend closer to the bottom surface of the wide-bandgap semiconductor layer structure than the shield region.

[0050] In some embodiments, the concentration of the dopant of the second conductivity type at the upper part of the shield region may exceed the concentration of the dopant of the second conductivity type in the source region.

[0051] In some embodiments, the drift region, the well region, the source region, and the shield region may include silicon carbide.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0053] Vertical silicon carbide-based power semiconductor devices having gate trenches, such as vertical power MOSFETs and IGBTs, are attractive for many applications because their inherent on-resistance is relatively low, which can result in more efficient operation for power-switching operations. Gate-trench vertical power devices exhibit lower specific resistance during on-state operation because the channel is formed on the sidewalls of the gate trenches. Furthermore, the carrier mobility of the sidewall channels of gate-trench power devices can be about two to four times higher than the corresponding carrier mobility of the horizontal channels of standard (i.e., non-gate-trench) vertical power devices. This improvement in channel mobility leads to an increase in current density during on-state operation and enables a higher switching speed. Additionally, the trench design allows for a reduction in the overall pitch of the device, enabling an increase in integration density. The reduction in conduction losses (due to the decrease in on-state resistance) and the improvement in switching speed make gate-trench power devices well-suited for high-frequency power applications with low to medium voltage blocking requirements (e.g., 600 - 1200 volts). These devices have fewer requirements for associated passive components, are low-cost and lightweight, and have a relatively simple cooling method required. Since MOSFETs are the most widely used silicon carbide-based trench-type power semiconductor gate devices, the following description will focus primarily on examples of MOSFETs. However, it will be understood that each of the described examples may alternatively be implemented using a non-oxide gate dielectric layer (e.g., nitride, high-k materials, etc.), and that the same technology can be used to form other gate-trench power semiconductor devices such as IGBTs, gate-controlled thyristors, etc.

[0054] A gate trench power MOSFET is susceptible to oxide reliability problems because a high electric field exists in the gate oxide layer that lines the bottom and sidewalls of the gate trench. The high electric field can deteriorate the gate oxide layer over time and ultimately lead to device failure. The highest electric fields occur in the corner regions of the gate oxide layer where the electric field level can increase dramatically due to the electric field crowding effect. When the gate trench MOSFET operates in reverse blocking mode (i.e., when the MOSFET is in the off state), the source terminal of the MOSFET is typically grounded, the gate terminal is typically grounded or biased to a negative voltage, and a high positive voltage is typically applied to the drain terminal. Under such reverse blocking operation, a high electric field extends upward from the drain terminal (which is on the bottom surface of the semiconductor layer structure) toward the top surface of the semiconductor layer structure. Thus, under reverse blocking operation, the bottom of the gate dielectric layer experiences the highest electric field level. Due to the electric field crowding effect, the electric field level at the lower corner of the gate oxide layer at the bottom edge of the gate trench can be particularly high. Additionally, due to the difference in dielectric constants between silicon carbide and silicon dioxide, the electric field in the silicon dioxide gate dielectric layer can be approximately 2.6 times higher than the electric field in the adjacent silicon carbide. When the electric field reaches the critical level Ecr, dielectric breakdown of the silicon oxide occurs. Therefore, the MOSFET may be operated at a lower drain voltage level during reverse blocking operation so that the electric field does not reach the level that causes dielectric breakdown.

[0055] To reduce the electric field level in the gate oxide layer during the reverse blocking operation, a so-called "trench shield region" is often provided directly below the gate trench of a conventional gate-trench power MOSFET. These trench shield regions include a highly doped semiconductor layer having the same conductivity type as the channel region of the device. The trench shield region may extend downward, for example, 0.5 to 1.0 micron or more from the bottom surface of the gate trench into the semiconductor layer structure of the device. The protection provided by these trench shield regions to the gate oxide layer increases as the depth of the trench shield region increases. The trench shield region may extend further laterally than the sidewalls of the trench and / or may extend along the lower side surface of the trench in some cases. The trench shield region is electrically connected to the source terminal of the MOSFET by a trench shield region connection pattern. The trench shield region is typically formed by an ion implantation process to the bottom surface of the gate trench. However, if the channel region of the sidewall of the gate trench is not masked during this ion implantation process, the doping concentration of the channel region may be adversely affected by the implantation process, which may degrade the device performance. As will be described below, according to an embodiment of the present invention, the same implantation can be used to form both the channel region and the trench shield region, thereby omitting the masking step (which increases the manufacturing cost) and at the same time enabling a deeper trench shield region.

[0056] Figures 2A through 2G and 2I are schematic vertical cross-sectional views showing a method of manufacturing a conventional silicon carbide-based gate-trench vertical power MOSFET 1. Figure 2H is a schematic horizontal cross-sectional view of the gate-trench vertical power MOSFET 1. As used herein, a vertical cross-sectional view of a power semiconductor device refers to a view of a cross-section of the device cut along a plane perpendicular to the main surface of the semiconductor layer structure of the device. Similarly, a horizontal cross-sectional view of a power semiconductor device refers to a view of a cross-section of the device cut along a plane parallel to the main surface of the semiconductor layer structure of the device.

[0057] As shown in FIG. 2A, the heavily doped (n + ) n-type silicon carbide substrate 10 on which lightly doped (n - ) A silicon carbide drift region 20 is formed. A moderately doped (p) p-type silicon carbide well layer 30 is formed on top of the n-type drift region 20 by epitaxial growth or, more commonly, by implanting p-type dopant ions into the top of the n-type drift region 20.

[0058] Referring to FIG. 2B, a heavily doped n + A silicon carbide source layer 40 is formed, for example by ion implantation, on top of the p-type silicon carbide well layer 30. The silicon carbide substrate 10, drift region 20, well layer 30, and source layer 40, together with various regions formed therein, constitute a semiconductor layer structure 50 of the power MOSFET 1.

[0059] Referring to FIG. 2C, the semiconductor layer structure 50 is implanted with p-type dopant ions to form a heavily doped p +A trench support shield 60 of silicon carbide is formed. To form the trench support shield 60, an ion implantation mask 62 is formed on the upper surface of the semiconductor layer structure 50. As shown in FIG. 2C, the ion implantation mask 62 is patterned to form an opening above the region of the semiconductor layer structure 50 where the trench support shield 60 is to be formed. Then, the trench support shield 60 is formed by ion implantation, and thereafter, the ion implantation mask 62 is removed. The trench support shield 60 may extend 0.5 to 10 microns in the depth direction (z direction) of the semiconductor layer structure 50. Alternatively, the trench support shield 60 may be formed before the formation of the source layer 40. The trench support shield 60 helps to reduce the electric field level of the gate oxide layer (described later) of the MOSFET1 and helps to prevent premature dielectric breakdown of the gate oxide layer. The trench support shield 60 also provides a low-resistance current path between the source terminal and the drain terminal of the MOSFET1 when the MOSFET undergoes avalanche breakdown. This low-resistance current path helps to reduce the amount by which the device is heated during an avalanche breakdown event and increases the likelihood that the MOSFET can withstand such events without being damaged.

[0060] Referring to FIG. 2D, next, an etching process may be performed to form a plurality of gate trenches 70 on the upper surface of the semiconductor layer structure 50. Each gate trench 70 may extend in a first direction (i.e., parallel to the main surface of the semiconductor layer structure 50) laterally across the length (or width) of the power MOSFET1. In FIGS. 2A-2G and 2I, the first direction is shown as being toward the paper surface and being the x direction. As shown, the gate trenches 70 may penetrate the source layer 40 and the well layer 30 and extend perpendicularly in a third direction (i.e., shown as the z direction, which is orthogonal to the main surface of the semiconductor layer structure) into the drift region 20, and the gate trenches 70 may be spaced apart from each other in a second direction (here, the y direction, which is orthogonal to the first and third directions). By the gate trenches 70, the moderately doped p-type silicon carbide well layer 30 is converted into a plurality of moderately doped p-wells 32, and the highly doped n-type silicon carbide source layer 40 is converted into a plurality of highly doped n-type source regions 42. The portion of each p-well 32 adjacent to the gate trench 70 functions as a transistor channel 34, as will be described below.

[0061] Referring to FIG. 2E, a spacer 78, such as an oxide spacer, is formed on the sidewalls of the gate trenches 70. The spacer 78 may be formed by thermal oxidation of silicon carbide or by depositing an oxide and then performing blanket etching (in this etching, since the horizontal plane is etched faster than the vertical plane, the oxide on the upper surface of the semiconductor layer structure and the bottom of the trench is removed while most of the oxide spacer remains). Next, by blanket implanting p-type ions on the upper surface of the semiconductor layer structure 50, via ion implantation, a highly doped (p +)A p-type silicon carbide trench shield region 80 is formed. Typically, the sidewalls of the gate trenches 70 are not perfectly vertical such that the upper part of each gate trench 70 is slightly wider than its lower part. For example, the sidewalls may form an angle of 95 to 105 degrees or more with respect to the bottom surface of the trench. Thus, if the spacers 78 are not formed, some p-type ions will be directly implanted into the sidewalls of the gate trenches 70. Additional p-type ions may scatter from the bottom surface of the gate trenches 70, and some of these ions will also be implanted into the sidewalls of the gate trenches 70. The spacers 78 can substantially prevent p-type ions from being implanted into the sidewalls of the gate trenches 70, thereby preventing the p-type ions implanted to form the trench shield region 80 from changing the doping concentration of the channel region 34 and / or converting the lower part of the sidewalls, which is part of the n-type drift region 20, into a p-type material.

[0062] Since the upper surface of the semiconductor layer structure 50 is exposed, a relatively low ion implantation energy is used during the ion implantation step performed to form the trench shield region 80, whereby the p-type dopant is implanted only to a depth in the depth direction (z-direction) below the depth of the source region 42 from the upper surface of the semiconductor layer structure 50. This ensures that the implantation step used to form the trench shield region 80 does not substantially change the doping concentration of the well region 32. The trench shield region 80 may extend along the entire length of each gate trench 70 (e.g., along the x-direction).

[0063] Referring to FIG. 2F, next, the sidewall spacers 78 may be removed using oxide etching.

[0064] Referring to FIG. 2G, a gate insulating layer 72 is formed on the bottom surface and side walls of each gate trench 70. Typically, the gate insulating layer 72 is an oxide layer and is thus referred to herein as the gate oxide layer 72. On each gate oxide layer 72, a gate electrode 74 is formed to fill each gate trench 70. An intermetal dielectric layer 76 is formed on the exposed portion of the gate electrode 74, and a source contact 90 is formed on the upper portion of the device. The source contact 90 is physically and electrically connected to the n-type source region 42. The p-well extension 36 physically and electrically connects the p-well 32 to the source contact 90 in a selected region of the device (see the plan view of FIG. 2H) that is not visible in the cross-sectional view of FIG. 2G. The source contact 90 may constitute the source terminal of the MOSFET1 or may be electrically connected to the source terminal. A drain contact 92 is formed on the lower surface of the substrate 10. Typically, a gate contact (not shown) connected to the gate electrode 74 via one or more gate buses (not shown) is also provided outside the cross-sectional view of FIG. 2D.

[0065] FIG. 2H is a horizontal cross-section of the device shown in FIG. 2G cut along line 2H-2H (i.e., this cross-section is taken along the upper surface of the semiconductor layer structure 50). FIG. 2H shows how the p-well extension 36 constitutes a series of islands that extend upward through the source region 42 to the upper surface of the semiconductor layer structure 50. FIG. 2I is a vertical cross-sectional view taken along line 2I-2I of FIG. 2H, showing the p-well extension 36 and the trench shield region connection pattern 38 that electrically connects the illustrated trench shield region 80 to the p-well extension 36. The trench shield region connection pattern 38 and the p-well extension 36 may be highly doped (p + ) p-type regions.

[0066] The trench shield region 80 serves to protect the corners of the gate oxide layer 72 from high electric fields during reverse blocking operation. However, the above-described conventional process for manufacturing the power MOSFET1 has at least two potential drawbacks.

[0067] First, the doping concentration of the channel region 34 of the silicon carbide power MOSFET 1 is typically very carefully controlled to ensure optimal device performance. Therefore, measures are typically taken to ensure that the doping concentration of the channel region 34 does not change due to the ion implantation step performed to form the trench shield region 80. In some cases, this measure may be achieved by forming an ion implantation mask over the source region 42 during the ion implantation step used to form the trench shield region 80 (this mask prevents p-type dopant ions from reaching the n-type source region 42). However, forming and removing this ion implantation mask increases the time and cost of manufacturing the device. As described above, in other cases, the masking step can be omitted, and instead, the trench shield region 80 may be formed to extend in the depth direction at a distance shallower than the depth of the source region 42 (this also ensures that the doping concentration of the channel region 34 does not increase). However, the shallow trench shield region 80 formed when not using an ion implantation mask provides weaker protection for the gate oxide layer 72 during reverse blocking operation. Therefore, using such a shallow trench shield region 80 may compromise the reliability of the MOSFET 1. The support shield regions 60 may improve the level of protection (and thus reliability), but forming these support shield regions 60 requires additional processing steps, increasing the manufacturing time and cost, and still does not provide the same level of protection as provided by the deep trench shield region. Adding the support shield regions 60 may also reduce the integration density of the MOSFET 1.

[0068] Second, as described above, spacers 78 are formed on the sidewalls of the gate trench 70 to prevent p-type ions from being implanted into the sidewalls of the gate trench 70 during the ion implantation process used to form the trench shield region 80. To form these spacers 78, an extra processing step is required because the spacer material must be selectively deposited on the sidewalls or, after blanket deposition, selectively removed from regions other than the sidewalls of the gate trench 70. These extra steps increase the processing time and cost.

[0069] According to an embodiment of the present invention, an improved technique for forming a trench shield region in a gate trench power semiconductor device is disclosed. In particular, the trench shield region may be at least partially formed during the ion implantation process used to form the well region, or may be formed prior to the formation of any source layer / region. In other words, the trench shield region and the p-well can be formed simultaneously by a single ion implantation process. Since the p-well is typically a relatively deep structure, the process according to an embodiment of the present invention enables the formation of a relatively deep trench shield region. In some embodiments, the source layer is doped with a first conductive dopant and is doped at a substantially higher concentration than the well region and the trench shield region, so that a second (opposite) conductive type dopant implanted into the source layer during the ion implantation step used to form the well region and the trench shield region does not substantially affect the doping concentration of the source layer. In other embodiments, the source layer may be doped at a higher concentration than desired so that there is an extra first conductive type dopant to cancel out the second (opposite) conductive type dopant implanted into the source layer during the ion implantation step used to form the well region and the trench shield region.

[0070] Since this ion implantation step is used to form both the well region and the trench shield region, there is no need to mask the semiconductor layer structure during the ion implantation step, yet a much deeper trench shield region can still be formed. Further, since the trench shield region may extend deeper within the semiconductor layer structure directly beneath the gate trench, the ion implantation step used to form the well region and the trench shield region may, in some embodiments, be performed without forming spacers on the sidewalls of the gate trench. Instead, ion implantation may be performed with the sidewalls of the gate trench exposed, and then the device may be subjected to an oxidation step that oxidizes that exposed surface (thus oxidizing portions of the sidewalls that were unintentionally implanted during the ion implantation step), and then the oxide formed by this process may be removed using oxide etching. This oxide etching reduces the distance that each trench shield pattern extends in the depth direction (since the upper portion of the trench shield pattern is oxidized and then removed), but this reduction is acceptable since these regions may initially be formed to extend much deeper in the depth direction. Thus, the above-described techniques for manufacturing the trench shield region may significantly simplify the device manufacturing process.

[0071] According to some embodiments of the present invention, a method of manufacturing a semiconductor device such as a power semiconductor device is provided. According to these methods, a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region is provided. A plurality of trenches are provided on the upper surface of the wide-bandgap semiconductor layer structure. The trenches may extend through the source regions and into the drift region. A dopant of a second conductivity type is implanted into the wide-bandgap semiconductor layer structure such that a well region directly beneath the source regions and a trench shield region directly beneath the trenches are simultaneously formed, and the well region and the trench shield region each have the second conductivity type.

[0072] The dopant of the second conductivity type may be implanted into the drift region through the source region to convert a part of the drift region having the first conductivity type into a well region having the second conductivity type. In some cases, when the dopant of the second conductivity type is implanted into the wide-bandgap semiconductor layer structure, the sidewalls of the trench may be exposed. In such an embodiment, an oxidation process may be performed after the well region and the trench shield region are formed, and the sidewalls and the bottom of the trench may be converted into an oxide material. Then, the oxide material may be removed and the trench may be converted into an enlarged trench. Using this oxidation and removal process, a portion of the sidewall of the trench unintentionally implanted during the formation of the well region and the trench shield region can be removed.

[0073] In some embodiments, the source region may extend in the depth direction by a first distance, and the shield region may extend in the depth direction by a second distance, and the second distance may exceed the first distance. For example, the second distance may be at least 1.5 times the first distance, or at least 2 times or 3 times the first distance. In some embodiments, a portion of the well region extending to the upper surface of the wide-bandgap semiconductor layer structure may extend in the depth direction by a third distance, and the third distance may be substantially the same as the second distance.

[0074] In some embodiments, the doping profile of the lower part of the trench shield region taken along a first axis extending in the depth direction through the center of the bottom of the gate trench varies by less than 15% from the doping profile of the well region taken along a second axis extending through the well region and parallel to the first axis.

[0075] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region including the first conductivity type on the well region, a gate electrode structure in a trench, and a shield region including the second conductivity type directly under the gate trench. In some embodiments, the shield region extends downward by a first distance from the bottom of the trench into the semiconductor layer structure, the well region extends downward by a second distance from the upper surface of the semiconductor layer structure into the semiconductor layer structure, and the first distance is within + / - 10% of the second distance (or, in other embodiments, within + / - 5% of the second distance). In other embodiments, the doping profile of the dopant of the second conductivity type in a part of the well region directly under the source region varies by less than 15% from the doping profile of the dopant of the second conductivity type in the lower part of the shield region extending longitudinally directly under the center of the bottom of the trench.

[0076] Next, with reference to FIGS. 3A - 5, embodiments of the present invention will be described in more detail. It will be understood that the features of the different embodiments disclosed herein may be combined in any manner to provide many additional embodiments. Thus, while various features of the present invention are described below with respect to specific examples, these features may be added to other embodiments and / or used in place of the exemplary features of other embodiments to provide many additional embodiments. Accordingly, the present invention should be understood to encompass these different combinations. Further, while the exemplary embodiments focus on embodiments of MOSFETs, it will be understood that the same techniques can be used in other gate - trench power semiconductor devices such as insulated gate bipolar transistors (IGBTs), gate - controlled thyristors, and the like.

[0077] Figs. 3A to 3L are schematic cross-sectional views showing the gate-trench power MOSFET 100 according to an embodiment of the present invention. More specifically, Figs. 3A to 3I are schematic vertical cross-sectional views showing a method of manufacturing the semiconductor layer structure of the gate-trench power MOSFET 100. Fig. 3K is a schematic horizontal cross-sectional view of the MOSFET 100 after the metallization is added, and Figs. 3J and 3L are schematic vertical cross-sectional views taken along lines 3J-3J and 3L-3L of Fig. 3K, respectively.

[0078] Referring to Fig. 3A, an n-type silicon carbide substrate 110 is provided. The substrate 110 can include, for example, a 4H-silicon carbide or 6H-silicon carbide substrate. In other embodiments, the substrate 110 may be a different semiconductor material (e.g., a group III nitride-based material, silicon, gallium arsenide, zinc oxide, etc.) or a non-semiconductor material (e.g., sapphire), or may include these. The substrate 110 may be doped at a high concentration with n-type impurities (n + ) (i.e., an n + silicon carbide substrate). The impurities can include, for example, nitrogen or phosphorus. The doping concentration of the substrate 110 may be, for example, 1×10 18 atoms / cm 3 ~1×10 21 atoms / cm 3 , but other doping concentrations may be used. The substrate 110 may be relatively thick in some embodiments (e.g., 20 to 100 microns or more). Although the substrate is shown as a relatively thin layer in the figure, it should be noted that this is done to enable the thicknesses of other layers and regions in the figure to be enlarged, and it will be understood that the substrate is typically much thicker than shown. Similarly, the thicknesses of various other layers of the MOSFET according to embodiments of the present invention may not be shown to scale in the figure so that other parts of the device can be enlarged.

[0079] doped at a low concentration (n -)The drift region 120 of silicon carbide may be provided on the substrate 110. The n-type drift region 120 can be formed, for example, by epitaxially growing it on the substrate 110. The n-type drift region 120 can have a doping concentration of, for example, 5×10 15 ~5×10 17 dopants / cm 3 . The n-type drift region 120 may be a thick region with a vertical height above the substrate 110 of, for example, 3 to 50 microns. In some embodiments, the upper part of the n-type drift region 120 may include an n-type current diffusion layer (not shown) doped at a higher concentration than the lower part of the n-type drift region 120.

[0080] doped at a low concentration (n - ) In the upper region of the drift region 120 of silicon carbide, a source layer 140 of (n + ) n-type silicon carbide doped at a high concentration is formed. The source layer 140 of n-type silicon carbide doped at a high concentration is typically formed by ion implantation to provide a more consistent doping density, but alternatively, it can also be formed by epitaxially growing it on the drift region 120 of silicon carbide. The source layer 140 of n-type silicon carbide doped at a high concentration can have a doping concentration of, for example, 1×10 19 atoms / cm 3 ~5×10 21 atoms / cm 3 . The silicon carbide substrate 110, the drift region 120, and the source layer 140, together with various regions / patterns formed therein, such as well regions and various shield regions (described later), constitute the semiconductor layer structure 150 of the power MOSFET 100.

[0081] Referring to FIG. 3B, a mask 162 is formed on the upper surface of the source layer 140. The mask 162 is patterned to form an opening that exposes a selected portion of the semiconductor layer structure 150. Then, an ion implantation process is performed to implant a p-type dopant into the exposed portion of the semiconductor layer structure 150, forming a trench support shield 160. The trench support shield 160 is a p-type region. The trench support shield 160 can have a maximum doping concentration of about 1×10 20 and may extend from the upper surface of the semiconductor layer structure 150 to a depth of 0.5 to 10 microns. If the trench support shield 160 is not provided, typically, it is necessary to significantly increase the doping concentration of the trench shield region formed in a subsequent processing step. Even if the doping level is increased in this way, the electric field of the gate oxide layer (described later) of the device will be high. The ion implantation mask 162 is removed after the trench support shield 160 is formed.

[0082] Referring to FIG. 3C, a plurality of gate trenches 170 are formed on the upper surface of the semiconductor layer structure 150 through etching. Only one complete gate trench 170 and a part of the second gate trench 170 are shown in FIG. 3C, but typically a number of gate trenches 170 are provided. Each gate trench 170 extends in a first direction above the substrate 110 (here, the gate trench 170 extends in the x direction). It should be understood that the gate trenches 170 are arranged at intervals in a second direction (here, the y direction) such that the gate trenches 170 extend longitudinally parallel to each other. Each gate trench 170 has a length (corresponding to the distance in the x direction), a width (corresponding to the distance in the y direction), and a depth (corresponding to the distance in the z direction). The length direction is the longest direction. Thus, the longitudinal axis of each gate trench 170 refers to the axis that extends in the length direction through the center of the gate trench 170. Each gate trench 170 has first and second opposing sidewalls and a bottom surface that each extend in the x direction and thus parallel to the longitudinal axis.

[0083] FIG. 3C shows a device having a plurality of gate trenches all extending parallel to each other in a first direction, but it will be understood that embodiments of the present invention are not limited thereto. Power MOSFETs with a wide variety of gate trench designs are known in the art. For example, some power MOSFETs have both a first set of gate trenches extending in a first direction through a semiconductor layer structure and a second set of gate trenches extending in a second (typically orthogonal) direction through the semiconductor layer structure, with the two sets of trenches being arranged to intersect each other. As another example, some MOSFETs have gate trenches formed in a rectangular, hexagonal, octagonal, or circular (when viewed from above) shape, with the trenches surrounding a well region (in which a source region is located). It will be understood that the techniques disclosed herein can be used in MOSFETs having any gate trench design, including the exemplary additional designs described above.

[0084] Each gate trench 170 extends in the z-direction (depth direction) through a highly doped n-type silicon carbide layer 140 in order to convert the source layer 140 into a plurality of spaced-apart, highly doped n-type silicon carbide regions 142 that function as the source region of the power MOSFET 100. Each gate trench 170 also extends onto the upper surface of the n-type drift region 120. The sidewalls of each gate trench 170 are the exposed surfaces of the layer / regions of the semiconductor layer structure 150 on both sides of each gate trench 170.

[0085] Referring to FIG. 3D, an ion implantation process is performed to implant p-type dopant ions into the semiconductor layer structure 150. This ion implantation step may be performed without an ion implantation mask. The p-type dopant is implanted into the highly doped n-type source region 142, passes through it, and is implanted into the underlying drift region 120 to form a plurality of p-wells 132 in the upper portion of the drift region 120 directly below the source region 142. The portion of each p-well 132 adjacent to the gate trench 170 functions as a transistor channel 134, as will be described below. The p-type dopant is also implanted into the portion of the drift region 120 directly below the bottom surface of the gate trench 170 to form a plurality of trench shield regions 180 extending below each gate trench 170. This ion implantation step is performed using a higher ion implantation energy than that used in the conventional process described above with reference to FIG. 2E because the p-type dopant is implanted through the n-type source region 142 to form the p-well 132 therebelow. Therefore, the trench shield region 180 may be formed to extend deeper into the semiconductor layer structure 150 than the trench shield region 80 formed in the conventional process described above. It should be noted that in this specification, the distance that a layer or region of the semiconductor layer structure extends in the depth direction refers to how far the layer or region extends in a direction perpendicular to the main surface of the semiconductor layer structure (i.e., how far the layer region extends in the vertical or "z" direction). The bottom of a region (such as the p-well 132 or the trench shield region 180) defined by doping with a dopant of a specific conductivity type refers to the point where the doping concentration has decreased by two orders of magnitude from the peak doping concentration of that region. In an exemplary embodiment, the trench shield region 180 may extend 1.5 to 10 times deeper in the depth direction than the trench shield region 80 of the MOSFET 1. The trench shield region 180 may extend 1.2 to 5 times deeper in the depth direction than the p-well 132. In this specification, the depth of a layer or region of the semiconductor layer structure refers to how far that layer or region extends in a direction perpendicular to the main surface of the semiconductor layer structure from the plane defined by the upper surface of the semiconductor layer structure.As shown in FIG. 3D, the depth of the trench shield region 180 may be deeper or shallower than the depth of the trench support shield 160. In an exemplary embodiment, the depth of the trench shield region 180 may be 0.75 to 0.95 times the depth of the trench support shield 160.

[0086] At least the lower portion of the p-well 132 and the trench shield region 180 may be a moderately doped p-type region. The doping density of the p-type well region 132 may be selected based on the desired doping density of the transistor channel of the MOSFET 100. In some embodiments, the moderately doped p-type well layer 130 and the lower portion of the trench shield region 180 may each have a doping concentration of, for example, 1×10 16 atoms / cm 3 ~1×10 19 atoms / cm 3 . The moderately doped p-type well layer 130 may have a graded doping profile in some embodiments.

[0087] Since the p-well 132 and the trench shield region 180 are formed together (i.e., simultaneously) by the same ion implantation process, the doping profile of the p-type dopant in the p-well 132 substantially coincides with (i.e., coincides within 15%) the doping profile of the p-type dopant at the lower part of the trench shield region 180. As used herein, the doping profile of a region of a semiconductor layer structure (e.g., the doping profile of a p-well or a trench shield region) refers to the variation of the concentration of a dopant of a specific type of conductivity type as a function of depth. Accordingly, the doping profile can be graphically represented using a two-dimensional graph having a curve showing the concentration of the dopant of the specified conductivity type as a function of the depthwise distance from a reference plane such as the upper surface of the semiconductor layer structure. It will be understood that the doping profile of a region is taken through the central portion of that region not adjacent to another region, rather than at the edge portion of that region. This is because the edge effect may cause unintentional variations in the doping profile that do not represent the doping profile of that region

[0088] The "variation" between two doping profiles refers to the variation between corresponding points on the two profiles. If there is no variation between two doping profiles, when the graphical representations of the two doping profiles are overlaid, the two curves will exactly overlap and appear as a single curve. This state rarely exists. In this specification, a reference that the first doping profile varies by less than X% from the second doping profile means that the average difference between the two doping concentrations at each corresponding depth is less than X%. What is referred to in this specification is the variation between the doping profile of the p-type dopant (or dopant of the second conductivity type) in the p-well 132 and the doping profile of the p-type dopant (or dopant of the second conductivity type) at the bottom of the trench shield region 180 formed by the same process used to form the p-well 132. It should be noted here that the p-well 132 and the trench shield region 180 are at different depths within the semiconductor layer structure 150 because the trench shield region is formed directly under the gate trench 170. Therefore, when comparing the variation between these two doping profiles, one of the depths of the curve is adjusted considering the depth offset so that the two curves generally overlap.

[0089] Since the gate trench 170 may affect the ion implantation process, the doping profiles of the p-type dopants in the p-well 132 and the trench shield region 180 are expected to show slight variations, which is why the above-mentioned doping profiles may not exactly match. Since the p-well 132 is formed by implanting p-type dopant ions through the n-type source region 142, the doping profile of the p-type dopant in the n-type source region 142 also substantially matches (i.e., within 15%) the doping profile of the p-type dopant at the top of the trench shield region 180. In some embodiments, the variation between the two doping profiles may be less than 10%, and even less than 5%.

[0090] FIG. 6 is a schematic graph showing how a semiconductor device according to an embodiment of the present invention can have a p-well. The doping profile of some p-type dopants in the p-well directly below the source region varies by less than 15% from the doping profile of the p-type dopants in the lower part of the trench shield region (the doping profile of the trench shield region is taken through a part of the trench shield region extending longitudinally directly below the center of the bottom of the gate trench). As shown in FIG. 6, the depth of the lower part of the trench shield region is adjusted by a constant offset so that the two curves are properly aligned. Then, the variation between the two doping profiles is determined by taking the average of the variations in the doping concentration values at each point (e.g., 100 equally spaced points) along the horizontal axis. FIG. 6 illustratively shows that the average is taken at three points where the values of the doping profile of the p-well are labeled as x1, x2, x3 and the values of the doping concentration of the trench shield region are labeled as y1, y2, y3.

[0091] The upper part of each trench shield region 180 (corresponding to the part that extends in the z - direction from the bottom of the gate trench 170 into the drift region 120 by a distance equal to the depth of the source region 142) can have a higher p - type doping concentration than the remaining part of each trench shield region 180. Since the upper part of each trench shield region 180 can inject a higher concentration of p - type dopant into the source region 142 without affecting the doping concentration of the well region 132 (and at the same time can be injected into the part of the drift region that is converted into the upper part of the trench shield region 180), it can have a higher doping concentration. In some cases, the dose amount of the n - type dopant injected to form the source region (see the description of FIG. 3A above) may be somewhat higher than the dose amount required to achieve the desired effective n - type dopant concentration in the source region 142, because the extra n - type dopant cancels out the p - type dopant injected into the source region 142 during the ion implantation step used to form the p - well 132 and the trench shield pattern 180. The trench shield region 180 may extend over the entire length of each gate trench 170.

[0092] As described above, the sidewalls of the gate trench 170 are typically not completely vertical, but instead slope outward as the distance from the bottom of each gate trench 170 increases. As a result, during the above - described ion implantation process carried out to form the p - well 132 and the trench shield region 180, some dopant ions are directly implanted into the sidewalls of each gate trench 170. In addition, an amount of dopant ions bounce back from the exposed part of the drift region 120 directly beneath each gate trench 170, and a portion of these "reflected" dopant ions are then implanted into the sidewalls of the gate trench 170. The injection of p - type dopant ions into the sidewalls of the gate trench via these two mechanisms during the ion implantation process carried out to form the p - well 132 and the trench shield region 180 can be problematic for two reasons.

[0093] First, as described above, the p-type doping concentration of the p-well 132 may be carefully selected such that the channel region 134 has a doping concentration for optimizing device performance. During the ion implantation process performed to form the p-well 132 and the trench shield region 180, if additional p-type dopant ions are implanted into the channel region 134, the performance of the MOSFET 100 may degrade. Second, the lowly doped n-type drift region 120 forms the lower part of each sidewall of each gate trench 170. If sufficient p-type dopant ions are implanted into these n-type regions of the sidewalls of the gate trench 170, the lower sidewalls may effectively become undoped or even doped p-type. When this occurs, the p-well 132 may short-circuit to the p-type trench shield region 180, and the unit cell may no longer operate as a transistor. As described above, an oxide spacer 78 is formed on the sidewalls of the gate trench 70 to prevent dopant ions from being implanted into the sidewalls during the ion implantation process performed to form the trench shield region 80 during the manufacturing process used to form the conventional MOSFET 1. This technique is effective but complicates the manufacturing process.

[0094] Figures 3E and 3F show the processing steps performed to remove dopant ions implanted in the sidewalls of the gate trench 170 during the ion implantation process executed to form the p-well 132 and the trench shield region 180. First, referring to FIG. 3E, an oxidation process is performed on the MOSFET 100. The oxidation process oxidizes the exposed surfaces of the semiconductor layer structure 150, including the upper surface of the semiconductor layer structure 150 and the sidewalls and bottom surface of the gate trench 170. Since different surfaces of the silicon carbide crystal structure are oxidized at different rates, the sidewalls of the gate trench 170 may be oxidized faster than the upper surface of the semiconductor layer structure 150 and the upper part of the trench shield region 180 in some embodiments (for example, in embodiments formed using a 4H silicon carbide substrate). The oxidation process may be performed to oxidize the portions of the sidewalls of the gate trench 170 whose doping concentration has substantially changed by the ion implantation process executed to form the p-well 132 and the trench shield region 180.

[0095] Next, referring to FIG. 3F, an etching process is performed to remove the oxidized silicon carbide. This etching process acts to remove the portions of the sidewalls of the gate trench 170 implanted during the ion implantation process executed to form the p-well 132 and the trench shield region 180. The etching process also removes the oxidized upper surface of the semiconductor layer structure 150 and the tops of each trench shield pattern 180.

[0096] Note that the oxidation and oxide removal steps described above with reference to FIGS. 3E and 3F act to widen the gate trench 170. Therefore, the gate trench 170 may initially be formed to have a width in the y direction that is smaller than the desired final width of the gate trench 170.

[0097] In some cases, it may be desirable to further increase the doping concentration of the upper portion 182 of each trench shield region 180. In some embodiments, a second ion implantation process may be performed, in which p-type dopants are implanted into the upper surface of the semiconductor layer structure and the bottom surface of the gate trench 170. This ion implantation process may be a relatively low-energy but high-dose ion implantation process. As a result, the p-type dopants are implanted at a high dose level without being implanted deeply. The implantation energy may be set such that the dopant ions implanted into the upper surface of the semiconductor layer structure 150 do not completely pass through the n-type source region 142, thereby ensuring that the doping concentration of the p-well 132 is not substantially affected by this ion implantation step. The p-type dopant ions are simultaneously implanted into the upper portion 182 of each trench shield region 180, which helps to reduce the magnitude of the electric field formed below the gate oxide layer of the device (described below) during reverse blocking operation. Since the implantation energy is set such that the dopant ions do not substantially affect the doping concentration of the p-well 132, there is no need to form an ion implantation mask covering the source region 142. When increasing the dopant concentration of the upper portion 182 of the trench shield region 180 in the manner described above, the second ion implantation process may be performed before the oxidation and removal steps described above with reference to FIGS. 3E and 3F, and the oxidation and removal steps may be able to remove the p-type dopants implanted into the sidewalls of the gate trench 170 during both ion implantation steps.

[0098] In other cases, the sidewalls of the gate trench 170 may be covered before the ion implantation step that increases the doping concentration at the top of the trench shield region 180 is performed. This process is shown in FIGS. 3G-3I. In particular, as shown in FIG. 3G, a spacer 178, such as an oxide spacer, is formed on the sidewalls of the gate trench 170. Since the spacer 178 can be formed in the same manner as the oxide spacer 78 described above with reference to FIG. 2E, further description thereof is omitted here. Next, as shown in FIG. 3H, supplementary ion implantation may be performed to increase the dopant concentration at the top 182 of the silicon carbide trench shield region 180. As described above, this supplementary ion implantation may be a relatively low-energy implantation with a high dose to ensure that the doping concentration of the p-well 132 does not substantially change due to the supplementary ion implantation.

[0099] Referring to FIG. 3I, the sidewall spacer 178 may then be removed via an etching process. It should be noted that the vertical doping profile of the well region 132 taken along a first axis extending through the well region 132 in a direction perpendicular to a plane parallel to the top surface of the semiconductor layer structure 150 may vary by less than 10% from the vertical doping profile of the lower portion of the trench shield region 180 taken along a second axis parallel to the first axis and passing through the center of the bottom of the trench 170. As described above, this occurs because the p-well 132 and the trench shield region 180 are formed together (i.e., simultaneously) by the same ion implantation process. Here, the lower portion of the trench shield region 180 refers to the portion of the trench shield region 180 that extends in the depth direction by the same distance as the depth to which the p-well 132 extends in the depth direction from the bottom of the trench shield region 180. Here, "vertical" refers to a direction perpendicular to a plane parallel to the top surface of the semiconductor layer structure 150.

[0100] Referring to FIG. 3J, the gate oxide layer 172 is conformally formed on the bottom and sidewalls of each gate trench 170. The conformal gate oxide layer 172 may be formed by annealing the exposed silicon carbide in an oxygen-containing environment to oxidize it. Alternatively, the conformal gate oxide layer 172 may be formed by an oxide deposition step. A portion of the conformal gate oxide layer may be removed to form an opening through which the source contact 190 (see FIG. 3J) can connect to the source region 142 and the p-well extension 136 (described below). Removing these portions of the conformal gate oxide layer leaves the gate oxide layer 172 in each gate trench 170.

[0101] A gate electrode 174 is formed on each gate oxide layer 172. In some embodiments, the gate electrode 174 can substantially fill each gate trench 170. The gate electrode 174 can include a conductive material such as, for example, polysilicon, silicate, or metal. An intermetal dielectric layer 176 is formed on the exposed portions of the gate oxide layer 172 and the gate electrode 174. Thereafter, a source contact 190 is formed on the top of the device. The source contact 190 can include one or more metals and is physically and electrically connected to the p-well 132 (see the following description with reference to FIG. 3L) and the n-type source region 142. The source contact 190 may constitute the source terminal of the MOSFET 100 or may be electrically connected to the source terminal. A drain contact 192 is formed on the bottom surface of the substrate 110. A gate contact (not shown) connected to the gate electrode 174 is also provided.

[0102] As described above, since the p-well 132 and the trench shield region 180 are formed together (i.e., simultaneously) by the same ion implantation process (see the description of FIG. 3D), the trench shield region 180 extends downward in the depth direction by a first distance from the bottom of each gate trench 170 into the semiconductor layer structure 150, and this distance is substantially the same as the second distance by which the p-well 132 extends downward from the upper surface of the semiconductor layer structure 150 into the semiconductor layer structure 150. For example, in some embodiments, the first distance may be within + / - 10% of the second distance. In other embodiments, the first distance may be within + / - 5% of the second distance. Here, the first and second distances respectively refer to the maximum depths of the p-well 132 and the trench shield region 180.

[0103] FIG. 3K is a horizontal cross-section of the device shown in FIG. 3J cut along line 3K-3K (i.e., this cross-section is taken along the upper surface of the semiconductor layer structure 150). FIG. 3K shows how a p-well extension 136 extending between the p-well 132 and the upper surface of the semiconductor layer structure 150 is formed. A series of p-well extensions 136 are provided between each pair of gate trenches 170 in the illustrated embodiment, and the p-well extensions 136 are spaced apart from each other in the x direction. The p-well extensions 136 may be formed, for example, by an additional ion implantation step not described above. The p-well extensions 136 may be highly doped p-type regions, and for example, may have a doping concentration equal to or higher than the doping concentration of the n-type source region 142. The p-well extensions 136 provide an electrical connection between the source contact 190 and the p-well 132.

[0104] FIG. 3L is a cross-sectional view taken along line 3L-3L of FIG. 3K, showing the p-well extension 136 and a trench shield region connection pattern 138 that electrically connects the illustrated trench shield region 180 to one of the p-well extensions 136. The trench shield region connection pattern 138 is a highly doped (p+ )It may be a p-type region. The trench shield region connection pattern 138 may be formed, for example, by an additional ion implantation step not described above.

[0105] As described above, including the p-type trench support shield 160 in the MOSFET 100 may help reduce the electric field in the gate oxide layer 172 during reverse blocking operation, and may be advantageous for providing a more preferable (lower resistance) avalanche current path in the case of avalanche breakdown. However, forming the trench support shield 160 requires an extra processing step, thus increasing the manufacturing cost, and in some applications, the extra cost may exceed the advantages of the trench support shield 160. FIGS. 4A to 4B show a MOSFET 100' according to a further embodiment of the present invention that does not include the trench support shield 160. The MOSFET 100' can be formed using the same processing steps described above with reference to FIGS. 3A to 3L, except that the processing steps described above with reference to FIG. 3B are omitted in the manufacture of the MOSFET 100'. FIGS. 4A and 4B respectively correspond to FIGS. 3J and 3L, and in these figures, similar elements are numbered using the same reference numerals. Since the MOSFET 100' is identical to the MOSFET 100 except that the trench support shield 160 is omitted, a further description of the MOSFET 100' is omitted.

[0106] FIG. 5 is a flowchart showing a method according to an embodiment of the present invention for manufacturing a gate-trench semiconductor device, such as a power wide-bandgap gate-trench semiconductor device.

[0107] As shown in FIG. 5, a semiconductor drift region may be formed on a substrate (block 200). The drift region can have a first conductivity type and may be doped at a relatively low concentration. The drift region may be formed, for example, by epitaxial growth. Next, a source layer having the first conductivity type is formed on the upper surface of the drift region (block 205). The source layer may be doped at a high concentration and may be formed, for example, by ion implantation. A trench support shield is also formed (block 210). The trench support shield can have a second conductivity type and may be doped at a high concentration. The trench support shield may be formed, for example, by ion implantation using an ion implantation mask. The trench support shield may be formed before or after the source layer.

[0108] A gate trench is formed through the source layer and into the drift region (block 215). The gate trench may be formed by masking the device and then performing an etching process. By forming the gate trench, the source layer may be subdivided into a plurality of source regions. The depth of each gate trench may be shallower than the depth of the trench support shield. Next, an ion implantation process may be performed to blanket implant a p-type dopant into the active region of the device (block 220). This ion implantation process simultaneously forms a plurality of second conductivity type well regions directly below the source regions and a plurality of second conductivity type trench shield regions directly below each trench. The well regions and the trench shield regions may be doped moderately with a second conductivity type dopant.

[0109] In some embodiments, the second ion implantation process (block 225) may be performed immediately after the ion implantation process of block 220. The second ion implantation may be a low-energy, high-dose ion implantation process that implants dopants of a second conductivity type on top of the source region of the first conductivity type and each trench shield region. Since the low-energy implantation process is performed, the dopant ions of the second conductivity type do not substantially enter the well region through the source region, and thus do not change the doping concentration of the well region. Further, since the source region can have a dopant concentration of the first conductivity type that is, for example, one order of magnitude greater than the dopant of the second conductivity type implanted into the source region, the effective doping concentration of the source region may not substantially change due to the second ion implantation process. The second ion implantation process can be used, for example, to convert the top of the trench shield region into a highly doped region to improve the electric field blocking ability of the trench shield region.

[0110] After the above-described ion implantation step is performed, an oxidation process that oxidizes the exposed surface of the device may be performed (block 230). The oxidation process may include pumping an oxygen-containing gas into a chamber containing the high-temperature device. The oxidation process can be carefully controlled to oxidize the sidewalls of the gate trench by a desired amount. Next, an etching process may be performed to remove the oxidized semiconductor material (block 235). As described above, the oxidation and removal processes of blocks 230 and 235 remove portions of the sidewalls of the gate trench that were unintentionally doped during the above-described ion implantation process.

[0111] In some embodiments, the second ion implantation process described above with reference to block 225 may be omitted. In such embodiments, the processes of blocks 240, 245, and 250 may be performed. In particular, sidewall spacers, such as oxide spacers, may be selectively formed on the sidewalls of the gate trenches (block 240). Next, a low-energy, high-dose ion implantation process is performed to implant dopants of a second conductivity type on top of the first conductivity type source region and each trench shield region (block 245). Since a low-energy implantation process is performed, the dopant ions of the second conductivity type do not substantially enter the well region through the source region, and thus do not change the doping concentration of the well region. Further, since the source region can have a dopant concentration of the first conductivity type that is, for example, one order of magnitude greater than the dopant of the second conductivity type implanted into the source region, the effective doping concentration of the source region may not substantially change due to the second ion implantation process. The second ion implantation process can be used, for example, to convert the upper part of the trench shield region into a highly doped region to improve the field blocking ability of the trench shield region. The sidewall spacers protect the sidewalls of the gate trenches during the ion implantation process. The sidewall spacers are removed at the completion of the ion implantation process (block 250).

[0112] Next, a gate oxide layer and a gate electrode may be sequentially formed in the gate trenches (block 255). An intermetal dielectric layer may be formed over the gate trenches, and then source and drain metallizations may be formed (block 260).

[0113] In the above description, each exemplary embodiment has a specific conductivity type. It will be understood that in each of the above embodiments, by simply reversing the conductivity of the n-type layer and the p-type layer, a device of the opposite conductivity type can be formed. Thus, it will be understood that the present invention covers both n-channel devices and p-channel devices for each of the different device structures (e.g., MOSFETs, IGBTs, etc.). In this specification, when a contact can be either a source contact or a drain contact, this contact may be referred to as a "source / drain contact".

[0114] Although the present invention has been described above with respect to embodiments of power MOSFETs and power IGBTs, it will be understood that the techniques described herein are equally applicable to other similar vertical power devices having gate trenches. Thus, the embodiments of the present invention are not limited to MOSFETs and IGBTs, and the techniques disclosed herein may be used in any suitable gate trench device.

[0115] The present invention has been mainly described with respect to silicon carbide-based power semiconductor devices. However, it will be understood that silicon carbide is used herein as an example, and the devices described herein may be formed of any suitable wide-bandgap semiconductor material system. By way of example, in any of the above embodiments, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide.

[0116] The embodiments of the present invention have been described above with reference to the accompanying drawings in which the embodiments of the present invention are shown. However, it will be understood that the present invention may be embodied in many different forms and should not be construed as limited to the above embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like numbers refer to like elements throughout.

[0117] As used herein, the term "plurality" means two or more. As used herein, "substantially" means within + / - 10%.

[0118] Throughout this specification, terms such as first, second, etc. are used to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0119] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0120] When an element such as a layer, region, or substrate is referred to as extending "on" or "onto" another element, it will be understood that the element is either directly on the other element, or extends directly onto it, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, or extending "directly onto" that element, no intervening elements are present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, no intervening elements are present.

[0121] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer or region to another element, layer or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0122] In this specification, embodiments of the invention are described with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Further, variations from the shapes of the figures are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Embodiments of the invention are also described with reference to flow diagrams. It will be understood that the steps shown in the flow diagrams need not be performed in the order shown.

[0123] Some embodiments of the present invention have been described with reference to semiconductor layers and / or regions, which are characterized by having a conductivity type such as n-type or p-type that indicates a majority carrier concentration in the layer and / or region. Thus, an n-type material has a majority equilibrium concentration of negatively charged electrons, while a p-type material has a majority equilibrium concentration of positively charged holes. Some materials are designated with a “+” or “-” (such as n+, n-, p+, p-, n++, n--, p++, p--), and may indicate a relatively larger (“+”) or smaller (“-”) majority carrier concentration compared to another layer or region. However, such notations do not imply the presence of a specific concentration of majority or minority carriers in the layer or region.

[0124] In the drawings and the specification, typical embodiments of the present invention are disclosed and specific terms are used, but they are not for the purpose of limitation and are used only in a general and explanatory sense, and the scope of the present invention is set forth in the following claims.

Claims

1. Providing a wide-bandgap semiconductor layer structure including a drift region having a first conductivity type and a source region having the first conductivity type on the drift region, wherein the wide-bandgap semiconductor layer structure includes a trench therein; Injecting a dopant of a second conductivity type into the wide-bandgap semiconductor layer structure to simultaneously form both a well region directly below the source region and a trench shield region directly below the trench, wherein the well region and the trench shield region each have the second conductivity type; A method of manufacturing a semiconductor device, comprising:

2. The method according to claim 1, wherein the trench extends through the source region and into the drift region.

3. The method according to claim 1 or 2, wherein the step of injecting a dopant of a second conductivity type into the wide-bandgap semiconductor layer structure includes injecting the dopant of the second conductivity type into the drift region through the source region.

4. The method according to claim 1 or 2, wherein the well region is formed by converting a part of the drift region having the first conductivity type into the well region having the second conductivity type.

5. The method according to claim 1 or 2, wherein the well region separates the source region from the drift region.

6. The method according to claim 1 or 2, wherein the source region forms upper portions of both a first sidewall and a second sidewall of the trench, the drift region forms lower portions of the first sidewall and the second sidewall, and the first sidewall faces the second sidewall.

7. The method according to claim 6, wherein when the dopant of the second conductivity type is injected into the wide-bandgap semiconductor layer structure, the first sidewall of the trench is exposed.

8. Performing an oxidation process to convert at least the first and second sidewalls and the bottom of the trench into an oxide material; Removing the oxide material to convert the trench into an enlarged trench; The method according to claim 7, further comprising:

9. The method according to claim 1 or 2, wherein the wide bandgap semiconductor layer structure extends in a length direction, a width direction, and a depth direction that are orthogonal to each other, and a lower surface of the wide bandgap semiconductor layer structure extends in the length direction and the width direction.

10. The method according to claim 9, wherein the source region extends a first distance in the depth direction, the shield region extends a second distance in the depth direction, and the second distance exceeds the first distance.

11. The method according to claim 10, wherein the second distance is at least 1.5 times the first distance.

12. The method according to claim 10, wherein the second distance is at least 2 times the first distance.

13. The method according to claim 10, wherein a part of the well region extending to an upper surface of the wide bandgap semiconductor layer structure extends a third distance in the depth direction, and the third distance is substantially the same as the second distance.

14. The concentration of the dopant of the second conductivity type in the source region is at least 5×10 １５ / cm ３ The method according to any one of claims 1 to 13, wherein the method is as described above.

15. The method according to any one of claims 1 to 14, wherein a doping profile of a lower portion of the trench shield region taken along a first axis extending in the depth direction through a center of a bottom of the gate trench varies by less than 15% from a doping profile of the well region taken along a second axis extending through the well region and parallel to the first axis.

16. The method according to claim 1 or 2, further comprising the step of implanting an additional dopant of a second conductivity type into the wide bandgap semiconductor layer structure directly below the trench.

17. The method according to claim 16, wherein the dopant of the second conductivity type and the additional dopant of the second conductivity type are implanted using the same ion implantation mask.

18. The method according to claim 16, wherein the additional dopant of the second conductivity type is implanted before the dopant of the second conductivity type is implanted.

19. The method according to claim 16, further comprising the step of forming a mask on sidewalls of the trench before implanting the additional dopant of the second conductivity type into the wide bandgap semiconductor layer structure.

20. The method according to claim 16, wherein an upper surface of the source region is exposed when the additional dopant of the second conductivity type is implanted into the wide bandgap semiconductor layer structure.

21. The method according to claim 8, further comprising the step of implanting a dopant of a second conductivity type additional to the wide bandgap semiconductor layer structure directly under the trench.

22. The method according to claim 16, wherein the dopant of the additional second conductivity type is implanted before an oxidation process that converts at least the first and second sidewalls and the bottom of the trench into an oxide material is performed.

23. The method according to any one of claims 1 to 22, wherein an upper surface of the source region is exposed when the dopant of the second conductivity type is implanted into the wide bandgap semiconductor layer structure.

24. The step of preparing the wide bandgap semiconductor layer structure comprises forming the drift region on an upper surface of a wide bandgap semiconductor substrate having the first conductivity type; implanting dopant ions of the first conductivity type into the upper surface of the drift region to form the source region, wherein the source region has a higher concentration of dopant of the first conductivity type than the drift region; forming the trench on the upper surface of the wide bandgap semiconductor layer structure The method according to any one of claims 1 to 23.

25. The method according to any one of claims 1 to 24, further comprising the step of implanting a dopant of a second conductivity type into the semiconductor layer structure to form first and second support shields in the semiconductor layer structure on each of the first and second sides of the trench.

26. The method according to any one of claims 1 to 25, further comprising the step of sequentially forming a gate oxide layer and a gate electrode in the trench.

27. The method according to any one of claims 1 to 26, further comprising the step of forming a trench shield region connection region that electrically connects the trench shield region to the well region.

28. A semiconductor device including a wide bandgap semiconductor layer structure, wherein the wide bandgap semiconductor layer structure comprises a drift region having a first conductivity type; a well region having a second conductivity type provided on the drift region; a source region having the first conductivity type on the well region; a gate electrode in a trench; a shield region having the second conductivity type directly under the gate trench and comprising A semiconductor device in which the doping profile of the dopant of the second conductivity type in a part of the well region directly below the source region varies by less than 15% from the doping profile of the dopant of the second conductivity type in the lower part of the shield region extending in the longitudinal direction directly below the center of the bottom of the trench.

29. The semiconductor device according to claim 28, wherein the well region is between the drift region and the source region, and the trench extends through the source region and the well region into the drift region.

30. The semiconductor device according to claim 28 or 29, wherein the semiconductor layer structure extends in a length direction, a width direction, and a depth direction orthogonal to each other, and a lower surface of the semiconductor layer structure extends in the length direction and the width direction.

31. The semiconductor device according to claim 29, wherein the source region extends a first distance in the depth direction, the shield region extends a second distance in the depth direction, and the second distance exceeds the first distance.

32. The semiconductor device according to claim 30, wherein the second distance is at least 1.5 times the first distance.

33. The semiconductor device according to claim 30, wherein the second distance is at least 2 times the first distance.

34. The semiconductor device according to any one of claims 28 to 33, further comprising first and second support shields having the second conductivity type in the wide bandgap semiconductor layer structure on each of the first and second sides of the trench, and the first and second support shields extending closer to the bottom surface of the wide bandgap semiconductor layer structure than the shield region.

35. The semiconductor device according to any one of claims 28 to 34, wherein the concentration of the dopant of the second conductivity type in the upper part of the shield region exceeds the concentration of the dopant of the second conductivity type in the source region.

36. The semiconductor device according to any one of claims 28 to 35, wherein the average concentration of the dopant of the second conductivity type in the upper half of the shield region exceeds the average concentration of the dopant of the second conductivity type in the lower half of the shield region.

37. The semiconductor device according to any one of claims 28 to 36, wherein the drift region, the well region, the source region, and the shield region contain silicon carbide.

38. A semiconductor device including a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region having the first conductivity type on the well region, a gate electrode in a trench, and a shield region having the second conductivity type directly below the trench and comprising: wherein the shield region extends downward by a first distance from the bottom of the trench into the semiconductor layer structure, the well region extends downward by a second distance from the upper surface of the semiconductor layer structure into the semiconductor layer structure, and the first distance is within + / −10% of the second distance.

39. The semiconductor device according to claim 38, wherein the well region is between the drift region and the source region, and the trench extends through the source region and the well region into the drift region.

40. The semiconductor device according to claim 39, wherein the source region extends downward by a third distance from the upper surface of the semiconductor layer structure into the semiconductor layer structure, and the first distance exceeds the third distance.

41. The semiconductor device according to claim 40, wherein the first distance is at least 1.5 times the third distance.

42. The semiconductor device according to claim 40, wherein the first distance is at least 2 times the third distance.

43. The semiconductor device according to any one of claims 38 to 42, further comprising first and second support shields having the second conductivity type in the wide bandgap semiconductor layer structure on each of the first and second sides of the trench, the first and second support shields extending closer to the bottom surface of the wide bandgap semiconductor layer structure than the shield region.

44. The semiconductor device according to any one of claims 38 to 43, wherein the concentration of the dopant of the second conductivity type at the upper part of the shield region exceeds the concentration of the dopant of the second conductivity type in the source region.

45. The semiconductor device according to any one of claims 38 to 44, wherein the drift region, the well region, the source region, and the shield region contain silicon carbide.

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