Gate trench power semiconductor device having improved breakdown performance and method of forming such a device

Abstract

The semiconductor device includes a semiconductor layer structure having a gate trench formed in an upper surface, a gate finger within the gate trench, an auxiliary dielectric layer on an upper surface of the gate finger and overlapping the gate trench in a direction perpendicular to the gate trench, and a gate connector on an upper surface of the auxiliary dielectric layer and on an upper surface of the gate finger.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 847,650, filed on June 23, 2023, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly, to gate trench power semiconductor devices.

Background Art

[0003] A metal-insulating semiconductor field effect transistor ("MISFET: Metal Insulating Semiconductor Field Effect Transistor") is a well-known type of semiconductor transistor that can be used as a switching device. The MISFET is a three-terminal device having a gate terminal, a drain terminal, and a source terminal, and a semiconductor body. In the semiconductor body, a source region and a drain region separated by a channel region are formed, and a gate electrode (often also called a gate finger) is separated from the channel region by a thin insulating layer called a "gate dielectric layer". The MISFET may be turned on or off by applying an appropriate bias voltage to the gate finger. When the MISFET is turned on (i.e., when the MISFET is in its "on state"), current flows through the channel region of the MISFET between the source region and the drain region. When the bias voltage is removed from the gate finger (or reduced below the threshold level, which may be a negative voltage in some cases), current stops flowing through the channel region. As an example, an n-type MISFET has an n-type semiconductor source region and drain region and a p-type semiconductor channel region. Thus, the n-type MISFET has an "n-p-n" design. When a gate bias voltage sufficient to generate a conductive n-type inversion layer that electrically connects the n-type source region and drain region is applied to the gate finger, the n-type MISFET turns on, thereby enabling majority carrier conduction therebetween.

[0004] In most cases, the gate dielectric layer that separates the gate fingers of the power MISFET from the channel region is implemented as a thin oxide layer (e.g., a silicon oxide layer). A MISFET having an oxide gate dielectric layer is called a metal oxide semiconductor field effect transistor (“MOSFET: Metal Oxide Semiconductor Field Effect Transistor”). Oxide-based gate dielectric layers are almost always used because of their excellent properties, and the discussion in this specification focuses on MOSFETs rather than MISFETs, but it will be understood that the techniques according to the embodiments of the invention described herein are equally applicable to devices having gate dielectric layers formed of materials other than oxides.

[0005] Since the gate fingers of the MOSFET are insulated from the channel region by the gate dielectric layer, a minimum gate current is required to maintain the MOSFET in its on state or to switch the MOSFET between its on state and its off state. Since the gate forms a capacitor with the channel region, the gate current during switching is kept small. Therefore, since only a minimum charge and discharge current is required during switching, it is possible to simplify the gate drive circuit and increase the switching speed. The MOSFET may be a stand-alone device or may be combined with other circuit devices. For example, an insulated gate bipolar transistor ("IGBT: Insulated Gate Bipolar Transistor") includes both a MOSFET and a bipolar junction transistor ("BJT: Bipolar Junction Transistor"), and combines the high impedance gate of the MOSFET with the small on-state conduction loss that can be achieved by the BJT. The IGBT may be implemented, for example, as a Darlington pair including a high-voltage n-channel MOSFET in the input section and a BJT in the output section. The base current of the BJT is supplied through the channel of the MOSFET, thereby enabling a simplified external drive circuit (the drive circuit only charges and discharges the gate of the MOSFET).

[0006] There is an increasing demand for high-power semiconductor switching devices that can conduct a large current in the on state and block a large voltage (e.g., hundreds or thousands of volts) in the reverse blocking state. To support high current density and block such high voltages, power MOSFETs and power IGBTs typically have a vertical structure with a source and a drain on both sides (e.g., top and bottom) of a thick semiconductor layer structure to block higher voltage levels. In very high-power applications, semiconductor switching devices are typically formed of a wide-bandgap semiconductor material system such as, for example, silicon carbide (“SiC:silicon carbide”) (as used herein, the term “wide-bandgap semiconductor” encompasses any semiconductor having a bandgap of at least 1.4 electron volts), and silicon carbide has several advantageous properties including, for example, high dielectric breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. For example, power semiconductor devices formed using silicon carbide may have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities than devices formed using other semiconductor materials such as silicon.

[0007] Vertical power semiconductor devices including MOSFET transistors can have a standard gate design with gate fingers formed on top of the semiconductor layer structure, or alternatively, may have gate fingers embedded in respective trenches within the semiconductor layer structure. MOSFETs having embedded gate fingers are commonly referred to as gate-trench MOSFETs. In a standard gate design, the channel region of each unit cell transistor is horizontally disposed under the gate fingers. In contrast, in a gate-trench MOSFET design, the channel is vertically disposed. Gate-trench MOSFETs can achieve performance enhancements but typically require a more complex manufacturing process.

[0008] One failure mechanism of a power MOSFET is the so-called "breakdown" of the gate dielectric layer. When the power MOSFET is in its conducting or on state, the gate dielectric layer is subjected to a high electric field. Due to the stress on the gate dielectric layer caused by these electric fields, defects are generated in the dielectric material over time. When the concentration of defects reaches a critical value, a so-called "percolation path" may be formed through the gate dielectric layer, which electrically connects the gate finger to the source region placed below it, resulting in a short circuit between the gate finger and the source region and potentially damaging the device. The "lifetime" of the gate dielectric layer (i.e., how long the device can operate before breakdown occurs) depends, among other things, on the magnitude of the electric field the gate dielectric layer experiences and the length of time the electric field is applied. Figure 1 is a schematic semi-logarithmic graph showing the relationship between the operating time until breakdown ("gate dielectric lifetime") and the level of the electric field applied to the gate dielectric layer. This graph assumes that the same electric field is always applied (which is not always the case) and assumes a gate dielectric layer with a specific thickness. An important point to note from Figure 1 is that the logarithm of the gate dielectric lifetime and the electric field can have a linear relationship, so as the electric field level increases, the lifetime of the gate dielectric layer can be shortened. The lifetime of the gate dielectric layer can be extended by increasing the thickness of the gate dielectric layer, but since the performance of the MOSFET also depends on the thickness of the gate dielectric layer, increasing the thickness of the gate dielectric layer is usually not an acceptable way to extend the lifetime of the gate dielectric layer.

[0009] Today, silicon carbide-based power MOSFETs are used in applications that require high voltage blocking. As an example, 10 A / cm that blocks voltages from 300 V to over 20 kV 2Silicon carbide MOSFETs with the above current density ratings are commercially available. To form such a device, typically, a plurality of "unit cells" are formed, and each unit cell includes a MOSFET transistor. In high-power applications, typically, a large number of these unit cells (e.g., hundreds or thousands) are provided on / in a semiconductor layer structure and electrically connected in parallel. On the upper side of the semiconductor layer structure, a gate pad connected to individual gate fingers through one or more gate buses is formed, and the gate pad is capable of sending a gate signal to all the unit cells. The opposite (bottom) side of the semiconductor layer structure serves as a common drain for all the unit cells of the device. A common source contact exposed between the gate fingers is formed on the source region of the semiconductor layer structure. The resulting device has three terminals, namely, a common source terminal, a common drain terminal, and a common gate terminal, which serve as terminals for hundreds or thousands of individual unit cell transistors electrically connected in parallel.

Summary of the Invention

Means for Solving the Problems

[0010] According to an embodiment of the present invention, there is provided a semiconductor device including a semiconductor layer structure having a gate trench formed in an upper surface, a gate finger in the gate trench, an auxiliary dielectric layer on an upper surface of the gate finger and overlapping the gate trench in a vertical direction, and a gate connector on an upper surface of the auxiliary dielectric layer and on an upper surface of the gate finger.

[0011] In some embodiments, the semiconductor device further includes a gate dielectric layer between the semiconductor layer structure and the gate finger in the gate trench. In some embodiments, the auxiliary dielectric layer is thicker than the gate dielectric layer. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer. In some embodiments, the auxiliary dielectric layer overlaps the gate finger in a vertical direction over less than half of the length of the gate finger.

[0012] In some embodiments, the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench. In some embodiments, the auxiliary dielectric layer also directly contacts the upper surface of the gate fin.

[0013] In some embodiments, the gate trench extends longitudinally within the semiconductor layer structure and has a longitudinally extending bottom surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other. The gate dielectric layer includes a first portion that extends upward along the first end wall of the gate trench, and the auxiliary dielectric layer is in direct contact with the first portion of the gate dielectric layer.

[0014] In some embodiments, the gate fin extends longitudinally within the gate trench and has a longitudinally extending upper surface, a longitudinally extending bottom surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other. The auxiliary dielectric layer extends over the first end wall of the gate fin.

[0015] In some embodiments, the semiconductor device further includes an inter-metal dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the inter-metal dielectric layer. In some embodiments, the inter-metal dielectric layer vertically overlaps the auxiliary dielectric layer. In some embodiments, the semiconductor device further includes a gate bus, the gate connector electrically connects the gate bus to the gate fin, and the gate connector is between the auxiliary dielectric layer and the inter-metal dielectric layer.

[0016] In some embodiments, the auxiliary dielectric layer is a field oxide layer, and the semiconductor device further includes a gate bus on the upper surface of the auxiliary dielectric layer.

[0017] In some embodiments, the semiconductor device further includes a gate pad electrically connected to the gate fin through the gate bus and the gate connector.

[0018] In some embodiments, the auxiliary dielectric layer is also on the upper surface of a portion of the semiconductor device that is in the inactive area of the semiconductor layer structure at the end of the gate trench.

[0019] In some embodiments, the semiconductor device comprises a metal oxide semiconductor field effect transistor, and the semiconductor layer structure comprises a silicon carbide drift layer having a first conductivity type, a silicon carbide well having a second conductivity type on an upper portion of the silicon carbide drift layer, and a silicon carbide source region having a first conductivity type on an upper portion of the silicon carbide well, and the gate fin contains silicon.

[0020] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is in direct contact with the upper surface of the semiconductor layer structure adjacent to the sidewall of the gate trench, and the thickness of the second dielectric layer exceeds the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench. In some embodiments, the thickness of the auxiliary dielectric layer is at least twice the thickness of the gate dielectric layer.

[0021] In some embodiments, the auxiliary dielectric layer overlaps the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate fin. In some embodiments, the auxiliary dielectric layer is in direct contact with the gate fin along substantially the entire length of the gate fin.

[0022] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate fin is electrically connected to the gate bond pad through at least a gate connector and the gate bus, and the auxiliary dielectric layer extends under both the gate bond pad and the gate bus.

[0023] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate fin in at least a portion of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate fin in at least a portion of the active region of the semiconductor device.

[0024] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor layer structure having a gate trench therein, a gate fin within the gate trench, a gate dielectric layer between the semiconductor layer structure and the gate fin within the gate trench, a gate fin within the gate trench, an auxiliary dielectric layer on the upper surface of the gate dielectric layer and on the upper surface of the gate fin, and an intermetal dielectric layer vertically overlapping the auxiliary dielectric layer.

[0025] In some embodiments, the auxiliary dielectric layer vertically overlaps the gate trench.

[0026] In some embodiments, the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench.

[0027] In some embodiments, the gate trench extends longitudinally within the semiconductor layer structure and has a longitudinally extending bottom surface, first and second longitudinally extending side walls on opposite sides of each other, and first and second end walls on opposite sides of each other. The gate dielectric layer includes a first portion that extends upward along the first end wall of the gate trench, and the auxiliary dielectric layer is in direct contact with the first portion of the gate dielectric layer.

[0028] In some embodiments, the auxiliary dielectric layer is at least four times as thick as the gate dielectric layer.

[0029] In some embodiments, the semiconductor device further comprises a gate bus and a gate connector that electrically connects the gate fin to the gate bus, and the gate connector is between the auxiliary dielectric layer and the intermetal dielectric layer.

[0030] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate fingers are electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer includes a field oxide layer extending under both the gate bond pad and the gate bus.

[0031] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is in direct contact with the upper surface of the semiconductor layer structure adjacent to the sidewalls of the gate trenches, and the thickness of the second dielectric layer is at least twice the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewalls of the gate trenches over the entire length of the gate trenches. In some embodiments, the auxiliary dielectric layer overlaps the gate fingers in a direction perpendicular to the gate fingers along substantially the entire length of the gate fingers.

[0032] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate fingers in at least a portion of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate fingers in at least a portion of the active region of the semiconductor device.

[0033] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor layer structure having a gate trench therein, a gate finger in the gate trench, a gate bus, a gate connector for electrically connecting the gate finger to the gate bus, and an auxiliary dielectric layer interposed between an end portion of the gate finger and the gate connector.

[0034] In some embodiments, the gate connector is in direct contact with both the gate finger and the auxiliary dielectric layer.

[0035] In some embodiments, the semiconductor device further comprises a gate dielectric layer between the semiconductor layer structure and the gate fin within the gate trench. In some embodiments, the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench. In some embodiments, the auxiliary dielectric layer also contacts directly the upper surface of the gate fin. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer.

[0036] In some embodiments, the semiconductor device further comprises an intermetallic dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the intermetallic dielectric layer. In some embodiments, the intermetallic dielectric layer overlaps vertically with the auxiliary dielectric layer.

[0037] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate fin is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer comprises a field oxide layer extending under both the gate bond pad and the gate bus.

[0038] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is in direct contact with the upper surface of the semiconductor layer structure adjacent to the sidewall of the gate trench, and the thickness of the second dielectric layer is at least four times the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench.

[0039] In some embodiments, the auxiliary dielectric layer overlaps vertically with the gate fin along substantially the entire length of the gate fin.

[0040] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate fin in at least a portion of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate fin in at least a portion of the active region of the semiconductor device.

[0041] According to an additional embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor layer structure, a gate trench extending longitudinally within the upper surface of the semiconductor layer structure, the gate trench having a longitudinally extending lower surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other, a gate dielectric layer on the lower surface, the first and second sidewalls, and the first and second end walls of the gate trench, a gate fin within the gate trench, and an auxiliary dielectric layer vertically overlapping the gate trench and directly contacting a portion of the gate dielectric layer that is at the first end wall of the gate trench.

[0042] In some embodiments, the auxiliary dielectric layer also directly contacts the upper surface of the gate fin. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer.

[0043] In some embodiments, the semiconductor device further comprises a gate bus, a gate connector, and an intermetal dielectric layer, the gate connector electrically connecting the gate fin to the gate bus, and the intermetal dielectric layer being on the upper surface of the gate connector. In some embodiments, the intermetal dielectric layer vertically overlaps the auxiliary dielectric layer.

[0044] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate fin being electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer comprising a field oxide layer extending under both the gate bond pad and the gate bus.

[0045] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is in direct contact with the upper surface of the semiconductor layer structure adjacent to the sidewall of the gate trench, and the thickness of the second dielectric layer is at least twice the thickness of the gate dielectric layer.

[0046] In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench.

[0047] In some embodiments, the auxiliary dielectric layer is in direct contact with the gate fin along substantially the entire length of the gate fin.

[0048] According to a further additional embodiment of the present invention, there is provided a semiconductor device including a semiconductor layer structure having a gate trench therein, a first dielectric layer on the sidewall and bottom surface of the gate trench, a gate fin on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that is in direct contact with the upper surface of the first dielectric layer. The second dielectric layer is at least twice the thickness of the first dielectric layer.

[0049] In some embodiments, the first dielectric layer includes a first portion of the gate dielectric layer that is within the gate trench.

[0050] In some embodiments, the second dielectric layer includes a combination of a second portion of the gate dielectric layer that extends over the upper surface of the semiconductor layer structure and an auxiliary dielectric layer that extends over the upper surface of the second portion of the gate dielectric layer.

[0051] In some embodiments, the second dielectric layer includes an auxiliary dielectric layer that extends over the upper surface of the semiconductor layer structure.

[0052] In some embodiments, the second dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench.

[0053] In some embodiments, the gate fin comprises first and second sidewalls extending in the longitudinal direction of the gate trench, and the second dielectric layer vertically overlaps both the first sidewall and the second sidewall of the gate fin.

[0054] In some embodiments, the gate fin comprises first and second sidewalls extending in the longitudinal direction of the gate trench, and the second dielectric layer includes a first portion vertically overlapping the first sidewall of the gate fin and a second portion vertically overlapping the second sidewall of the gate fin. In some embodiments, the semiconductor device further comprises a gate connector electrically connecting the gate fin to the gate bus. In some embodiments, a portion of the gate connector is positioned between the first portion and the second portion of the second dielectric layer.

[0055] According to yet another embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor layer structure having a gate trench therein, a first dielectric layer on the sidewalls and the bottom surface of the gate trench, a gate fin on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that is in direct contact with and vertically overlaps the gate fin.

[0056] In some embodiments, the second dielectric layer is at least twice as thick as the first dielectric layer.

[0057] In some embodiments, the semiconductor device further comprises a gate connector that is in direct contact with both the second dielectric layer and the gate fin.

[0058] In some embodiments, the first dielectric layer includes a first portion within the gate trench of the gate dielectric layer.

[0059] In some embodiments, the second dielectric layer includes a combination of a second portion extending on the upper surface of the semiconductor layer structure of the gate dielectric layer and an auxiliary dielectric layer extending on the upper surface of the second portion of the gate dielectric layer.

[0060] In some embodiments, the second dielectric layer includes an auxiliary dielectric layer extending over the top surface of the semiconductor layer structure.

[0061] In some embodiments, the second dielectric layer is in direct contact with the gate fingers along substantially the entire length of the gate fingers.

[0062] In some embodiments, the gate fingers include first and second sidewalls extending in the longitudinal direction of the gate trench, and the second dielectric layer includes a first portion overlapping the first sidewall of the gate finger in a vertical direction and a second portion overlapping the second sidewall of the gate finger in a vertical direction.

[0063] In some embodiments, the semiconductor device further includes a gate connector electrically connecting the gate fingers to the gate bus, and a portion of the gate connector is positioned between the first portion and the second portion of the second dielectric layer.

[0064] In some embodiments, at least a portion of the second dielectric layer extends laterally across the entire width of the gate fingers in at least a portion of the inactive region of the semiconductor device, and at least a portion of the auxiliary dielectric layer extends laterally across less than the entire width of the gate fingers in at least a portion of the active region of the semiconductor device.

[0065] According to further additional embodiments of the present invention, a method of forming a semiconductor device is provided. According to these methods, a gate trench is formed in a semiconductor layer structure. A gate dielectric layer is formed in the gate trench. Gate fingers are formed on the gate dielectric layer within the gate trench. An auxiliary dielectric layer is formed on the gate fingers and on the gate dielectric layer. A gate bus is formed on the auxiliary dielectric layer.

[0066] In some embodiments, the auxiliary dielectric layer is formed over a portion of the gate fingers that is within the gate trench.

[0067] In some embodiments, the auxiliary dielectric layer overlaps the gate trench in a direction perpendicular to the gate trench.

[0068] In some embodiments, the method further includes forming a gate connector on the auxiliary dielectric layer. In some embodiments, the auxiliary dielectric layer is interposed between the gate connector and the gate finger. In some embodiments, the gate connector extends between the gate bus and the gate finger and electrically connects the gate finger to the gate bus.

[0069] In some embodiments, the auxiliary dielectric layer extends over the gate trench over less than half the length of the gate trench.

[0070] In some embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate trench in a direction perpendicular to the gate trench along substantially the entire length of the gate trench.

[0071] In some embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate finger in a direction perpendicular to the gate finger along substantially the entire length of the gate trench.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0073] Vertical power semiconductor devices based on silicon carbide having gate trenches, such as vertical power MOSFETs and vertical IGBTs, are attractive for many applications due to their inherently low specific on-resistance, which allows for more efficient operation in power switching operations. In a gate trench vertical power device, since the channel is formed on the sidewalls of the gate trench, it exhibits a lower specific resistance during on-state operation. Further, the carrier mobility in the sidewall channels of a gate trench power device can be about 2 to 4 times higher than the corresponding carrier mobility in the horizontal channels of a standard (i.e., non-gate trench) vertical power device. This improvement in channel mobility increases the current density during on-state operation and enables higher switching speeds. Additionally, the trench design reduces the overall pitch of the device, allowing for improved integration. The reduction in conduction losses (due to the reduced on-state resistance) and the improvement in switching speed result in gate trench power devices suitable for high-frequency power applications with low to medium voltage blocking requirements (e.g., 600 to 1200 volts). These devices can reduce the requirements for associated passive components, achieve low cost and low weight, and may require a relatively simple cooling scheme. Since MOSFETs are the most widely used silicon carbide-based power semiconductor gate devices, the following discussion will mainly focus on examples of MOSFETs. However, alternatively, each of the described embodiments may be implemented using a non-oxide gate dielectric layer (e.g., nitride, high-k materials, etc.), and it will be understood that the same techniques may be used to form other gate trench power semiconductor devices such as IGBTs, gate-controlled thyristors, etc.

[0074] A gate-trench power MOSFET is susceptible to oxide reliability problems due to the presence of high electric fields in the gate oxide layer that lines the bottom and sidewalls of the gate trench. High electric fields can degrade the gate oxide layer over time and ultimately cause device failure. High electric fields occur in the lower corner region and upper corner region of the gate oxide layer, and the field crowding effect can dramatically increase the level of the electric field in the gate oxide layer. When the gate-trench MOSFET operates in reverse-blocking mode (i.e., when the MOSFET is in its off state), the electric field extends upward from the drain terminal (which is on the bottom surface of the semiconductor layer structure) toward the top surface of the semiconductor layer structure. Thus, under reverse-blocking operation, the bottom portion of the gate dielectric layer is subject to high electric field levels, and the electric field is highest along the lower corner of the gate oxide layer formed at the bottom edge of the gate trench. A so-called "trench shielding region" (which is a high-concentration semiconductor layer having the same conductivity type as the channel region) is typically provided under and / or beside the gate trench of the gate-trench power MOSFET to reduce the electric field level in the gate oxide layer during reverse-blocking operation.

[0075] During the on-state or "forward" operation, the electric field is highest in the upper portion of the gate oxide layer. Typically, the gate fingers are recessed such that the upper surface of each gate finger is within the gate trench (i.e., below the upper surface of the semiconductor layer structure), thereby reducing the electric field at the upper corner of the gate oxide layer. However, at the end of the gate trench where the gate finger connects to the gate bus, the gate structure needs to extend over the gate oxide layer in the upper corner region to make an electrical connection between each gate finger and the gate bus. Thus, the upper corner of the gate oxide layer at one or both ends of the gate trench can be the most vulnerable part of the gate dielectric layer to breakdown during on-state operation.

[0076] Another potential problem with conventional gate-trench power MOSFETs is that the field oxide layer formed under the gate bus can be laterally undercut during the fabrication process. Such lateral undercut can occur because the field oxide layer is a blanket deposited over the device and thus can be formed within the gate trench. Wet etching is performed to remove the field oxide layer from the gate trench. Unfortunately, it can be difficult to control this wet etching process, and as a result, lateral undercut of the field oxide layer under the gate bus can occur. When this undercut occurs, it can cause the photoresist used during wet etching to detach and / or result in wafer-to-wafer uniformity issues, which is undesirable.

[0077] According to embodiments of the present invention, there is provided a gate-trench power semiconductor device having a gate dielectric layer with strengthened upper corner portions at one or both ends of the gate trench. In some embodiments, these strengthened gate dielectric layers may comprise both a conventional gate dielectric layer and an auxiliary dielectric layer placed on top of the conventional gate dielectric layer. The strengthened dielectric layer can be thicker than the conventional dielectric layer (and can often be several times thicker), thus achieving improved protection against oxide breakdown at the upper corner portions of the ends of the gate trench. Accordingly, the gate-trench power semiconductor device according to embodiments of the present invention can exhibit an extended lifespan. Also, in the fabrication of the gate-trench power semiconductor device according to embodiments of the present invention, the wet etching performed to remove the field oxide from the gate trench may be omitted. Accordingly, potential lateral undercut of the field oxide layer under the gate bus that can occur during such wet etching can be avoided. This further improves the reliability of the gate-trench power semiconductor device according to embodiments of the present invention.

[0078] According to a further embodiment of the present invention, the enhanced gate dielectric layer may extend along the length of the gate trench over the upper surface of the semiconductor layer structure to achieve an improved protection against breakage of the gate dielectric layer along the entire length of the upper corner of the gate trench. In some embodiments, this may be achieved by having an auxiliary dielectric layer that vertically overlaps a portion of each gate dielectric layer that extends along the sidewall of its respective gate trench, thereby "thickening" the upper portion of each gate dielectric layer along the entire length of each gate trench. In other embodiments, the auxiliary dielectric layer may extend laterally and vertically overlap the gate fingers. Such embodiments may achieve even greater protection against dielectric breakdown.

[0079] Before discussing the gate trench power semiconductor device according to an embodiment of the present invention and a method of forming such a device, it is beneficial to evaluate a conventional gate trench power semiconductor device.

[0080] FIG. 2A is a schematic top view of a conventional power MOSFET 100. FIG. 2B is a schematic plan view of the power MOSFET 100 with various upper side metal layers and dielectric layers omitted to show the gate fingers and the gate bus. FIG. 3A is a greatly enlarged view of part C of the top view of FIG. 2B. FIGS. 3B to 3D are schematic cross-sectional views taken along lines B-B, C-C, and D-D of FIG. 3A. It will be understood that the thicknesses of the various layers, patterns, and elements in FIGS. 3A to 3D and other figures in this specification are not necessarily to scale.

[0081] First, referring to FIGS. 3B to 3D, it can be seen that the power MOSFET 100 includes a semiconductor layer structure 150 and a plurality of metal layers and dielectric layers formed on both sides of the semiconductor layer structure 150.

[0082] Referring to FIG. 2A, gate bond pads 102 and one or more source bond pads 104-1, 104-2 are formed on the upper side of the semiconductor layer structure 150, and a drain pad (not shown) may be provided on the bottom side of the MOSFET 100. Each of the gate pad 102 and the source pad 104 may be formed of a metal such as aluminum to which a bond wire can be easily attached via a conventional technique such as thermocompression or soldering. A protective layer 109 such as a polyimide layer may cover the entire upper surface of the MOSFET 100 other than the gate pad 102 and the source pad 104.

[0083] The MOSFET 100 includes source contacts 170 / 172 (shown by the dashed box in FIG. 2A) that electrically connect the source region 130 (FIGS. 3B to 3D) in the semiconductor layer structure 150 to the source bond pads 104-1, 104-2. In some embodiments, the source bond pads 104-1, 104-2 may be the portions of the source contacts 170 / 172 that are exposed through the openings in the protective layer 109. The source contacts 170 / 172 are generally placed on or corresponding to the "active region" 106 of the MOSFET where the unit cell transistors are located. The inactive region 108 of the MOSFET 100 surrounds the active region 106. The inactive region 108 may include a guard ring, a junction termination element or other termination structure, a gate pad region placed under the gate pad 102, and a termination region extending to the periphery of the device including a gate bus region (discussed below).

[0084] Bond wires are shown in FIG. 2A, which can be used to connect the gate bond pads 102 and the source bond pads 104 to an external circuit or the like. A drain pad (not shown) on the bottom side of the MOSFET 100 may be connected to an external circuit, for example, through a submount (not shown) placed below.

[0085] Referring to FIG. 2B, the MOSFET 100 further includes a plurality of gate fingers 166 connected to the gate pad 102 via one or more gate buses 174. The gate fingers 166 may include, for example, a doped polysilicon pattern. The gate fingers 166 may extend horizontally across the semiconductor layer structure 150 (as shown in FIG. 2B), or may extend vertically across the semiconductor layer structure 150. Other configurations may be used (for example, the unit cell may have a hexagonal configuration). The gate fingers 166 are formed in gate trenches within the upper surface of the semiconductor layer structure 150. The gate pad 102 and the gate buses 174 may comprise a metal structure in the exemplary embodiment and are within the inactive region 108 of the MOSFET 100.

[0086] FIG. 3A is a highly enlarged view of portion “C” of FIG. 2B showing the portion of the MOSFET 100 where some of the gate fingers 166 of the MOSFET 100 connect to one of the gate buses 174. As shown in FIG. 3A, the gate bus 174 is connected to a gate pad 176 (the gate pad 176 may be the gate bond pad 102 or may be a separate structure electrically connected to the gate bond pad 102). The connection between the gate bus 174 and the gate pad 176 may be a direct connection as shown in FIG. 3A or alternatively may be through a gate resistor (not shown). A plurality of gate trenches 160 are formed within the semiconductor layer structure 150 and terminate near the gate bus 174. The source contacts 170 / 172 extend over the gate trenches 160 in the inactive region 108. The intermetal dielectric layer 168 (for example, a silicon oxide layer) insulates the gate fingers 166, the gate buses 174, and the gate pad 176 from the source contacts 170 / 172.

[0087] Figures 3B to 3D show the layer structure of the MOSFET 100. First, referring to FIGS. 3C and 3D, the MOSFET 100 includes a substrate 110. The substrate 110 may include, for example, a single crystal 4H silicon carbide semiconductor substrate highly doped with n-type impurities (i.e., an n+ silicon carbide substrate). An n-type silicon carbide drift region 112 is formed on the upper surface of the substrate 110. The n-type silicon carbide drift region 112 may be formed, for example, by epitaxial growth on the silicon carbide substrate 110. The n-type silicon carbide drift region 112 may be a low-concentration n-type (n - ) region, and in this specification, it may be referred to as either a drift "region" or a drift "layer". In the exemplary embodiment, the n-type silicon carbide drift region 112 may have a doping concentration of 1×10 14 to 5×10 16 dopants / cm 3 . The n-type silicon carbide drift region 112 may be, for example, a thick region having a vertical height of 3 to 100 microns above the substrate 110. The upper portion of the n-type silicon carbide drift region 112 is doped at a higher concentration than its lower portion (for example, 1×10 16 to 1×10 17 dopants / cm 3 ), and a current diffusion layer may be provided in the upper portion of the n-type silicon carbide drift region 112.

[0088] A medium-concentration (p)p-type silicon carbide well region 120 ("p-well") is formed on the upper surface of the current diffusion layer 114. The p-well 120 may be formed, for example, by ion implantation. Then, for example, by ion implantation, a high-concentration (n + ) n-type silicon carbide source region 130 is formed in the upper portion of the p-type well 120. As shown in FIGS. 3B and 3D, a deep shielding region 124 is provided in the drift region 112 and the current diffusion layer 114. (Since the deep shielding connection pattern 122 is outside the portion shown in cross-section in FIGS. 3B to 3D), although not visible in the figure, a high-concentration (p +)A p-type silicon carbide deep shielding connection pattern 122 is formed. Finally, a high-concentration p-type (p - ) region 140 is formed in the upper portion of the n-type drift region 112 by ion implantation. The high-concentration p-type (p - ) region 140 is formed in the inactive region 108 of the MOSFET 100. The high-concentration p-type (p - ) region 140 is formed under the gate bus 174 and the gate pad 176. The substrate 110, the drift region 112, the current diffusion layer 114, the p-well 120, the deep shielding connection pattern 122, the source region 130, and the high-concentration p-type (p - ) region 140 form a semiconductor layer structure 150. Each of these regions may contain silicon carbide. Therefore, the semiconductor layer structure 150 may be a wide-bandgap semiconductor layer structure 150.

[0089] A plurality of gate trenches 160 are formed on the upper surface of the semiconductor layer structure 150 (for example, by etching). It will be understood that only a small portion of each gate trench 160 can be seen in FIG. 3A. A gate dielectric layer 164 lines the bottom, sidewalls, and end walls of each gate trench 160. Each gate fin 166 may substantially fill each gate trench 160 and is separated from the semiconductor layer structure 150 by the gate dielectric layer 164. At the end of the gate trench 160, each gate fin 166 includes a gate fin extension 167 that protrudes laterally across the semiconductor layer structure 150 from the gate trench 160. The gate dielectric layer 164 and the field oxide layer 162 separate each gate fin extension 167 from the semiconductor layer structure 150. The gate bus 174 is formed on the gate fin extension 167 to provide an electrical connection between the gate fin 166 and the gate bus 174.

[0090] During the on-state operation, a high electric field is generated in a portion of the gate dielectric layer 164 that extends along the upper sidewalls and end walls of each gate trench 160. Due to the field mixing effect, a high electric field is generated at the upper corners of the gate trench 160 where the sidewalls and end walls of the gate trench 160 merge with the upper surface of the semiconductor layer structure 150. The electric field along the upper surface of the sidewall of the gate trench 160 can be reduced by recessing the upper surface of the gate fin 166 below the upper surface of the gate trench 160. However, at the end of the gate trench 160 where the gate fin extension 167 protrudes from the gate trench 160 and connects to the gate bus 174, the gate fin 166 cannot be recessed. As a result, a very high electric field (as indicated by the arrow) can be generated in a portion of the gate dielectric layer 164 within the region labeled E in FIG. 3B. These high electric fields may damage the corner regions of the gate dielectric layer 164 that are circled in region E.

[0091] The upper corner of the gate trench 160 refers to the region where the sidewalls (or end walls) of the gate trench 160 on opposite sides of each other meet or intersect with the upper surface of the semiconductor layer structure 150, and the lower corner of the gate trench 160 refers to the region where the sidewalls (or end walls) of the trench 160 on opposite sides of each other meet or intersect with the bottom surface of the gate trench 160. Thus, it will be understood that "corner / corner" can refer to both two-dimensional corners / corners (such as those shown in region E of FIG. 3B) and / or three-dimensional corners / corners existing, for example, in a cubic shape.

[0092] As discussed above, one common failure mechanism in power semiconductor devices is device failure due to breakdown of the gate dielectric layer. The strength of the electric field generated in the gate dielectric layer of a conventional power semiconductor device during on-state operation is not constant. The gate dielectric layer 164 of the MOSFET 100 in FIGS. 3A - 3D may be regarded as the dielectric of a U-shaped parallel plate capacitor, with each gate finger 166 acting as the inner plate of the capacitor, and the portion of the gate dielectric layer 164 on the other side of the gate finger 166 in the semiconductor layer structure 150 acting as the outer plate of the capacitor. Since the bottom and side walls of the U-shaped capacitor act like those of a standard parallel plate capacitor, during on-state operation, the electric field will generally have a constant value throughout these "parallel plate" regions of the gate dielectric layer. However, in the lower and upper "corner regions" of the gate dielectric layer 164, which are the portions where the vertical extension of the gate dielectric layer 164 transitions to the horizontal extension, the electric field mixing effect raises the level of the electric field. During the off state (reverse blocking operation), the highest electric field occurs at the lower corner of the dielectric layer 164 where the side wall of the gate trench 160 merges with its bottom surface. During the on state (forward conduction operation), the highest electric field occurs at the upper corner of the gate dielectric layer 164 where the gate dielectric layer 164 extends from the upper side wall and end wall of the gate trench 160 to the upper surface of the semiconductor layer structure 150. As described above, the upper surface of the gate finger 166 may be recessed below the upper surface of the gate trench 160, thereby reducing the electric field of the gate dielectric layer 164 along the upper side wall of the gate trench 160. However, as shown in FIG. 3B, in order to electrically connect the gate finger 166 to the gate bus 174, the corresponding gate finger connector 167 needs to extend beyond the end wall of each gate trench 160 and contact each gate finger 166 within the gate trench 160. Therefore, such a recess cannot occur adjacent to at least one end wall of each gate trench 160.

[0093] When a gate - bias voltage is applied so that MOSFET100 enters its on - state, a very high electric field is formed in a portion where the electric field makes a 90° transition after extending vertically on the end - walls of the gate - trench 160 in the gate - oxide layer 164 and then extending horizontally over the semiconductor layer structure 150. Here, the electric field becomes particularly high due to the electric - field mixing effect that occurs in the corner / corner region of the dielectric layer. Therefore, this portion of the gate - oxide layer 164 is particularly prone to breakdown.

[0094] As discussed above, according to an embodiment of the present invention, an improved gate - trench power semiconductor device is provided that has a thicker dielectric layer lining the end - walls of the gate - trench. By providing a thickened dielectric layer adjacent to the upper portion of the end - walls of the gate - trench, the electric field is more diffused in these regions during on - state operation to reduce its level, and more dielectric material is provided between the gate structure and the semiconductor layer structure. Therefore, the semiconductor device according to the embodiment of the present invention is less prone to breakdown.

[0095] Figures 4A - 4D are various views of a gate - trench MOSFET200 according to an embodiment of the present invention. Specifically, Figure 4A is a highly magnified view of the MOSFET showing the region corresponding to portion C shown in Figure 2B of MOSFET200 (Figures 2A and 2B show MOSFET100, but note that the corresponding figures of MOSFET200 are the same as those shown in Figures 2A and 2B and are not provided or described in this specification). Figure 4B is a schematic cross - sectional view taken along line B - B of Figure 4A. Figure 4C is a schematic cross - sectional view taken along line C - C of Figure 4A. Finally, Figure 4D is a schematic cross - sectional view taken along line D - D of Figure 4A.

[0096] As shown in FIGS. 4B to 4D, the silicon carbide drift region 212 is provided on the upper surface of the substrate 210. The substrate 210 may include, for example, a single crystal 4H silicon carbide semiconductor substrate highly doped with an n-type impurity (i.e., an n+-silicon carbide substrate). However, other polytype silicon carbide substrates may be used, or the substrate may be made of a material other than silicon carbide. The n-type silicon carbide drift region 212 may be formed, for example, by epitaxial growth on the silicon carbide substrate 210. The n-type silicon carbide drift region 212 may be lightly doped with an n-type dopant (n - ). For example, the n-type silicon carbide drift region 212 may have a doping concentration of 1×10 14 to 5×10 16 dopants / cm 3 . The n-type silicon carbide drift region 212 may be, for example, a thick region having a vertical height of 3 to 100 microns above the substrate 210. The upper portion of the n-type silicon carbide drift region 212 is doped at a higher concentration than its lower portion (for example, 1×10 16 to 1×10 17 dopants / cm 3 ), and a current diffusion layer 214 may be provided on the upper portion of the n-type silicon carbide drift region 212.

[0097] A medium-concentration (p)p-type silicon carbide well region 220 (“p-well”) is formed on the upper surface of the current diffusion layer 214. The p-well 220 may be formed, for example, by ion implantation. Next, a high-concentration (n + ) n-type silicon carbide source region 230 is formed, for example, by ion implantation, in the upper portion of the p-type well 220. As shown in FIGS. 4B and 4D, a deep shielding region 224 is provided in the drift region 212 and the current diffusion layer 214. (Since the deep shielding connection pattern 222 is outside the portion shown in cross section in FIGS. 4B to 4D), although not visible in the figure, a high-concentration (p +)A p-type silicon carbide deep shielding connection pattern 222 is formed. Finally, a high-concentration p-type (p - ) region 240 is formed in the upper portion of the n-type drift region 212 by ion implantation. By ion implantation in at least a part of the inactive region 208 of the device (corresponding to the region 108 in FIG. 2A), a high-concentration p-type (p - ) region 240 is formed in the upper portion of the n-type drift region 212. Specifically, the high-concentration p-type (p - ) region 240 is formed in the portion of the inactive region 208 of the MOSFET 200 that is under the gate bus 274 and the gate pad 276. The substrate 210, the drift region 212, the current diffusion layer 214, the p-well 220, the deep shielding connection pattern 222, the source region 230, and the high-concentration p-type (p - ) region 240 form a semiconductor layer structure 250. Each of these regions and layers may contain silicon carbide. It will be understood that the semiconductor layer structure 250 shown in FIGS. 10A to 10D is only an example, and other configurations of the semiconductor layer structure 250 may be used without departing from the embodiments described herein. For example, the semiconductor layer structure 250 may include additional layers or regions, or a region (for example, the current diffusion layer 214) may be omitted.

[0098] A plurality of gate trenches 260 are formed on the upper surface of the semiconductor layer structure 250 (for example, by etching). It will be understood that only a small portion of each gate trench 260 can be seen in FIG. 4A. A gate dielectric layer 264 lines the bottom, side walls, and end walls of each gate trench 260. The gate dielectric layer 264 also extends into the high-concentration p-type (p - ) region 240. Each gate fin 266 may substantially fill each gate trench 260 and is separated from the semiconductor layer structure 250 by the gate dielectric layer 264.

[0099] At the end of the gate trench 160, each gate finger 166 includes a gate finger extension 167 that protrudes laterally across the semiconductor layer structure 150 from the gate trench 160. The gate dielectric layer 164 and the field oxide layer 162 separate each gate finger extension 167 from the semiconductor layer structure 150. The gate bus 174 is formed on the gate finger extension 167 to achieve an electrical connection between the gate finger 166 and the gate bus 174. The auxiliary dielectric layer 262 extends over a portion of the gate dielectric layer 264 that extends to the high-concentration p-type (p - ) region 240. The auxiliary dielectric layer 262 further extends to the upper surface of the gate finger 266. The auxiliary dielectric layer 262 may have a thickness that is, for example, two to fifteen times that of the gate dielectric layer 264. In some embodiments, the auxiliary dielectric layer 262 may be a field oxide layer.

[0100] As described above, the auxiliary dielectric layer 262 overlaps both the gate trench 260 and the gate finger 266 in the vertical direction. In this specification, two elements of a semiconductor device "vertically overlap" when an axis perpendicular to the bottom surface of the semiconductor layer structure of the device intersects both elements.

[0101] As best shown in FIG. 4B, the auxiliary dielectric layer 262 increases the amount of dielectric material provided at the upper edge of the end of the gate trench 260. This diffuses the electric field in this region of the gate dielectric layer 264 during the on-state operation. Also, by thickening the layer of dielectric material in this region of the device, more dielectric material needs to be damaged before the dielectric layer is damaged enough to allow a short circuit between the gate finger 266 and the semiconductor layer structure 250, so the time to breakdown is extended. Thus, the auxiliary dielectric layer 262 can significantly extend the expected lifetime of the MOSFET 200 compared to the expected lifetime of the MOSFET 100 under the same operating conditions.

[0102] FIGS. 5A to 5D through FIGS. 20A to 20D are various diagrams showing a method of manufacturing the MOSFET 200 of FIGS. 4A to 4D. Specifically, FIGS. 5A to 20A are schematic top views corresponding to region C shown in FIG. 2B. FIGS. 5B to 20B are schematic cross-sectional views taken along corresponding B-B lines of FIGS. 5A to 20A, FIGS. 5C to 20C are schematic cross-sectional views taken along corresponding C-C lines of FIGS. 5A to 20A, and FIGS. 5D to 20D are schematic cross-sectional views taken along corresponding D-D lines of FIGS. 5A to 20A. Note that in FIGS. 5A to 20A, only cross-hatching is shown in order not to obscure the drawings, and labels B-B, C-C, and D-D are not shown. FIG. 4A includes labels B-B, C-C, and D-D, and it will be understood that the corresponding cross-hatching in FIGS. 5A to 20A is the same as that shown in FIG. 4A.

[0103] Referring to FIGS. 5A to 5D, a low-concentration n-type drift layer 212 is formed on a high-concentration n-type semiconductor substrate 210. Optionally, an n-type current diffusion layer 214 doped at a higher concentration than the drift layer 212 may be formed within or on an upper portion of the drift layer 212. For example, after a medium-concentration (p)p-type silicon carbide p-well 220 is formed on the current diffusion layer 214 by ion implantation, for example, by ion implantation, a high-concentration (n + )n-type silicon carbide source region 230 is formed in an upper portion of the p-well 220. Finally, as shown in FIG. 5A, a high-concentration (p + )p-type silicon carbide deep shielding connection pattern 222 is formed that electrically connects a deep trench shielding region formed under a gate trench to source contacts 270 / 272 in a later processing step. The deep shielding connection pattern 222 is outside of what is shown in cross-section in FIGS. 5B to 5D.

[0104] Referring to FIGS. 6A to 6D, an ion implantation mask (e.g., a photoresist mask) 242 is formed over the active area 206 of the MOSFET 200.

[0105] Referring to FIGS. 7A to 7D, in order to form the high-concentration p-type (p + ) region 240 in the inactive region 208 of the MOSFET 200, p-type dopants are implanted into the exposed region of the semiconductor layer structure 250 through ion implantation.

[0106] Referring to FIGS. 8A to 8D, thereafter, the ion implantation mask 242 may be removed.

[0107] Referring to FIGS. 9A to 9D, a plurality of gate trenches 260 are formed on the upper surface of the semiconductor layer structure 250. The gate trenches 260 mainly extend across the active region 206 of the MOSFET 200, but the end portions of the gate trenches 260 may extend into the inactive region 208. As shown in FIGS. 9C and 9D, the gate trenches 260 may extend vertically through the p-well 220 and may also extend partially or completely through the current diffusion layer 214. In this specification, the "vertical" direction is a direction that extends perpendicular to the main surface of the semiconductor layer structure of the device. The gate trenches 260 may have a depth of, for example, from 0.5 to 3.0 microns. The sidewalls of the p-well 220 exposed by the gate trenches 260 serve as the channel region of the completed MOSFET 200.

[0108] Referring to FIGS. 10A to 10D, an annealing step is performed to round the upper edge portion of the gate trench 260. Also, by ion implantation, a high-concentration p-type (p + ) deep shielding region 224 is formed under the gate trench 260 in the semiconductor layer structure 250, and as shown in FIG. 10A, as part of this ion implantation process, a p-type deep shielding connection pattern 222 may be formed at selected locations on the sidewalls of each gate trench 260. The mask used to form the deep shielding region 224 and the deep shielding connection pattern 222 is not shown.

[0109] As shown, at this processing stage, the device includes a semiconductor layer structure comprising a substrate 210, a drift layer 212, a current diffusion layer 214, a well region 220, a deep shielding connection pattern 222, a deep shielding pattern 224, a source region 230, and a high concentration p-type layer 240. A trench 260 is provided on the upper surface of the semiconductor layer structure 250, and a deep shielding region 224 is formed under each gate trench 260.

[0110] Referring to FIGS. 11A-11D, the gate dielectric layer 264 is a blanket formed in the active region 206 of the device (and extending into a portion of the inactive region 208). The gate dielectric layer 264 can include a stable dielectric material having a bandgap of approximately 2 eV (or more) greater than the semiconductor material placed under the gate dielectric layer 264. The gate dielectric layer 264 is typically implemented as a silicon oxide (SiO2) layer, although other materials may be used. For example, the gate dielectric layer 264 may alternatively include silicon nitride, silicon oxynitride, etc. In some cases, the gate dielectric layer 264 may be a multilayer structure including at least two layers of different dielectric materials.

[0111] The gate dielectric layer 264 may be a conformal layer lining the bottom, sidewalls, and end walls of the gate trench 260. As shown, the gate dielectric layer 264 may also extend onto the upper surface of the semiconductor layer structure 250. In other embodiments, the gate dielectric layer 264 may not extend onto the upper surface of the semiconductor layer structure 250, or a part or all of any such portion may be removed. Typically, the thickness of the gate dielectric layer is based on the desired equivalent electrical oxide thickness to optimize various performance characteristics of the device. For example, when a silicon oxide dielectric layer is used, the typical thickness of the gate oxide layer in a silicon carbide-based power semiconductor device may be, for example, approximately 300 - 1500 nm. After the gate dielectric layer 264 is formed, an annealing step may be performed in a nitrogen / oxygen atmosphere to densify the gate dielectric layer 264.

[0112] As used herein, when referring to the "thickness" of a gate dielectric layer (e.g., gate dielectric layer 264), it should be noted that this thickness refers to the extent of the gate dielectric layer in a direction perpendicular to the underlying surface on which the gate dielectric layer is formed. Thus, for the portion of the gate dielectric layer 264 that is on the upper surface of the semiconductor layer structure 250 and the portion that is below the gate trench 260, the vertical thickness of the gate dielectric layer 264 is measured, and for the portion of the gate dielectric layer 264 that is on the sidewalls and end walls of the gate trench 260, the horizontal thickness is measured.

[0113] Continuing to refer to FIGS. 11A - 11D, the conductive layer 265 is a deposited blanket that is patterned in a later processing step to form the gate fingers 266 of the MOSFET 200. In an exemplary embodiment, the conductive layer 265 may be a doped polysilicon layer. In other embodiments, the conductive layer 265 may include a silicide (e.g., NiSi, TiSi, WSi, CoSi), a metal, or another stable conductor. Other suitable materials for the gate electrode include various metals such as Ti, Ta, or W, or metal nitrides such as TiN, TaN, or WN. The conductive layer 265 may fill the gate trench 260 and may further cover the entire semiconductor layer structure 250.

[0114] Referring to FIGS. 12A to 12D, an etch-back process is performed on the conductive layer 265 to remove the conductive layer 265 except for the portion within the gate trench 260. The conductive layer 265 is a conformal layer deposited to have a thickness exceeding twice the width of the gate trench 260. As a result, the conductive layer 265 may fill the gate trench 260 and have a small depression (a place where the thickness decreases, not shown) extending longitudinally above the central portion of each trench 260. This etch-back process may be reactive ion etching and may remove the conductive pattern 265 except for the portion within the gate trench 260. This etch-back process converts the conductive layer 265 into a plurality of gate fingers 266 formed within each gate trench 260. Depending on the selection of the etch recipe, the portion of the gate oxide layer 264 outside the gate trench 260 may or may not be removed during this etch-back process. Although the gate oxide layer 264 is shown in FIGS. 12A to 12D as not being removed from the upper surface of the semiconductor layer structure 250, it will be understood that if a different etch recipe is used, the portion of the gate oxide layer 264 outside the gate trench may be removed.

[0115] Referring to FIGS. 13A - 13D, an auxiliary dielectric layer 262 is deposited on the semiconductor layer structure 250. The auxiliary dielectric layer 262 may be a single oxide layer or a combination of dielectric layers, such as one or more silicon oxide layers, for example. The auxiliary dielectric layer 262 may be a thick layer (e.g., having a thickness of 4000 - 15,000 angstroms). In an exemplary embodiment, the auxiliary dielectric layer 262 may be 2 - 15 times thicker than the gate dielectric layer 264. In other embodiments, the auxiliary dielectric layer 262 may be 4 - 12 times thicker than the gate dielectric layer 264, or 6 - 10 times thicker than the gate dielectric layer 264. In an exemplary embodiment, the auxiliary dielectric layer 262 may be a field oxide layer 262. The auxiliary dielectric layer 262 may be formed, for example, using a high - temperature oxide deposition process. The auxiliary dielectric layer 262 may be formed throughout the inactive region 208 of the device or may be a blanket formed across the entire device.

[0116] Referring to FIGS. 14A - 14D, an etch - back process is performed on the auxiliary dielectric layer 262. The auxiliary dielectric layer 262 is etched so as to hardly cover the gate trench 260, but as shown in FIGS. 14A and 14B, the auxiliary dielectric layer 262 covers the end portions of the gate trench 260. Specifically, the auxiliary dielectric layer 262 extends to the upper surface of the end of each gate fin 266 and to the source region 230 adjacent to the end of the gate trench 260 (FIG. 14C). Thus, the auxiliary dielectric layer 262 extends over the gate fins in the longitudinal direction of the gate fins. In particular, the auxiliary dielectric layer 262 increases the thickness of the dielectric material layer provided above the end wall of the gate trench 260. For this reason, the electric field formed in the portion of the gate dielectric layer 264 extending from the end wall of the trench 260 to the upper surface of the p - type region 240 can have its value reduced by diffusing from the gate dielectric layer 264 to the auxiliary dielectric layer 262.

[0117] Referring to FIGS. 15A - 15D, the conductive layer 282 is selectively formed over the auxiliary dielectric layer 262 and the gate fingers 266. In an exemplary embodiment, the conductive layer 282 may include, for example, a polysilicon layer, but alternatively or additionally, other semiconductor materials or metals may be used.

[0118] Referring to FIGS. 16A - 16D, a photoresist mask 242 is formed to cover a portion of the conductive layer 282. Thereafter, an etch - back process is performed to planarize the portion of the conductive layer 282 exposed to the photoresist mask 242.

[0119] Referring to FIGS. 17A - 17D, the photoresist mask 242 is removed.

[0120] Referring to FIGS. 18A - 18D, a photoresist mask 244 is formed to cover a portion of the conductive layer 282. Then, another etch - back process is performed to further planarize the portion of the conductive layer 282 exposed to the photoresist mask 244 to convert the conductive layer 282 into one or more gate connectors 280. The gate connectors 280 are used to electrically connect each gate finger 266 to a gate bus formed in a later processing step. The gate connectors 280 may include a plurality of individual gate connectors that each connect a respective gate finger 266 to the (later - formed) gate bus, or may comprise one or more larger conductive structures where each electrically connects a number of gate fingers 266 to the gate bus. Note that in some embodiments, as shown in FIGS. 16A - 16D, since the conductive layer 282 can function as the gate connector 280, the processing steps shown in FIGS. 18A - 18D may be omitted.

[0121] Referring to FIGS. 19A to 19D, the inter-metal dielectric layer 268 is a blanket formed in the active region 206. The inter-metal dielectric layer 268 may include, for example, a silicon oxide layer, but embodiments of the present invention are not limited thereto. For example, in other embodiments, alternatively or additionally, the inter-metal dielectric layer 268 may include silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, or the like. Then, as can be seen by looking at FIGS. 19C and 19D, the inter-metal dielectric layer 268 is selectively etched to expose the semiconductor layer structure 250 between the gate trenches 260 (e.g., the source region 220 and the deep shield connection pattern 222). This etching step may convert a portion of the inter-metal dielectric layer 268 in the active region 206 into a plurality of elongated gate insulating fingers that cover the upper surfaces of the respective gate fins 266.

[0122] Continuing to refer to FIGS. 19A to 19D, an ohmic source contact metal 270 is formed in the exposed region of the semiconductor layer structure 250 in the active region 206. The ohmic source contact metal 270 may be selectively deposited (not shown), or may be a blanket deposited so as to extend into the inter-metal dielectric layer 268 and then etched back. In an exemplary embodiment, the ohmic source contact metal 270 may include a metal that forms an ohmic contact using silicon carbide. The ohmic source contact metal 270 may include one or more layers that perform various functions, such as a layer that forms an ohmic contact, a layer that forms a diffusion barrier, and the like. As best shown in FIGS. 19B to 19D, the inter-metal dielectric layer 268 covers the gate fins 266 to prevent the gate fins 266 from shorting to the source contact metallization 270. The inter-metal dielectric layer 268 also electrically isolates the gate connector 280 from the ohmic source contact metal 270.

[0123] Referring to FIGS. 20A to 20D, the inter-metal dielectric layer 268 is etched in the inactive region 208 to expose the end portions of the gate connector 280.

[0124] Referring again to FIGS. 4A - 4D (showing the completed device), the metal for forming all three of the bulk source contact metal layer 272, the gate bus 274, and the gate pad 276 is deposited (by either selectively etching the metal or selectively depositing the metal after the metal has been deposited). The bulk source contact metal layer 272 is formed in the active region 206 of the MOSFET 200, and the gate bus 274 and the gate pad 276 are formed in the inactive region 208 of the MOSFET 200. A metal drain contact (not shown) is formed on the lower surface of the substrate 210, which is on the opposite side of the drift layer 212.

[0125] As best shown in FIG. 4B, the auxiliary dielectric layer 262 extends to the ends of the gate fingers 266 adjacent to the gate bus 274. For this reason, the auxiliary dielectric layer 262 increases the amount of dielectric material provided at the upper edge of the end of each gate trench 260. Thus, when a gate bias voltage is applied such that the MOSFET 200 is in its on state, the electric field generated in this region of the gate dielectric layer 264 diffuses into the auxiliary dielectric layer 262, which serves to reduce the magnitude of the electric field received in this corner region of the gate dielectric layer 264. Also, by thickening the layer of dielectric material in this region of the device, more dielectric material needs to be damaged before the dielectric layer is damaged enough to allow a short circuit between the gate finger 266 and the semiconductor layer structure 250, so the time until breakdown is extended. Thus, the auxiliary dielectric layer 262 can significantly extend the expected lifetime of the MOSFET 200 compared to the expected lifetime of the MOSFET 100 under the same operating conditions.

[0126] Accordingly, as shown in FIGS. 4A-4D, according to an embodiment of the present invention, a gate-trench semiconductor device is provided that includes a semiconductor layer structure 250 having a gate-trench 260 formed on an upper surface. Gate fingers 266 are formed within the gate-trench 260. An auxiliary dielectric layer 262 is formed on an upper surface of the gate fingers 266 and, in some embodiments, may be in direct contact with the gate fingers 266. The auxiliary dielectric layer 262 also overlaps the gate-trench 260 in a direction perpendicular thereto. In some embodiments, the auxiliary dielectric layer 262 may be a field oxide layer. In some embodiments, the auxiliary dielectric layer 262 may extend under a gate pad 276 and / or one or more gate buses 274 of the gate-trench semiconductor device. The auxiliary dielectric layer 262 may be significantly thicker than the gate dielectric layer 264 (e.g., two to ten times thicker). The semiconductor device may further include a gate connector 280 on the upper surface of the auxiliary dielectric layer 262 and on the upper surface of the gate fingers 266.

[0127] The semiconductor device may further include a gate dielectric layer 264 between the semiconductor layer structure 250 and the gate fingers 266 within the gate-trench 260. The auxiliary dielectric layer 262 is in direct contact with a portion of the gate dielectric layer 264 that at least partially covers an upper corner of the gate-trench 260. The gate-trench 260 extends longitudinally within the semiconductor layer structure 250 and has a longitudinally extending lower surface, first and second longitudinally extending side walls on opposite sides of each other, and first and second end walls on opposite sides of each other. The gate dielectric layer 264 has a first portion that extends upward along the first end wall of the gate-trench. The auxiliary dielectric layer 262 may be in direct contact with this first portion of the gate dielectric layer 264.

[0128] The semiconductor device may further include an inter-metal dielectric layer 268 on the upper surface of the gate connector 280, source contacts 270 / 272 on the upper surface of the inter-metal dielectric layer 268, and a gate bus 274 on the upper surface of the auxiliary dielectric layer 262. The inter-metal dielectric layer 268 may overlap the auxiliary dielectric layer 262 in the vertical direction. The gate connector 280 may electrically connect the gate bus 274 to the gate fin 266, and the gate connector 280 may be between the auxiliary dielectric layer 262 and the inter-metal dielectric layer 268.

[0129] In some embodiments, the auxiliary dielectric layer 262 may extend over the upper surface of a portion of the semiconductor layer structure 250 that is in the inactive area 208 of the semiconductor device adjacent to the end of the gate trench 260.

[0130] According to a further embodiment of the present invention, there is provided a gate trench semiconductor device comprising a semiconductor layer structure 250 having a gate trench 260 therein, with a gate fin 266 and a gate dielectric layer 264 disposed within the gate trench 260. An auxiliary dielectric layer 262 is formed on the upper surface of the gate dielectric layer 264 and on the upper surface of the gate fin 266. An inter-metal dielectric layer 268 overlaps the auxiliary dielectric layer 262 in the vertical direction and / or overlaps the gate trench 260 in the vertical direction.

[0131] According to yet another embodiment of the present invention, there is provided a gate trench semiconductor device comprising a semiconductor layer structure 250 having a gate trench 260 therein and a gate fin 266 within the gate trench 260. These semiconductor devices further comprise a gate bus 274 and a gate connector 280 for electrically connecting the gate fin to the gate bus 274. An auxiliary dielectric layer 262 is inserted between the end portion of the gate fin 266 and the gate connector 280. In some embodiments, the gate connector 280 may directly contact both the gate fin 266 and the auxiliary dielectric layer 262. According to a further additional embodiment of the present invention, a gate-trench semiconductor device comprising a semiconductor layer structure 250 is provided. A gate-trench 260 extends longitudinally within the upper surface of the semiconductor layer structure 250. The gate-trench 260 has a longitudinally extending bottom surface, first and second longitudinally extending side walls on opposite sides of each other, and first and second end walls on opposite sides of each other. A gate dielectric layer 264 is provided on the bottom surface, the first and second side walls, and the first and second end walls of the gate-trench 260. A gate finger 266 is formed within the gate-trench 266. An auxiliary dielectric layer 262 overlaps the gate-trench 260 in a direction perpendicular thereto and is in direct contact with a portion of the gate dielectric layer 264 that is at the first end wall of the gate-trench 260. The auxiliary dielectric layer 262 may also be in direct contact with the upper surface of the gate finger 266.

[0132] According to a further embodiment of the present invention, the above manufacturing process may be modified such that a portion of the auxiliary dielectric layer 262 is enabled to extend across the entire active area between the gate-trenches 260. FIG. 21 is a cross-sectional view taken across one of the gate-trenches of a MOSFET 300 including such a design.

[0133] As shown in FIG. 21, the auxiliary dielectric layer 262 is formed in the active area of the device so as to extend over the semiconductor layer structure 250 on both sides of each gate-trench 260. The auxiliary dielectric layer 262 may extend slightly into the gate-trench 260 so as to overlap the gate dielectric layer 264 extending along the side walls of the gate-trench 260 in a direction perpendicular thereto. As a result, the auxiliary dielectric layer 262 acts to increase the thickness of the side walls of the gate dielectric layer 264, whereby the electric field in the portion of the gate dielectric layer 264 that extends along the upper side wall of the gate-trench 260 can diffuse into the auxiliary dielectric layer 262, reducing the electric field level in the gate dielectric layer 264.

[0134] As shown in FIG. 21, the MOSFET 300 may be regarded as having a first dielectric layer lining the bottom and sidewalls of the gate trench 260. Here, this first dielectric layer has a thickness of "x" and corresponds to the gate dielectric layer 264. A second dielectric layer extends on the upper surface of the semiconductor layer structure 250 adjacent to each side of each gate trench 260. This second dielectric layer has a thickness of "y" and may correspond to a combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262. The thickness "y" may be greater than the thickness x, thereby improving the dielectric breakdown performance of the device. In some embodiments, the thickness y may be at least 2 times, at least 3 times, at least 4 times, at least 6 times, at least 8 times, or at least 10 times the thickness "x". In the illustrated embodiment, the second dielectric layer corresponds to a combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262, but in other embodiments, it will be understood that the gate dielectric layer 264 may be removed from the upper surface of the semiconductor layer structure so that the second dielectric layer corresponds only to the auxiliary dielectric layer 262. In other words, in some embodiments, the gate dielectric layer 264 may not extend under the auxiliary dielectric layer 262 to the upper surface of the semiconductor layer structure 250, and in such embodiments, the auxiliary dielectric layer 262 may be placed directly on the semiconductor layer structure 250. Since the auxiliary dielectric layer 262 can be significantly thicker than the gate dielectric layer 264, this still serves to improve the breakdown performance of the device.

[0135] To clarify the above discussion, FIG. 21 schematically shows a semiconductor device 300 including a semiconductor layer structure 250 having a gate trench 260 therein. A first dielectric layer is formed on the sidewalls and bottom surface of the gate trench 260. Here, the first dielectric layer corresponds to the portion of the gate dielectric layer 264 that is within the gate trench 260. A gate finger 266 is formed on the first dielectric layer 264 within the gate trench 260. A second dielectric layer is provided on the upper surface of the semiconductor layer structure 250, and this second dielectric layer is in direct contact with the upper surface of the first dielectric layer 264. Here, the second dielectric layer corresponds to the combination of the auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 that is adjacent to the gate trench 260 and is on the upper surface of the semiconductor layer structure 250. As shown in FIG. 21, the second dielectric layer 262 / 264 is thicker than the first dielectric layer 264. In the illustrated embodiment, the second dielectric layer corresponds to the combination of the auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 that is adjacent to the gate trench 260 and is on the upper surface of the semiconductor layer structure 250. However, in other embodiments, it will be understood that the gate dielectric layer 264 may not be formed on the upper surface of the semiconductor layer structure 250, or may be removed therefrom before the auxiliary dielectric layer 262 is formed. In such embodiments, the second dielectric layer may correspond to only the auxiliary dielectric layer 262. As described above, since the auxiliary dielectric layer 262 can be 2 to 15 times thicker than the gate dielectric layer 264, by making the auxiliary dielectric layer 262 that extends over the portion of the gate dielectric layer 264 covering the sidewalls of the gate trench much thicker, the breakdown performance in the on state of the MOSFET 300 can be significantly improved compared to conventional gate trench power semiconductor devices.

[0136] FIGS. 22A and 22B show a MOSFET 400 according to a further embodiment of the present invention. The MOSFET 400 is a modified version of the MOSFET 300. FIG. 22A is a cross-sectional view of the MOSFET 400 taken along line B - B of FIG. 4A. FIG. 22B is a cross-sectional view of the MOSFET 400 taken along line E - E of FIG. 4A.

[0137] As shown in FIG. 22A, in MOSFET 400, the auxiliary dielectric layer 262 extends inwardly over the gate dielectric layer 264 onto the gate trench 260, such that the auxiliary dielectric layer 262 overlaps the gate dielectric layer 264 in the gate trench 260 in a direction perpendicular thereto and also overlaps the gate fin 266 in a direction perpendicular thereto, which is different from MOSFET 300. In other words, the auxiliary dielectric layer 262 extends longitudinally adjacent to each side of each gate trench 260 and also extends laterally so as to partially cover each gate trench 260. As a result, the auxiliary dielectric layer 262 serves to further increase the amount of dielectric material present along the upper corner portion of the gate dielectric layer 264 extending along the length of the gate trench 260. Thereby, the electric field in the portion of the gate dielectric layer 264 extending along the upper sidewall of the gate trench 260 can diffuse into the auxiliary dielectric layer 262, and the electric field level in the gate dielectric layer 264 is reduced.

[0138] As further shown in FIG. 22A, the MOSFET 400 may be considered to have a first dielectric layer lining the bottom and sidewalls of the gate trench 260. Here, this first dielectric layer has a thickness of “x” and corresponds to the gate dielectric layer 264. A second dielectric layer extends over the top surface of the semiconductor layer structure 250 adjacent to each side of each gate trench 260. This second dielectric layer has a thickness of “y” and may correspond to the combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262. The thickness “y” may be greater than the thickness x, thereby improving the dielectric breakdown performance of the device. In some embodiments, the thickness y may be at least 2 times, at least 3 times, at least 4 times, at least 6 times, at least 8 times, or at least 10 times the thickness “x”. Further, the second dielectric layer may extend inwardly by a distance t from the plane defined by the sidewalls of the gate trench 260, while the first dielectric layer only extends inwardly by a distance x from the plane defined by the sidewalls of the gate trench 260. In some embodiments, the distance t may be at least 2 times, at least 3 times, at least 4 times, at least 6 times, at least 8 times, or at least 10 times the thickness “y”.

[0139] FIG. 22A is a cross-sectional view of the gate trench 260 in the active area of the MOSFET 400. In contrast, FIG. 22B is a cross-sectional view of the gate trench 260 in the inactive area of the MOSFET 400. As can be seen by comparing FIGS. 22A and 22B, the main difference is that in the inactive region of the MOSFET 400, the auxiliary dielectric layer 262 extends laterally across the gate finger 266 so as to cover the entire top surface of the end portion of the gate finger, while in the active region of the MOSFET 400, the auxiliary dielectric layer 262 only covers a portion on each side of the gate finger 266. Thereby, a conductive layer (which may be the gate connector 280) can contact the top surface of the gate finger 266 to supply a gate signal to the gate finger 266.

[0140] To clarify the above discussion, FIGS. 22A - 22B schematically show a semiconductor device 400 comprising a semiconductor layer structure 250 having a gate trench 260 therein. A first dielectric layer is formed on the sidewalls and bottom surface of the gate trench 260. Here, the first dielectric layer corresponds to the portion of the gate dielectric layer 264 that is within the gate trench 260. A gate finger 266 is formed on the first dielectric layer 264 within the gate trench 260. A second dielectric layer is provided on the upper surface of the semiconductor layer structure 250, and this second dielectric layer directly contacts and vertically overlaps the gate finger 266. In other words, the second dielectric layer extends from the upper surface of the semiconductor layer structure 250 (on each side of the gate trench 260) onto the gate trench 260 and extends a sufficient distance over the gate trench 260 until it reaches above the gate finger 266 and can directly contact the gate finger 266. Here, the second dielectric layer corresponds to a combination of the auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 that is adjacent to the gate trench 260 and on the upper surface of the semiconductor layer structure 250. However, in other embodiments, the second dielectric layer may be implemented as only the auxiliary dielectric layer 262 in the same form as discussed above with reference to the MOSFET 300 of FIG. 21. The second dielectric layer may be significantly thicker than the first dielectric layer (e.g., 2 to 15 times thicker).

[0141] MOSFETs 300 and 400 include an auxiliary dielectric layer 262 that realizes enhanced protection for the portion of the gate dielectric layer 264 that is on the upper sidewall of the gate trench 260 and can be formed in various ways. In a first approach, the conductive layer 265 (FIGS. 11A - 11D) can be planarized as shown in FIGS. 12A - 12D to form gate fingers 266, in which case the auxiliary dielectric layer 262 can be a blanket formed over the device as shown in FIGS. 13A - 13D. The auxiliary dielectric layer 262 can then be etched in a similar manner as shown in FIGS. 14A - 14D, except that small stripes of the auxiliary dielectric layer 262 can be left on each side of each gate trench (the remaining portion of the auxiliary dielectric layer 262 in the region between adjacent gate trenches can be removed so that the source contact metallizations 270 / 272 contact the semiconductor layer structure 250).

[0142] In a second approach, as shown in FIGS. 11A - 11D, the conductive layer 265 can be partially planarized, although not as shown in FIGS. 12A - 12D. An oxidation process can then be performed to oxidize the upper portion of the (polysilicon) conductive layer 265 to form the auxiliary dielectric layer 262 in the active region of the device over the gate fingers 266. The auxiliary dielectric layer 262 also extends outwardly beyond the sidewalls of the gate trench 260 as shown in FIGS. 21 and 22A - 22D. Thus, it will be appreciated that MOSFETs 300 and 400 can be fabricated in a variety of different ways.

[0143] In still other embodiments of the present invention, the auxiliary dielectric layer 262 may be formed before the gate trench 260 is formed by etching the upper surface of the semiconductor layer structure 250. In these embodiments, the devices shown in FIGS. 8A-8D may be formed first. FIGS. 23A-23D show how the gate trench may be formed. Referring to FIGS. 23A-23D, FIG. 23A is a reproduction of FIG. 8D, but with 100 added to all the reference numerals in FIG. 8D. Referring to FIG. 23B, the auxiliary dielectric layer 262 is a blanket formed over the device. Thereafter, the auxiliary dielectric layer 262 is etched. In the active regions of the device, the auxiliary dielectric layer 262 may be etched as shown in FIG. 23B, which is a cross-section taken along the same line as FIG. 23A (FIG. 8D), but the cross-section of FIG. 23B is a longer cross-section extending across the region where some gate trenches 260 are to be formed.

[0144] Referring to FIG. 23C, to form the gate trench 260, trench etching may be performed using the auxiliary dielectric layer 262 as a mask.

[0145] Referring to FIG. 23D, a conductive layer 265 (e.g., a doped polysilicon layer) may be formed that fills the gate trench 260 and extends across the upper surface of the semiconductor layer structure 250. Thereafter, appropriate etching of the conductive layer 265 and the auxiliary dielectric layer 262 may be performed to fabricate the MOSFET 200 (or MOSFET 300, 400).

[0146] The above figures focus on the regions of the illustrated MOSFETs 200, 300, 400 where the gate fingers are supplied via the gate bus, but it will be understood that some gate fingers may be supplied directly from the gate pad rather than from the gate bus. In such embodiments, the gate connector may extend between the gate pad and the gate finger, and the auxiliary dielectric layer according to an embodiment of the present invention may still overlap perpendicularly the gate trench and the corresponding gate finger that is directly connected to the gate pad.

[0147] FIG. 24 is a flow chart showing a method of fabricating a gate-trench semiconductor device according to an embodiment of the present invention. As shown in FIG. 24, the operation may start with a gate-trench being formed within a semiconductor layer structure (block 500). The semiconductor layer structure may include, for example, a silicon carbide semiconductor layer structure. Next, a gate dielectric layer is formed within the trench (block 510). In an exemplary embodiment, the gate dielectric layer may include, for example, a thin high-quality silicon oxide layer. Next, a gate finger is formed on the gate dielectric layer within the gate-trench such that the gate dielectric layer comes between the semiconductor layer structure and the gate finger (block 520). In an exemplary embodiment, the gate finger may include doped polysilicon.

[0148] Next, a secondary dielectric layer is formed on the gate finger and on the gate dielectric layer (block 530). The secondary dielectric layer may be formed over a portion of the gate finger that is within the gate-trench and may overlap the gate-trench in a direction perpendicular thereto. In some embodiments, the secondary dielectric layer may be interposed between the gate connector and the gate finger. In some cases, the secondary dielectric layer makes direct contact with both the gate connector and the gate finger. Then, a gate bus and / or a gate pad may be formed on the secondary dielectric layer (block 540). The method may also include forming a gate connector on the secondary dielectric layer (block 550). The gate connector may extend between the gate bus and the gate finger and may electrically connect the gate finger to the gate bus.

[0149] In some embodiments, the auxiliary dielectric layer may extend only over the end portions of the gate trench, and thus may extend over less than half of the length of the gate trench, or over less than a quarter of the length of the gate trench. In such embodiments, the auxiliary dielectric layer may be designed mainly to protect the portion of the gate dielectric layer that extends over the upper end wall of the gate trench. In other embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate trench in a direction perpendicular to the gate trench along substantially the entire length of the gate trench. In these embodiments, the auxiliary dielectric layer may be designed to protect the portion of the gate dielectric layer that extends over both the upper sidewall and the upper end wall of the gate trench. In some cases, the auxiliary dielectric layer may extend over substantially the entire length of the gate trench and may extend inwardly over the gate trench so as to overlap the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate trench.

[0150] The above description uses the MOSFET200 as an example, but the techniques described in this specification can be understood to be applicable to any gate trench semiconductor device that uses a metal oxide and / or a metal insulator interface, such as, for example, a MISFET, an IGBT device, and a gate-controlled thyristor. Therefore, it will be understood that the same fabrication techniques can be used to form other devices having an auxiliary dielectric layer that protects the upper corner of the gate oxide layer extending from the gate trench without departing from the embodiments described in this specification. Also, it will be understood that the above description is for an n-type MOSFET. In a p-type device, the locations of the source contact and the drain contact may be reversed, and the conduction types of other n-type and p-type regions may be swapped. All of the embodiments disclosed in this specification can be implemented as either an n-type device or a p-type device.

[0151] The present invention has been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it is to be understood that this element or layer is directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like reference numerals refer to like elements throughout.

[0152] In this specification, the terms first and second are used to describe various regions, layers, and / or elements, but it should be understood that these regions, layers, and / or elements are not to be limited by these terms. These terms are only used to distinguish one region, layer, or element from another region, layer, or element. Thus, without departing from the scope of the present invention, the first region, layer, or element discussed below could be termed the second region, layer, or element, and similarly, the second region, layer, or element could be termed the first region, layer, or element.

[0153] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the drawings. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the drawings. For example, if the device is turned over within the drawing, an element described as being on the "lower" side of another element will face the "upper" side of the other element. Thus, the exemplary term "lower side" can encompass both the "lower side" and the "upper side" depending on the particular orientation of the figure. Similarly, if the device is turned over in one of the figures, an element described as being "below" or "under" another element will face "above" the other element. Thus, exemplary terms such as "below" or "under" encompass both upward and downward orientations.

[0154] The technical terms used herein are for the sole purpose of describing particular embodiments and are not intended to limit the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0155] As used herein, "substantially" means within 10%.

[0156] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic diagrams. For this reason, for example, variations from the illustrated shape are expected as a result of manufacturing techniques and / or manufacturing tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to the specific shapes of the regions shown herein, but should include, for example, departures in shape resulting from manufacturing. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or a gradient in implantation concentration, rather than a binary change from an implanted region to an unimplanted region. Thus, the regions shown in the figures are essentially schematic, and their shapes are not intended to represent the actual shape of regions of the device and are not intended to limit the scope of the present invention.

[0157] It will be understood that the embodiments disclosed herein are combinable. Thus, features depicted and / or described with respect to a first embodiment may equally be included in a second embodiment, and vice versa.

[0158] The above embodiments have been described with reference to specific figures, but some embodiments of the present invention may include additional and / or intervening layers, structures, or elements, and / or specific layers, structures, or elements may be removed. Although some exemplary embodiments of the present invention have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without departing significantly from the novel teachings and advantages of the present invention. Accordingly, it is intended that all such modifications be included within the scope of the present invention as defined by the claims. Therefore, the above is illustrative of the present invention and should not be construed as limiting the specific embodiments disclosed, and it should be understood that the disclosed embodiments, as well as modifications to other embodiments, are intended to be included within the scope of the appended claims. The present invention is defined by the following claims, and equivalents of the claims are also included within its scope.

Claims

1. A semiconductor layer structure including a gate trench formed therein on an upper surface, a gate finger within the gate trench, an auxiliary dielectric layer on an upper surface of the gate finger and overlapping in a direction perpendicular to the gate trench, and a gate connector on the upper surface of the auxiliary dielectric layer and on the upper surface of the gate finger A semiconductor device comprising.

2. The semiconductor device according to claim 1, further comprising a gate dielectric layer between the semiconductor layer structure and the gate finger within the gate trench.

3. The semiconductor device according to claim 1, wherein the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers an upper corner portion of the gate trench.

4. The semiconductor device according to claim 3, wherein the auxiliary dielectric layer is also in direct contact with the upper surface of the gate finger.

5. The gate trench extends longitudinally within the semiconductor layer structure and has a longitudinally extending lower surface, first and second longitudinally extending side walls on opposite sides, and first and second end walls on opposite sides. The gate dielectric layer includes a first portion extending upward along the first end wall of the gate trench, and the auxiliary dielectric layer is in direct contact with the first portion of the gate dielectric layer. The semiconductor device according to claim 2.

6. The semiconductor device according to any one of claims 1 to 5, wherein the auxiliary dielectric layer overlaps the gate finger in a direction perpendicular to the gate finger over less than half of the length of the gate finger.

7. The semiconductor device according to any one of claims 2 to 6, wherein the auxiliary dielectric layer is thicker than the gate dielectric layer.

8. The semiconductor device according to claim 7, wherein the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer.

9. The gate finger extends longitudinally within the gate trench and has a longitudinally extending upper surface, a longitudinally extending lower surface, first and second longitudinally extending side walls on opposite sides, and first and second end walls on opposite sides. The auxiliary dielectric layer extends on the first end wall of the gate finger. The semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device according to any one of claims 1 to 9, further comprising an inter-metal dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the inter-metal dielectric layer.

11. The semiconductor device according to claim 10, wherein the inter-metal dielectric layer overlaps the auxiliary dielectric layer in a vertical direction.

12. The semiconductor device according to claim 10, further comprising a gate bus, wherein the gate connector electrically connects the gate bus to the gate fin, and the gate connector is between the auxiliary dielectric layer and the inter-metal dielectric layer.

13. The semiconductor device according to any one of claims 1 to 12, wherein the auxiliary dielectric layer is a field oxide layer, and the semiconductor device further comprises a gate bus on the upper surface of the auxiliary dielectric layer.

14. The semiconductor device according to claim 13, further comprising a gate pad electrically connected to the gate fin through the gate bus and the gate connector.

15. The semiconductor device according to any one of claims 1 to 14, wherein the auxiliary dielectric layer is also on the upper surface of a portion of the semiconductor device that is in an inactive area at an end of the gate trench in the semiconductor layer structure.

16. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device comprises a metal-oxide-semiconductor field-effect transistor, the semiconductor layer structure includes a silicon carbide drift layer having a first conductivity type, a silicon carbide well having a second conductivity type on an upper portion of the silicon carbide drift layer, and a silicon carbide source region having the first conductivity type on an upper portion of the silicon carbide well, and the gate fin contains silicon.

17. The semiconductor device according to any one of claims 2 to 16, wherein the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is adjacent to a sidewall of the gate trench and directly contacts the upper surface of the semiconductor layer structure, and the thickness of the second dielectric layer exceeds the thickness of the gate dielectric layer.

18. The semiconductor device according to claim 17, wherein the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench.

19. The semiconductor device according to claim 18, wherein the thickness of the auxiliary dielectric layer is at least twice the thickness of the gate dielectric layer.

20. The semiconductor device according to any one of claims 1 to 19, wherein the auxiliary dielectric layer overlaps the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate fin.

21. The semiconductor device according to claim 20, wherein the auxiliary dielectric layer is in direct contact with the gate fin along substantially the entire length of the gate fin.

22. The semiconductor device according to any one of claims 1 to 21, further comprising a gate bond pad and a gate bus, wherein the gate fin is electrically connected to the gate bond pad through at least the gate connector and the gate bus, and the auxiliary dielectric layer extends under both the gate bond pad and the gate bus.

23. A semiconductor layer structure having a gate trench therein, a gate fin in the gate trench, a gate dielectric layer between the semiconductor layer structure and the gate fin in the gate trench, a gate fin in the gate trench, an auxiliary dielectric layer on the upper surface of the gate dielectric layer and on the upper surface of the gate fin, and an inter-metal dielectric layer overlapping the auxiliary dielectric layer in a vertical direction A semiconductor device comprising.

24. The semiconductor device according to claim 23, wherein the auxiliary dielectric layer overlaps the gate trench in a direction perpendicular to the gate trench.

25. The semiconductor device according to claim 23 or 24, wherein the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench.

26. The gate trench extends in the longitudinal direction in the semiconductor layer structure and has a bottom surface extending in the longitudinal direction, first and second side walls extending in the longitudinal direction on opposite sides of each other, and first and second end walls on opposite sides of each other. The gate dielectric layer includes a first portion extending upward along the first end wall of the gate trench, and the auxiliary dielectric layer is in direct contact with the first portion of the gate dielectric layer. The semiconductor device according to any one of claims 23 to 26.

27. The semiconductor device according to any one of claims 23 to 26, wherein the auxiliary dielectric layer has a thickness of at least four times that of the gate dielectric layer.

28. The semiconductor device according to any one of claims 23 to 27, further comprising a gate bus and a gate connector for electrically connecting the gate fin to the gate bus, wherein the gate connector is between the auxiliary dielectric layer and the inter-metal dielectric layer.

29. The semiconductor device according to any one of claims 23 to 28, further comprising a gate bond pad and a gate bus, wherein the gate fin is electrically connected to the gate bond pad through at least the gate bus, and the auxiliary dielectric layer includes a field oxide layer extending under both the gate bond pad and the gate bus.

30. The semiconductor device according to any one of claims 23 to 29, wherein the auxiliary dielectric layer includes at least a part of a second dielectric layer that is adjacent to the side wall of the gate trench and directly contacts the upper surface of the semiconductor layer structure, and the thickness of the second dielectric layer is at least twice that of the gate dielectric layer.

31. The semiconductor device according to claim 30, wherein the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the side wall of the gate trench over the entire length of the gate trench.

32. The semiconductor device according to claim 30 or 31, wherein the auxiliary dielectric layer overlaps the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate fin.

33. A semiconductor layer structure having a gate trench therein, a gate fin in the gate trench, a gate bus, a gate connector for electrically connecting the gate fin to the gate bus, and an auxiliary dielectric layer inserted between an end portion of the gate fin and the gate connector. A semiconductor device comprising the above.

34. The semiconductor device according to claim 33, wherein the gate connector directly contacts both the gate fin and the auxiliary dielectric layer.

35. The semiconductor device according to claim 34, further comprising a gate dielectric layer between the semiconductor layer structure and the gate fin in the gate trench.

36. The semiconductor device according to claim 35, wherein the auxiliary dielectric layer is in direct contact with a portion that at least partially covers an upper corner of the gate trench in the gate dielectric layer.

37. The semiconductor device according to claim 36, wherein the auxiliary dielectric layer is also in direct contact with the upper surface of the gate fin.

38. The semiconductor device according to claim 37, wherein the auxiliary dielectric layer has a thickness of at least twice that of the gate dielectric layer.

39. The semiconductor device according to any one of claims 33 to 38, further comprising an intermetal dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the intermetal dielectric layer.

40. The semiconductor device according to claim 39, wherein the intermetal dielectric layer overlaps the auxiliary dielectric layer in a vertical direction.

41. The semiconductor device according to any one of claims 33 to 40, further comprising a gate bond pad and a gate bus, wherein the gate fin is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer includes a field oxide layer extending under both the gate bond pad and the gate bus.

42. The semiconductor device according to any one of claims 35 to 41, wherein the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is adjacent to a sidewall of the gate trench and in direct contact with the upper surface of the semiconductor layer structure, and the thickness of the second dielectric layer is at least four times that of the gate dielectric layer.

43. The semiconductor device according to claim 42, wherein the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench.

44. The semiconductor device according to any one of claims 33 to 43, wherein the auxiliary dielectric layer overlaps the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate fin.

45. A semiconductor layer structure, A gate trench extending longitudinally within the upper surface of the semiconductor layer structure, the gate trench having a longitudinally extending lower surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other. A gate dielectric layer on the lower surface, the first and second sidewalls, and the first and second end walls of the gate trench. A gate fin within the gate trench, and an auxiliary dielectric layer that overlaps the gate trench in a vertical direction and directly contacts a portion of the gate dielectric layer that is on the first end wall of the gate trench A semiconductor device comprising the same. **Claim 46** The semiconductor device according to claim 45, wherein the auxiliary dielectric layer also directly contacts the upper surface of the gate fin. **Claim 47** The semiconductor device according to claim 46, wherein the auxiliary dielectric layer has a thickness that is at least twice the thickness of the gate dielectric layer. **Claim 48** The semiconductor device according to any one of claims 45 to 47, further comprising a gate bus, a gate connector, and an intermetal dielectric layer, wherein the gate connector electrically connects the gate fin to the gate bus, and the intermetal dielectric layer is on the upper surface of the gate connector. **Claim 49** The semiconductor device according to claim 48, wherein the intermetal dielectric layer overlaps the auxiliary dielectric layer in a vertical direction. **Claim 50** The semiconductor device according to any one of claims 45 to 49, further comprising a gate bond pad and a gate bus, wherein the gate fin is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer includes a field oxide layer that extends under both the gate bond pad and the gate bus. **Claim 51** The semiconductor device according to any one of claims 45 to 50, wherein the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is adjacent to the side wall of the gate trench and directly contacts the upper surface of the semiconductor layer structure, and the thickness of the second dielectric layer is at least twice the thickness of the gate dielectric layer. **Claim 52** The semiconductor device according to claim 51, wherein the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the side wall of the gate trench over the entire length of the gate trench. **Claim 53** A semiconductor layer structure having a gate trench therein, a first dielectric layer on the side wall and bottom surface of the gate trench, a gate fin on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that directly contacts the upper surface of the first dielectric layer A semiconductor device comprising: wherein the second dielectric layer has a thickness that is at least twice the thickness of the first dielectric layer. A semiconductor device. **Claim 54** The semiconductor device according to claim 53, wherein the first dielectric layer includes a first portion within the gate trench of the gate dielectric layer.

55. The semiconductor device according to claim 53 or 54, wherein the second dielectric layer includes a combination of a second portion extending on the upper surface of the semiconductor layer structure of the gate dielectric layer and an auxiliary dielectric layer extending on the upper surface of the second portion of the gate dielectric layer.

56. The semiconductor device according to any one of claims 53 to 55, wherein the second dielectric layer includes an auxiliary dielectric layer extending on the upper surface of the semiconductor layer structure.

57. The semiconductor device according to any one of claims 53 to 56, wherein the second dielectric layer extends on the semiconductor layer structure adjacent to the side walls of the gate trench over the entire length of the gate trench.

58. The semiconductor device according to any one of claims 53 to 57, wherein the gate finger has first and second side walls extending in the longitudinal direction of the gate trench, and the second dielectric layer vertically overlaps both the first side wall and the second side wall of the gate finger.

59. The semiconductor device according to any one of claims 53 to 58, wherein the gate finger has first and second side walls extending in the longitudinal direction of the gate trench, and the second dielectric layer includes a first portion vertically overlapping the first side wall of the gate finger and a second portion vertically overlapping the second side wall of the gate finger.

60. The semiconductor device according to claim 59, further comprising a gate connector that electrically connects the gate finger to a gate bus.

61. The semiconductor device according to claim 60, wherein a portion of the gate connector is positioned between the first portion and the second portion of the second dielectric layer.

62. A semiconductor layer structure having a gate trench therein, a first dielectric layer on the side walls and bottom surface of the gate trench, a gate finger on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that directly contacts and vertically overlaps the gate finger. A semiconductor device comprising.

63. The semiconductor device according to claim 62, wherein the second dielectric layer is at least twice as thick as the first dielectric layer.

64. The semiconductor device according to claim 62 or 63, further comprising a gate connector that is in direct contact with both the second dielectric layer and the gate fin.

65. The semiconductor device according to any one of claims 62 to 64, wherein the first dielectric layer includes a first portion that is within the gate trench of the gate dielectric layer.

66. The semiconductor device according to any one of claims 62 to 65, wherein the second dielectric layer includes a combination of a second portion that extends on the upper surface of the semiconductor layer structure of the gate dielectric layer and an auxiliary dielectric layer that extends on the upper surface of the second portion of the gate dielectric layer.

67. The semiconductor device according to any one of claims 62 to 66, wherein the second dielectric layer includes an auxiliary dielectric layer that extends on the upper surface of the semiconductor layer structure.

68. The semiconductor device according to any one of claims 62 to 67, wherein the second dielectric layer is in direct contact with the gate fin along substantially the entire length of the gate fin.

69. The gate fin includes first and second sidewalls that extend in the longitudinal direction of the gate trench, and the second dielectric layer includes a first portion that vertically overlaps the first sidewall of the gate fin and a second portion that vertically overlaps the second sidewall of the gate fin. The semiconductor device according to any one of claims 62 to 68.

70. The semiconductor device according to claim 69, further comprising a gate connector that electrically connects the gate fin to a gate bus, and a portion of the gate connector is positioned between the first portion and the second portion of the second dielectric layer.

71. A method of forming a semiconductor device, comprising: forming a gate trench in a semiconductor layer structure; forming a gate dielectric layer in the gate trench; forming a gate fin on the gate dielectric layer within the gate trench; forming an auxiliary dielectric layer on the gate fin and on the gate dielectric layer; forming a gate bus on the auxiliary dielectric layer and including a method.

72. The method according to claim 71, wherein the auxiliary dielectric layer is formed on a portion of the gate fin that is within the gate trench.

73. The method according to claim 71, wherein the auxiliary dielectric layer overlaps the gate trench in a direction perpendicular to the gate trench.

74. The method according to any one of claims 71 to 73, further comprising the step of forming a gate connector on the auxiliary dielectric layer.

75. The method according to claim 74, wherein the auxiliary dielectric layer is inserted between the gate connector and the gate finger.

76. The method according to claim 75, wherein the gate connector extends between the gate bus and the gate finger and electrically connects the gate finger to the gate bus.

77. The method according to any one of claims 71 to 73, wherein the auxiliary dielectric layer extends over less than half of the length of the gate trench on the gate trench.

78. The method according to any one of claims 71 to 77, wherein the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate trench in a direction perpendicular to the gate trench along substantially the entire length of the gate trench.

79. The method according to any one of claims 71 to 78, wherein the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate finger in a direction perpendicular to the gate finger along substantially the entire length of the gate trench.

80. The semiconductor device according to any one of claims 1 to 22, wherein the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

81. The semiconductor device according to claim 28, wherein the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

82. The semiconductor device according to claim 33, wherein the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a part of the inactive region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a part of the active region of the semiconductor device.

83. The semiconductor device according to claim 62, wherein at least a part of the second dielectric layer extends laterally across the entire width of the gate finger in at least a part of the inactive region of the semiconductor device, and at least a part of the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a part of the active region of the semiconductor device.

84. The semiconductor device according to any one of claims 45 to 51, wherein the auxiliary dielectric layer is in direct contact with the gate finger along substantially the entire length of the gate finger.

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