Semiconductor device including a lateral super junction field effect transistor

Abstract

A semiconductor device comprising: a substrate (1) of a first conductivity type serving as a base of the semiconductor device; a high-voltage junction field-effect transistor (JFET) on the substrate (1), the JFET including a plurality of parallel conductive layers (p; n); a first conductive layer (n1) of a second conductivity type of parallel conductive layers (p; n) extending on the substrate (1, 2); and a plurality of layers for forming a parallel conductive layer having a channel formed by a plurality of doped epitaxial layers (n2 - n6) of the second conductivity type having a plurality of gate layers (p1 - p5) of the first conductivity type on both sides thereof are disposed above the first conductive layer (n1) of the second conductivity type, and the lowermost layer (p1) of the first conductivity type is arranged in the form of continuous dots (5) having different lengths and distances (6) between them. Representative drawing: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a lateral superjunction field effect transistor, a JFET, which can be realized by alternately stacking a plurality of n-type layers and p-type layers on top of each other and connecting them in parallel.

Background Art

[0002] Such devices have already been described in many patent documents, for example, US Patent No. 11,031,480 (US11,031,480 B2), US Patent Application Publication No. 2019 / 01986091 (US2019 / 0198609A1), US Patent Application Publication No. 2017 / 0222043 (US2017 / 0222043A1), and US Patent Application Publication No. 2011 / 0127606 (US2011 / 0127606A1).

[0003] A stack of alternating n-layers and p-layers can form a uniform electric field within the material with almost optimal use of the material in terms of breakdown voltage if the charges match and they completely deplete each other. The stack of alternating n-layers and p-layers needs to be terminated at the bottom, and since the substrate is grounded and has a constant potential along the entire drift region, the electric field needs to be rotated by 90 degrees. This locally increases the electric field, and this increase in the electric field induces an electrical breakdown lower than the breakdown within the stack. Several different attempts have been proposed to shape the electric field.

[0004] US Patent Application Publication No. 2011 / 0127606 proposes an n-buffer layer (160) disposed under the bottom channel, either between the source and the drain or in a partial region (160-1) between the source and the drain. Another proposal is to place a floating n+ region (661) in the substrate under the drain to shield the drain from the high electric field.

[0005] U.S. Patent Application Publication No. 2017 / 0222043 also proposes diffused p-regions (253) and / or diffused n-regions (252) respectively under the source and drain to shape the electric field and reduce the maximum electric field.

[0006] U.S. Patent Application Publication No. 2019 / 01986091 proposes a region (202) whose thickness increases linearly or non-linearly from the source towards the drain. This is also intended to shape the electric field.

[0007] Stacks of n-layers and p-layers have already been shown in several places in the above-cited references. Usually, the bottom channel abruptly ends at the drain, and under the channel, the substrate functions as the bottom gate and also as the substrate that should support the breakdown voltage of the device. Inside the channel, the electric field is completely horizontal, but since the back surface is grounded, it has to rotate vertically under the drain. This means that the field has to rotate 90 degrees under the bottom channel of the substrate. If nothing is done, the electric field profile from the source to the drain forms a U-shape with the highest electric field near the drain. The U-shape means that the electric field is not uniformly distributed and the breakdown voltage is lower than the value that would otherwise be possible.

[0008] The object of the present invention is to mitigate the above drawbacks and obtain a higher breakdown voltage.

Summary of the Invention

[0009] This object is achieved by a device according to the present invention, wherein the lowermost layer of the first conductivity type is arranged in the form of dots having different lengths and distances between deep polycrystalline trenches of the second conductivity type at the bottom of the JFET. Further improvements can be obtained through the devices defined in the dependent claims.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

[0011] Here, the present invention will be described with reference to some non-limiting embodiments of semiconductor devices focused on a JFET portion as shown in the accompanying drawings. FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a second embodiment of a further development of the present invention.

[0012] FIG. 1 is a diagram showing the present invention and starts with a highly doped substrate 1 of a first conductivity type connected to a grounded back contact. On the substrate, there is an epitaxially grown thick low-doped layer 2 of the first conductivity type. The thickness of the epitaxial layer must be large enough to support the breakdown voltage of the device. On the low-doped layer 2 of the first conductivity type, there is an epitaxially grown layer n1 of a second conductivity type. An implantation mask is disposed on the epitaxial layer n1, and ion implantation is performed to form a masked layer p1 of the first conductivity type. By splitting the layer and varying the length and distance of the resulting p-region in the masked layer p1 of the first conductivity type, the effective amount of charge of the first conductivity type decreases towards the drain side D of the structure. This reduces the electric field near the drain, resulting in a more uniform electric field and a higher breakdown voltage being achieved. On top of the structure, a second epitaxial layer n2 of the second conductivity type is now disposed, and a first gate of the first conductivity type is embedded on the channel n2 or grown epitaxially. These two layers are then repeated upwards as shown in some prior publications, for example, the above-cited patent documents.

[0013] Deep trenches are etched from the surface and then filled with highly doped silicon. The figure shows two filled trenches 3 that are of the second conductivity type and connect the channels n2 - n6 of the second conductivity type. The filled trench 4 of the first conductivity type is used to connect the layers p1 - p5 of the first conductivity type. The gates p2 - p5 are connected to ground in three dimensions by forming breaks in the source trench, as shown, for example, in U.S. Patent No. 11,031,480, or by forming filled trench pillars of the first conductivity type, as shown in U.S. Patent Application Publication 2019 / 0198609 and U.S. Patent Application Publication 2017 / 022043.

[0014] The semiconductor device according to the present invention can be combined with an additional insulating region X disposed on a substrate, which includes logic and analog control functions insulated on both sides by deep polycrystalline trenches 4 of the first conductivity type, on the left side of the components shown in the figure. Such semiconductor devices are disclosed, for example, in U.S. Patent No. 11,031,480.

[0015] Preferably, the successive dots 5 of different lengths have a decreasing length in the direction towards the drain side D of the structure, and the distance 6 between the dots 5 increases in the direction towards the drain side D of the structure.

[0016] The overall structure is mirrored around the symmetry line L that enables a high voltage on the drain trench.

[0017] Figure 2 shows a modified device made by ion implantation through a photoresist mask in which the gate layers p2 - p5 create an interruption 7 in the layer p2 - p5 of the first conductivity type. The doping of the interrupted part is the same as that of the adjacent channel regions n2 - n5 of the second conductivity type. The interruption 7 is evenly distributed along the drift region. The interruption 7 in the layer divides the region into several shorter regions 8 of the first conductivity type. The leftmost region of the shorter regions is connected to the ground as described above, and the other regions are floating. In the case of a small drain voltage, the floating regions of the first conductivity type deplete a smaller channel region than the long p - gate grounded along the entire drift region. Thereby, in the case of a low drain voltage, the current passing through the device increases. In the case of a higher voltage, the current flows through the shorter regions and connects them together.

[0018] For this to occur, the length of the interruption 7 must not be too large. For example, the distance 7 between the regions 8 can be about 0.3 μm, and the length of the region 8 can be about 5 μm.

[0019] In the drawings, the device according to the invention is described for the case where the first conductivity type is p - type and the second conductivity type is n - type. However, the device according to the invention can also be realized such that the first conductivity type is n - type and the second conductivity type is p - type.

Claims

1. A substrate (1) of a first conductivity type serving as a base of a semiconductor device; A high-voltage junction field-effect transistor (JFET) on the substrate (1), the JFET including a plurality of parallel conductive layers (p; n), and the JFET being insulated by a deep polycrystalline trench (4) of the first conductivity type on the source side (S) of the JFET; A first conductive layer (n1) of a second conductivity type of the parallel conductive layers (p; n) extending on the substrate (1, 2); and Above the first conductive layer (n1) of the second conductivity type, a plurality of layers are arranged to form the parallel conductive layers having a channel formed by a plurality of doped epitaxial layers (n2 - n6) of the second conductivity type having a plurality of gate layers (p1 - p5) of the first conductivity type on both sides thereof; A semiconductor device, wherein the lowermost layer (p1) of the first conductivity type is arranged in the form of continuous dots (5) having different lengths and distances (6) therebetween.

2. The semiconductor device according to claim 1, wherein the continuous dots (5) of different lengths have lengths decreasing in a direction toward the drain side of the structure, and the distance (6) between the dots (5) increases in a direction toward the drain side of the structure.

3. The semiconductor device according to claim 1 or 2, wherein the conductive layers (p2 - p5) of the first conductivity type on the first conductive layer (p1) of the first conductivity type include continuous regions (8) having different lengths and distances (7) between each region and the deep polycrystalline trench (3) of the second conductivity type.

4. The semiconductor device according to any one of claims 1 to 3, further comprising an insulating region (X) having logic and analog control functions and insulated on both sides by the deep polycrystalline trench (4) of the first conductivity type, the insulating region (X) being arranged on the substrate.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first conductivity type is p-type and the second conductivity type is n-type.

6. The semiconductor device according to any one of claims 1 to 4, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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