Image sensor and method of manufacturing the image sensor

A 3D-IC image sensor with stacked SWIR and VIS/NIR pixels and shared readout circuitry enables simultaneous imaging across multiple spectral regions, addressing the limitations of existing sensors and enhancing applications in compact devices.

JP2025522398APending Publication Date: 2025-07-15AMS SENSORS USA INC
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Patent Information

Application Number
JP2024572701
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2022-06-29
Filing Date
2023-06-27
Publication Date
2025-07-15

AI Technical Summary

Technical Problem

Existing image sensors cannot simultaneously image in the visible, near-infrared, and short-wave infrared spectral regions using the same device footprint and readout circuitry, limiting their scalability and application in compact devices.

Method used

A three-dimensional integrated circuit (3D-IC) is developed with stacked wafers, where a SWIR-sensitive sub-pixel is integrated on top of a VIS-light sensitive sub-pixel, sharing a common readout circuitry, and utilizing backside illumination and metasurfaces to focus incident light, enabling simultaneous or sequential imaging across all spectral regions.

Benefits of technology

The solution allows for simultaneous imaging in VIS, NIR, and SWIR spectral regions using the same device footprint, maintaining excellent dark noise performance and optical alignment, suitable for applications in AR/VR, consumer, health, and security.

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Abstract

The image sensor comprises a three-dimensional integrated circuit having a stack with at least upper, middle and lower tiers. The lower tier (BTR) comprises an array of first photodetectors, represented as first pixels (PDl), the first pixels being sensitive in the visible and / or near-infrared spectral regions. The middle tier (MTR) comprises an array of second photodetectors, represented as second pixels (PD2), the second pixels being sensitive in the short-wave infrared spectral region. The upper tier (TTR) comprises an application-specific integrated circuit, represented as an ASIC, operable to read out the arrays of first and second photodiodes (PD1, PD2).
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Citation Information

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