GaN trench MOSFET and method for manufacturing the same

Abstract

The present invention discloses a GaN trench MOSFET and a method for manufacturing the same. The GaN trench MOSFET according to the present invention is characterized in that there is an n-GaN region containing both Mg and donor impurities at a location reaching the n - -GaN drift layer from the bottom of the trench. The n-GaN region is formed in the Mg-doped p-GaN at the bottom of the trench by using ion implantation several times. Also, the side surfaces that have been ion-implanted are removed by dry etching several times to form an electron channel at the interface between the p-GaN and the oxide film layer.

Description

Technical Field

[0001] (Cross - reference to related fields) This application claims the benefit of priority to U.S. Application No. 63 / 389,363, entitled "GaN TRENCH MOSFET AND FABRICATION METHOD" by Tadao Hashimoto, filed on July 14, 2022. The above application is incorporated by reference in its entirety as if fully set forth below.

[0002] This application is related to the following patent applications.

[0003] PCT Patent Application No. US2005 / 024239 (attorneys docket number 30794.0129 - WO - 01(2005 - 339 - 1)), entitled "METHOD FOR GROWING GROUP III NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA USING AN AUTOCLAVE" by Kenji Fujito, Tadao Hashimoto, and Shuji Nakamura, filed on July 8, 2005,

[0004] Under 35 U.S.C. § 119(c), this U.S. Patent Application No. 11 / 784,339, filed Apr. 6, 2007, by Tadao Hashimoto, Makoto Saito, and Shuji Nakamura, entitled "METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS" (attorney docket number 30794,179-US-U1 (2006-204)), claims the benefit of U.S. Provisional Patent Application No. 60 / 790,310, filed Apr. 7, 2006, by Tadao Hashimoto, Makoto Saito, and Shuji Nakamura, entitled "METHOD FOR GROWING LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS IN SUPERCRITICAL AMMONIA AND LARGE SURFACE AREA GALLIUM NITRIDE CRYSTALS" (attorney docket number 30794,179-US-P1 (2006-204)).

[0005] This U.S. Patent Application No. 60 / 973,602, filed Sep. 19, 2007, by Tadao Hashimoto and Shuji Nakamura, entitled "GALLIUM NITRIDE BULK CRYSTALS AND THEIR GROWTH METHOD" (attorney docket number 30794.244-US-P1 (2007-809-1)).

[0006] U.S. Patent Application No. 11 / 977,661 (attorneys docket number 30794.253-US-U1 (2007-774-2)) entitled "METHOD FOR GROWING GROUP III-NITRIDE CRYSTALS IN A MIXTURE OF SUPERCRITICAL AMMONIA AND NITROGEN, AND GROUP III-NITRIDE CRYSTALS GROWN THEREBY" filed on October 25, 2007 by Tadao Hashimoto,

[0007] U.S. Patent Application No. 12 / 392,960 (attorney docket number SIXPOI-003US) entitled "METHOD FOR PRODUCING GROUP III-NITRIDE WAFERSAND GROUP III-NITRIDE WAFERS" filed on February 25, 2009 by Tadao Hashimoto, Edward Letts, Masanori Ikari,

[0008] U.S. Patent Application No. 12 / 455,760 (attorney docket number SIXPOI-002US) entitled "METHOD FOR PRODUCING IMPROVED CRYSTALLINITY GROUP III-NITRIDE CRYSTALS FROM INITIAL GROUP III-NITRIDE SEED BY AMMONOTHERMAL GROWTH" filed on June 4, 2009 by Edward Letts, Tadao Hashimoto, Masanori Ikari,

[0009] U.S. Patent Application No. 12 / 455,683 (attorney docket number SIXPOI-005US), titled "HIGH-PRESSURE VESSEL FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS USING HIGH-PRESSURE VESSEL AND GROUP III NITRIDE CRYSTAL", filed on June 4, 2009, by Tadao Hashimoto, Edward Letts, and Masanori Ikari

[0010] U.S. Patent Application No. 12 / 455,181 (attorney docket number SIXPOI-001US), titled "METHOD FOR TESTING III-NITRIDE WAFERS AND III-NITRIDE WAFERS WITH TEST DATA", filed on June 12, 2009, by Tadao Hashimoto, Masanori Ikari, and Edward Letts

[0011] U.S. Patent Application No. 12 / 580,849 (attorney docket number SIXPOI-004US), titled "REACTOR DESIGN FOR GROWING GROUP III NITRIDE CRYSTALS AND METHOD OF GROWING GROUP III NITRIDE CRYSTALS", filed on October 16, 2009, by Tadao Hashimoto, Masanori Ikari, and Edward Letts

[0012] U.S. Patent Application No. 13 / 781,509 (attorney docket number SIXPOI-012US), titled "COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE", filed on February 28, 2013, by Tadao Hashimoto

[0013] U.S. Patent Application No. 13 / 781,543 (attorney docket number SIXPOI-013US) entitled "A BISMUTH-DOPED SEMI-INSULATING GROUP III NITRIDE WAFER" by Tadao Hashimoto, Edward Letts, and Sierra Hoff, filed on February 28, 2013,

[0014] U.S. Patent Application No. 13 / 833,443 (attorney docket number SIXPOI-014US1) entitled "METHOD OF GROWING GROUP III NITRIDE CRYSTALS" by Tadao Hashimoto, Edward Letts, and Sierra Hoff, filed on March 15, 2013,

[0015] U.S. Patent Application No. 13 / 834,015 (attorney docket number SIXPOI-014US2) entitled "METHOD OF GROWING GROUP III NITRIDE CRYSTALS" by Tadao Hashimoto, Edward Letts, and Sierra Hoff, filed on March 15, 2013,

[0016] U.S. Patent Application No. 13 / 834,871 (attorney docket number SIXPOI-015US1) entitled "GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD" by Tadao Hashimoto, Edward Letts, and Sierra Hoff, filed on March 15, 2013,

[0017] U.S. Patent Application No. 13 / 835,636, entitled "GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD" by Tadao Hashimoto, Edward Letts, Sierra Hoff, filed on March 15, 2013 (attorney docket number SIXPOI-015US2),

[0018] U.S. Patent Application No. 13 / 798,530, entitled "GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD" by Tadao Hashimoto, filed on March 13, 2013 (attorney docket number SIXPOI-016US),

[0019] U.S. Patent Application No. 14 / 329,730, entitled "ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD" by Tadao Hashimoto, filed on July 23, 2014 (attorney docket number SIXPOI-017US),

[0020] and are related thereto. All of the above applications are incorporated by reference in their entirety as if set forth in full below. [Background Art]

[0021] [Field of the Invention] The present invention relates to semiconductor electronic devices mainly used in high-power and / or high-frequency electric and electronic circuits. In particular, the present invention relates to transistors using group III nitride semiconductors. [Description of the Related Art]

[0022] (Note: This patent application refers to several publications and patents, as indicated using numbers in parentheses, e.g., [x]. A list of these publications and patents can be found in the section entitled (References).)

[0023] Gallium nitride (GaN) and its related group III nitride mixed crystals are key semiconductor materials for various electronic devices such as power switching transistors. Despite the fact that the theoretical maximum capacity of GaN, estimated by Baliga's figure of merit (BFOM), exceeds five times that of silicon carbide (SiC), GaN-based power switching devices have not been able to achieve their inherent performance due to the difficulty of device fabrication and the lack of inexpensive, low-defect GaN substrates.

[0024] Currently, the majority of GaN devices are fabricated using group III nitride thin films grown heteroepitaxially on hetero-substrates such as silicon (Si), SiC, and sapphire. Regarding GaN power devices, a lateral field-effect transistor (FET) fabricated on Si has been commercialized. However, in a lateral device, the channel through which current flows is thin, so there is a limit to the achievable power. Also, due to the poor quality of GaN grown on Si, it is impossible to realize high-voltage devices with a breakdown voltage exceeding 1500V.

[0025] A vertical GaN FET fabricated on a GaN substrate is ideal for applications requiring high output and high reliability. Homoepitaxial growth on a GaN substrate keeps the dislocation density low, showing low leakage current, high linearity, and high reliability. However, despite many development efforts, vertical GaN metal-oxide-semiconductor FETs (MOSFETs) have not yet reached their inherent performance. This is because it is difficult to fabricate the three-dimensional p-GaN structure required to prevent electric field concentration within the device.

[0026] Here, the specific problems of these devices and characteristics will be described in detail.

Summary of the Invention

[0027] The present invention discloses a GaN trench MOSFET and a method for manufacturing the same. The GaN trench MOSFET according to the present invention has an n-GaN region containing both Mg and donor impurities in a portion from the bottom of the trench to the n - -GaN drift layer. By using ion implantation, an n-type region is formed in the Mg-doped p-GaN region and at the bottom of the trench of the MOSFET. Further, by removing a part of the side surface of the trench implanted with ions by dry etching, an electron channel necessary for manufacturing the GaN trench MOSFET can be formed between the Mg-doped p-GaN and the oxide film layer.

Brief Description of the Drawings

[0028] Here, reference is made to the drawings in which like reference numerals represent corresponding parts throughout.

[0029]

Figure 1

[0030] In this drawing, each number indicates the following. 101 n-type substrate 102 n - -type drift layer 103 p-type region 104 trench 104c corner at the bottom of the trench 106 n-type source 107 electron channel 108 gate insulating film 109 gate contact 110 body contact 111 source contact 112 drain contact 113 deep p-type region

[0031] Numbers 105 and 205 are not used to make it easier to compare the differences between a conventional trench MOSFET and the GaN trench MOSFET according to the present invention. Figures 3 and 4 showing the GaN trench MOSFET according to the present invention show the structure corresponding to "5".

[0032]

Figure 2

[0033] In this drawing, each number indicates the following. 201 n-GaN substrate 202 n - -GaN drift layer 203 p-GaN region 204 Trench 204c Corner at the bottom of the trench 206 n-GaN source 207 Electron channel 208 Gate insulating film 209 Gate contact 210 Body contact 211 Source contact 212 Drain contact

[0034]

Figure 3

[0035] In this drawing, each number indicates the following. 1 GaN substrate 2 n - -GaN drift layer 3 Mg-doped GaN layer 4 Trench 4c Corner at the bottom of the trench 5 n-GaN region 6 n-GaN source 7 Electron channel on the p-GaN facet 8 Gate insulating film 9 Gate contact 10 Body contact 11 Source contact 12 Drain contact

[0036]

Figure 4

Embodiments for Carrying Out the Invention

[0037] (Detailed Description of the Invention) (Problems to be Solved by the Invention) 1. Consideration of Existing Trench MOSFETs and Their Problems A. Existing MOSFETs Manufactured from Semiconductors Other than GaN Such as Si and SiC Various trench MOSFETs have been manufactured using Si and SiC semiconductors. Reference 1 is a review of trench MOSFETs, and FIG. 1 shows an example of a conventional trench MOSFET. A low-doped (i.e., n - -type) drift layer 102 is grown on an n-type substrate 101. During operation, a high voltage is applied to this drift layer. Due to this high voltage, the carrier density in the drift layer is 10 16 cm -3is set to a value equal to or lower than the threshold, maximizing the breakdown electric field of this layer. On top of the drift layer, a p-type region 103 and a deep p-type region 113 are formed by ion-implanting an electron acceptor several times. In the case of Si or SiC, a p-type region can be easily formed by ion-implanting an acceptor into the drift layer 102. Thereafter, an n-type source 106 is formed by ion-implanting a donor onto the surface. The trench 104 is formed by etching a p-type material, and then a gate insulating film (usually silicon dioxide) and a gate metal are deposited. The p-body contact 110, the source contact 111, and the drain contact 112 are formed by ordinary metal deposition techniques for semiconductors. The p-body contact 110 and the source contact 111 are short-circuited to fix the potentials of the p-type region and the deep p-type region to the potential of the source.

[0038] One of the key technologies for achieving a high breakdown voltage in a conventional MOSFET is a deep p-type region. In the absence of a deep p-type region, the electric field concentrates at the corners of the bottom of the trench, causing physical breakdown at the corners 104c of the bottom of the trench and damaging the trench in a non-reparable form. To prevent this problem, the deep p-type region extends to the substrate 101. The breakdown that occurs at the interface between the deep p-type region and the drift layer is not a physical breakdown but an electron avalanche breakdown, so the dielectric breakdown does not cause non-reparable damage. That is, a device recovered from an electron avalanche breakdown can be used again. Conventional MOSFET using B.GaN semiconductor

[0039] GaN is one of the wide-bandgap semiconductors, and its material properties exceed those of SiC. Therefore, many studies have been conducted to develop GaN trench MOSFETs. However, since it is difficult to obtain p-GaN by ion-implanting an acceptor (usually Mg), the deep p-type region described above does not exist in the reported devices, as shown in References 2 and 3. Fig. 2 shows an example of a conventional GaN trench MOSFET. A GaN trench MOSFET usually has an n on a GaN substrate -- The -GaN drift layer 202 is grown, and a GaN layer doped with an acceptor is grown on the drift layer 202, followed by a p-type activation heat treatment (usually about 800 °C) for fabrication. Then, the trench 204 is formed by dry etching. As shown in Fig. 2, the etched trench bottom reaches the n - -GaN drift layer 202. In Fig. 2, it can be seen that the gate insulating film 208 and the gate contact 209 are located at a position lower than the interface between the p-GaN region and the n - -GaN drift layer 202. Since there is no deep p-type region in the GaN trench MOSFET, the breakdown of the device physically occurs at the corner 204c of the trench bottom, resulting in an irreparable breakdown of the device.

[0040] As an attempt to fabricate a deep p-type region, research has been conducted on ion-implanting an acceptor (such as Mg) into GaN to make it p-type. It has been reported that p-GaN can be obtained by heat treatment at high pressure (about 1 GPa) and high temperature (1000 °C or higher) after Mg ion implantation, but the high-temperature and high-pressure heat treatment is not suitable for mass production.

[0041] Another possible method for fabricating a deep p-type region is to - etch the n-GaN drift layer and selectively grow p-GaN. However, silicon impurities usually accumulate at the regrowth interface, resulting in a problem of high leakage current under high-voltage bias. (Means for Solving the Problem) 2. The Present Invention

[0042] To realize a practical GaN trench MOSFET having a deep p-type region, the present invention provides a new structure and fabrication procedure described below. Fig. 3 is an example of the GaN trench MOSFET of the present invention. The device has an n - -GaN drift layer 2 grown on a GaN substrate 1. Similar to the conventional MOSFET, the electron density of the n - -GaN is 10 16 cm -3 or less, preferably 2 x 10 16 cm-3 More preferably, it is 8x10 15 cm -3 or less. The p-type Mg-doped GaN layer 3 is on the n - -GaN drift layer, but is separated by the n-GaN region 5 at the lower part of the trench 4. One of the important procedures in the present invention is the formation of the n-GaN region 5. The n-GaN region 5 is formed by ion-implanting donors into a part of the Mg-doped GaN layer 3. The carrier concentration of the n-GaN region 5 is n - close to the carrier concentration of the n - -GaN drift layer, and the carrier concentration difference is within + / - 50% of the carrier concentration of the n 16 cm -3 or less at the pedestal.

[0043] As shown in FIG. 3, in the final device, the n-GaN region 5 is almost under the trench and extends vertically up to the n - -GaN drift layer 2. The n-GaN region 5 also extends laterally from the trench side surface, and by contacting the end of the n-GaN region with the electron channel 7 on the p-GaN facet, electrons passing through the electron channel 7 on the p-GaN facet under the gate insulating film are collected. In this structure, the interface between the n - -GaN drift layer 2 and the p-GaN formed from the Mg-doped GaN layer 3 is closer to the substrate 1 than the interface with the end of the n-GaN region 5 and the electron channel on the p-GaN facet. Therefore, electric field concentration does not occur at the corner 4c at the bottom of the trench. Dielectric breakdown occurs at the interface between the p-GaN formed from the Mg-doped GaN layer 3 and the n - -GaN drift layer, and it occurs not as a physical breakdown but as an electron avalanche breakdown.

[0044] To form the electron channel 7 on the p-GaN facet formed from the Mg-doped GaN layer 3, the p-GaN facet is formed by dry etching. The p-GaN facet is preferably a crystallographic plane orientation such as the (101), (201), or (102) plane. The (101), (201), and (102) planes form angles of approximately 62°, 75°, and 43° respectively from the c-plane. Since these crystallographic planes are stable planes, it is difficult to form surface levels during the deposition of the insulating film layer. The manufacturing procedure will be described in detail later.

[0045] Figure 4 shows an example of the manufacturing procedure of the GaN trench MOSFET of the present invention. The manufacturing starts with growing an n - -GaN drift layer 2 on the n-GaN substrate 1 (Figure 4A). Any method of manufacturing the n-GaN substrate can be used, but it is preferably to use a GaN substrate with a low dislocation density. The GaN substrate manufactured by the ammonothermal method usually has a dislocation density of 2x10 5 cm -2 or less, which is about one order of magnitude lower than the dislocation density of the GaN substrate manufactured by the vapor phase growth method. It is preferable to use a substrate with a dislocation density of less than 5x10 5 cm -2 The n - -GaN drift layer is preferably grown by the metalorganic chemical vapor deposition (MOCVD) method. This is because the MOCVD method can grow a GaN layer with a low impurity concentration at a practical speed (about 5 microns / hour).

[0046] After the growth of the drift layer, an Mg-doped GaN layer 3 is grown. The growth of the Mg-doped GaN layer 3 is preferably carried out without interruption immediately after the growth of the n - -GaN drift layer 2 to prevent the accumulation of silicon impurities at the interface between the n - -GaN drift layer 2 and the Mg-doped GaN layer 3 (Figure 4B). After growth, the wafer is heat-treated at about 800°C to activate the Mg impurities. By the activation heat treatment, the Mg-doped GaN layer 3 becomes p-type GaN.

[0047] After growth, the wafer is removed from the growth apparatus and etched using an appropriate mask to form trench 4. The etching mask can use a photoresist, a metal layer, or a dielectric layer. To fabricate a trench with a nearly vertical side, it is preferable to use dry etching. Trench 4 has a trench bottom 4a and a trench side 4b formed therein (FIG. 4C). The etching should stop before reaching the interface of p-GaN formed from the n - -GaN drift layer 2 and the Mn-doped GaN layer 3. Further, by ion implantation performed on the p-GaN of the bottom surface 4a of trench 4 after trench formation, the bottom 4a of the trench is made n - -GaN so that most of this region can be converted to n-GaN at a location sufficiently close to the interface of p-GaN formed from the -GaN drift layer 2 and the Mn-doped GaN layer 3. Practically, it is desirable that the thickness of this region from the bottom of the trench to the drift layer is less than 1 micron, preferably less than 0.5 micron, and more preferably about 0.2 micron or less.

[0048] Thereafter, donor impurities are ion-implanted into the wafer. Any donor impurities such as Si, O, and Ge can be used, but since Si is the most common donor for GaN, it is preferable to use Si. The doping concentration is adjusted so that the region below the bottom of the trench becomes n-GaN and its electron density is n - -close to the electron density of the GaN drift layer, within a difference of + / -50% of the electron density of the n - -GaN drift layer. As described above, the electron concentration is 10 16 cm -3 or less, preferably less than 2x10 16 cm -3 and more preferably less than 8x10 15 cm -3 . As a result, the region below the bottom of the trench is converted to n-GaN (n-GaN region 5). And all regions near the exposed surface (trench side and n-GaN source region) become n-type as shown in FIG. 4D.

[0049] To increase the electron concentration and form the n-GaN source 6, it is preferable to protect the trench with the mask 6a and perform further donor ion implantation into the n-GaN source region 6 (Fig. 4E). After the ion implantation, the mask 6a is removed.

[0050] To remove the n-GaN region formed on the surface of the trench sidewall and expose the p-GaN, as shown in Fig. 4F, the n-GaN region is removed by dry etching. To expose the p-GaN facet while partially retaining the n-GaN region under the trench bottom, the angle of the facet is precisely controlled. Details of the technique for controlling the angle are well known and are described in Reference 6 included as a whole in this specification. To control the facet angle, it is desirable to perform dry etching using a photoresist mask. The surface on the p-GaN facet becomes the electron channel 7.

[0051] When the electron channel 7 is exposed, the gate insulating film 8 is deposited as shown in Fig. 4G. The pattern of the gate insulating film can be formed by a conventional semiconductor manufacturing process. As is well known in the prior art, an appropriate gate insulating film material is selected to minimize the interface energy levels. It is preferable to use aluminum nitride, aluminum oxide, silicon nitride, or silicon oxide, but a novel insulating material may be used to reduce and minimize the surface levels.

[0052] Using a conventional semiconductor process, the gate contact 9 is deposited on the gate insulating film 8 (Fig. 4H), the p-type body contact 10 is formed (Fig. 4I), and the source contact 11 (Fig. 4J) and the drain contact 12 (Fig. 4K) are formed. (Embodiments for Carrying Out the Invention) Example 1

[0053] The bulk crystal of GaN is grown by the near-equilibrium ammonothermal method. The bulk crystal of GaN is grown on the c-plane of the GaN seed crystal. The bulk GaN is sliced, ground, lapped, polished, and chemically mechanically polished to a dislocation density of 2x10 5 cm -3, carrier concentration 2x10 18 cm -3 , a c-plane 2” GaN substrate with an off-angle of 0.04° in the m-axis direction and 0.00° in the a-axis direction is fabricated.

[0054] A 10-micron-thick n - -GaN drift layer and a 0.9-micron-thick Mg-doped GaN layer are grown by metalorganic chemical vapor deposition (MOCVD) using trimethylgallium and ammonia. To lightly dope the n - -GaN drift layer with Si, SiH4 gas diluted with hydrogen is introduced during the growth of the drift layer. The electron density of the n - -GaN drift layer is 1x10 16 cm -3 . To grow the Mg-doped GaN layer, biscyclopentadienylmagnesium (CpMg) carried by hydrogen gas is introduced into the MOCVD reactor. After MOCVD growth, the wafer is taken out of the MOCVD reactor and heat-treated at 800 °C in a nitrogen atmosphere to activate the Mg dopant. By the activation heat treatment, the Mg-doped GaN layer is converted into a p-GaN layer. The Mg concentration of the p-GaN layer is 2x10 18 cm -3 .

[0055] The wafer undergoes a photolithography process and dry etching is performed to form trenches on the wafer. Using inductively coupled plasma (ICP) etching with Cl2 gas, a commonly known method, dry etching is carried out using a photoresist as a mask to obtain trenches with vertical sides. When looking at the wafer from above, the trenches are hexagonal and the distance between their opposing vertices is about 1 micron. The sides of the trenches are aligned with the m-plane of GaN. The depth of the trenches is about 0.7 micron. The dry etching ends before the n - -GaN drift layer 2 is exposed, leaving a p-GaN region of about 0.2 micron sandwiched at the interface between the trench bottom and the n - -GaN drift layer and the p-GaN layer.

[0056] Perform Si ion implantation on the wafer without masking, and convert the p-GaN region sandwiched at the interface between the trench bottom and the n - -GaN drift layer and the p-GaN layer. After ion implantation, the wafer is heat-treated at 800 °C in nitrogen gas to activate Si. As a result, the electron density in this region becomes about 1x10 16 cm -3 , which matches the electron density of the n - -GaN drift layer. It is preferable to control the electron density in this region within + / - 50% of the electron density of the n - -GaN drift layer.

[0057] After covering the trench bottom and the trench sidewall with a dielectric mask to increase the electron density of the source region, additional Si ion implantation is performed. The electron density of the n-GaN source region is about 5x10 18 cm -3 . After ion implantation, the dielectric mask is removed by wet etching or the like.

[0058] Inductively coupled plasma (ICP) etching is performed using a photoresist mask to expose the p-GaN facet that forms the electron channel. In this case, the (101) plane of p-GaN is exposed using different types and thicknesses of photoresist. The facet angle is about 62° from the (002) plane of the reference plane. The detailed method for adjusting the facet angle is described in Reference 6. In this way, a part of the n-GaN on the sidewall of the trench is removed and the p-GaN facet is exposed. Then, an alumina layer and an SiO2 layer are deposited as the gate dielectric film, and Ti / Al is deposited as the gate contact. The gate contact is patterned using a conventional semiconductor process.

[0059] Similarly, using a conventional semiconductor process, n-GaN is dry-etched and Ni / Au is pattern-deposited to form a body contact on the p-GaN layer. Finally, a source contact of Ti / Al and a drain contact of Ti / Al are formed to complete the GaN MOSFET structure.

[0060] The completed GaN MOSFET structure has a deep p-type region. The breakdown voltage exceeds 1000V, and since the bottom of the trench is farther from the substrate than the interface of the p-GaN and n - -GaN drift layer, breakdown occurs at locations other than the trench. In the device according to the present invention, the dielectric breakdown that occurs at the interface of the p-GaN and n - -GaN drift layer is electron avalanche breakdown and is not a mode of physical breakdown, so the device does not break down in a non-reproducible (physical) form. By preventing the physical breakdown at the bottom of the trench that occurs in the conventional device shown in Figure 2, the device according to the present invention is more reliable. Also, the device structure according to the present invention prevents electric field concentration at the corners of the bottom of the trench and can achieve a higher breakdown voltage than conventional devices. (Possible modifications)

[0061] In a preferred embodiment, the use of a GaN substrate fabricated by the ammonothermal method is described, but GaN substrates fabricated by other methods such as the HVPE method may also be used.

[0062] In a preferred embodiment, the use of MOCVD for the growth of the layer structure is described, but other methods such as the HVPE method or molecular beam epitaxy may also be used.

[0063] In a preferred embodiment, the use of ICP etching for the formation of the trench is described, but other dry etching methods such as reactive ion etching (RIE) may also be used.

[0064] The preferred embodiments of the present invention described above are presented for display and explanation purposes. It is not presented for the purpose of prescribing the invention in minute detail or limiting it only to the disclosed forms. Many modifications and changes are possible as long as the key points taught by the above forms are grasped. The key points of the present invention are not limited by this detailed description but are defined by the appended claims. (References)

[0065] The following references are incorporated herein by reference.

[0066] [1] R.K. Williams, et al., ”The Trench Power MOSFET: Part I - History, Technology, and Prospects,” IEEE Transactions, on Electron Devices Vol. 64 (2017) 674.

[0067] [2] T. Oka, et al., ”1.8mΩcm 2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation,” Applied Physics Express 8 (2015) 054101.

[0068] [3] R. Li, et al., ”600V / 1.7mΩcm 2 Normally-Off GaN Vertical Trench Metal-Oxide-Semiconductor Field-Effect Transistor,” IEEE Electron Devices 37 (2016) 1466.

[0069] [4] H. Sakurai, et al., ”Highly effective activation of Mg-implanted p-type GaN by ultra-high-pressure annealing,” Appl. Phys. Lett. 115 (2019) 142104.

[0070] [5] A. Uedono, et al., ”Effects of ultra-high-pressure annealing on characteristics of vacancies in Mg-implanted GaN studies using monoenergitic positron beam,” Sci. Rep. 10 (2020) 17349。https: / / doi.org / 10.1038 / s41598-020-74362-9。

[0071] [6] H. Hahn, et al., ”Influence of mask material and process parameters on etch angle in a chlorine-based GaN dry etch,” J. Vac. Sci. Technol. A30 (2012) 051302。

[0072] These references are incorporated by reference in their entirety as if fully set forth herein, particularly the method of fabricating a GaN trench MOSFET, the activation of Mg-ion implanted p-GaN, and the method of fabricating sloped sidewalls by etching through the selection of mask materials and process conditions are incorporated in the specification.

Claims

1. fabricated on an n-type GaN substrate, a) An n-type GaN drift layer (2) in contact with the interface of the n-type GaN substrate (1); － and b) a p-type GaN layer (3) doped with Mg and in contact with the interface of the drift layer, c) a trench (4) having an inclined surface (7) formed in the p-type GaN layer doped with Mg, d) an n-type GaN region (5) below the bottom surface of the trench, and e) an n-type GaN source (6) outside the region of the trench (4) above the GaN layer (3) doped with Mg, characterized in that the n-type GaN region (5) contains both Mg and donor impurities, a GaN trench MOSFET (Figure 3).

2. The GaN trench MOSFET according to claim 1, wherein the n-type GaN region extends from the bottom of the trench to the drift layer.

3. The GaN trench MOSFET according to claim 1 or 2, characterized in that the n-type GaN region extends laterally from below the trench and from the bottom surface of the trench, such that the interface between the drift layer and the p-type GaN layer doped with Mg is closer to the substrate than the interface between the n-type GaN region and the p-type GaN layer doped with Mg.

4. The electron density of the n-type GaN region is such that the difference from the electron density of the n- － type GaN drift layer is within ±50%, and the GaN trench MOSFET according to any one of claims 1 to 3, characterized in that.

5. The GaN trench MOSFET according to any one of claims 1 to 4, characterized in that the inclined surface formed in the p-type GaN layer doped with Mg is a surface selected from the crystal planes of (101), (201), or (102).

6. The GaN trench MOSFET according to claim 5, characterized in that the trench has a plurality of inclined surfaces in the p-type GaN layer, and each of the surfaces is a surface selected from the (101), (201), or (102) planes.

7. The GaN trench MOSFET according to any one of claims 1 to 6, characterized in that the trench is hexagonal.

8. In a method for manufacturing a GaN trench MOSFET (a) When the MOSFET is placed vertically, n-type GaN drift layer is formed on the n-type GaN substrate and under the p-type GaN doped with Mg, and trenches are formed in the p-type GaN doped with Mg having such a structure. － Step of forming trenches in the p-type GaN doped with Mg having a structure with an n-type GaN drift layer. (b) a step of converting the region between the bottom of the trench of p-type GaN doped with Mg and the drift layer into an n-type conductivity type by ion implantation of donor ions, (c) a step of exposing the inclined surface of the p-type GaN doped with Mg by etching a part of the side surface of the trench, and (d) a step of forming a source region of n-type GaN outside the trench region characterized by having a method for manufacturing a GaN trench MOSFET.

9. The method for manufacturing a GaN trench MOSFET according to claim 8, characterized in that Si is used in the donor ion implantation.

10. The method for manufacturing a GaN trench MOSFET according to claim 8 or 9, characterized in that the angle between the side surface of the trench and the n-type GaN substrate is steeper than the angle between the inclined surface of the p-type GaN doped with Mg and the n-type GaN substrate.

11. The method for manufacturing a GaN trench MOSFET according to any one of claims 8 to 10, characterized in that the inclined surface of the p-type GaN doped with Mg is a surface selected from the (101), (201), or (102) plane.

12. The said n － The electron density of the drift layer of the n-type GaN is less than 2x10 １６ cm －３ , and the electron density of the region between the trench bottom of the p-type GaN layer doped with the said Mg and the drift layer is less than 2x10 １６ cm －３ The method for manufacturing a GaN trench MOSFET according to any one of claims 8 to 11, characterized in that

13. The dislocation density of the n-type GaN substrate is 2x10 ５ cm －２ The method for manufacturing a GaN trench MOSFET according to any one of claims 8 to 12, characterized in that it is less than.

14. The method for manufacturing a GaN trench MOSFET according to any one of claims 8 to 13, characterized in that the trench is hexagonal.

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