Through-Silicon Via Macro with High-Density Layout for Placement in an Integrated Circuit Floorplan

Abstract

A system and method for efficiently designing a silicon through-silicon via (TSV) macroblock are described. In various embodiments, a processor circuit executes instructions of a placement and routing tool that provides automatic placement of macroblocks and standard cells onto an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes various standard cells and macroblocks. The processor places two functional macros in a floorplan such that there is a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside the TSV macro. The processor prevents placement of boundary cells adjacent to at least one side of the TSV macro, even though there is free space because there are no standard cells or macros around at least one side thereof.

Description

Background Art

[0001] (Description of Related Art) The floorplan of a semiconductor die (or die) is a graphical representation of the die's partitioning. The partitioning uses shapes such as rectangles to represent the placement of multiple components, such as one or more processing units, one or more blocks of memory, and one or more interface units. The components are often referred to as macroblocks or macros. The shapes used in the floorplan have the dimensions of the macroblocks they represent. To place all components on the same die, there are limitations on the dimensions of the shapes. The limitations are set by various factors such as the placement of standard cells from a standard library such as boundary cells. Boundary cells do not contain active devices such as transistors but include a plurality of base layers and one or more metal layers not connected to the power supply. Boundary cells improve semiconductor manufacturability and increase yield. Other examples of factors that limit floorplan dimensions are the area for bonding pads, input / output (I / O) line drivers for signals corresponding to the bonding pads, timing constraints of macroblocks, predefined rectangles for at least one processing unit and other intellectual property blocks (IP blocks), and reserved areas. Some examples of reserved areas are clock signals across the entire die and areas for routing and buffering data and control signals.

[0002] A further example of a reservation area is an area used for a combination of through silicon vias (TSVs) and their corresponding keep-out zones. TSVs are used as interconnections between dies of a three-dimensional integrated circuit (3D IC) in which two or more layers of active electronic components are integrated into a single circuit in both the vertical and horizontal directions. Each of a first die, such as a host die or a base die, and at least one other die is used in 3D packaging for a computing system. This type of packaging is called a System in Package (SiP). Typically, the dimensions of the TSVs and the corresponding keep-out zones are significantly smaller than the minimum TSV pitch. Thus, the resulting TSV macroblocks consume a significant amount of empty space on the die and the corresponding floorplan.

[0003] A channel containing a column of TSVs for carrying power signals exists between two macroblocks, such as two memory macroblocks. The first macroblock has boundary cells disposed on its side within the channel. The TSV macroblock is disposed within the channel used for carrying a power supply voltage or a ground reference voltage. This TSV macroblock has boundary cells disposed on each of its four sides. The second macroblock also has boundary cells disposed on its side within the channel. Thus, along the channel dimension, a minimum width sufficient to allow the placement of two boundary cells for the macroblocks, the placement of two boundary cells for the TSV macroblock, and the placement of the TSV macroblock is required. If the minimum width does not exist in the floorplan, the required components will not fit on the same die. Thus, significant redesign is required along with possible movement or shifting of the macroblocks within the floorplan. Such redesign consumes a significant amount of design time and delays the product release.

[0004] In view of the above, there is a need for an efficient method and system for efficiently designing silicon through via macro blocks.

Brief Description of the Drawings

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Modes for Carrying Out the Invention

[0006] Although the present invention is subject to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the present invention to the particular forms disclosed, but on the contrary, the present invention is to cover modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims.

[0007] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail in order to avoid obscuring the present invention. Further, for the sake of brevity and clarity of the description, it should be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements.

[0008] A system and method for efficiently designing a silicon through-via macro block are contemplated. As disclosed herein, a computing device used by a user includes hardware such as a processor circuit to execute instructions (e.g., a placement and routing tool or other tool) that provide for the automatic placement of macro blocks and standard cells on a die. The instructions use a copy of the integrated circuit netlist and a standard cell library that includes various standard cells and macro blocks. As used herein, the term "automatically generate" or "automatically generating" refers to the ability to perform a generation or generation step without user intervention. Similarly, as used herein, the term "automatically place" or "automatically placing" refers to the ability to perform a placement or placement step without user intervention. For example, when a processor of a computing device executes the instructions of a tool, the processor automatically selects positions for the placement of components and the routing of signals between the components. In other words, based on access to the netlist of the integrated circuit being designed and the standard cell library, when executing the instructions of a placement and routing tool, the processor generates data indicating the placement of components in the floorplan of the die of the integrated circuit being designed. Similarly, when a processor of a computing device executes the instructions of a placement and routing tool, the processor prevents the automatic placement of certain components, such as boundary cells, in the floorplan of the die that can be automatically placed. In other words, the processor generates data indicating positions within the floorplan of the die where these certain components are not allowed. This data prevents these certain components from being placed in the area of the die.

[0009] When a processor of a computing device executes instructions of a placement routing tool, the processor places (or automatically places) two functional macroblocks, such as two memory macroblocks, in the floorplan of an integrated circuit. In other words, the processor generates data indicating the placement of two memory macroblocks in the floorplan of a die of the integrated circuit being designed. The two functional macroblocks have a channel between them. The processor places a column of silicon through via (TSV) macroblocks in the channel to carry a power supply voltage or a ground reference voltage to one or more of the two functional macroblocks (or macros). Typically, the TSV macroblocks are placed at a specific distance from the two macros based on a predetermined power grid design for the floorplan. When generating a column of TSV macroblocks in the channel, the processor places a first type of TSV macroblock. In various embodiments, the first type of TSV macroblock includes at least one boundary cell inside the TSV macroblock. In an embodiment, the first type of TSV macroblock includes a first boundary cell on a first side and a second boundary cell on a second side different from the first side, and each of the first side and the second side is placed within the TSV macroblock along a predetermined dimension of the floorplan. An example of the predetermined dimension is the horizontal dimension or x-dimension of the floorplan.

[0010] Also, the processor places at least one boundary cell adjacent to the first functional macro among the two functional macros. For example, the processor places the boundary cell on the side of the first functional macro within a channel along a predetermined dimension of the floor plan, such as the x-th dimension of the floor plan. Usually, the boundary cells are placed around one or more sides of the macro to fill the empty space on the die between a pair of macros, between a pair of macros and standard cells, or between the macro and the edge of the die. The boundary cells improve the manufacturability of the semiconductor and increase the yield. However, the processor prevents the placement of boundary cells in the floor plan adjacent to at least one side of the first type of TSV macro. In other words, the processor generates data indicating positions in the floor plan where boundary cells adjacent to at least one side of the first type of TSV macro are not allowed. In an embodiment, the data includes the identification of the first type of TSV macro and one side. In another embodiment, the data includes a boundary including an area on one side of the first type of TSV macro. When the processor reaches the step of automatically placing boundary cells around the macro by executing the instructions of the placement wiring tool, the processor uses the data indicating the prevention of the placement of boundary cells to prevent the placement of boundary cells adjacent to at least one side of the first type of TSV macro. In some embodiments, the processor prevents the placement of boundary cells in the floor plan adjacent to the first side and the second side of the first type of TSV macro. In such embodiments, the first type of TSV macro includes boundary cells on the first side and the second side inside thereof. The use of the first type of TSV macro reduces the required distance between the two functional macros.

[0011] In an embodiment, the standard cell library includes a second type of TSV macro having the same dimensions as the first type of TSV macro. However, there are no boundary cells in the second type of TSV macro. Thus, when the second type of TSV is selected and placed, the processor places boundary cells around the sides of the second type of TSV macro. In some embodiments, the processor selects and places the first type of TSV macro between two functional macros when the distance between the two functional macros is less than a threshold distance. The processor selects and places the second type of TSV macro between two functional macros when the distance between the two functional macros is greater than or equal to the threshold distance.

[0012] Referring to FIG. 1, a schematic diagram of a portion 100 of a floorplan of an integrated circuit is shown. The portion 100 of the integrated circuit floorplan (or floorplan) includes functional macros 110, 112, 130, 132, and through-silicon via (TSV) macros 120, 140. The functional macros 110, 112, 130, 132 and the TSV macro 120 have various types of boundary cells 150, 160, 170 disposed adjacent thereto. However, in an embodiment, the TSV macro 140 includes a boundary cell 150 within the macro and does not have a boundary cell 150 disposed adjacent thereto. The TSV macro 140 has boundary cells 160 disposed adjacent above and below in the y-dimension in addition to boundary cells 170 disposed adjacent at the corners of the TSV macro 140. However, there are no boundary cells 150 disposed adjacent on the left and right sides in the x-dimension of the TSV macro 140. The TSV 140 includes a TSV block 144 including a through-silicon via, a corresponding keep-out region, a guard ring, and a fill layer, in addition to the boundary cell 150 within the macro. The portion 100 of the floorplan relies on standard cells and individual Boolean gate cells. The standard cell library includes multiple versions of individual Boolean gate cells having various available transistor sizes. The cells within the standard cell library use active devices. Examples of active devices are one or more of n-type and p-type planar transistors and n-type and p-type non-planar transistors.

[0013] As used herein, a "standard cell" is the smallest building block of a standard cell library on top of a cell of an individual Boolean gate. Standard cells and individual Boolean gate cells are used to provide the functionality of a larger design block by having copies of standard cells and Boolean gates instantiated within the larger design block, followed by routing steps to provide interconnections. In addition to indicating the Boolean and other functions of the components used within a standard cell, a standard cell also includes mask layout data. The mask layout data for a particular standard cell includes one or more mask layers associated with one or more layers of the particular standard cell. One or more layers of a particular standard cell include a base layer and a plurality of metal layers used for signal interconnection. The mask layout data includes mask patterns used in photolithography performed during semiconductor fabrication of an integrated circuit. The pattern indicates the placement location of components within a particular standard cell relative to a reference point such as a corner of the particular standard cell. Examples of components are active devices and passive elements (e.g., resistors, capacitors, inductors) arranged within the standard cell. Also included in the mask layout data are parasitic information of components such as resistance of wiring and nodes, coupling capacitance of wiring and transistor terminals, and load capacitance.

[0014] As described above, standard cells and individual Boolean gate cells are used to provide the functionality of a larger design block by having copies of standard cells and Boolean gates instantiated within the larger design block, followed by routing steps to provide interconnections. Copies of certain larger design blocks that can be instantiated multiple times in a floorplan are referred to as "macroblocks" or simply "macros". Most macros contain active devices to provide functionality. When used herein, these types of macros are also referred to as "functional macros". However, TSV macros 120, 140 are examples of macros that do not contain active devices. In some embodiments, each of the functional macros 110, 112, 130, 132 is an instantiation of the same functional macro. Thus, each of the functional macros 110, 112, 130, 132 provides the same functionality. In an embodiment, each of the functional macros 110, 112, 130, 132 is a memory macro that includes static random access memory cells arranged in rows and columns. In other embodiments, one or more of the functional macros 110, 112, 130, 132 provide a different functionality than other macros among the functional macros 110, 112, 130, 132. Similar to standard cells, macros such as the functional macros 110, 112, 130, 132, and the TSV macros 120, 140 contain mask layout data.

[0015] Some macros do not include any active devices, such as TSV macros 120, 140, etc. TSVs are used as interconnections between dies in a three-dimensional integrated circuit (3D IC) where two or more active device layers are integrated into a single circuit both vertically and horizontally. In a 3D IC, a first semiconductor die (or die), such as a host die or a base die, and each of at least one other die are used in three-dimensional (3D) packaging for a computing system. This type of packaging is called a system-in-package (SiP). TSVs are used as interconnections within the SiP between a base die at the bottom of a vertical stack of dies and one or more other dies stacked on top of the base die. When horizontal on-chip signaling is used in a 3D IC, the host die has another die placed horizontally adjacent to the host die, and chip communication uses the TSVs in the host die and the other die together with an interposer-based integrated connection between these TSVs. The printed circuit board is placed under the interposer.

[0016] Each of TSV macro 120 and TSV block 144 includes at least a TSV, a guard ring indicating the area of a corresponding keep-out zone, and a fill layer. Further details of these components will be provided later in the following description of TSV macro 200 (of FIG. 2). In an embodiment, TSV macro 140 includes boundary cells 150 arranged adjacent to the left and right along the x-dimension of TSV block 144. Similar to other macros, TSV macro 120 does not include any of boundary cells 150, 160, 170. TSV macro 120 is arranged in the channel between functional macro 110 and functional macro 112. In an embodiment, TSV macro 120 supplies a power supply voltage or a ground reference voltage to one or more of functional macros 110, 112. Similarly, TSV macro 140 is arranged in the channel between functional macro 130 and functional macro 132. In an embodiment, TSV macro 140 supplies a power supply voltage or a ground reference voltage to one or more of functional macros 130, 132.

[0017] TSV macros 120 and 140 are arranged to be aligned with each other in the y-dimension. In the illustrated embodiment, the y-dimension is aligned vertically. For example, function macro 130 is arranged above function macro 110 in the vertical direction (or y-dimension) in the illustrated orientation. Similarly, function macro 112 is arranged to the right of function macro 110 in the horizontal direction (or x-dimension) in the illustrated orientation. TSV macros 120 and 140 are arranged to be vertically aligned in the y-dimension according to the power grid specification. Thus, each of TSV macros 120 and 140 has the same distance from the center of the corresponding TSV to the leftmost end of the die in the x-dimension. In addition to having an aligned arrangement, in some embodiments, each of TSV macros 120 and 140 has the same macro width. In other words, macro width 122 of TSV macro 120 is equal to macro width 142 of TSV 140. Placing at least boundary cells such as boundary cell 150 inside TSV macro 140 while making macro width 122 equal to macro width 142 provides a high-density layout for TSV macro 140. The high-density layout of TSV macro 140 maximizes the use of the channel width between function macro 130 and function macro 132.

[0018] Boundary cells are arranged around each of function macros 110, 112, 130, and 132. For example, boundary cell 150 is arranged on the side aligned with the x-dimension. Boundary cell 160 is arranged on the side aligned with the y-dimension. At the corners, boundary cell 170 is arranged. Thus, in various embodiments, boundary cells 150, 160, and 170 form a ring around each of function macros 110, 112, 130, and 132. Each of boundary cells 150, 160, and 170 does not provide a function, does not receive a signal connection, and does not include an active device. Thus, boundary cells 150, 160, and 170 are in the standard cell library used in the design, but boundary cells 150, 160, and 170 are not part of the netlist for the design including portion 100 of the floorplan. Boundary cells 150, 160, and 170 are used to improve the manufacturability of the semiconductor and increase the yield of the die being manufactured.

[0019] Each of the boundary cells 150, 160, 170 includes one or more manufacturing structures such as one or more base layers and one or more metal layers. Examples of base layers are n-type or p-type diffused well layers, dummy metal gate layers such as polysilicon or other metal layers, and implanted layers. The metal layer includes a specific pattern of one or more metal layers. In some embodiments, the boundary cells 150, 160, 170 include a pattern in each of the available signal metal layers. The pattern of the metal layer in the boundary cells 150, 160, 170 fills the empty regions of the floorplan, providing regular planarization of the resulting manufactured wafer.

[0020] In some embodiments, the standard cell library includes multiple deformed forms of each of the boundary cells 150, 160, 170, and each deformed form has a different number of one or more layers from another deformed form. For example, the number of dummy metal gates can vary between different standard cells because a specific number depends on the position within the floorplan where the boundary cell is instantiated. In some embodiments, the boundary cell 150 disposed adjacent to the functional macros 110, 112, 130, 132 has a different width from the boundary cell 150 disposed adjacent to the TSV macro 120. In some embodiments, one or more of the boundary cells 150, 160, 170 include tap cells used to connect an n-type well to a power supply voltage and connect a silicon substrate to a ground reference voltage. In an embodiment, one or more of the boundary cells 150, 160, 170 include end cap cells that improve well and row alignment and help subsequent semiconductor manufacturing processes use the correct laser wavelength.

[0021] The TSV macro 120 is surrounded by the boundary cells 150, 160, 170, similar to the functional macros 110, 112, 130, 132. The channel between the functional macro 110 and the functional macro 112 includes a distance 124 measured from the edge of the boundary cell 150 disposed adjacent to the functional macro 110 to the center of the TSV within the TSV macro 120. There is sufficient distance for the placement of the TSV macro 120 and the extra surrounding boundary cell 150. In other words, the distance 124 is equal to or greater than the threshold distance. However, in the channel between the functional macro 130 and the functional macro 132, the distance 144 is smaller than the distance 124 and smaller than the threshold distance. The distance 144 is measured from the edge of the boundary cell 150 disposed adjacent to the functional macro 130 to the center of the TSV within the TSV macro 140. The TSV macro 120 and the surrounding boundary cell 150 cannot be disposed within this channel. Since the TSV macro disposed within the channel is aligned to specific dimensions such as the requirements of the power grid, a shift along the x dimension is not possible.

[0022] In contrast to the functional macros 110, 112, 130, 132 and the TSV macro 120, the TSV macro 140 includes one or more boundary cells 150, 160, 170 therein. In the illustrated embodiment, the TSV macro 140 includes a boundary cell 150 on each of the first and second sides of the TSV block 144 along the x-dimension. Despite including the boundary cell 150, the TSV macro 140 has a macro width 142 equal to the macro width 122 of the TSV macro 120. The placement routing tool determines that the TSV macro 140, rather than the TSV macro 120, should be placed in the channel between the functional macro 130 and the functional macro 132. In some embodiments, the placement routing tool measures the distance 144, determines that the distance 144 is less than a threshold distance, and thus selects the TSV macro 140. Also, the placement routing tool prevents the placement of the boundary cell 150 adjacent to the TSV macro 140. In other words, the processor generates data indicating a position in the floorplan where a boundary cell 150 adjacent to at least one side of the TSV macro 140 is not allowed. However, the placement routing tool places the boundary cells 160, 170 adjacent to the TSV macro 140 as is done for the functional macros 110, 112, 130, 132 and the TSV macro 120. The use of the TSV macro 140 enables the placement of the required boundary cells 150, 160, 170, supports the power grid specification, and prevents any redesign in the floorplan for moving the functional macro 130.

[0023] Referring to FIG. 2, a schematic diagram of a silicon through via (TSV) macro 200 is shown. The TSV macro 200 includes a TSV 210 and a guard ring 220. Boundary cells 240 are disposed on each of a first side and a second side along a horizontal dimension or x-dimension. There is a filling layer 230 between the boundary cells 240 and the guard ring 220. The boundary cells 240 include the same components as those previously described for the boundary cells 150, 160, 170 (of FIG. 1). The boundary cells 240 include a plurality of instantiations of boundary cells within a standard cell library. The TSV 210 indicates where the TSV is formed using any of various conductive metals or metal alloys based on design requirements. The TSV conveys data and control signals or power signals between dies of a 3D IC. The guard ring 220 indicates a keep-out zone for the TSV 210. The empty space between the TSV 210 and the guard ring 220 is a keep-out zone or region.

[0024] Similar to the boundary cell 240, each of the guard ring 220 and the fill layer 230 includes one or more manufacturing structures such as one or more base layers and one or more metal layers. The selection of which base layers and metal layers to include in the guard ring 220 and the fill layer 230 is based on design choices. The boundary cell 240 and the fill layer 230 are used to provide a uniform distribution of the metal layer across the die by including shapes in the metal layer within the opening region. These shapes are not used to carry signals. The uniform distribution provides the uniformity that aids the semiconductor manufacturing process. For example, the addition of one or more metal layers that do not carry signals in the boundary cell 240 and the fill layer 230 reduces thickness variations during the chemical-mechanical polishing (CMP) manufacturing step, improves the electrochemical deposition (ECD), etching, and lithography steps, and reduces stress effects across the die. The standard cell library includes one or more standard cells called "fill cells" or "filler cells". These standard cells or filler cells in the library are used to generate the fill layer 230. These filler cells are used to provide both front end of line (FEOL) fill and back end of line (BEOL) fill in the filling of the fill layer 230. In other words, the fill layer 230 shown in the TSV macro 200 includes one or more of these standard cells or filler cells from the standard cell library.

[0025] In addition to the use of the boundary cell 240 and the filling layer 230, the guard ring 220 defines a keep-out zone for the TSV 210. In some embodiments, the generation of the TSV macro 200 includes using one or more barriers. Since these barriers do not remain in the TSV macro 200, they are not shown. These barriers include shapes that do not carry signals in the metal layer that is also used in the filler cells of the filling layer 230. The purpose of the barriers is to ensure sufficient free space between the filling layer 230 and the guard ring 220 when the filling layer 230 is formed within the TSV macro 200. In an embodiment, the placement wiring tool automatically places the filling layer 230 between the boundary cell 240 and the guard ring 220. However, by placing the boundary cell 240, the amount of area of the filling layer 230 is reduced.

[0026] The filling layer 230 has requirements for having a specific number of components such as at least some dummy metal gates. To meet the design rule check (DRC) requirements, the placement routing tool places the filling layer 230 at an end different from the leftmost end or the rightmost end of the TSV macro 200. In contrast to a TSV macro without boundary cells, each of the leftmost and rightmost ends of the TSV macro 200 is occupied by a boundary cell 240. In some embodiments, the guard ring 220 does not have a metal layer shape sufficient to be shown to the placement routing tool at its outer edge to end the formation of the filling layer 230 at a specific distance from the guard ring 220. In such a case, a barrier is placed adjacent to a specific side of the guard ring 220, and the placement routing tool is shown to end the formation of the filling layer 230 at a specific distance from the specific side of the guard ring 220. One or more of the width and length of the barrier are adjusted until the placement (or formation) of the filling layer 230 provides a threshold distance from the guard ring 220 to the filling layer 230. After the filling layer 230 is placed within the TSV macro 200 and meets the DRC requirements, the barrier is removed from the TSV macro 200. These steps of placing the barrier, adjusting the width and length of the barrier, forming the filling layer 230, and removing the barrier are repeated for one or more other sides of the guard ring 220 if necessary.

[0027] The boundary cells 240 are shown at each of the leftmost and rightmost along the x-dimension in the TSV macro 200, but in other embodiments, the TSV macro 200 includes the boundary cells 240 at one or more of the upper and lower sides along the y-dimension. In embodiments, the TSV macro 200 includes boundary cells 240 at each of the four sides in addition to each of the four corners. Any combination of the placement of the boundary cells 240 in the TSV macro 200 is possible and contemplated. For each combination, the placement of the filling layer 230, and the use and subsequent removal of any barriers during the placement of the filling layer 230 are adjusted accordingly.

[0028] After being formed by a mask layout editor and passing a design rule check (DRC) verification, the TSV macro 200 is placed in a standard cell library. The TSV macro 200 is used to provide interconnections such as the interconnection between the power supply voltage between functional macros on the die and the bonding pads of the die. The TSV macro 200 is an example of a macro that does not contain active devices and thus does not provide a Boolean function. The TSV macro 200 in the standard cell library contains mask layout data. As described above, the mask layout data of a specific standard cell includes one or more mask layers associated with one or more layers of the specific standard cell. One or more layers of a specific standard cell include a base layer and a plurality of metal layers used for signal interconnection. The mask layout data includes a mask pattern used in photolithography performed during semiconductor manufacturing of an integrated circuit. The pattern indicates the arrangement positions of components within a specific standard cell with respect to a reference point such as a corner of the specific standard cell. Examples of components are active devices and passive elements (e.g., resistors, capacitors, inductors) arranged within the standard cell. Also, the mask layout data includes parasitic information of components such as the resistance of wiring and nodes, the coupling capacitance of wiring and transistor terminals, and load capacitance.

[0029] Next, referring to FIG. 3, a schematic diagram of a portion 300 of an integrated circuit floorplan is shown. The portion 300 of the integrated circuit floorplan (or floorplan) includes functional macros 310, 320 that are instantiated multiple times across the die. Also, the portion 300 of the floorplan includes a TSV macro 340. Although not shown, boundary cells are placed around the functional macros 310, 320. In an embodiment, the TSV macro 340 supplies a power supply voltage or a ground reference voltage to one or more of the functional macros 310, 320 and any surrounding logic gates (not shown).

[0030] In various embodiments, one or more of the TSVs 340 include components of the TSV macro 140 (of FIG. 1) and the TSV macro 200 (of FIG. 2). In some embodiments, the use of these types of TSV macros supports a smaller channel width between the functional macros 310 than when other types of TSV macros are used. Further, in embodiments, the use of these types of TSV macros enables Boolean logic gates, data buffers, and other types of standard cells to be placed between the TSV macro 340 and the nearby functional macro 310. The TSV macros 340 are aligned with each other in the y-dimension within the channels between the functional macros 310 and within the channels between the functional macros 320. In some embodiments, the alignment is based on a predetermined power grid.

[0031] In some embodiments, each of the functional macros 310 is an instantiation of the same functional macro. Thus, each of the functional macros 310 provides the same function. In embodiments, each of the functional macros 310 is a memory macro including static random access memory cells arranged in rows and columns. In such embodiments, the functional macro 320 includes access circuitry such as one or more of a read word line driver, a write word line driver, a read storage latch or register, a write data storage latch or register, etc. In other embodiments, the functional macros 310 and 320 provide other functions.

[0032] Referring to FIG. 4, a schematic block diagram of a computing system 400 is shown. In the illustrated embodiment, the computing system 400 includes a client computing device 450, servers 420A-420D including hardware for executing software and supporting the organization center 410, a network 440, and a data storage device 430 including one or more data stores supported and used by the organization center 410. Although a single client computing device 450 is shown, any number of client computing devices may utilize the organization center 410 via the network 440. The client computing device 450 (also referred to as client device 450) includes hardware such as a circuit of a processor for executing instructions of an automatic placement and routing (PNR) generator 460. The automatic PNR generator 460 (or PNR generator 460) uses a copy of the data stored in the data storage device 430. Examples of the copy of the data are integrated circuit (IC) mask layout data 432 and IC netlist 434.

[0033] The IC mask layout data 432 is available in a standard cell library that includes various cells using devices of various sizes to provide specific functions. Also, the IC mask layout data 432 includes macro mask layout data. As described above, the IC mask layout data 432 of a specific standard cell includes one or more mask layers associated with one or more layers of the specific standard cell. One or more layers of a specific standard cell include a base layer and a plurality of metal layers used for signal interconnection. The mask layout data includes a mask pattern used in photolithography performed during semiconductor manufacturing of an integrated circuit. The pattern indicates the arrangement positions of components within a specific standard cell relative to a reference point such as a corner of the specific standard cell. Examples of components are active devices and passive elements (e.g., resistors, capacitors, inductors) arranged within the standard cell. Also, the IC mask layout data 432 includes parasitic information of components such as resistance of wiring and nodes, coupling capacitance of wiring and transistor terminals, and load capacitance.

[0034] In an embodiment, the user starts using the PNR generator 460 using a graphical user interface (GUI) 462, a script, a command line, or a combination of these elements. The PNR generator 460 generates a representation of the hardware layout from a schematic diagram of the integrated circuit being designed. To do so, the PNR generator 460 further uses a copy of the mask layout data 432 and the RDL netlist 434, and specifications of the dimensions of the floorplan of the IC to identify the placement of standard cells and macros in the floorplan of the IC die being designed.

[0035] Also, the PNR generator 460 uses the DRC 436 to verify whether the placement of standard cells, macros, boundary cells, and fill layers violates the design rules of the layout. The output of the PNR generator 460 is later sent to the semiconductor wafer manufacturer. This output shows the placement and connectivity of components across the entire die of the designed IC. This output uses one or more TSV macros that include one or more boundary cells. Examples of these TSV macros are TSV macro 140 (of FIG. 1) and TSV macro 200 (of FIG. 2). When the placement of standard cells, macros, boundary cells, and fill layers passes the DRC and LVS checks, one or more copies of the updated version of the mask layout data 432 are stored in the client device 450 and the data storage device 430. Subsequently, a semiconductor chip tape-out process is performed on the integrated circuit under development, and the semiconductor manufacturing process provides the hardware of the integrated circuit for testing.

[0036] The client device 450 includes a desktop computer or a mobile computing device such as a laptop or a tablet computer. The client device 450 includes a hardware circuit such as a processing unit 470 for processing the instructions of a computer program. In some embodiments, the processing unit 470 includes one or more homogeneous cores of a processor. In other embodiments, the processing unit includes heterogeneous cores such as parallel processing architecture cores and general-purpose cores used in a central processing unit (CPU). The parallel architecture cores may be, for example, a graphics processing unit (GPU), a digital signal processing unit (DSP), or the like.

[0037] The client device 450 includes a network interface (not shown) that supports one or more communication protocols for data and message transfer via the network 440. The network 440 includes a plurality of switches, routers, cables, wireless transmitters, and the Internet for transferring messages and data. Thereby, the network interfaces of the organization center 410 and the client device 450 support at least the Hypertext Transfer Protocol (HTTP) for communication across the World Wide Web. In addition to communicating with the client device 450 via the network 440, the organization center 410 communicates with the data storage device 430 to store and retrieve data.

[0038] In various embodiments, the organization center 410 is an infrastructure for a vendor to produce one or more hardware products. The organization center 410 includes an intranet network that provides a private network accessible only to the staff of the organization. The intranet portal is used to provide access to resources and has a user-friendly interface such as a graphical user interface (GUI) and a dashboard. The information and services made available by the organization center 410 are not available to the general public via direct access. Through user authentication, staff members can access resources via the organization center 410 to communicate with other staff members, collaborate on projects, monitor product development, update products, documents, and tools stored in a centralized repository, and so on.

[0039] The organization center 410 and the servers 420A-420D used to support the resources accessed via the organization center 410 include various server types such as database servers, computing servers, application servers, file servers, mail servers, etc. In various embodiments, the servers 420A-420D and the client device 450 operate in a client-server architecture model. The client device 450 includes a copy of a specific version of a predetermined software product or tool such as the PNR generator 460. In some embodiments, the version of the PNR generator 460 is based at least on the operating system and the processor used by the client device 450. The PNR generator 460 includes an engine 464 that, when executed by the processor of the processing unit 470, automatically causes the processing unit 470 to generate a layout mask for the components across the entire die of an IC designed according to a specific floorplan.

[0040] Referring to FIG. 5, a schematic diagram of a method 500 for efficiently generating a floorplan layout using an efficient through-silicon via macro block is shown. For the sake of explanation, the steps in this embodiment (as well as FIGS. 6-7) are shown in order. However, in other embodiments, some steps occur in a different order than shown, some steps are executed simultaneously, some steps are combined with other steps, and some steps do not exist.

[0041] The hardware of the processor of the corresponding computing device executes an automatic placement and routing (PNR) tool or generator. The PNR tool (based on the execution of the processor's hardware) selects the netlist of the IC being designed, accesses the specifications of the dimensions of the IC's floorplan, and accesses the standard cell library. The PNR generator places the first functional macro in the floorplan of the integrated circuit (block 502). The PNR generator places the through-silicon via (TSV) macro in the floorplan (block 504). The PNR generator places at least one boundary cell adjacent to the functional macro (block 506). The PNR generator prevents the placement of boundary cells adjacent to at least one side of the TSV macro in the floorplan (block 508). In other words, the PNR generator generates data indicating positions within the floorplan where boundary cells adjacent to at least one side of the TSV macro are not allowed. The PNR generator performs design rule check (DRC) verification and layout versus schematic (LVS) verification (block 510). Any errors are corrected by the designer. When the verification is performed without errors, the IC design is taped out and manufactured (block 512).

[0042] If no potential is applied to the first node of the integrated circuit within the semiconductor package (condition block 514: "No"), the semiconductor package waits for power-on (block 516). However, if a potential that generates a potential difference is applied to the first node (condition block 514: "Yes"), the input node passes current from the motherboard to the functional macro (block 518).

[0043] Referring to FIG. 6, a schematic diagram of a method 600 for efficiently generating a floorplan layout using an efficient through-silicon via macro block is shown. The hardware of the processor of the corresponding computing device executes an automatic placement and routing (PNR) tool or generator. The PNR tool (based on the execution of the hardware of the processor) selects the netlist of the IC being designed, accesses the specifications of the dimensions of the floorplan of the IC, and accesses the standard cell library. The PNR tool places functional macros in the floorplan of the integrated circuit (block 602). The PNR tool determines the distance between the edge of the functional macro and the placement of the power grid (block 604). The PNR tool compares the measured distance with a distance threshold. The distance threshold includes the placement of boundary cells adjacent to the side of the functional macro facing the power grid, the placement of boundary cells adjacent to the side of the TSV macro facing the functional macro, and the minimum distance supporting the distance from the side of the TSV macro facing the functional macro to the center of the TSV macro.

[0044] If the PNR tool determines that the measured distance is less than the distance threshold (conditional block 606: "Yes"), the PNR tool places a first type of through-silicon via (TSV) macro including at least one boundary cell on the power grid (block 608). Examples of this first type of TSV macro are TSV macro 140 (of FIG. 1) and TSV macro 200 (of FIG. 2). The PNR tool prevents the placement of boundary cells adjacent to at least one side of the first type of TSV macro (block 610). If the PNR tool determines that the measured distance is greater than or equal to the distance threshold (conditional block 606: "No"), the PNR tool places a second type of TSV macro on the power grid in a channel where there are no boundary cells from the second type of TSV macro (block 612). Subsequently, the PNR tool places boundary cells adjacent to the side of the second type of TSV macro (block 614). Regardless of the comparison between the measured distance and the threshold distance, the PNR tool places boundary cells adjacent to the side of the functional macro (block 616).

[0045] Referring to FIG. 7, a schematic diagram of a method 700 for efficiently designing a silicon through - via macro block is shown. The hardware of the processor of the corresponding computing device executes a mask layout editor tool (or editor tool). The editor tool forms a through - silicon via (TSV) within a TSV macro (block 702). The editor tool forms a guard ring around the TSV (block 704). The editor tool places boundary cells on at least one side of the TSV macro (block 706). Between any boundary cell and the guard ring, the editor tool forms a fill layer (block 708). Between any side without a boundary cell and the guard ring, the editor tool forms a fill layer (block 710).

[0046] The editor tool performs DRC verification on the TSV macro. If the TSV macro fails the DRC verification (conditional block 712: "No"), the editor tool places one or more barriers within the TSV macro to control the formation of the fill layer (block 714). As described above, these barriers include shapes that do not carry signals in the metal layers that are also used in the fill cells of the fill layer. The purpose of the barriers is to ensure sufficient free space between the fill layer and the guard ring when the fill layer is formed within the TSV macro. Then, the control flow of method 700 returns to block 708, where the editor tool forms the fill layer. In some embodiments, the editor tool removes some or all of a previously formed fill layer. If the TSV macro passes the DRC verification (conditional block 712: "Yes"), the barriers are removed from the TSV macro (block 716). The TSV macro is ready to be used in an integrated circuit floorplan. In some embodiments, the TSV macro is placed within a standard cell library.

[0047] Referring to FIG. 8, a schematic diagram of a system-in-package (SiP) 800 is shown. In various embodiments, three-dimensional (3D) packaging is used within a computing system to generate the SiP 800. The SiP 800 includes a semiconductor-based die 820 (or die 820) and semiconductor dies 830A - 830C (or dies 830A - 830C). Here, the SiP 800 uses layers of active electronic components integrated into a single circuit in both the horizontal and vertical directions. Die stacking technology is a manufacturing process that enables physically stacking together multiple individual silicon pieces (integrated chips) within the same package with high-bandwidth and low-latency interconnects. The SiP 800 includes additional components not shown for ease of illustration, such as one or more of an interposer, a package substrate, a redistribution layer (RDL), bonding pads, etc. Four dies 820 and 830A - 830C are shown, but in other embodiments, any number of dies, any number of types of dies, and vertical stacking in any order may be used.

[0048] As shown, in one embodiment, SiP800 includes die 830C stacked on die 830B. In other words, die 830C is disposed on the side of die 820B away from a printed circuit board (not shown), such as a motherboard, located under package external connection 860. In this configuration, die 830C and die 830B use through-silicon vias (TSVs) 842 therebetween to transfer data signals, control signals, and power signals. The printed circuit board (not shown) is disposed under SiP800 and communicates with base die 820 via package external connection 860. In various embodiments, package external connection 860 can be any of a variety of surface mount device (SMD) pins that allow SiP800 to be placed directly on the surface of the printed circuit board or, when a redistribution layer (RDL) is used, directly on the RDL. Examples of SMD pins are solder ball grid array (BGA), bumps or microbumps, flat contacts, or bonding pads, etc.

[0049] Base die 820 and dies 830A-830C are contemplated to include one or more of various processing units, a cache memory subsystem, an array of data storage devices, one or more of various application specific integrated circuits (ASICs), a display controller, a communication interconnect or fabric, etc. For example, one or more of base die 820 and dies 830A-830C are system on chips (SoCs). Multiple paths use vertical hops between base die 820 and dies 830A-830C. These paths include signal paths such as commands, messages, and packets, address information, response data, write data, data snooping requests, etc. Also, the paths include power connection paths such as one or more power lines for transmitting power supply voltage levels and ground reference voltage levels. In addition to using TSVs 842, SiP 800 uses an in-package horizontal low latency integrated interconnect 846 (or interconnect 846) that provides reduced length interconnect signals for long off-chip interconnects. Interconnect 846 uses specific signals and protocols as if chips such as base die 820 and dies 830A-830C were mounted within separate packages on a circuit board.

[0050] Each active device layer of base die 820 and dies 830A-830C has direct vertical interconnects that tunnel through them or otherwise traverse them, such as TSVs 842. TSVs 842 are alternative interconnects to wire bonds and flip chips. The keep-out zones corresponding to individual TSVs among TSVs 842 define the regions around the TSVs and provide the active devices with predicted stress above a threshold. The stress is caused by the placement of the TSVs. The regions outside the keep-out zones provide the active devices with predicted stress below the threshold. The size and density of the TSVs that can tunnel between different device layers vary based on the underlying technology used to manufacture the 3D IC.

[0051] In some embodiments, base die 820 and dies 830A - 830C do not include through - silicon vias (TSVs) that completely tunnel through them to carry signals between them and other dies. Rather, one or more TSVs pass through the silicon substrate and oxide layer and terminate at specific metal layers within base die 820 and dies 830A - 830C. The metal layer can be any of the metal layers from the bottom - most metal 0 (M0) layer to the top - most metal layer used by a particular die. In some embodiments, a particular TSV reaches an upper metal layer and does not proceed further. Thus, no active devices (transistors) are formed at the location where this particular TSV is created. In various embodiments, the placement of TSVs 842 on the floorplan of base die 820 and dies 830A - 830C uses the techniques described previously with respect to TSV macro 140 (of FIG. 1) and TSV macro 200 (of FIG. 2).

[0052] Note that one or more of the above-described embodiments include software. In such embodiments, program instructions for implementing the method and / or mechanism are transmitted or stored on a computer-readable medium. A number of types of media are available for storing program instructions, including hard disks, floppy (registered trademark) disks, CD-ROMs, DVDs, flash memories, programmable ROMs (Programmable ROM, PROM), random access memories (random access memory, RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, computer-accessible storage media includes any storage media that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media includes magnetic or optical media, such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or storage media such as Blu-Ray (registered trademark). Storage media further includes volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (synchronous dynamic RAM, SDRAM), double data rate (double data rate, DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (low-power DDR, LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (static RAM, SRAM), etc.), ROM, flash memory, and non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface. Storage media includes microelectromechanical systems (microelectromechanical system, MEMS), as well as storage media accessible via communication media such as networks and / or wireless links.

[0053] Additionally, in various embodiments, the program instructions include operation-level descriptions or register-transfer level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII stream format (GDSII). In some cases, the description is read by a synthesis tool that synthesizes the description to generate a netlist containing a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including the system. The netlist can then be placed and routed to generate a dataset that describes the geometric shapes to be applied to the mask. The mask is then used in various semiconductor manufacturing steps to generate a semiconductor circuit or circuit corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium can be, optionally, a netlist (with or without a synthesis library) or a dataset. Additionally, the instructions are utilized for emulation by hardware-based types of emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0054] Although the above embodiments have been described in considerable detail, many variations and modifications will become apparent to those skilled in the art upon a full understanding of the above disclosure. The following claims are intended to be construed to embrace all such variations and modifications.

Claims

1. Based at least in part on a netlist corresponding to an integrated circuit and a standard cell library, an arrangement in a floorplan of the integrated circuit of a first type of through-silicon via (TSV) macro, a functional macro including a plurality of active devices, and at least one boundary cell adjacent to the functional macro, a position within the floorplan of the integrated circuit where boundary cells are not permitted adjacent to at least a first side of the first type of TSV macro, a circuit configured to generate data indicative of, a processor.

2. The first type of TSV macro comprises at least one boundary cell, The processor of Claim 1.

3. The circuit is configured to generate data indicative of a position within the floorplan of the integrated circuit where boundary cells are not permitted adjacent to a second side of the first type of TSV macro that is different from the first side, based at least in part on the netlist and the standard cell library, The processor of Claim 2.

4. The first type of TSV macro comprises a first boundary cell on the first side and a second boundary cell on the second side, The processor of Claim 3.

5. The first type of TSV macro includes a threshold distance between a fill layer and a guard ring, The processor of Claim 1.

6. The circuit is configured to determine a distance between an edge of the functional macro and an arrangement of a power grid, based at least in part on the netlist and the standard cell library, generate data indicative of an arrangement in the floorplan of the integrated circuit of the first type of TSV macro on the power grid in response to determining that the distance is less than a threshold distance, and is configured to perform, The processor of Claim 1.

7. The circuit is configured to, based at least in part on the netlist and the standard cell library, in response to determining that the distance is greater than or equal to the threshold distance, a second type of TSV macro different from the first type of TSV macro on the power grid, where boundary cells do not exist in the second type of TSV macro, and at least one boundary cell adjacent to the second type of TSV macro, configured to generate data indicating the placement in the floorplan of the integrated circuit The processor of claim 1. **Claim 8** The circuit of the processor receives a netlist of the integrated circuit, The circuit accesses a standard cell library including a plurality of standard cells and a plurality of macros, Based at least in part on the netlist and the standard cell library, the placement in the floorplan of the integrated circuit of a first type of through-silicon via (TSV) macro, a functional macro including a plurality of active devices, and at least one boundary cell adjacent to the functional macro, a position within the floorplan of the integrated circuit where boundary cells are not allowed adjacent to at least a first side of the first type of TSV macro, generating data indicating the same, A method. **Claim 9** The first type of TSV macro includes at least one boundary cell, The method of claim 8. **Claim 10** Based at least in part on the netlist and the standard cell library, the circuit generates data indicating a position within the floorplan of the integrated circuit where boundary cells are not allowed adjacent to a second side different from the first side of the first type of TSV macro, The method of claim 9. **Claim 11** The first type of TSV macro includes a first boundary cell on the first side and a second boundary cell on the second side, The method of claim 10. **Claim 12** The first type of TSV macro includes a threshold distance between a filling layer and a guard ring, The method of claim 8. **Claim 13** The circuit determines a distance between an edge of the functional macro and the placement of a power grid, Based at least in part on the netlist and the standard cell library, generating data indicating the placement in the floorplan of the integrated circuit of the first type of TSV macro on the power grid in response to determining that the distance is less than a threshold distance, The method of claim 8. **Claim 14** Based at least in part on the netlist and the standard cell library, the circuit In response to determining that the distance is equal to or greater than a threshold distance, a second type of through-silicon via (TSV) macro different from the first type of TSV macro on the power grid, wherein a boundary cell does not exist in the second type of TSV macro, a second type of TSV macro, and at least one boundary cell adjacent to the second type of TSV macro, generating data indicating an arrangement in the floorplan of the integrated circuit of The method of claim 8. **Claim 15** A computing system, comprising: a processing unit; and a memory coupled to the processing unit, wherein the memory is configured to store a netlist of an integrated circuit and a standard cell library including a plurality of standard cells and a plurality of macros, and the circuitry of the processing unit is configured to receive the netlist, access the standard cell library, generate data indicating an arrangement in the floorplan of the integrated circuit of a first type of through-silicon via (TSV) macro, a functional macro including a plurality of active devices, and at least one boundary cell adjacent to the functional macro, based at least in part on the netlist and the standard cell library, and generate data indicating a position within the floorplan of the integrated circuit where boundary cells are not allowed adjacent to at least a first side of the first type of TSV macro, and perform. A computing system. **Claim 16** The first type of TSV macro includes at least one boundary cell. The computing system of claim 15. **Claim 17** The circuitry is configured to generate data indicating a position within the floorplan of the integrated circuit where boundary cells are not allowed adjacent to a second side of the first type of TSV macro different from the first side, based at least in part on the netlist and the standard cell library. The computing system of claim 16. **Claim 18** The first type of TSV macro includes a first boundary cell on the first side and a second boundary cell on the second side. The computing system of claim 17. **Claim 19** The first type of TSV macro includes a threshold distance between a filling layer and a guard ring. The computing system of claim 15. **Claim 20** The circuitry Determining a distance between an edge of the functional macro and an arrangement of a power grid; Based at least in part on the netlist and the standard cell library; Generating data indicative of an arrangement in the floorplan of the integrated circuit of the first type of TSV macro on the power grid in response to determining that the distance is less than a threshold distance; Configured to perform; The computing system of claim 15.

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