Superconducting interconnection structure

Abstract

Superconducting interconnection structure. A method for forming a superconducting interconnection structure, comprising providing a substrate (1), forming a superconducting layer (21), forming a layer of a first dielectric material (22), and forming a pattern including a first set of line structures (4) including a first set of superconducting line structures (41) and a first set of line structures (42) made of a first dielectric material, removing a part of the layers of the first dielectric material (22) and the superconducting layer (21), forming a second dielectric material (50) between the first set of line structures (4), forming a layer made of a third dielectric material (6), providing a patterning mask (73), transferring the pattern to the first dielectric material (42) and the layer made of the third dielectric material to form at least one via hole (43), removing the patterning mask (73), and forming a superconducting material layer (8) to form at least one via (81).

Description

Technical Field

[0001] The present invention relates to the field of superconducting interconnections for integrated circuits. In particular, the present invention relates to a method for forming superconducting lines and vias.

Background Art

[0002] Superconducting digital technology has high potential as a technology beyond CMOS. The advantages associated with superconducting digital technology are high energy efficiency, high computing density, and high interconnect bandwidth. Superconducting digital technology is typically based on single flux quantum (SFQ) pulses that are fast, low power, and low dispersion / low loss on superconducting transmission lines.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Superconducting interconnections may connect different devices within an integrated circuit based on superconducting digital technology. To form such superconducting interconnections, metal etching is typically performed in the art. However, while metal etching is suitable for use with many superconducting materials, the potential to miniaturize the interconnect structure may be limited. For example, conventional Nb wires are highly sensitive to parasitics and magnetic coupling and require multiple ground planes and special layout wiring algorithms. On the other hand, high kinetic inductance wires are less sensitive to parasitic magnetic coupling and enable high-density wiring if the spread of material parameters can be tightly controlled throughout the manufacturing process.

[0004] Therefore, there is a need for a technology to further miniaturize the superconducting interconnection structure. However, for excellent superconducting logic and memory, a post-process wiring process that is compatible with high kinetic inductance materials (e.g., NbTiN), can form several layers of superconducting line structures with a pitch of 100 nm or less, and can form vias that match the pitch of the superconducting line structures is desirable. At the same time, it is preferable to precisely control the cross-sectional control of the superconducting line structure and vias (the cross-section that determines the inductance per unit length).

[0005] Therefore, in this technical field, there is still a need for devices and methods that address at least some of the above problems.

[0006] An object of the present invention is to provide a good method for forming a superconducting interconnection structure of an integrated circuit, and a good superconducting interconnection structure obtained thereby.

Means for Solving the Problems

[0007] The above object is achieved by the method and structure according to the present invention.

[0008] The fact that the miniaturization of the superconducting interconnection structure can be made possible is an advantage of the embodiments of the present invention. In fact, the fact that the pitch between the superconducting line structure of the first entity and the superconducting line structure of the second entity overlapping on the first entity can be as small as, for example, 100 nm or less is an advantage of the embodiments of the present invention.

[0009] The fact that the superconducting interconnection structure can have a superconducting line structure and vias whose cross-sections can be precisely controlled is an advantage of the embodiments of the present invention. The fact that the vias can have a small parasitic inductance is a further advantage of the embodiments of the present invention. The fact that a high filling rate can be achieved for the superconducting line structure is a further advantage of the embodiments of the present invention.

[0010] The fact that shallow vias (i.e., vias with a low aspect ratio) can be formed is an advantage of the embodiments of the present invention.

[0011] The ability to be compatible with high-mobility inductance materials (such as NbTiN) for which film formation in trenches can be difficult is an advantage of embodiments of the present invention.

[0012] A method of forming a superconducting interconnection structure of an integrated circuit, forming a first entity on a substrate by a.a1.~a7., a1. providing a substrate, a2. forming a first superconducting layer of a first superconducting material having a first critical temperature on the substrate, a3. forming a layer of a first dielectric material on the first superconducting layer, a3’. Optionally, forming a protective dielectric layer having a thickness of, for example, 1 to 20 nm, such as 10 nm, for example 5 to 15 nm, on top of the first dielectric material. a4. removing a part of the layer of the first dielectric material and a part of the first superconducting layer, where the part extends from the bottom surface of the first superconducting layer to the top surface of the first dielectric material so as to form a pattern having a first set of line structures having an upper surface, and the first set of line structures includes a first set of superconducting line structures and a first set of line structures made of the first dielectric material that overlap and are aligned above the first set of superconducting line structures. a5. forming a second dielectric material different from the first dielectric material on and between the first set of line structures, a6. planarizing the second dielectric material so that the upper surface of the second dielectric material is coplanar with the upper surface of the first set of line structures, a7. forming a layer made of a third dielectric material on the first set of line structures and the second dielectric material, thereby forming a first entity. b. providing a patterned mask on the first entity, where the pattern has at least one opening that overlaps a superconducting line structure underlying the first set of superconducting line structures to form at least one via hole in the layer made of the first dielectric material and the third dielectric material. c. Form at least one via hole extending through the layer formed of the first dielectric material and the third dielectric material, and thereby transfer the pattern of the patterning mask to the layer formed of the first dielectric material and the third dielectric material so as to expose a part of the superconducting line structure in the lower layer. d. Remove the patterning mask, thereby exposing the perforated surface, and e. Form one or more superconducting units made of a superconducting material, each having a critical temperature within 1 K of the first critical temperature, on the perforated surface, and thereby also form at least one via by filling at least one via hole, and at least one via extends through the layer formed of the first dielectric material and the third dielectric material such that the formed superconducting unit physically contacts the first set of superconducting line structures in the lower layer. including.

[0013] In a second aspect, the present invention relates to a superconducting interconnection structure that can be formed by the method according to any embodiment of the first aspect, and the interconnection structure is i. A first set of line structures having an upper surface, - a first set of superconducting line structures, and - a first set of line structures made of a first dielectric material that is aligned and overlaps on the first set of superconducting line structures and has an upper surface, including the first set of line structures, ii. A second dielectric material different from the first dielectric material, the second dielectric material being between the first set of line structures and having an upper surface coplanar with the upper surface of the first set of line structures, iii. A third dielectric material overlapping on the first set of line structures and the second dielectric material having a first entity including, The via extends through the layer formed of the first dielectric material and the third dielectric material, and the via contains a superconducting material that physically contacts the superconducting line structure in the lower layer.

[0014] Certain preferred embodiments of the present invention are described in the appended independent and dependent claims. The features of the dependent claims may be combined with the features of the independent claims, and are not only explicitly described in the claims, but may also be appropriately combined with the features of other dependent claims.

[0015] Although there have been continuous improvements, changes, and evolutions in the devices in this field, the concept of the present invention represents a substantially new and innovative improvement, including deviations from conventional practices. As a result, it is considered possible to provide more efficient, stable, and reliable devices of this kind.

[0016] The above and other characteristics, features, and advantages of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings that exemplify the principles of the present invention. This description is provided for illustrative purposes only without limiting the scope of the present invention. The reference figures cited below refer to the accompanying drawings.

Brief Description of the Drawings

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[0018] In different figures, the same reference numerals refer to the same or similar elements.

[0019] The present invention will be described with reference to specific drawings with respect to specific embodiments, but the present invention is not limited thereto and is limited only by the claims. The described drawings are schematic and non-limiting. In the drawings, the sizes of some elements may be exaggerated for illustrative purposes and may not be drawn to scale. Dimensions and relative dimensions do not correspond to actual drawings for the implementation of the present invention.

[0020] Furthermore, the terms first, second, third, etc. in this specification and the claims are used to distinguish similar elements and are not necessarily used to describe a sequence in a temporal, spatial, ranking, or other manner. When used in this way, the terms are interchangeable under appropriate circumstances, and it should be understood that the embodiments of the invention described herein are operable in an order other than that described or illustrated herein.

[0021] Furthermore, the terms upper, lower, above, below, etc. in this specification and the claims are used for purposes of explanation and are not necessarily for describing relative positions. When used in this way, the terms are interchangeable under appropriate circumstances, and it should be understood that the embodiments of the invention described herein are operable in an orientation other than that described or illustrated herein.

[0022] The terms "above", "overlying", and "upward" are used synonymously and cover cases with and without physical contact. The term "above" means "in physical contact above".

[0023] It should be noted that the term "comprising" used in the claims should not be construed as being limited to the means recited thereafter and does not exclude other elements or steps. Thus, this term is construed to identify the presence of the recited features, integers, steps, or components, but does not exclude the presence or addition of one or more other features, integers, steps, or components or groups thereof. Thus, the term "comprising" is directed to situations where only the recited features are present and to situations where these features and one or more other features are present. Thus, the term "comprising" according to the present invention also includes, as one embodiment, the absence of further components. Thus, the scope of the expression "a device comprising means A and B" should not be construed as being limited to a device consisting only of components A and B. This expression means, with respect to the present invention, that the relevant components of the device are only A and B.

[0024] The phrase "one embodiment" or "one embodiment" used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrase "in one embodiment" or "in one embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment, and may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0025] Similarly, in describing exemplary embodiments of the invention, it will be understood that various features of the invention may be grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in understanding one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are expressly incorporated herein, with each claim standing on its own as a separate embodiment of the invention.

[0026] Furthermore, some embodiments described herein include some features included in other embodiments but not other features, but combinations of features of different embodiments are meant to be within the scope of the present invention and form different embodiments, as would be understood by one of ordinary skill in the art. For example, in the following claims, any of the claimed embodiments may be used in any combination.

[0027] Furthermore, some embodiments are described herein as a method or a combination of method elements that can be implemented by a processor of a computer system or other means for implementing functions. Accordingly, a processor having instructions necessary to implement such a method or method elements forms means for implementing the method or method elements. Further, the elements described herein in the embodiments of the apparatus are an example of means for performing the functions executed by the elements for the purpose of implementing the present invention.

[0028] Numerous specific details are set forth herein. However, it is understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this specification.

[0029] The following terms are provided only to assist in the understanding of the present invention.

[0030] As used herein, unless otherwise specified, when an entity is described as being superconducting, it means that the entity has the ability to become superconducting at a temperature below a certain critical temperature. This does not mean that the entity is superconducting at the time it is formed in the method. On the contrary, the steps of the method are usually carried out at a temperature higher than the critical temperature of the superconducting material involved. Thus, for example, forming a first superconducting layer does not result in a layer that becomes superconducting as soon as it is formed, but rather a layer that can become superconducting after its temperature has dropped below its critical temperature.

[0031] In a first aspect, the present invention relates to a method for forming a superconducting interconnect structure of an integrated circuit, a. forming a first entity (44) on a substrate (1) by methods a1 to a7, a1. providing a substrate (1), a2. Forming a first superconducting layer (21) of a first superconducting material having a first critical temperature on a substrate (1). a3. Forming a layer of a first dielectric material (22) on the first superconducting layer (21). a3’. Optionally, forming a protective dielectric layer having a thickness of, for example, 1 to 20 nm, such as 10 nm, or for example 5 to 15 nm, on the first dielectric material (22). a4. Removing a part of the layer of the first dielectric material (22) and the first superconducting layer (21), where the part extends from the lower surface of the first superconducting layer (21) to the upper surface of the first dielectric material (22) so as to form a pattern including a first set of line structures (4) having an upper surface (420), and the first set of line structures includes a first set of superconducting line structures (41) and a first set of dielectric material - made line structures (42) that are aligned and overlap above the first set of superconducting line structures (41) and have an upper surface (420). a5. Forming a second dielectric material (50) different from the first dielectric material on and between the line structures of the first set (4). a6. Planarizing the second dielectric material (50) so that the upper surface of the second dielectric material (51) is coplanar with the upper surface (420) of the first set of line structures (4), and then a7. Forming a layer made of a third dielectric material (6) on the first set of line structures (4) and the second dielectric material (50), thereby forming a first entity (44). b. Providing a patterned mask (73) on the first entity, where the pattern includes at least one opening (730) that overlaps with a superconducting line structure in the lower layer of the first set of superconducting line structures (41) to form at least one via hole (43) in the layer formed by the first dielectric material (42) and the third dielectric material (6). c. Transferring the pattern of the patterned mask (73) to the layer formed of the first dielectric material (42) and the third dielectric material (6) to form at least one via hole (43) extending through the layer formed of the first dielectric material (42) and the third dielectric material (6), thereby exposing a part of the underlying superconducting line structure (41). d. Removing the patterned mask (73), thereby exposing the perforated surface (60). e. Forming one or more superconducting units (81, 201, 8) made of a superconducting material, each having a critical temperature within 1 K of the first critical temperature, on the perforated surface (60), thereby also forming at least one via (81) by filling at least one via hole (43), where at least one via (81) extends through the layer formed of the first dielectric material (42) and the third dielectric material (6) such that the formed superconducting unit (81, 201, 8) physically contacts the underlying first superconducting line structure (41).

[0032] The inventors have found that some superconducting materials that are practically preferable may be particularly difficult to deposit in via holes or trenches having a high aspect ratio. As used herein, the aspect ratio is the ratio of the height (e.g., of a via, via hole, wire, or trench) in a direction perpendicular to the upper surface of the superconducting line structure to the width (e.g., of a via, via hole, wire, or trench) in a direction parallel to the upper surface of the superconducting line structure. Thus, the superconducting line structure is preferably as narrow as possible so as to obtain a high density of interconnections in the superconducting interconnection structure, but it may be difficult to form using a damascene process. At the same time, the via preferably has a small aspect ratio, i.e., is preferably shallow, so that a high density of interconnections in the superconducting interconnection structure can be achieved. The inventors have found that by combining a metal etching type process for forming the superconducting line structure and a damascene type process for forming the via, good miniaturization of the superconducting interconnection structure can be achieved.

[0033] In an embodiment, the method of the present invention is for forming a superconducting interconnect structure in a post-process of manufacturing an integrated circuit.

[0034] The nature of the substrate is not important. The substrate is typically composed of a semiconductor wafer with or without a dielectric layer thereon. For example, it can consist of a bare silicon wafer or a silicon wafer having a silicon oxide layer thereon.

[0035] In some embodiments, the substrate can be composed of individual insulated devices. The upper surface of the substrate may include a dielectric surface including conductive or superconducting island portions for establishing connections to the individual insulated devices. In the method of the present invention, the first set of semiconductive line structures formed during step a. may form physical contact with one or more of these island portions. These physical contacts can become electrical contacts when the temperature of the semiconductive line structures drops below the critical temperature.

[0036] The substrate may also include existing vias connected to existing superconducting line structures. The upper surface of the substrate may include a dielectric surface including the upper surfaces of the conductive or superconducting vias. In the method of the present invention, the first set of semiconductive line structures formed during step a. may form physical contact with one or more of these existing vias.

[0037] The method of the present invention is adaptable to the formation of superconducting interconnections in most types of superconducting materials. For example, the first, second, and third superconducting materials can be independently selected from superconducting chemical elements (e.g., Al, Ti, Nb, ...) and superconducting compounds (e.g., MoN, Nb3Sn, NbTi, NbTiN, and NbN). A preferred superconducting material consists of Nb, a more preferred superconducting material consists of Nb and at least one of Ti and N, and the most preferred superconducting material consists of Nb, Ti, and N (e.g., NbTiN). In these last compounds, the atomic ratio N / (Nb + Ti) is preferably equal to 0.5, and the atomic ratio Nb / (Nb + Ti) is preferably typically from 0.65 to 0.84. These last compounds have particularly high critical temperatures. Preferably, the critical temperature of the first superconducting material is 10 K or higher. More preferably, it is 12 K or higher. Even more preferably, it is 14 K or higher. Even more preferably, it is 16 K or higher. For example, it can be from 16.5 K to 17.5 K.

[0038] In an embodiment, each superconducting layer used in the method may have a thickness independently selected within the range of 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm.

[0039] In a preferred embodiment, step a2. is performed by physical vapor deposition. Alternatively, atomic layer deposition or chemical vapor deposition can be used, but the present invention enables the use of physical vapor deposition, which is a technique that can be easily implemented. The inventors have also found that good control of the dimensions of vias and superconducting line structures can be achieved by physical vapor deposition when used in the present invention.

[0040] When step a3’ is performed, step a4. consists of removing a protective dielectric layer, a layer (22) of a first dielectric material, and a portion of the first superconducting layer (21), the portion extending from the lower surface of the first superconducting layer (21) to the upper surface of the protective dielectric layer, thereby forming a pattern consisting of a first set of line structures (4). The first set of line structures (4) is The first set of superconducting line structures (41), and aligned and overlapping above the first set of superconducting line structures (41), a first set of dielectric material line structures (42) having an upper surface (420), and a first set of protective dielectric line structures aligned and overlapping above the first set of dielectric material line structures (42) are included.

[0041] In an embodiment, step a4. of removing a part of the layer of the first dielectric material and the first superconducting layer may be performed by first forming a hard mask (e.g., a layer or a stack of layers) on the layer of the first dielectric material, then forming a photoresist pattern mask on the hard mask, then using the photoresist pattern mask as a mask to etch through the hard mask, thereby transferring the pattern of the photoresist pattern mask to the hard mask, and then using the hard mask as a mask to etch through the first dielectric layer and through the superconducting layer.

[0042] In an embodiment, the line structures of the first set of line structures have a rectangular cubic shape. In an embodiment, the line structures of the first set of superconducting line structures have a rectangular cubic shape. In an embodiment, the height of the superconducting line structure in the direction perpendicular to the upper surface of the superconducting line structure is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the width of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the length of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure and perpendicular to the width is at least 200 nm, preferably at least 500 nm. In this specification, the length is longer than the width. In an embodiment, the aspect ratio of the line structure, that is, the ratio of its height to its width, is 1 to 4.

[0043] In an embodiment, the sidewall of the superconducting line structure forms an angle of 85° to 93°, preferably 88° to 92°, more preferably 89° to 90° with the upper surface of the substrate. Typically, this angle is 90°.

[0044] In an embodiment, the line structure made of the first dielectric material of the first set has a rectangular cubic shape. In an embodiment, the height of the line structure made of the first dielectric material in the direction perpendicular to the upper surface of the line structure made of the first dielectric material is 1 to 50 nm, preferably 5 to 20 nm. In an embodiment, the width of the line structure made of the first dielectric material in the direction parallel to the upper surface of the line structure made of the first dielectric material is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the length of the line structure made of the first dielectric material in the direction parallel to the upper surface of the line structure made of the first dielectric material and perpendicular to the width is at least 200 nm, preferably at least 500 nm. In this specification, the length is longer than the width. In an embodiment, the width of the line structure made of the first dielectric material is within 2% of the width of the superconducting line structure, for example, within 1%, for example, the same. In an embodiment, the length of the line structure made of the first dielectric material is within 2% of the length of the superconducting line structure, for example, within 1%, for example, the same.

[0045] In an embodiment, the first set of protective dielectric line structures may have a rectangular cubic shape. In an embodiment, the height of the protective dielectric line structure in a direction perpendicular to the upper surface of the first dielectric material line structure may be 1 to 50 nm. In an embodiment, the width of the protective dielectric line structure in a direction parallel to the upper surface of the first dielectric material line structure is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the length of the protective dielectric line structure in a direction parallel to the upper surface of the first dielectric material line structure and perpendicular to the width is at least 200 nm, preferably at least 500 nm. In this specification, the length is longer than the width. In an embodiment, the width of the protective dielectric line structure is within 2% of the width of the superconducting line structure, for example, within 1%, for example, the same. In an embodiment, the length of the protective dielectric line structure is within 2% of the length of the superconducting line structure, for example, within 1%, for example, the same.

[0046] In an embodiment, the first set of line structures are parallel to each other. In an embodiment, the first set of line structures all have the same width, the same length, and the same height.

[0047] In an embodiment, the first set of line structures may have a pitch of 30 to 500 nm, for example, 100 to 400 nm.

[0048] In an embodiment, the first dielectric material may be selected from silicon nitride and silicon carbonitride, while the second dielectric material may be selected from silicon oxide and high-k oxides such as aluminum oxide and hafnium oxide. In an embodiment, the first dielectric material is silicon nitride and the second dielectric material is silicon oxide. Typically, the second dielectric material is the same as the material of the protective dielectric layer. In an embodiment, the first dielectric material is silicon nitride, the second dielectric material is silicon oxide, and the protective dielectric is silicon oxide. The advantage of these embodiments is that silicon nitride can be selectively etched with respect to silicon oxide.

[0049] When there is a protective dielectric line structure, step a6 stops when the protective dielectric line structure is removed.

[0050] In an embodiment, the layer formed of the third dielectric material has a thickness of, for example, 2 to 30 nm, preferably 1 to 50 nm.

[0051] Preferably, the third dielectric material is an oxide. For example, the third dielectric material may be selected from silicon oxide and high-k oxides such as hafnium oxide and aluminum oxide. For example, it may contain silicon dioxide, or for example, it may consist of silicon dioxide.

[0052] Typically, the patterned mask provided in step b includes a photoresist mask.

[0053] In an embodiment, the method includes, after step a7. and before step b., forming a hard mask layer (e.g., on top) on the first set of line structures, the second dielectric material, and the third dielectric material. In step b., a patterned mask is provided (e.g., on top) on the hard mask layer. In step b1., after step b. and before step c., the pattern of the patterned mask is transferred to the hard mask layer. In step c., transferring the pattern of the patterned mask to the layer formed of the first dielectric material and the third dielectric material includes transferring the pattern from the patterned hard mask layer to the layer formed of the third dielectric material and the first dielectric material. Step d. further includes removing the patterned hard mask layer. In these embodiments, the perforated surface is exposed only after removing both the patterned mask and the patterned hard mask layer. The removal of the patterned mask in step d. may be performed after step b1. and before step c. The removal of the patterned hard mask layer in step d. may be performed after step c. and before step e. Preferably, the transfer of the pattern of the patterned mask to the hard mask layer is performed by selectively etching the hard mask layer with respect to the third dielectric material using the patterned mask as a mask. The fact that the third dielectric material can function as an etch stop layer is an advantage of these embodiments.

[0054] Any hard mask layer / multilayer is suitable as long as it can be selectively removed with respect to the protective dielectric layer if present, or with respect to the first dielectric material if the protective dielectric layer is not present.

[0055] In some embodiments, the hard mask may include one or more layers selected from amorphous carbon, spin-on carbon (SOC), spin-on glass (SOG), and spin-on carbon (SiOC).

[0056] In some embodiments, the hard mask can be a thick (15 - 30 nm) silicon oxide layer that replaces the (thinner than normal) protective dielectric layer.

[0057] In embodiments, in step c., the transfer includes selectively etching the first dielectric material with respect to the second dielectric material. The advantage of these embodiments is that self - alignment of the via holes on the underlying superconducting line structure can be achieved.

[0058] In embodiments, the perforated surface is the upper surface of the third dielectric material obtained after step d.

[0059] In embodiments, step e. may include depositing a second superconducting layer made of a single superconducting material having a critical temperature within 1 K of the first critical temperature on the perforated surface so as to fill at least one via hole extending through the layer formed of the first dielectric material and the third dielectric material and such that the deposited second superconducting layer is in electrical contact with the underlying first set of superconducting line structures. Step f. is performed immediately after step e. These embodiments are particularly advantageous when the density of the via holes is less than 5%. This density is calculated based on the total upper surface composed of the upper surface of the second dielectric material and the upper surface of the first set of line structures coplanar therewith. In other words, it is the portion of the total upper surface occupied by the via holes. This is calculated by dividing the upper surface occupied by the via holes by the total upper surface coplanar therewith. These embodiments are also particularly advantageous when no subsequent entities (described later), and thus no further vias and no further sets of superconducting line structures, are provided. In fact, as the number of non - planar layers increases in these embodiments, the non - planarity increases to an unacceptable level.

[0060] The advantage of these embodiments is that for forming at least one via, the superconducting material layer deposited in step e. can be used to form a second set of superconducting line structures, thereby saving superconducting material and reducing the number of steps.

[0061] Preferably, the first superconducting layer and the second superconducting layer are made of the same material.

[0062] In different embodiments, step e. comprises: e1. forming a first portion of the superconducting unit by depositing a second superconducting layer made of a single superconducting material having a critical temperature within 1 K of the first critical temperature on the perforated surface so as to form at least one via by filling at least one via hole, wherein at least one via extends through a first dielectric material and through a layer formed from a third dielectric material such that the formed second superconducting layer is in electrical contact with a first set of underlying superconducting line structures; e2. planarizing the deposited second superconducting layer so as to remove the upper portion of the second superconducting layer without removing at least one via; and e3. forming a second portion of the superconducting unit by depositing a third superconducting layer made of a single superconducting material having a critical temperature within 1 K of the first critical temperature on the planarized second superconducting layer.

[0063] In an embodiment, the removed upper portion is such that the upper surface of the third dielectric layer is exposed. In such an embodiment, all of the superconducting unit except for the vias is removed.

[0064] In other embodiments, the removed upper portion is such that the third dielectric layer remains covered by the lower portion of the second superconducting layer. In such an embodiment, the thickness of the upper portion is at least equal to the depth of the cavity.

[0065] Typically, the upper surface of the superconducting unit formed in step e. may include a cavity above the via, and as a result, the upper surface of the superconducting unit may not be flat. This may be a problem, for example, when forming a plurality of superconducting line structures and vias alternately stacked, because the cavities overlapping each other may reinforce each other. Therefore, preferably, the superconducting unit has a flat upper surface. By first planarizing the deposited second superconducting layer and then depositing the third superconducting layer on the planarized superconducting material layer, the resulting superconducting unit does not include these cavities.

[0066] In an embodiment, step e2. includes using chemical mechanical polishing and / or etching. In an embodiment, the chemical mechanical polishing is selectively performed on the superconducting material with respect to the third dielectric material. As a result, all the superconducting materials extending above the third dielectric material may be removed, and the upper surface of at least one via and the upper surface of the third dielectric material may be coplanar.

[0067] In an embodiment, the materials for forming the first set of superconducting line structures and the superconducting unit are independently selected from MoN, Nb3Sn, NbTi, Nb, NbTiN, and NbN. Preferably, the materials for forming the first set of superconducting line structures and the superconducting unit are the same. The inventors have found that although these materials have good superconducting properties, they may be particularly difficult to deposit in via holes or trenches having a high aspect ratio.

[0068] In an embodiment, step e. of forming the superconducting unit may be performed by physical vapor deposition.

[0069] Preferably, the first superconducting layer, the second superconducting layer, and the third superconducting layer are made of the same material.

[0070] In an embodiment, at least one via hole (and at least one via) in the first dielectric material and in the layer formed of the third dielectric material has an aspect ratio of at most 0.5. The aspect ratio is the ratio of the height of the via hole (and via) in the direction perpendicular to the upper surface of the superconducting line structure to the width of the via hole (or via) in the direction parallel to the upper surface of the superconducting line structure. In an embodiment, the via hole (or via) may have an aspect ratio of 0.1 to 0.5, for example 0.10 to 0.40, more preferably 0.15 to 0.35, and still more preferably 0.20 to 0.30. In an embodiment, the height of the via hole (or via) is 1 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 25 nm. In an embodiment, the width of the via hole (or via) is 2 nm to 200 nm, preferably 20 nm to 100 nm, and more preferably 30 nm to 70 nm. In an embodiment, the length of the via hole (or via) is 5 nm to 200 nm, preferably 10 nm to 100 nm, and more preferably 30 nm to 70 nm in the direction parallel to the upper surface of the superconducting line structure and perpendicular to the width. In an embodiment, the length of the via hole (or via) is 0.5 times to 2 times, preferably 0.9 times to 1.1 times the width of the via hole (or via).

[0071] In an embodiment, the method includes, after step e., step f. forming a layer of a fourth dielectric material over the superconducting unit, and step g. removing a portion of the layer of the fourth dielectric material and the superconducting unit so as to form a pattern including a second set of line structures including a second set of superconducting line structures and a second set of line structures made of the fourth dielectric material and overlapping and aligned with the first set of superconducting line structures, thereby providing a second entity over the superconducting unit, thereby providing the second entity over the first entity.

[0072] In an embodiment, the fourth dielectric material may be the same as the first dielectric material.

[0073] The second set of superconducting line structures forms a non-zero angle with the first set of the first set of superconducting line structures. Preferably, the angle is 80° to 100°, preferably 90°, with the first set.

[0074] The dimensions of the lines of the first set of superconducting line structures may be the same as or different from the dimensions of the lines of the second set of superconducting line structures. The dimensions of the lines of the second set of superconducting line structures may be as defined for the lines of the first set of superconducting line structures.

[0075] In an embodiment, the line structure of the second set of line structures has a rectangular cubic shape. In an embodiment, the line structure of the second set of superconducting line structures has a rectangular cubic shape. In an embodiment, the height of the superconducting line structure in the direction perpendicular to the upper surface of the superconducting line structure is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the width of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In an embodiment, the length of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure and perpendicular to the width is at least 200 nm, preferably at least 500 nm. In this specification, the length is longer than the width. In an embodiment, the aspect ratio of the line structure, that is, the ratio of the height to the width, is 1 to 4.

[0076] In an embodiment, the side wall of the superconducting line structure forms an angle of 85° to 93°, preferably 88° to 90°, more preferably 89° to 90° with the upper surface of the substrate. Typically, this angle is 90°.

[0077] In an embodiment, the second set of line structures are parallel to each other. In an embodiment, the second set of line structures all have the same width, the same length, and the same height.

[0078] In an embodiment, the second set of line structures may have a pitch of 30 to 500 nm, for example, 100 to 400 nm. The pitch of the second set of superconducting line structures may be the same as or different from the pitch of the first set of superconducting line structures.

[0079] In an embodiment, step g. of removing a portion of the fourth dielectric material layer and the superconducting unit may be performed by first forming a hard mask (e.g., a layer or stack of layers) on the fourth dielectric material layer, then forming a photoresist pattern mask on the hard mask, then etching through the hard mask using the photoresist pattern mask as a mask, thereby transferring the pattern of the photoresist pattern mask to the hard mask, and then etching through the fourth dielectric layer and the superconducting unit using the hard mask as a mask.

[0080] In an embodiment, by repeating steps b. to g., a subsequent entity may be provided after step g., thereby forming additional vias and an additional set of superconducting line structures. The additional sets of superconducting line structures form a non-zero angle with each other. Preferably, the additional sets of superconducting line structures form an angle of 80° to 100°, preferably 90°, with each other.

[0081] In an embodiment, the method includes the following steps h to k after step a and before step b, or after step e and before step f. In step h, if present, a third patterned mask is provided on the first entity. The pattern includes at least one additional opening overlapping a superconducting line structure underlying a first set of superconducting line structures to form at least one additional via hole in a layer formed of a first dielectric material and a third dielectric material. In step i, the pattern of the third pattern mask is transferred to the layer formed of the first dielectric material and the third dielectric material to form at least one additional via hole extending through the layer formed of the first dielectric material and the third dielectric material and exposing at least a part of the underlying superconducting line structure. In step j, the third pattern mask is removed to expose the second perforated surface. In step k, a resistive material is deposited on the second perforated surface. The resistive material has a resistivity of at least 100 μΩ·cm at a temperature of 1 K so as to fill at least one additional via hole extending through the layer formed of the first dielectric material and the third dielectric material and so that the deposited resistive material contacts the underlying superconducting line structure. In some embodiments, the resistor may not have a critical temperature or may have a critical temperature below 1 K. An advantage of an embodiment of the present invention is that a superconducting interconnection structure composed of a resistor can be formed. The resistor, if present, may connect the superconducting line structure of the first set of superconducting line structures to the superconducting line structure of the second set of superconducting line structures. In an embodiment, the resistive material consists of the same chemical element as the first set of superconducting line structures. The chemical composition of the resistive material is different from the chemical composition of the first set of superconducting line structures. In other words, the resistive material is composed of the same chemical elements as the superconducting line structure, but the relative amounts of the chemical elements are different between the resistive material and the first set of superconducting line structures. By changing the relative amounts of different chemical elements, the critical temperature of the material can be adjusted so that the resistive material has a resistivity of at least 100 μΩ·cm at a temperature of 1 K.The advantages of these embodiments are that deposition materials and techniques similar to those for forming resistors can be used for forming the superconducting vias.

[0082] Most preferably, all superconducting layers or units, and all resistors formed during the method, are formed by physical vapor deposition (e.g., DC magnetron sputtering).

[0083] Any feature of any embodiment of the first aspect may be separately described so as to correspond to any embodiment of the second aspect of the invention.

[0084] In a second aspect, the invention relates to a superconducting interconnect structure that can be formed by the method according to any of the preceding claims, the interconnect structure including a first entity (44), the first entity (44) being i. a first set of line structures (4) having an upper surface (420), the first set of line structures (4) including - a first set of superconducting line structures (41), and - a first set of line structures (42) made of a first dielectric material that are aligned and overlap above the first set of superconducting line structures (41) and include the upper surface (420), and including the line structures (4); ii. a second dielectric material (50) different from the first dielectric material (42), the second dielectric material (50) having an upper surface (51) coplanar with the upper surface of the first set of line structures (4), the second dielectric material (50) being between the first set of line structures (4); iii. a third dielectric material (6) overlapping the first set of line structures (4) and the second dielectric material (50), and including A via (81) extends through a layer formed of the first dielectric material (22) and the third dielectric material (6), and the via (81) includes a superconducting material that physically contacts the underlying superconducting line structure (21). Any feature of any embodiment of the second aspect may be separately described so as to correspond to any embodiment of the first aspect of the invention.

[0085] The features of the second aspect are as described corresponding to the first aspect.

[0086] For example, the superconducting line structure may be as follows. - At least one via (81) in the layer formed of the first dielectric material (22) and the third dielectric material (6) may have an aspect ratio of at most 0.5, for example, 0.10 to 0.40, more preferably 0.15 to 0.35, and even more preferably 0.20 to 0.30. - The height of the superconducting line structure in the direction perpendicular to the upper surface of the superconducting line structure may be 20 to 500 nm, preferably 50 to 200 nm. - The width of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure may be 20 to 500 nm, preferably 50 to 200 nm. - The length of the superconducting line structure in the direction parallel to the upper surface of the superconducting line structure and perpendicular to the width is at least 200 nm, preferably at least 500 nm. - The aspect ratio of the superconducting line structure, that is, the ratio of the height to the width, is 1 to 3. And / or - The side wall of the superconducting line structure forms an angle of 85° to 93°, preferably 88° to 90°, more preferably 89° to 90° with the upper surface of the substrate. Typically, this angle is 90°.

[0087] Hereinafter, the present invention will be described by detailed description of some embodiments of the present invention. It is obvious that other embodiments of the present invention can be configured according to the knowledge of those skilled in the art without departing from the technical teachings of the present invention, and the present invention is limited only by the language of the appended claims.

[0088] Example: Formation of superconducting interconnection structure Please refer to FIG. 1. The substrate (1) includes, in this example, a silicon wafer (11) covered by an insulator layer (12), such as a silicon oxide layer. A superconducting layer (21), such as NbTiN, is formed on the substrate 1, and this may be deposited by any technique suitable for depositing superconducting materials. Preferably, physical vapor deposition is used for forming the superconducting layer (21), because this technique is also very suitable for forming vias (described later) and may lead to simplification of the manufacture of superconducting interconnection structures. Next, a layer of a first dielectric material (22), such as silicon nitride, is formed on the superconducting layer (21). There may be a thin (1 to 10 nm, such as 5 nm) protective silicon oxide layer (not shown) on the silicon nitride.

[0089] In this example, a patterning mask (31, 32, 33) including an ashing-removable hard mask (31) is formed on a layer of a first dielectric material (22). The ashing-removable hard mask (31) is a hard mask that can be removed by an oxygen plasma. In some cases, complete removal of the hard mask is achieved by performing an additional wet or dry etching process following ashing, for example, when the ashing-removable hard mask leaves a residue that cannot be removed by ashing alone. The patterning mask (31, 32, 33) further includes a silicon oxycarbide layer (32) covering the ashing-removable hard mask (31). The patterning mask further includes a patterned photoresist (33) overlapping the silicon oxycarbide layer (32). The pattern of the patterned photoresist (33) including a set of line structures is first transferred (not shown) to the ashing-removable hard mask (31) and the silicon oxycarbide layer (32) using an etching that selectively etches the ashing-removable hard mask (31) and the silicon oxycarbide layer (32) with respect to the patterned photoresist (33). Subsequently, the patterned photoresist (33) is removed (not shown). An etching is performed to selectively etch the layer of the first dielectric material (22) and the superconducting layer (21) (not shown) with respect to the ashing-removable hard mask (31) and the silicon oxycarbide layer (32) so as to transfer the pattern from the ashing-removable hard mask (31) and the silicon oxycarbide layer (32) to the layer of the first dielectric material (22) and the superconducting layer (21). Thereby, a part of the layer of the first dielectric material (22) and the superconducting layer (21) extending from the lower surface of the superconducting layer (21) to the upper surface of the layer of the first dielectric material (22) is removed (not shown). Finally, the ashing-removable hard mask (31) and the silicon oxycarbide layer (32) are removed (not shown).

[0090] Refer to FIG. 2. By transferring a pattern to the first dielectric material and the superconducting layer, a first set of line structures (4) is formed on the substrate (1). The first set of line structures (4) includes a first set of superconducting line structures (41). Further, the first set of line structures (4) includes a first set of line structures made of the first dielectric material that are aligned and overlap above the first set of superconducting line structures (41). The first set of line structures (4) includes the upper surface (420), which is the upper surface (420) of the first set of line structures (42) made of the first dielectric material.

[0091] Refer to FIG. 3. A second dielectric material (50) different from the first dielectric material is formed on, for example, above and between the first set of line structures (4). The second dielectric material (50) may be, for example, silicon oxide.

[0092] Refer to FIG. 4. The second dielectric material (50) is planarized such that the upper surface (51) of the second dielectric material (50) is coplanar with the upper surface (420) of the first set of line structures (42) made of the first dielectric material. For example, chemical mechanical polishing may be used, and the polishing is selective with respect to the first dielectric material (42) towards the second dielectric material (50).

[0093] Refer to FIG. 5. A layer formed of a third dielectric material (6) is formed on the first set of line structures (4), in this example, above the upper surface of the first set of line structures (42) made of the first dielectric material, for example, on the second dielectric material (50), for example, on the second dielectric material (50). Thereby, a first entity is formed that includes the first set of line structures (4), the second dielectric material (50) between the first set of line structures (4), and the layer formed of the third dielectric material (6).

[0094] Please refer to FIG. 6. To form vias in the layer formed of the third dielectric material (6) and the first set of line structures (42) made of the first dielectric material, first, a spin-on carbon layer (71) is deposited, for example, on the layer formed of the third dielectric material (6). Next, a spin-on glass layer (72) is formed, for example, on the spin-on carbon layer (71). In this embodiment, in particular, the spin-on carbon and the spin-on glass are described, but different masks, for example, hard masks, can also be used. A mask selectively etchable with respect to the third dielectric material (6) may be used so that the third dielectric material (6) functions as an etch stop layer. Finally, a photoresist mask is deposited, for example, on the spin-on glass layer (72), and then patterned to form a patterned photoresist mask (73). The patterned photoresist mask (73) includes at least one opening (730) (six openings in this example) overlapping with the superconducting line structure in the lower layer of the first set of superconducting line structures (41). Each opening (730) is for forming via holes in the first dielectric material (42) and the third dielectric material (6). The pattern of the patterned photoresist mask (73) is transferred to the spin-on glass layer (72) and the spin-on carbon layer (71). In this example, etching that selectively etches the spin-on glass layer (72) and the spin-on carbon layer (71) with respect to the patterned photoresist mask (73) and the third dielectric material (6) is used. Thus, the third dielectric material (6) functions as an etch stop layer. That is, the etching of the spin-on glass layer (72) and the spin-on carbon layer (71) may stop at the third dielectric material (6). In this example, the patterned photoresist mask (73) and the patterned spin-on glass layer (72) are then removed.

[0095] Please refer to FIG. 7. The pattern of the patterned spin-on carbon layer (71) over the first entity (44) is transferred to the layer formed of the third dielectric material (6) and the first dielectric material (42) so as to form via holes (43) extending through the layer formed of the third dielectric material (6) and the first dielectric material (42). Thereby, a part of the underlying superconducting line structure (41) is exposed. Preferably, etching that selectively etches the first dielectric material (42), for example silicon nitride, with respect to the second dielectric material (50), for example silicon oxide, is used. Thereby, self-alignment of the via holes (43) over the superconducting line structure (41) may be achieved.

[0096] Please refer to FIG. 8. In this example, the patterned spin-on carbon layer (71) is selectively removed with respect to the third dielectric material (6) so that the perforated surface, which is the upper surface (60) of the third dielectric material (6) perforated by the via holes (43), is exposed.

[0097] Please refer to FIG. 9. The superconducting material layer (8) is formed over the perforated surface, in this example over the upper surface of the third dielectric material (6), so as to form vias (81) by filling at least one via hole. The superconducting material (8) is deposited so as to be in electrical contact with, for example physically contact, the exposed underlying superconducting line structure (41).

[0098] In the case of the superconducting material (8) such as MoN, Nb3Sn, NbTi, Nb, NbTiN, and NbN, it may have pits (82) overlapping the vias (81) so that a non-planar superconducting layer can be formed over the perforated surface.

[0099] Refer to FIG. 10. In order to provide a flat superconducting layer on the perforated surface, the superconducting material layer filling at least one via hole, i.e., the superconducting material layer may be planarized such that the upper part of the superconducting material layer is removed without removing the part of the via (81). In this example, all of the deposited superconducting material extending above the perforated surface (60) is removed such that the upper surface of the via (81) is coplanar with the upper surface (60) of the third dielectric material (6). For example, chemical mechanical polishing may be performed to selectively polish the deposited superconducting material with respect to the third dielectric material (6) such that polishing stops at the third dielectric material (6). Alternatively, etching may also be used. Also, the removal of the superconducting material layer may be limited to the upper part of the superconducting material layer. As a result, a planar superconducting material layer may be formed on the perforated surface.

[0100] Please refer to FIG. 11. To form the second entity, in this example, a stack similar to that deposited on the substrate of FIG. 1 is deposited on the perforated surface, i.e., the upper surface of the third dielectric material (6). For this purpose, first, if it does not exist (or is not thick enough as in this example), an additional superconducting material layer (201) is deposited so as to physically contact the via (81). The superconducting material layer (201) preferably includes the same superconducting material as the via (81) and the superconducting line structure (41). A layer of a fourth dielectric material (202), which may be the same as the first dielectric material, is deposited on top of the additional superconducting material layer (201), for example, on the superconducting material layer (201). In this example, a patterning mask including an ashing - able hard mask (301) is formed on the layer of the fourth dielectric material (202). The patterning mask further includes a silicon oxycarbide layer (302) covering the ashing - able hard mask (301). The patterning mask further includes a patterned photoresist (303) overlapping on the silicon oxycarbide layer (32). The patterned photoresist (303) includes a line structure for forming a second set of line structures, which includes a second set of superconducting line structures formed of an additional superconducting material layer (201) and a second set of line structures made of the fourth dielectric material (202). In the present specification, the line structure of the patterned photoresist (303) is oriented such that the second set of line structures is oriented at an angle, for example, perpendicularly, with respect to the first set of line structures. Steps similar to those described above for forming the first entity may be used to form the second entity.

[0101] In the present specification, preferred embodiments, specific structures and configurations, and materials of the device according to the present invention have been described. However, it should be understood that various changes or modifications may be made in form and detail without departing from the scope of the present invention. Steps may be added or deleted with respect to the methods described within the scope of the present invention.

Claims

1. A method for forming a superconducting interconnect structure for an integrated circuit, a. On the substrate (1), a1. Provide a substrate (1), a2. A first superconducting layer (21) of a first superconducting material having a first critical temperature is formed on the substrate (1). a3. A layer of the first dielectric material (22) is formed on the first superconducting layer (21). a4. The layer of the first dielectric material (22) and a portion of the first superconducting layer (21) are removed, wherein the portion extends from the lower surface of the first superconducting layer (21) to the upper surface of the first dielectric material (22) to form a pattern including a first set of line structures (4) having an upper surface (420), the first set of line structures (4) including a first set of superconducting line structures (41) and a first set of line structures (42) made of the first dielectric material that are aligned with and overlap the first set of superconducting line structures (41) and include an upper surface (420). a5. A second dielectric material (50) different from the first dielectric material is formed on and between the first set of line structures (4), a6. The second dielectric material (50) is planarized so that the upper surface of the second dielectric material (51) is coplanar with the upper surface (420) of the first set of line structures (4), and thereafter, a7. A layer formed of the third dielectric material (6) is formed on the first set of line structures (4) and the second dielectric material (50). By doing so, the first entity (44) is formed. b. Providing a patterned mask (73) on the first entity, wherein the pattern includes at least one opening (730) that overlaps with the superconducting line structure of the lower layer of the first set of superconducting line structures (41) in order to form at least one via hole (43) in the layer formed of the first dielectric material (42) and the third dielectric material (6), c. Transferring the pattern of the patterning mask (73) to the layer formed of the first dielectric material (42) and the third dielectric material (6) such that at least one via hole (43) extends through the layer formed of the first dielectric material (42) and the third dielectric material (6), thereby exposing a portion of the underlying superconducting line structure (41), d. Removing the patterned mask (73) to expose the perforated surface (60), and e. Forming one or more superconducting units (81, 201, 8) made of superconducting material, each having a critical temperature within 1 K of the first critical temperature, on the perforated surface (60), thereby forming at least one via (81) by filling at least one via hole (43), wherein the at least one via (81) extends through the layer formed of the first dielectric material (42) and the third dielectric material (6) such that the formed superconducting units (81, 201, 8) are in physical contact with the first set of superconducting line structures (41) of the underlying layer. Methods that include...

2. After step a7 and before step b, a7': Further comprising forming hard mask layers (71, 72) on the first set of line structures (41), the second dielectric material (50), and the third dielectric material (6), In step b, the patterned mask (73) is provided on the hard mask layers (71, 72). In step b1, after step b. and before step c., the pattern of the patterned mask (73) is transferred to the hard mask layers (71, 72). In step c, transferring the pattern of the patterned mask (73) to the layer formed of the first dielectric material (42) and the third dielectric material (6) includes transferring the pattern from the patterned hard mask layers (71, 72) to the layer formed of the third dielectric material (6) and the first dielectric material (42), Step d further includes removing the patterned hard mask layers (71, 72). The method according to claim 1.

3. Step f. Form a fourth dielectric material (202) on the superconducting unit (81, 201, 8). Step g. Remove a portion of the layers of the fourth dielectric material (202) and the superconducting units (81, 201, 8) to form a pattern comprising a second set of line structures, which includes a second set of line structures made of the fourth dielectric material and aligned with and overlapping the second set of superconducting line structures, thereby forming a second entity on the first entity. The second entity is provided on the superconducting unit (81, 201, 8) after step e., including The method according to claim 1 or 2.

4. Step e consists of depositing the second superconducting layer (8) made of a single second superconducting material having a critical temperature within 1 K of the first critical temperature on the perforated surface (60) such that it fills at least one via hole (43) extending through the layer formed of the first dielectric material (42) and the third dielectric material (6), and the deposited second superconducting layer (8) is in physical contact with the underlying first set of superconducting line structures (41), and step f is performed immediately after step e. The method according to claim 3.

5. Step e. However, e1. Forming a first portion (81) of the superconducting unit (81, 201) by depositing a second superconducting layer (8) made of a single superconducting material having a critical temperature within 1 K of the first critical temperature onto the perforated surface (60) such that at least one via (81) is formed by filling the at least one via hole (43), wherein the at least one via (81) extends through the first dielectric material (22) and through the layer formed of the third dielectric material (6), and the second superconducting layer (8) formed thereby is in physical contact with the first set of superconducting line structures (41) in the underlying layer. e2. Planarizing the deposited second superconducting layer (8) such that the upper part of the second superconducting layer (8) is removed without removing the at least one via (81), and e3. Forming the second portion (201) of the superconducting unit (81, 201) by depositing a single third superconducting layer (201) made of a third superconducting material having a critical temperature within 1 K of the first critical temperature on the planarized second superconducting layer (8). The method according to claim 1 or 2, including the method according to claim 1 or 2.

6. Step e2 includes using chemical mechanical polishing and / or etching. The method according to claim 5.

7. The material forming the first set of superconducting line structures (41) and the superconducting units (81, 201, 8) is MoN, Nb ３ Independently selected from Sn, NbTi, Nb, NbTiN, and NbN, The method according to claim 1 or 2.

8. The at least one via hole (43) in the layer formed of the first dielectric material (22) and the third dielectric material (6) has an aspect ratio of at most 0.

5. The method according to claim 1 or 2.

9. If it exists following step a and before step b, or after step e and before step f, h. Providing a third patterning mask on the first entity, wherein the pattern includes at least one further opening that overlaps with the underlying superconducting line structure (21) of the first set of superconducting line structures (21) in order to form at least one further via hole in the layer formed of the first dielectric material (22) and the third dielectric material (6), i. Transferring the pattern of the third patterning mask to the layer formed of the first dielectric material and the third dielectric material (6) such that at least one further via hole extends through the first dielectric material and the layer formed of the third dielectric material (6) and a portion of the superconducting line structure (21) of the lower layer is exposed. j. Remove the third patterned mask so as to expose the second perforated surface, and k. Depositing a resistive material, wherein the resistive material has a resistivity of at least 100 μΩ·cm at a temperature of 1 K, on ​​the second perforated surface, such that it fills at least one further via hole extending through the layer formed of the first dielectric material (22) and the third dielectric material (6), and the deposited resistive material is in physical contact with the underlying superconducting line structure (21). The method according to claim 1 or 2.

10. The resistive material consists of the same chemical elements as the superconducting line structure (21), and its chemical composition is different from that of the first superconducting material. The method according to claim 9.

11. The first dielectric material (22) is silicon nitride, and the second dielectric material (50) is silicon oxide. The method according to claim 1 or 2.

12. Step e includes the step of depositing the superconducting material layer (8) by physical vapor deposition, The method according to claim 1 or 2.

13. Step a2 is carried out by physical vapor deposition. The method according to claim 12.

14. A superconducting interconnect structure that can be formed by the method of claim 1, the interconnect structure comprising a first entity (44), the first entity being i. A first set of line structures (4) having an upper surface (420), - The first set of superconducting line structures (41), - Aligned with and overlapping the first set of superconducting line structures (41), and including the upper surface (420), the first set of first dielectric material line structures (42) The first set of line structures (4) includes, ii. A second dielectric material (50) between the first set of line structures (4), which is different from the first dielectric material (42) and has a coplanar upper surface (51) with the upper surface of the first set of line structures (4), iii. The third dielectric material (6) covering the first set of line structure (4) and the second dielectric material (50) Includes, The via (81) extends through the layer formed of the first dielectric material (22) and the third dielectric material (6), and the via (81) includes a superconducting material that is in physical contact with the superconducting line structure (21) of the lower layer. Superconducting interconnect structure.

15. At least one via (81) between the first dielectric material (22) and the layer formed of the third dielectric material (6) has an aspect ratio of up to 0.

5. The superconducting interconnect structure according to claim 14.

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