Silicon carbide device and method for manufacturing the same

Abstract

The silicon carbide device includes an n-type silicon carbide substrate (21), an n-type silicon carbide layer (22) formed on the n-type silicon carbide substrate (21), a plurality of gate trenches (31) formed in the n-type silicon carbide layer (22), and p-type body regions (23) formed on both sides of each gate trench (31), the p-type body region (23) including a first p-type body region (23a) and a second p-type body region (23b) located between the first p-type body region (23a) and the adjacent gate trench (31), n-type source regions (25) and current channel regions (10) formed in each p-type body region (23), and two gate electrodes (27) formed in each gate trench (31), the two gate electrodes (27) being respectively located on two sidewalls of each gate trench (31) and extending to above the horizontal channel regions (10a) on the corresponding sides respectively. The current channel region (10) includes a horizontal channel region (10a) and a vertical channel region (10b). The gate electrode (27) is insulated and separated from the n-type silicon carbide layer (22) through a gate electrode insulating layer (26) between the gate electrode (27) and the n-type silicon carbide layer (22), and the gate electrode (27) is provided to control the on and off of the current channel region (10) by a gate electrode voltage.

Description

Technical Field

[0001] This application belongs to the technical field of silicon carbide devices, and relates to, for example, silicon carbide devices and manufacturing methods thereof. This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on June 16, 2023, with an application number of 202310715907.5, and all the contents of the above application are incorporated herein by reference.

Background Art

[0002] As one of the representatives of the third-generation wide-bandgap semiconductor materials, silicon carbide materials have characteristics such as a large bandgap, a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation drift velocity, and are expected to have a wide range of applications in the fields of high-power, high-temperature, and high-frequency power electronics. The mobility of planar silicon carbide devices is low, and the on-resistance of silicon carbide devices increases due to the resistance of parasitic junction field-effect transistors (JFETs), resulting in a large chip area. Trench-type silicon carbide devices eliminate the JFET resistance parasitic in planar silicon carbide devices, reduce the cell size, and significantly improve the current density. Therefore, trench-type silicon carbide devices have gradually replaced planar silicon carbide devices and become the mainstream. Silicon carbide devices usually use silicon dioxide as the gate dielectric layer material. However, since the dielectric constant of silicon carbide is about 2.5 times that of silicon dioxide, when the silicon carbide device is in the off state, the gate dielectric layer is subjected to about 2.5 times the drift layer electric field. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, and the gate dielectric layer at the bottom corner of the gate trench is easily broken before the avalanche breakdown of the silicon carbide device occurs, which affects the breakdown voltage of the silicon carbide device and the reliability and stability of the device.

Summary of the Invention

Problems to be Solved by the Invention

[0003] This application provides a silicon carbide device and a method for manufacturing the same, which improve the breakdown voltage performance of the silicon carbide device and reduce the on-resistance of the silicon carbide device.

Means for Solving the Problem

[0004] An embodiment of this application is an n-type silicon carbide substrate, an n-type silicon carbide layer formed on the n-type silicon carbide substrate, a plurality of gate trenches formed in the n-type silicon carbide layer, p-type body regions respectively formed on both sides of each gate trench, n-type source regions and current channel regions formed in each p-type body region, two gate electrodes formed in each gate trench, the two gate electrodes being respectively located on two sidewalls of each gate trench and extending to above the horizontal channel regions on their respective corresponding sides, each p-type body region on each side includes a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, the depth of the second p-type body region is smaller than the depth of the first p-type body region, the depth of the gate trench is smaller than the depth of the first p-type body region and larger than the depth of the second p-type body region, the current channel region includes a horizontal channel region and a vertical channel region, the gate electrode is insulated and separated from the n-type silicon carbide layer through a gate electrode insulating layer between the gate electrode and the n-type silicon carbide layer, and the gate electrode is provided to control the on and off of the current channel region by a gate electrode voltage. A silicon carbide device is provided.

[0005] Preferably, the thickness of the gate electrode insulating layer at the bottom of the gate trench is larger than the thickness of the gate electrode insulating layer on the sidewall of the gate trench.

[0006] Preferably, the n-type source region is located within a first p-type body region in the p-type body region where it is located, and the horizontal channel region is located within a second p-type body region in the p-type body region where it is located.

[0007] Preferably, the n-type source region is located within a first p-type body region in the p-type body region where it is located, the horizontal channel region is located within a second p-type body region in the p-type body region where it is located, and extends into the first p-type body region in the p-type body region where it is located.

[0008] Preferably, the n-type source region is located within a first p-type body region in the p-type body region where it is located, extends into the second p-type body region in the p-type body region where it is located, and the horizontal channel region is located within the second p-type body region in the p-type body region where it is located.

[0009] Preferably, the silicon carbide device further includes a p-type body contact region located within each of the first p-type body regions.

[0010] Preferably, the silicon carbide device further includes an n-type doped region located within the n-type silicon carbide layer and below each gate trench, and each n-type doped region overlaps a gap between two gate electrodes within its corresponding gate trench.

[0011] Embodiments of the present application forming an n-type silicon carbide layer on an n-type silicon carbide substrate; forming a first insulating layer on the n-type silicon carbide layer; etching the first insulating layer to form a mask pattern; performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions within the n-type silicon carbide layer; Using the first insulating layer as a mask, perform p-type ion implantation that is inclined toward one side of each first p-type body region, and form a second p-type body region located on one side of each first p-type body region within the n-type silicon carbide layer. Using the first insulating layer as a mask, perform p-type ion implantation that is inclined toward the other side of each first p-type body region, and form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer. The plurality of first p-type body regions and the plurality of second p-type body regions form the plurality of p-type body regions of the silicon carbide device. Etch and remove the first insulating layer, perform n-type ion implantation, and form n-type source regions within each p-type body region. Etch the n-type silicon carbide layer to form a plurality of gate trenches within the n-type silicon carbide layer. Form a gate electrode insulating layer on the surfaces of the bottom and sidewalls within each gate trench and on the surface of the n-type silicon carbide layer. Form a first conductive layer on the surface of the gate electrode insulating layer so as to form two gate electrodes within each gate trench, and etch the first conductive layer. The two gate electrodes are respectively located on two sidewalls of each gate trench and extend respectively up to the horizontal channel regions on their respective corresponding sides. Further provide a method for manufacturing a silicon carbide device.

[0012] Preferably, the method for manufacturing a silicon carbide device further includes performing n-type ion implantation into the n-type silicon carbide layer through the gap between the two gate electrodes within each gate trench to form an n-type doped region located below each gate trench within the n-type silicon carbide layer.

[0013] Preferably, the method for manufacturing a silicon carbide device further includes performing p-type ion implantation and forming p-type body contact regions within each p-type body region before forming n-type source regions within each p-type body region.

Brief Description of the Drawings

[0014] The following is a brief description of the drawings necessary for explaining the embodiments. In the drawings, for convenience of explanation, the thicknesses of the layers and regions are enlarged, and the sizes shown do not represent actual dimensions. The drawings are schematic diagrams of idealized embodiments of the present application, and the embodiments shown in the present application are not limited to the specific shapes of the regions shown in the drawings, and should include the obtained shapes such as variations due to manufacturing. For example, curves obtained by etching usually have the characteristics of being curved or rounded, but in the embodiments of the present application, they are all represented as rectangles. The representations in the drawings are schematic, but this does not limit the scope of the present application.

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Mode for Carrying Out the Invention

[0015] FIG. 1 is a schematic cross-sectional view of a silicon carbide device provided according to an embodiment of the present application. As shown in FIG. 1, the silicon carbide device includes an n-type silicon carbide substrate 21, an n-type silicon carbide layer 22 located on the n-type silicon carbide substrate 21, and several gate trenches 31 located within the n-type silicon carbide layer 22. For the sake of convenience of display, only two gate trenches 31 are exemplarily shown in the embodiment of the present application.

[0016] The p-type body regions 23 located within the n-type silicon carbide layer 22 and on both sides of the gate trench 31 include a first p-type body region 23a and a second p-type body region 23b located between the first p-type body region 23a and the gate trench 31. The depth of the second p-type body region 23b is smaller than the depth of the first p-type body region 23a, the depth of the gate trench 31 is smaller than the depth of the first p-type body region 23a, and is larger than the depth of the second p-type body region 23b.

[0017] The n-type source region 25 and the current channel region 10 are located within the p-type body region 23. The current channel region 10 includes a horizontal channel region 10a and a vertical channel region 10b, and the vertical channel region 10b is located within a second p-type body region 23b. Preferably, the n-type source region 25 is located within the first p-type body region 23a, and the horizontal channel region 10a is located within the second p-type body region 23b. Preferably, the n-type source region 25 is located within the first p-type body region 23a, and the horizontal channel region 10a is located within the second p-type body region 23b and extends into the first p-type body region 23a. Preferably, the n-type source region 25 is located within the first p-type body region 23a and extends into the second p-type body region 23b, and the horizontal channel region 10a is located within the second p-type body region 23b. In an embodiment of the present application, as an example, the n-type source region 25 is located within the first p-type body region 23a, the horizontal channel region 10a is located within the second p-type body region 23b, and extends into the first p-type body region 23a.

[0018] The p-type body contact region 24 located within the first p-type body region 23a can reduce the contact resistance when the p-type body region 23 contacts an external electrode.

[0019] The two gate electrodes 27 are located within the gate trench 31, are respectively located on two side walls of the gate trench 31, and each extend over the horizontal channel region 10a on the corresponding side. The silicon carbide device includes a horizontal channel region 10a and a vertical channel region 10b corresponding to each gate electrode 27. The gate electrode 27 is insulated and separated from the n-type silicon carbide layer 22 through a gate electrode insulating layer 26, and the material of the gate electrode insulating layer 26 is usually silicon oxide. Preferably, the thickness of the gate electrode insulating layer 26 at the bottom of the gate trench 31 is greater than the thickness of the gate electrode insulating layer 26 on the side wall of the gate trench 31, which can improve the breakdown voltage of the silicon carbide device.

[0020] The gate electrode 27 controls the on and off states of the current channel region 10 located within the p-type body region 23 based on the gate electrode voltage. The current channel region is an inversion layer formed within the body region when the semiconductor device is turned on.

[0021] In the silicon carbide device according to the embodiment of the present application, by providing an n-type doped region located below the gate trench within the n-type silicon carbide layer, the parasitic JFET resistance can also be reduced. The current channel region of the silicon carbide device according to the embodiment of the present application includes a horizontal channel region at the top and a vertical channel region on the sidewall, thereby overcoming the problem of low mobility of planar silicon carbide devices. The embodiment of the present application also adopts a shallow gate trench structure, which not only relaxes the parasitic JFET effect but also reduces the on-resistance. At the same time, since the depth of the gate trench is shallow, the electric field in the oxide layer at the bottom of the gate trench is reduced, making it less likely to be damaged, and the reliability and stability of the silicon carbide device can be improved.

[0022] Figures 2 to 11 are schematic cross-sectional structure diagrams formed in the steps of the manufacturing method of the silicon carbide device according to the embodiment of the present application. The manufacturing method of the silicon carbide device according to the embodiment of the present application includes the following steps.

[0023] In step 1, as shown in Figure 2, an n-type silicon carbide layer 22 is formed on the provided n-type silicon carbide substrate 21, and a first insulating layer 30 is formed on the n-type silicon carbide layer 22. The material of the first insulating layer 30 is usually silicon oxide or a stack of silicon oxide and silicon nitride. After defining the position of the first p-type body region 23a by a photolithography process, the first insulating layer 30 is etched to expose the n-type silicon carbide layer 22.

[0024] In step 2, as shown in Figure 3, vertical p-type ion implantation is performed using the first insulating layer 30 as a mask to form the first p-type body region 23a within the n-type silicon carbide layer 22.

[0025] In step 3, as shown in FIG. 4, using the first insulating layer 30 as a mask, p-type ion implantation is performed obliquely toward one side of each first p-type body region to form a second p-type body region 23b located on one side of the first p-type body region 23a in the n-type silicon carbide layer 22.

[0026] In step 4, as shown in FIG. 5, using the first insulating layer 30 as a mask, p-type ion implantation is performed obliquely toward the other side of each first p-type body region to form a second p-type body region 23b located on the other side of the first p-type body region 23a in the n-type silicon carbide layer 22. The first p-type body region 23a and the second p-type body region 23b together form the p-type body region of the silicon carbide device.

[0027] In step 5, as shown in FIG. 6, after removing the first insulating layer 30 by etching, the position of the p-type body contact region 24 is defined by a photolithography process, and then p-type ion implantation is performed to form the p-type body contact region 24 in the p-type body region 23.

[0028] In the embodiments of the present application, all the structural regions of the silicon carbide device are shown as rectangular. However, in the actual manufacturing process, the edges of the structural regions of the silicon carbide device are usually curved or rounded. For example, the stepped shape between the first p-type body region 23a and the second p-type body region 23b in the embodiments of the present application usually presents an arc shape after the annealing process in the actual manufacturing process, that is, as shown in FIG. 7, actually, the region between the first p-type body region 23a and the second p-type body region 23b is not stepped but arc-shaped 40. However, for the convenience of display, it is shown as stepped in the embodiments of the present application. When the region between the first p-type body region 23a and the second p-type body region 23b is arc-shaped, the depth of the second p-type body region 23b being smaller than the depth of the first p-type body region 23a means that the depth of the side of the second p-type body region 23b closer to the gate trench 31 is smaller than the depth of the first p-type body region 23a. Also, it can be understood that the minimum depth of the second p-type body region 23b is smaller than the depth of the first p-type body region 23a.

[0029] In step 6, as shown in FIG. 8, after defining the position of the n-type source region 25 by a photolithography process, n-type ion implantation is performed to form the n-type source region 25 in the p-type body region 23. The positions of the n-type source regions 25 formed in one p-type body region 23 are on both sides of the p-type body contact region 24.

[0030] In step 7, as shown in FIG. 9, after defining the position of the gate trench 31 by a photolithography process, the n-type silicon carbide layer 22 is etched to form a plurality of gate trenches 31 in the n-type silicon carbide layer 22. However, only two gate trenches 31 are exemplarily shown in the embodiments of the present application.

[0031] In step 8, as shown in FIG. 10, a gate electrode insulating layer 26 is formed on the surface of the gate trench 31 and the surface of the n-type silicon carbide layer 22. Then, a first conductive layer is formed on the surface of the gate electrode insulating layer 26 so as to form two gate electrodes 27 located in the gate trench 31, and the formed first conductive layer is etched. The two gate electrodes 27 are respectively located on the two side walls of the gate trench 31 and extend respectively up to the horizontal channel regions 10a on the corresponding sides.

[0032] In step 9, as shown in FIG. 11, n-type ion implantation is performed on the n-type silicon carbide layer 22 through the gap between the two gate electrodes 27 in the same gate trench 31 to form an n-type doped region 28 located below the gate trench in the n-type silicon carbide layer 22. The n-type doped region can reduce the parasitic JFET resistance.

[0033] In step 10, a passivation layer is formed on the surface of the formed structure to form a silicon carbide device. After the formed passivation layer is etched to form contact holes, a metal layer is formed. This step is not shown in the figure.

[0034] As shown in FIG. 12, the method for manufacturing a silicon carbide device according to the embodiment of the present application includes: S1 of forming an n-type silicon carbide layer on an n-type silicon carbide substrate; S2 of forming a first insulating layer on the n-type silicon carbide layer; S3 of etching the first insulating layer to form a mask pattern; S4 of performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions in the n-type silicon carbide layer; S5 of performing p-type ion implantation inclined toward one side of each first p-type body region using the first insulating layer as a mask to form a second p-type body region located on one side of each first p-type body region in the n-type silicon carbide layer; To form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer, p-type ion implantation is performed so as to be inclined toward the other side of each first p-type body region using the first insulating layer as a mask. The plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of the silicon carbide device, S6, Etch and remove the first insulating layer, perform n-type ion implantation, and form an n-type source region within each p-type body region, S7, Etch the n-type silicon carbide layer so as to form a plurality of gate trenches within the n-type silicon carbide layer, S8, Form a gate electrode insulating layer on the surfaces of the bottom and sidewalls within each gate trench and on the surface of the n-type silicon carbide layer, S9, To form two gate electrodes within each gate trench, form a first conductive layer on the surface of the gate electrode insulating layer, etch the first conductive layer, and the two gate electrodes are respectively located on the two sidewalls of each gate trench and extend to above the horizontal channel regions on the corresponding sides respectively, S10, including.

Claims

1. An n-type silicon carbide substrate, An n-type silicon carbide layer formed on the n-type silicon carbide substrate, A plurality of gate trenches formed in the n-type silicon carbide layer, P-type body regions respectively formed on both sides of each gate trench, An n-type source region and a current channel region formed in each p-type body region, Two gate electrodes formed in each gate trench, the two gate electrodes being respectively located on two sidewalls of each gate trench and extending to above the horizontal channel regions on their respective corresponding sides, Each p-type body region on each side includes a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, the depth of the second p-type body region is smaller than the depth of the first p-type body region, the depth of the gate trench is smaller than the depth of the first p-type body region and larger than the depth of the second p-type body region, The current channel region includes a horizontal channel region and a vertical channel region, The gate electrode is insulated and separated from the n-type silicon carbide layer through a gate electrode insulating layer between the gate electrode and the n-type silicon carbide layer, and the gate electrode is provided to control the on and off of the current channel region by a gate electrode voltage. A silicon carbide device.

2. The thickness of the gate electrode insulating layer at the bottom of the gate trench is larger than the thickness of the gate electrode insulating layer on the sidewall of the gate trench. The silicon carbide device according to Claim 1.

3. The n-type source region is located in the first p-type body region in the p-type body region where it is located, and the horizontal channel region is located in the second p-type body region in the p-type body region where it is located. The silicon carbide device according to Claim 1.

4. The n-type source region is located in the first p-type body region in the p-type body region where it is located, the horizontal channel region is located in the second p-type body region in the p-type body region where it is located, and extends into the first p-type body region in the p-type body region where it is located. The silicon carbide device according to Claim 1.

5. The n-type source region is located within the first p-type body region in the p-type body region where it is located, extends into the second p-type body region in the p-type body region where it is located, and the horizontal channel region is located within the second p-type body region in the p-type body region where it is located. The silicon carbide device according to claim 1.

6. Further comprising a p-type body contact region located within each of the first p-type body regions. The silicon carbide device according to claim 1.

7. Further comprising an n-type doped region within the n-type silicon carbide layer and located below each gate trench, and each n-type doped region overlaps with the gap between two gate electrodes within its corresponding gate trench. The silicon carbide device according to claim 1.

8. Forming an n-type silicon carbide layer on an n-type silicon carbide substrate. Forming a first insulating layer on the n-type silicon carbide layer. Etching the first insulating layer to form a mask pattern. Performing vertical p-type ion implantation using the first insulating layer as a mask to form a plurality of first p-type body regions within the n-type silicon carbide layer. Performing p-type ion implantation inclined towards one side of each first p-type body region using the first insulating layer as a mask to form a second p-type body region located on one side of each first p-type body region within the n-type silicon carbide layer. Performing p-type ion implantation inclined towards the other side of each first p-type body region using the first insulating layer as a mask to form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer, and the plurality of first p-type body regions and the plurality of second p-type body regions form the plurality of p-type body regions of the silicon carbide device. Etching and removing the first insulating layer, performing n-type ion implantation, and forming an n-type source region within each p-type body region. Etching the n-type silicon carbide layer to form a plurality of gate trenches within the n-type silicon carbide layer. Forming a gate electrode insulating layer on the surfaces of the bottom and sidewalls within each gate trench and on the surface of the n-type silicon carbide layer. Forming a first conductive layer on the surface of the gate electrode insulating layer so as to form two gate electrodes within each gate trench, and etching the first conductive layer. The two gate electrodes are respectively located on two sidewalls of each gate trench and extend to above the horizontal channel regions on the corresponding sides respectively. A method for manufacturing a silicon carbide device. Claim 9 The method further includes performing n-type ion implantation into the n-type silicon carbide layer through a gap between the two gate electrodes in each gate trench to form an n-type doped region located below each gate trench in the n-type silicon carbide layer. The method for manufacturing a silicon carbide device according to claim 8. Claim 10 Before forming an n-type source region in each p-type body region, the method further includes performing p-type ion implantation to form a p-type body contact region in each p-type body region. The method for manufacturing a silicon carbide device according to claim 8.

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