Display substrate and display device

Abstract

A display substrate and a display device, in which display substrate, a driving transistor controls a light-emitting device to emit light, a data line is connected to a first electrode of a data writing transistor and is configured to provide a data signal to the data writing transistor, the data writing transistor is configured to write the data signal to a gate electrode of the driving transistor in response to a first scanning signal applied to its gate electrode, and a first connection structure is connected to the gate electrode of the driving transistor and a first electrode plate of a storage capacitor. Both the data line and the first connection structure extend along a first direction, the data line includes an overlapping portion, and the overlapping portion of the first connection structure and the data line is at least partially opposed to each other. A second direction is parallel to a base substrate and perpendicular to the first direction. The overlapping portion of the first connection structure and the data line are insulated from each other, and the overlapping portion of the first connection structure and the data line respectively form a first electrode plate and a second electrode plate of a parasitic capacitance. The ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application with the application number 202210811589.8 filed on July 12, 2022, and the entire content disclosed in that application is incorporated herein by reference.

[0002] At least one embodiment of the present invention relates to a display substrate and a display device.

Background Art

[0003] Compared with conventional liquid crystal displays (LCDs), active matrix organic light-emitting diode (AMOLED) displays have advantages such as self-emission, a wide color gamut, high contrast, and thinness. They are widely used in fields such as mobile phones and tablet computers, and are also widely used in flexible wearable fields such as smart watches. Usually, a pixel circuit is provided in the display area, and a gate driving circuit such as a GOA driving circuit is provided in the frame area to provide a driving signal to the pixel circuit.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present invention provides a display substrate including a base substrate provided with a plurality of pixels arranged in an array, each of at least some of the plurality of pixels including a plurality of sub-pixels, at least some of the plurality of sub-pixels including a pixel circuit, and the pixel circuit including a light-emitting device, a storage capacitor, a driving transistor, a data writing transistor, a data line, and a first connection structure. In the light-emitting device, the storage capacitor, the driving transistor, and the data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate electrode, a first electrode, and a second electrode. The driving transistor is configured to control the light-emitting device to emit light. The data line is connected to the first electrode of the data writing transistor and is configured to provide a data signal to the data writing transistor. The data writing transistor is configured to write the data signal to the gate electrode of the driving transistor in response to a first scanning signal applied to the gate electrode of the data writing transistor. The first connection structure is connected to the gate electrode of the driving transistor and the first electrode plate of the storage capacitor. Both the data line and the first connection structure extend along a first direction. The data line includes an overlapping portion. The overlapping portion of the first connection structure and the data line is at least partially opposed in a second direction. The second direction is parallel to the base substrate and perpendicular to the first direction. The overlapping portion of the first connection structure and the data line is insulated from each other. The overlapping portion of the first connection structure and the data line constitutes a first electrode plate and a second electrode plate of a parasitic capacitance, respectively. The ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.

[0005] For example, in the display substrate provided by an embodiment of the present invention, the size of the sub-pixel in the second direction is greater than 50 μm, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is less than 0.005.

[0006] For example, in the display substrate provided by an embodiment of the present invention, the size of the sub-pixel in the second direction is 68 μm or less, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is 0.003 or more.

[0007] For example, in the display substrate provided by an embodiment of the present invention, the size of the sub-pixel in the second direction is less than 50 μm, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.005 and less than 0.006.

[0008] For example, in the display substrate provided by an embodiment of the present invention, the first connection structure includes a first portion extending along the first direction. An edge of the first portion of the first connection structure close to the overlapping portion of the data line is the first edge. The first portion of the first connection structure further has a second edge away from the overlapping portion of the data line. An edge of the overlapping portion of the data line close to the first connection structure is the third edge. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The distance between the orthographic projection of the second edge of the first connection structure of the first sub-pixel on the base substrate and the projection of the third edge of the overlapping portion of the data line of the second sub-pixel on the base substrate is the first distance. The distance between the first edge of the first connection structure of the first sub-pixel and the third edge of the overlapping portion of the data line of the first sub-pixel is the second distance. The ratio of the first distance to the second distance is greater than 14.

[0009] For example, in the display substrate provided by an embodiment of the present invention, the size of the sub-pixel in the second direction is less than 50 μm, and the ratio of the first distance to the second distance is greater than 14 and less than 15.5.

[0010] For example, in the display substrate provided by an embodiment of the present invention, the size of the sub-pixel in the second direction is greater than 50 μm, and the ratio of the first distance to the second distance is greater than 15.5.

[0011] For example, in a display substrate provided by an embodiment of the present invention, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in the second direction. The first connection structure of the first sub-pixel is located between the data line of the first sub-pixel and the data line of the second sub-pixel in the second direction. The distance between the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the data line of the first sub-pixel on the base substrate is smaller than the size of one of the sub-pixels in the second direction. The distance between the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the data line of the second sub-pixel on the base substrate is smaller than the size of one of the sub-pixels in the second direction.

[0012] For example, in a display substrate provided by an embodiment of the present invention, the first connection structure of the first sub-pixel is located between the data line of the first sub-pixel and the data line of the second sub-pixel in the second direction. The distance between the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the data line of the first sub-pixel on the base substrate is smaller than the size of one of the sub-pixels in the second direction. The distance between the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the data line of the second sub-pixel on the base substrate is larger than the size of one of the sub-pixels in the second direction.

[0013] For example, in a display substrate provided by an embodiment of the present invention, an edge of the gate electrode of the driving transistor of the first sub-pixel, which is close to the overlapping portion of the data line of the second sub-pixel, is a fourth edge. The distance between the second edge of the first sub-pixel and the third edge of the second sub-pixel is equal to the sum of the distance between the second edge of the first sub-pixel and the fourth edge and the distance between the fourth edge of the first sub-pixel and the third edge of the second sub-pixel.

[0014] For example, in a display substrate provided by an embodiment of the present invention, the first connection structure and the data line are disposed in different layers, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the overlapping portion of the data line on the base substrate overlap at least partially, or the first connection structure and the data line are disposed in different layers, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the overlapping portion of the data line on the base substrate do not overlap.

[0015] For example, in a display substrate provided by an embodiment of the present invention, the first connection structure and the data line are disposed in the same layer, and the overlapping portions of the first connection structure and the data line face each other in the second direction.

[0016] For example, in a display substrate provided by an embodiment of the present invention, at least one of the overlapping portion of the data line and the first connection structure includes a recess, and the recess of either the overlapping portion of the data line or the first connection structure is recessed in a direction away from the other of the overlapping portion of the data line and the first connection structure in the second direction.

[0017] For example, in a display substrate provided by an embodiment of the present invention, the overlapping portion of the data line includes a first recess, and the first recess is recessed in a direction away from the first connection structure in the second direction. The portion of the first connection structure facing the data line is in a straight strip shape.

[0018] For example, in a display substrate provided by an embodiment of the present invention, the first connection structure includes a second recess, and the second recess is recessed in a direction away from the overlapping portion of the data line in the second direction, and the overlapping portion of the data line is in a straight strip shape.

[0019] For example, in the display substrate provided by an embodiment of the present invention, the overlapping portion of the data lines includes a first recess, and the first recess is recessed in a direction away from the first connection structure in the second direction. The first connection structure includes a second recess that is recessed in a direction away from the overlapping portion of the data lines in the second direction.

[0020] For example, the display substrate provided by an embodiment of the present invention further includes a first reset scan signal line, a second reset scan signal line, a first reset signal line, and a second reset signal line. The pixel circuit further includes a first reset transistor and a second reset transistor. The first reset transistor includes an active layer. The first reset scan signal line is configured to provide a first reset scan signal to the gate electrode of the first reset transistor. The first pole of the first reset transistor is electrically connected to the gate electrode of the drive transistor. The second pole of the first reset transistor is electrically connected to the first reset signal line and configured to receive a first reset signal. The first reset transistor is configured to write the first reset signal to the gate electrode of the drive transistor in response to the first reset scan signal. The second reset scan signal line is configured to provide a second reset scan signal to the gate electrode of the second reset transistor. The first pole of the second reset transistor is electrically connected to the first display electrode of the light-emitting device. The second pole of the second reset transistor is electrically connected to the second reset signal line and configured to receive a second reset signal. The second reset transistor is configured to write the second reset signal to the first display electrode of the light-emitting device in response to the second reset scan signal. The active layer of the first reset transistor extends along the first direction. The first reset scan signal line extends along the second direction. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in the second direction. The plurality of sub-pixels further include a third sub-pixel that is adjacent to the second sub-pixel in the first direction.A portion of the second reset signal line located at one of the sub-pixels extends along the second direction, and includes a horizontal portion having a first end and a second end facing each other in the second direction, and a first vertical portion connected to the first end of the horizontal portion and extending along the first direction. A front projection of the horizontal portion of the second reset signal line of the second sub-pixel on the base substrate and a front projection of the first reset scanning signal line of the third sub-pixel on the base substrate at least partially overlap. The first vertical portion of the second reset signal line of the second sub-pixel and the active layer of the first reset transistor of the third sub-pixel are arranged at intervals in the second direction.

[0021] For example, in a display substrate provided according to an embodiment of the present invention, a planar pattern of a sub-portion of the second reset signal line corresponding to one sub-pixel is in an inverted "ji" shape. The "ji" shaped sub-portion includes a U-shaped groove, and the horizontal portion of the second reset signal line functions as the bottom of the U-shaped groove.

[0022] For example, a display substrate provided according to an embodiment of the present invention further includes a compensation scanning signal line. The pixel circuit further includes a compensation transistor including an active layer, a gate electrode, a first electrode, and a second electrode. The compensation scanning signal line is configured to apply a second scanning signal to the gate electrode of the compensation transistor. The compensation transistor is configured to perform threshold compensation on the driving transistor in response to the second scanning signal. The active layer of the compensation transistor and the active layer of the first reset transistor form an integral structure.

[0023] For example, in the display substrate provided by an embodiment of the present invention, a portion of the second reset signal line located in one of the sub-pixels is connected to the second end of the horizontal portion, and further includes a second vertical portion extending along the first direction. The active layer of the second reset transistor is located between the first vertical portion and the second vertical portion. In the same sub-pixel, in the second direction, the distance between the first vertical portion and the data line is greater than the distance between the second vertical portion and the data line. The distance between the active layer of the second reset transistor of the third sub-pixel and the first vertical portion of the second reset signal line of the second sub-pixel is smaller than the distance between the active layer of the second reset transistor of the third sub-pixel and the second vertical portion of the second reset signal line of the second sub-pixel.

[0024] For example, in the display substrate provided by an embodiment of the present invention, the gate electrode of the driving transistor and the first electrode plate of the storage capacitor are arranged in the same layer to form an integrally formed structure. The second reset scan signal line and the gate electrode of the driving transistor are arranged in the same layer. The gate electrode of the driving transistor and the first electrode plate of the storage capacitor are located on the side away from the base substrate of the active layer of the driving transistor. The second electrode plate of the storage capacitor is located on the side away from the base substrate of the gate electrode of the driving transistor and the first electrode plate of the storage capacitor. The compensation scan signal line and the second electrode plate of the compensation transistor are arranged in the same layer. The active layer of the compensation transistor is located on the side away from the base substrate of the second electrode plate of the storage capacitor. The second reset signal line is located on the side away from the base substrate of the active layer of the compensation transistor.

[0025] For example, the display substrate provided by an embodiment of the present invention further includes a first reset scan signal line and a first reset signal line, and the pixel circuit further includes a first reset transistor. The first reset transistor includes an active layer, and the first reset scan signal line is configured to provide a first reset scan signal to the gate electrode of the first reset transistor. The first pole of the second reset transistor is electrically connected to the gate electrode of the drive transistor, and the second pole of the first reset transistor is electrically connected to the first reset signal line and configured to receive a first reset signal. The first reset transistor is configured to write the first reset signal to the gate electrode of the drive transistor in response to the first reset scan signal. The active layer of the first reset transistor and the active layer of the drive transistor are formed of different materials and disposed in different layers, and the first reset signal line and the second electrode plate of the storage capacitor are disposed in the same layer.

[0026] For example, in the display substrate provided by an embodiment of the present invention, both the gate electrode of the compensation transistor and the gate electrode of the first reset transistor have a dual gate structure. The gate electrode of the compensation transistor includes a first gate electrode and a second gate electrode, and the gate electrode of the first reset transistor includes a first gate electrode and a second gate electrode. The orthographic projection of the first gate electrode of the compensation transistor on the base substrate overlaps with the orthographic projection of the second gate electrode of the compensation transistor on the base substrate, and the orthographic projection of the first gate electrode of the first reset transistor on the base substrate overlaps with the orthographic projection of the second gate electrode of the first reset transistor on the base substrate.

[0027] For example, in the display substrate provided by an embodiment of the present invention, the first gate electrode of the compensation transistor and the first gate electrode of the first reset transistor are arranged in the same layer as the second electrode plate of the storage capacitor. The second gate electrode of the compensation transistor and the second gate electrode of the first reset transistor are located on the side away from the base substrate of the active layer of the compensation transistor and the active layer of the first reset transistor, and are located on the side close to the base substrate of the second reset signal line.

[0028] For example, in the display substrate provided by an embodiment of the present invention, the material of the active layer of the first reset transistor is an oxide semiconductor, and the materials of the active layers of the driving transistor and the data writing transistor are low-temperature polysilicon.

[0029] For example, in the display substrate provided by an embodiment of the present invention, the first connection structure is located on the side away from the base substrate of the second electrode plate of the storage capacitor. The second electrode plate of the storage capacitor has a first via hole for exposing the first electrode plate of the storage capacitor. The first connection structure penetrates through the first via hole and is connected to the first electrode plate of the storage capacitor. The second electrode plate of the storage capacitor includes a first portion located on the first side in the second direction of the first via hole and a second portion located on the second side in the second direction of the first via hole. The first side of the first via hole faces the second side of the first via hole, and the second portion of the second electrode plate is located on the side close to the data line of the first portion of the second electrode plate. In the second direction, the orthographic projection on the base substrate of the edge of the first connection structure close to the second portion of the second electrode plate of the storage capacitor, the orthographic projection on the base substrate of the edge of the first display electrode close to the first connection structure, and the orthographic projection on the base substrate of the edge of the second portion of the second electrode plate close to the first connection structure overlap.

[0030] For example, in the display substrate provided by an embodiment of the present invention, when the first connection structure and the second reset signal line are arranged in the same layer, and the first connection structure and the data line are arranged in different layers, the data line is located on the side away from the base substrate of the first connection structure, or the data line is located on the side close to the base substrate of the first connection structure.

[0031] For example, in the display substrate provided by an embodiment of the present invention, the first connection structure includes a first portion extending along the first direction and a second portion extending along the second direction. The second portion of the first connection structure is connected to the first portion of the first connection structure. The active layer of the compensation transistor is located on the side away from the data line of the first connection structure, and the second portion of the first connection structure is connected to the active layer of the compensation transistor.

[0032] For example, in the display substrate provided by an embodiment of the present invention, the orthographic projection of the entire first connection structure on the base substrate is located within the orthographic projection of the first display electrode of the light-emitting device on the base substrate. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The first display electrode of the first sub-pixel covers the boundary between the first sub-pixel and the second sub-pixel. The orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the first connection structure of the second sub-pixel on the base substrate are both located within the orthographic projection of the first display electrode of the first sub-pixel on the base substrate.

[0033] For example, in the display substrate provided by an embodiment of the present invention, the orthographic projection on the base substrate of the edge of the first display electrode of the first sub-pixel that is away from the second sub-pixel overlaps with the orthographic projection on the base substrate of the edge of the first connection structure of the first sub-pixel that is close to the data line of the first sub-pixel, and the orthographic projection on the base substrate of the edge of the first display electrode of the first sub-pixel that is close to the second sub-pixel overlaps with the orthographic projection on the base substrate of the edge of the first connection structure of the second sub-pixel that is close to the data line of the second sub-pixel.

[0034] For example, in the display substrate provided by an embodiment of the present invention, a part of the orthographic projection of the first connection structure on the base substrate is located within the orthographic projection of the first display electrode of the light-emitting device on the base substrate. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in the second direction. The first display electrode of the first sub-pixel covers the boundary between the first sub-pixel and the second sub-pixel, and both a part of the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and a part of the orthographic projection of the first connection structure of the second sub-pixel on the base substrate are located within the orthographic projection of the first display electrode of the first sub-pixel on the base substrate.

[0035] For example, in the display substrate provided by an embodiment of the present invention, the light-emitting material of the light-emitting device of the first sub-pixel emits green light.

[0036] For example, in the display substrate provided by an embodiment of the present invention, the first electrode plate of the storage capacitor has an upper surface away from the base substrate and a side surface intersecting with the upper surface. The second electrode plate of the storage capacitor includes an intermediate portion and an edge portion. The orthographic projection of the intermediate portion on the base substrate at least partially overlaps with the orthographic projection of the first electrode plate of the storage capacitor on the base substrate, and includes a bottom surface facing the upper surface of the first electrode plate of the storage capacitor. The edge portion at least partially surrounds the intermediate portion, is connected to the intermediate portion, and includes a bottom surface close to the base substrate and an inner side surface intersecting with the bottom surface. The inner side surface faces the side surface of the first electrode plate of the capacitor. The orthographic projection of the inner side surface on a reference plane perpendicular to the base substrate at least partially overlaps with the orthographic projection of the side surface of the first electrode plate of the storage capacitor facing the inner side surface on the reference plane. The distance between the inner side surface of the edge portion and the side surface of the first electrode plate of the storage capacitor facing the inner side surface is smaller than the distance between the bottom surface of the intermediate portion and the upper surface of the first electrode plate of the storage capacitor.

[0037] For example, in the display substrate provided by an embodiment of the present invention, the first display electrode of the light-emitting device has a first end and a second end that face each other in the second direction. The display substrate includes a first semiconductor layer, and the first semiconductor layer includes the active layer of the driving transistor and the active layer of the data writing transistor. The data line is connected to the first semiconductor layer through a second via hole. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel that are adjacent to each other in the second direction. The first display electrode of the first sub-pixel covers the boundary between the first sub-pixel and the second sub-pixel. The orthographic projection of the first end of the first display electrode of the first sub-pixel on the base substrate has a first protruding portion that protrudes in a tapered manner toward the orthographic projection of the second via hole of the first sub-pixel on the base substrate in the second direction. The orthographic projection of the second end of the first display electrode of the first sub-pixel on the base substrate has a second protruding portion that protrudes in a tapered manner toward the orthographic projection of the second via hole of the second sub-pixel on the base substrate in the second direction. The orthographic projection of the first protruding portion and the second via hole of the first sub-pixel on the base substrate face each other in the second direction. The orthographic projection of the second protruding portion and the second via hole of the second sub-pixel on the base substrate face each other in the second direction. The light-emitting material of the light-emitting device of the first sub-pixel emits blue light.

[0038] For example, in a display substrate provided by an embodiment of the present invention, the gate electrode of the driving transistor and the first electrode plate of the storage capacitor are arranged in the same layer and formed in an integrally molded structure. The gate electrode of the driving transistor and the first electrode plate of the storage capacitor are located on the side of the active layer of the driving transistor away from the base substrate. The second electrode plate of the storage capacitor is located on the side of the gate electrode of the driving transistor and the first electrode plate of the storage capacitor away from the base substrate. The display substrate is connected to a first voltage terminal and is configured to supply a first power supply voltage to the pixel circuit, and further includes a first power supply line extending along a first direction. The pixel circuit is located between the first power supply line and the second electrode plate of the storage capacitor in a direction perpendicular to the base substrate, and further includes a second connection structure connecting the first power supply line and the second electrode plate of the storage capacitor. The second connection structure includes a horizontal portion extending along the second direction and a vertical portion connected to the horizontal portion and extending along the first direction. The orthographic projection of the first power supply line on the base substrate overlaps the orthographic projection of the horizontal portion of the second connection structure on the base substrate and does not overlap the orthographic projection of another structure arranged in the same layer as the second connection structure on the base substrate.

[0039] For example, in a display substrate provided by an embodiment of the present invention, the vertical portion is basically aligned with the first connection structure in the first direction, and the orthographic projection of the horizontal portion on the base substrate extends from the orthographic projection of the vertical portion on the base substrate along the first direction to the orthographic projection of the first power supply line on the base substrate.

[0040] For example, the display substrate provided by an embodiment of the present invention further includes a first insulating layer and a second insulating layer. The first insulating layer is located between the first power line and the second connection structure, and the second insulating layer is located between the second connection structure and the second electrode plate of the storage capacitor. The horizontal portion of the first power line is connected to the second connection structure through a third via hole penetrating the first insulating layer, and the vertical portion of the second connection structure is connected to the second electrode plate of the storage capacitor through a third via hole penetrating the second insulating layer.

[0041] For example, in the display substrate provided by an embodiment of the present invention, the first power line and the data line are arranged in the same layer, and the second connection structure and the first connection structure are arranged in the same layer.

[0042] For example, in the display substrate provided by an embodiment of the present invention, the pixel circuit is connected to the first electrode of the driving transistor and the first voltage terminal, and further includes a first light-emitting transistor configured to apply the first power supply voltage of the first voltage terminal to the first electrode of the driving transistor in response to a first light-emitting control signal applied to the gate electrode of the first light-emitting transistor. The display substrate includes a first semiconductor layer, the first semiconductor layer includes the active layer of the driving transistor, the active layer of the data writing transistor, and the active layer of the first light-emitting transistor, and the horizontal portion of the second connection structure is connected to the first semiconductor layer through a fifth via hole.

[0043] For example, in the display substrate provided by an embodiment of the present invention, the horizontal portion of the second connection structure has a first end and a second end facing each other in the second direction, the first end of the horizontal portion is located on the side close to the vertical portion of the first power line and is connected to the vertical portion, the second end of the horizontal portion is located on the side away from the vertical portion of the first power line, and is connected to the first semiconductor layer through the fifth via hole.

[0044] At least one embodiment of the present invention further provides a display device including any display substrate provided by an embodiment of the present invention.

[0045] To more clearly explain the technical solution of the embodiments of the present invention, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present invention and do not limit the present invention.

Brief Description of the Drawings

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[0047] In order to more clearly illustrate the objectives, technical solutions, and advantages of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts are included within the protection scope of the present invention.

[0048] Unless otherwise defined, technical terms or scientific terms used in this specification shall have the ordinary meanings understood by those skilled in the technical field to which the present invention pertains. The terms "first", "second", and similar words used in the specification and claims of the patent application of the present invention do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similar words such as "comprising" or "containing" mean that the elements or things appearing before such words include the elements or things listed after such words and their equivalents without excluding other elements or things. Words such as "inside", "outside", "above", "below", etc. are only used to express relative positional relationships, and if the absolute position of the object being described changes, the corresponding relative positional relationship may also change accordingly.

[0049] The drawings in the present invention are not drawn strictly based on actual ratios, and the number of sub-pixels and virtual pixels in the display substrate is not limited to the numbers shown in the drawings. The specific sizes and quantities of each structure can be determined according to actual needs. The drawings described in the present invention are only schematic diagrams of the structures.

[0050] In the present application, the orthographic projection of the base substrate with a specific structure refers to the orthographic projection on the main surface of the base substrate with such a structure, and the main surface of the base substrate refers to the surface of the base substrate on which the pixel circuit is arranged.

[0051] In the present invention, "arranged in the same layer" refers to a structure formed by patterning two (or more) structures by the same vapor deposition process and the same patterning process, and their materials may be the same or different. The "continuous integral structure" in the present invention refers to an interconnected structure formed by patterning two (or more) structures by the same patterning process in the same film layer, and their materials may be the same or different.

[0052] Note that Scan(N)(n) represents the scanning signal line of the nth row connected to the N-type TFT, Scan(N)(n - 1) represents the scanning signal line of the (n - 1)th row connected to the N-type TFT, and Scan(N)(n + 1) represents the scanning signal line of the (n + 1)th row connected to the N-type TFT. Scan(P)(n) represents the scanning signal line of the nth row connected to the P-type TFT, and Scan(P)(n + 1) represents the scanning signal line of the (n + 1)th row connected to the P-type TFT.

[0053] Generally, a plurality of transistors are provided in the pixel driving circuit of an AMOLED, and a parasitic capacitance is often formed between the gate node of the driving transistor of the driving circuit of one pixel and the adjacent data line. As a result, the jump voltage of the data line affects the driving voltage of the driving transistor during display.

[0054] At least one embodiment of the present invention provides a display substrate including a base substrate provided with a plurality of pixels arranged in an array, wherein each of at least some of the plurality of pixels includes a plurality of sub-pixels, at least some of the plurality of sub-pixels include a pixel circuit, and the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor, a data writing transistor, a data line, and a first connection structure. In the light-emitting device, the storage capacitor, the driving transistor, and the data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate electrode, a first electrode, and a second electrode. The driving transistor is configured to control the light-emitting device to emit light. The data line is connected to the first electrode of the data writing transistor and is configured to provide a data signal to the data writing transistor. The data writing transistor is configured to write the data signal to the gate electrode of the driving transistor in response to a first scanning signal applied to its gate electrode. The first connection structure is connected to the gate electrode of the driving transistor and the first electrode plate of the storage capacitor. Both the data line and the first connection structure extend along a first direction. The data line includes an overlapping portion. The overlapping portion of the first connection structure and the data line is at least partially opposed in a second direction. The second direction is parallel to the base substrate and perpendicular to the first direction. The overlapping portion of the first connection structure and the data line is insulated from each other. The overlapping portion of the first connection structure and the data line constitutes a first electrode plate and a second electrode plate of a parasitic capacitance respectively. The ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.

[0055] It should be noted that the capacitance value of the parasitic capacitance related to the protection scope of the claims of the present invention shall be in accordance with the calculation method disclosed in the specification.

[0056] At least one embodiment of the present invention further provides a display device including any display substrate provided by the embodiments of the present invention.

[0057] Exemplarily, FIG. 1 is a schematic plan view of a display substrate provided according to an embodiment of the present invention. For example, as shown in FIG. 1, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting device and a pixel circuit for driving the light-emitting device to emit light. For example, the pixel circuit can include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, 4T2C, 5T1C, 7T1C, or an nTmC (n and m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit can further include a compensation sub-circuit including an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit can include transistors, capacitors, etc. For example, if necessary, the pixel circuit can further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc.

[0058] For example, as shown in FIG. 1, the plurality of pixels 100 are located in the display area. For example, in the display substrate 10 provided by some embodiments, some of the plurality of pixels 100 are dummy pixels 1000, the dummy pixels 1000 do not participate in the display operation, each dummy pixel 1000 includes a plurality of dummy sub-pixels, and does not include sub-pixels that play a role in display driving.

[0059] For example, in some embodiments, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED. The display substrate 10 includes a plurality of scan lines and a plurality of data lines for providing a scan signal (control signal) and a data signal to the plurality of sub-pixels to drive the plurality of sub-pixels. If necessary, the display substrate 10 can further include a power line, a detection line, etc.

[0060] FIG. 2A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present invention. As shown in FIG. 2A, the pixel circuit unit includes a driving sub-circuit 122, a compensation sub-circuit 128, a data writing sub-circuit 126, a memory sub-circuit 127, a first light emission control sub-circuit 123, a second light emission control sub-circuit 124, a first reset sub-circuit 125, and a second reset sub-circuit 129.

[0061] For example, the driving circuit 122 includes a control terminal 122a, a first terminal 122b, and a second terminal 122c, is connected to the light emitting device 20, and is configured to control the driving current flowing through the light emitting device 20. The control terminal 122a of the driving sub-circuit 122 is connected to the first node N1, the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2, is configured to receive the first power supply voltage VDD, and the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.

[0062] For example, the data writing sub-circuit 126 includes a control terminal 126a configured to receive the first scan signal Ga1, a first terminal 126b configured to receive the data signal Vd, and a second terminal 126c connected to the first terminal 122b (i.e., the second node N2) of the driving sub-circuit 122. The data writing sub-circuit 126 is configured to write the data signal Vd to the first terminal 122b of the driving sub-circuit 122 in response to the first scan signal Ga1. For example, the first terminal 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scan line to receive the first scan signal Ga1. For example, in the data writing and compensation stages, the data writing sub-circuit 126 is turned on in response to the first scan signal Ga1, can write the data signal to the first terminal 122b (the second node N2) of the driving sub-circuit 122, store the data signal in the memory sub-circuit 127, and for example, generate a driving current for driving the light emitting device 20 to emit light based on the data signal during the light emitting stage.

[0063] For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c. The control terminal 128a of the compensation sub-circuit 128 is configured to receive the second scan signal Ga2, and the first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the drive sub-circuit 122, respectively. The compensation sub-circuit 128 is configured to perform threshold compensation on the drive sub-circuit 122 in response to the second scan signal Ga2.

[0064] For example, the first scan signal Ga1 and the second scan signal Ga2 may be the same. For example, the first scan signal Ga1 and the second scan signal Ga2 may be connected to the same signal output terminal. For example, the first scan signal Ga1 and the second scan signal Ga2 may be transmitted by the same scan line.

[0065] In some other examples, the first scan signal Ga1 may be different from the second scan signal Ga2. For example, the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals. For example, the first scan signal Ga1 and the second scan signal Ga2 may be transmitted by different scan lines, respectively.

[0066] For example, the memory sub-circuit 127 includes a first terminal 127a and a second terminal 127b. The first terminal 127a of the memory sub-circuit is configured to receive the first power supply voltage VDD, and the second terminal 127b of the memory sub-circuit is electrically connected to the control terminal 122a of the drive sub-circuit.

[0067] For example, the memory sub-circuit 127 is electrically connected to the control terminal 122a and the first voltage terminal vdd of the drive sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126. For example, in the data writing and compensation stages, the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, and as a result, the data signal written by the data writing sub-circuit 126 can be stored in the memory sub-circuit 127. For example, at the same time, in the data writing and compensation stages, the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the drive sub-circuit 122, and as a result, the related information regarding the threshold voltage of the drive sub-circuit 122 can also be stored in the memory sub-circuit accordingly. Thereby, in the light-emitting stage, the stored data signal and the threshold voltage can be used to control the drive sub-circuit 122, whereby the output of the drive sub-circuit 122 is compensated.

[0068] For example, the first light-emitting control sub-circuit 123 is connected to the first terminal 122b (second node N2) and the first voltage terminal vdd of the drive sub-circuit 122, and is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first terminal 122b of the drive sub-circuit 122 in response to the first light-emitting control signal EM1. For example, as shown in FIG. 2A, the first light-emitting control sub-circuit 123 is connected to the first light-emitting control terminal EM1, the first voltage terminal vdd, and the second node N2.

[0069] For example, the second light-emitting control sub-circuit 124 is connected to the second light-emitting control terminal EM2, the first terminal 134 of the light-emitting device 20, and the second terminal 122c of the drive sub-circuit 122, and is configured to apply a drive current to the light-emitting device 20 in response to the second light-emitting control signal.

[0070] For example, in the light-emitting stage, the second light-emitting control sub-circuit 124 turns on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2. As a result, the drive sub-circuit 122 is electrically connected to the light-emitting device 20 via the second light-emitting control sub-circuit 124, and thereby drives the light-emitting device 20 under the control of the drive current to emit light. In the non-light-emitting stage, the second light-emitting control sub-circuit 124 turns off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting device 20 to cause light emission, and enhancing the contrast of the corresponding display device.

[0071] As another example, in the initialization stage, the second light-emitting control sub-circuit 124 can also turn on in response to the second light-emitting control signal EM2, and as a result, can cooperate with the reset sub-circuit to reset the drive sub-circuit 122 and the light-emitting device 20.

[0072] For example, the second light-emitting control signal EM2 may be the same as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 may be connected to the same signal output terminal as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 may be transmitted by the same light-emitting control line as the first light-emitting control signal EM1.

[0073] In some other examples, the second light-emitting control signal EM2 may be different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be connected to different signal output terminals respectively. For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be transmitted by different light-emitting control lines respectively.

[0074] For example, the first reset sub-circuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (the first node N1) of the drive sub-circuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the drive sub-circuit 122 in response to the first reset control signal Rst1.

[0075] For example, the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 134 (the fourth node N4) of the light-emitting device 20, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light-emitting device 20 in response to the second reset control signal Rst2.

[0076] For example, the first reset sub-circuit 125 and the second reset sub-circuit 129 are turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2 respectively, and apply the second reset voltage Vinit2 to the first node N1 and the first reset voltage Vinit1 to the first terminal 134 of the light-emitting device 20 respectively, so as to reset the drive sub-circuit 122, the compensation sub-circuit 128 and the light-emitting device 20, and eliminate the influence of the previous light-emitting stage.

[0077] For example, the second reset control signal Rst2 of the sub-pixels in each row may be the same signal as the first scanning signal Ga1 of the sub-pixels in the same row, and both may be transmitted by the same gate line (for example, the reset control line 220b in FIG. 3A). For example, the first reset control signal Rst1 of the sub-pixels in each row may be transmitted by the same gate line (for example, the reset control line 220a in FIG. 3A) as the first scanning signal Ga1 of the sub-pixels in the previous row.

[0078] For example, as shown in FIG. 2A, the light-emitting device 20 includes a first terminal 134 and a second terminal 135. The first terminal 134 of the light-emitting device 20 is configured to be connected to the second terminal 122c of the drive sub-circuit 122, and the second terminal 135 of the light-emitting device 20 is configured to be connected to the second voltage terminal VSS. For example, in one example, as shown in FIG. 2A, the first terminal 134 of the light-emitting device 20 may be connected to the fourth node N4 via the second light-emitting control sub-circuit 124. Embodiments of the present disclosure include, but are not limited to, this.

[0079] In the description of each embodiment of the present invention, note that the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actually existing components, but represent the confluence points of related circuit connections in the circuit diagram.

[0080] In addition, in the description of the embodiments of the present invention, the symbol Vd can represent both a data signal terminal and the level of a data signal. Similarly, the symbols Ga1 and Ga2 can represent a first scanning signal and a second scanning signal, and can also represent a first scanning signal terminal and a second scanning signal terminal. The symbol Rst1 can represent both a first reset control terminal and a first reset control signal, and the symbol Rst2 can represent both a second reset control terminal and a second reset control signal. The symbols Vinit1 and Vinit2 can represent a first reset voltage terminal and a second reset voltage terminal, and can also represent a first reset voltage and a second reset voltage. The symbol VDD can represent both a first power supply voltage and a first power supply line, and the symbol VSS can represent both a common power supply voltage and a common power supply line. Since the following embodiments are the same, they will not be described repeatedly.

[0081] FIG. 2B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 2A. As shown in FIG. 2B, the pixel circuit 10 includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst. For example, the third transistor T3 is used as a driving transistor, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor are used as switching transistors.

[0082] For example, as shown in FIG. 2B, the drive sub-circuit 122 can be implemented as a third transistor T3. The gate electrode of the third transistor T3 functions as the control terminal 122a of the drive sub-circuit 122 and is connected to the first node N1. The first pole of the third transistor T3 functions as the first terminal 122b of the drive sub-circuit 122 and is connected to the second node N2. The second pole of the third transistor T3 functions as the second terminal 122c of the drive sub-circuit 122 and is connected to the third node N3.

[0083] For example, as shown in FIG. 2B, the data writing sub-circuit 126 can be implemented as a fourth transistor T4. The gate electrode T4g of the fourth transistor T4 is connected to the first scanning line (first scanning signal terminal Ga1) to receive the first scanning signal, the first electrode T4s of the fourth transistor T4 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second pole T4d of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the drive sub-circuit 122.

[0084] For example, as shown in FIG. 2B, the compensation sub-circuit 128 can be implemented as a second transistor T2. The gate electrode T2g, the first pole T2s, and the second pole T2d of the second transistor T2 function as the control terminal 128a, the first terminal 128b, and the second terminal 128c of the compensation sub-circuit, respectively. The gate electrode of the second transistor T2 is connected to the second scanning line (second scanning signal terminal Ga2) and configured to receive the second scanning signal. The first pole T2s of the second transistor T2 is connected to the second pole T3d (third node N3) of the third transistor T3, and the second pole T3d of the second transistor T2 is electrically connected to the gate electrode T1g (first node N1) of the third transistor T3. For example, as shown in FIG. 2B, the memory sub-circuit 127 can be implemented as a storage capacitor Cst. The storage capacitor Cst includes a first electrode plate Cst1 electrically connected to the first voltage terminal vdd and a second electrode plate Cst2 electrically connected to the gate electrode T1g (first node N1) of the third transistor T3.

[0085] For example, as shown in FIG. 2B, the first light emission control sub-circuit 123 can be realized as the fifth transistor T5. The fifth transistor T5 is, that is, the first light emission control transistor. The gate electrode T5g of the fifth transistor T5 is connected to the first light emission control line (the first light emission control terminal EM1) to receive the first light emission control signal. The first pole T5s of the fifth transistor T5 is connected to the first voltage terminal vdd to receive the first power supply voltage VDD. The second pole T5d of the fifth transistor T5 is connected to the first terminal 122b (the second node N2) of the drive sub-circuit 122.

[0086] For example, the light emitting device 20 can be realized as a light emitting diode (LED), and for example, it may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or an inorganic light emitting diode. For example, it may be a micro light emitting diode (Micro LED) or a micro OLED. For example, the light emitting device 20 may have a top emission type structure, a bottom emission type structure, or a dual emission type structure. The light emitting device 20 can emit red light, green light, blue light, white light, or the like. The embodiments of the present invention do not limit the specific structure of the light emitting device.

[0087] For example, the first terminal of the light emitting device 20 is connected to the fourth node N4 and includes a first display electrode 21 (shown in FIG. 4A) configured to be connected to the second terminal 122c of the drive sub-circuit 122 via the second light emission control sub-circuit 124. The second terminal 122c of the light emitting device 20 includes a second display electrode (for example, a cathode), and the second display electrode is configured to be connected to the common power supply voltage terminal VSS and receive the common power supply voltage VSS. This common power supply voltage VSS flows from the second terminal 122c of the drive sub-circuit 122 into the circuit of the light emitting device 20 to determine the brightness of the light emitting device. For example, the common power supply voltage terminal VSS can be grounded, that is, VSS may be 0V. For example, the common power supply voltage VSS may be a negative voltage.

[0088] For example, the second light emission control sub-circuit 124 can be realized as the sixth transistor T6. The sixth transistor T6 is, that is to say, the second light emission control transistor. The gate electrode T6g of the sixth transistor T6 is connected to the second light emission control line (the second light emission control terminal EM2) to receive the second light emission control signal. The first pole T6s of the sixth transistor T6 is connected to the second terminal 122c (the third node N3) of the drive sub-circuit 122, and the second pole T6d of the sixth transistor T6 is connected to the first terminal 134 (the fourth node N4) of the light emitting device 20.

[0089] For example, the first reset sub-circuit 125 can be realized as the first transistor T1, that is to say, the second reset sub-circuit 129 can be realized as the seventh transistor T7. The gate electrode T1g of the first transistor T1 is connected to the first reset control terminal Rst1 and configured to receive the first reset control signal Rst1. The first pole T1s of the first transistor T1 is connected to the first reset voltage terminal Vinit1 and configured to receive the first reset voltage Vinit1. The second pole T1d of the first transistor T1 is configured to be connected to the first node N1. The gate electrode T7g of the seventh transistor T7 is connected to the second reset control terminal Rst2 and configured to receive the second reset control signal Rst2. The first pole T7s of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 and configured to receive the second reset voltage Vinit2. The second pole T7d of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0090] Note that the transistors used in the embodiments of the present invention may be thin film transistors, field effect transistors, or other switching devices having the same characteristics. In the embodiments of the present invention, thin film transistors are taken as examples for description. Since the structures of the source electrode and the drain electrode of the transistor used here are symmetric, there is no structural difference between the source electrode and the drain electrode. In the embodiments of the present invention, in order to distinguish the two poles of the transistor excluding the gate electrode, one pole is directly denoted as the first pole and the other pole is denoted as the second pole.

[0091] Also, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other appropriate voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other appropriate voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other appropriate voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other appropriate voltages). For example, as shown in FIG. 2B, the first to seventh transistors T1 to T7 are all P-type transistors such as low-temperature polysilicon thin-film transistors. However, the embodiments of the present invention do not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted as appropriate.

[0092] Combined with the signal timing diagram shown in FIG. 2C, the operating principle of the pixel circuit shown in FIG. 2B will be described below. As shown in FIG. 2C, the display process of the image of each frame includes three stages: an initialization stage 1, a data writing and compensation stage 2, and a light-emitting stage 3.

[0093] For example, referring to FIGS. 2B and 3A - 3B, the first scan signal Ga1 is provided by the first scan signal line Scan(P)(n), the second scan signal Ga2 is provided by the second scan signal line Scan(N)(n), and both the first emission control signal EM1 and the second emission control signal EM2 are provided by the emission control line EM(P)(n). FIG. 2C is a signal timing diagram of a driving method of a pixel circuit provided according to at least one embodiment of the present invention. As shown in FIG. 2C, in this embodiment, the first scan signal Ga1 and the second scan signal Ga2 employ the same signal, and the first emission control signal EM1 and the second emission control signal EM2 employ the same signal. For example, the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 can also use the same signal, that is, the second reset control signal Rst2 and the first scan signal Ga1 / second scan signal Ga2 have the same waveform, that is, the first reset signal Rst1 of the sub - pixels in this row has the same waveform as the first scan signal Ga1 / second scan signal Ga2 of the sub - pixels in the previous row, that is, the same signal is used. However, this does not limit the present invention. In other embodiments, different signals can be used as the first scan signal Ga1, the second scan signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first emission control signal EM1 and the second emission control signal EM2.

[0094] In the first initialization stage, the first reset control signal Rst1 is input to turn on the first transistor T1, and the first reset voltage Vinit1 is applied to the gate electrode of the third transistor T3 to reset the first node N1.

[0095] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2 (i.e., the compensation scanning signal), and the data signal Vd are input, the fourth transistor T4 and the second transistor T2 are turned on, the data signal Vd is written into the second node N2 by the fourth transistor T4, the potential of the first node N1 changes to Vd + Vth, and until the third transistor T3 is turned off, the first node N1 is charged through the third transistor T3 and the second transistor T2, where Vth is the threshold voltage of the third transistor. The potential of the first node N1 is stored and maintained in the storage capacitor Cst, that is, the voltage information including the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, and in the subsequent light emission stage, it is used to provide grayscale display data to compensate for the threshold voltage of the third transistor T3 itself.

[0096] In the data writing compensation stage 2, the second reset control signal Rst2 is input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4 to reset the fourth node N4. For example, the fourth node N4 may be reset in the initialization stage 1. For example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiments of the present invention are not limited thereto.

[0097] In the light emission stage 3, the first light emission control signal EM1 and the second light emission control signal EM2 are input to turn on the fifth transistor T5, the sixth transistor T6, and the third transistor T3, and the sixth transistor T6 applies a driving current to the OLED to cause it to emit light. The value of the driving current Id flowing through the OLED is obtained by the following formula. Id = K(VGS - Vth)2 = K[(Vd + Vth - VDD) - Vth]2 = K(Vd - VDD)2

[0098] Here, K is the conductivity of the first transistor.

[0099] In the above formula, Vth represents the threshold voltage of the third transistor T3, VGS is the voltage between the gate electrode and the source electrode (here, the first electrode) of the third transistor T3, and K is a constant value related to the third transistor T3 itself. From the above calculation formula of Id, it can be seen that the drive current Id flowing through the OLED has nothing to do with the threshold voltage Vth of the third transistor T3. Thereby, the compensation of the pixel circuit can be realized, and the problem of threshold voltage drift of the drive transistor (in the embodiment of the present invention, the third transistor T3) due to the process and long-time operation can be solved, the influence on its drive current Id can be eliminated, and the display effect of the display device can be improved.

[0100] FIG. 3A is a schematic plan view of a laminate of a first semiconductor layer and a first conductive layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3B is a schematic plan view of a laminate of a second conductive layer and a second semiconductor layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3C is a schematic plan view of a laminate of a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3D is a schematic plan view of a laminate of a second conductive layer and a third conductive layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3E is a schematic plan view of a laminate of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3F is a schematic plan view of a laminate of a first interlayer insulating layer and a fourth conductive layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3G is a schematic plan view of a laminate of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer of a sub-pixel, and a laminate of a first interlayer insulating layer and a fourth conductive layer according to an embodiment of the present invention. FIG. 3H is a schematic plan view of a laminate of a first planarization layer and a fifth conductive layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3I is a schematic plan view of a laminate of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer of a sub-pixel, and a laminate of a first interlayer insulating layer, a fourth conductive layer, a first planarization layer, and a fifth conductive layer according to an embodiment of the present invention. FIG. 3J is a schematic plan view of a laminate of a second planarization layer, a first display electrode, and a pixel defining layer of a sub-pixel of a display substrate provided according to an embodiment of the present invention. FIG. 3K is a schematic plan view of a sub-pixel of a display substrate provided according to an embodiment of the present invention, that is, a schematic plan view of a laminate of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a second conductive layer of a sub-pixel, a laminate of a first interlayer insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, a second planarization layer, a first display electrode, and a pixel defining layer. FIG. 4A is a schematic cross-sectional view taken along the active layer direction of the third transistor and the sixth transistor in FIG. 3K in sequence. FIG. 4B is a schematic structural view of the display substrate.

[0101] As shown in FIGS. 3A to 3I and FIG. 4A, the display substrate 10 includes a base substrate 200, a first signal line that extends entirely along the second direction D2 on the base substrate 200, and a second signal line that extends entirely along the first direction D1 intersecting the second direction D2. For example, the first signal line and the second signal line intersect to define a plurality of sub-pixels 100. Note that the boundary of each of the plurality of sub-pixels is not necessarily the first signal line and the second signal line. The fact that the first signal line and the second signal line intersect to define a plurality of sub-pixels means that the arrangement method of the plurality of sub-pixels is consistent with the arrangement method of the plurality of regions defined by the intersection of the first signal line and the second signal line. That is, it means that the plurality of sub-pixels correspond one-to-one to the plurality of regions defined by the intersection of the first signal line and the second signal line. For example, the first signal line is a gate line as a scanning signal line, the second signal line is a data line, or in some other embodiments, the first signal line is a data line and the second signal line is a gate line as a scanning signal line.

[0102] In the present invention, "extending entirely along the second direction" means extending substantially along the second direction, and it is only necessary that at least the overall extending tendency extends along the second direction. For example, taking the first signal line as an example, in some examples, the first signal line extending entirely along the second direction may have a specific curved portion. For example, it can include a corrugated portion. Alternatively, in some examples, the edge of the first signal line extending along the second direction that extends entirely along the second direction does not have to be a smooth line. For example, there may be burrs or jagged edges on the edge of the first signal line. In short, the first signal line only needs to satisfy the condition of being in a strip shape that extends entirely along the second direction. Similarly, the same applies to "extending entirely along the first direction". For example, the data line extends entirely along the first direction. As a further example, the following first connection structure extends entirely along the first direction.

[0103] Each of at least some of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes the light-emitting device 20, the driving transistor T1, and the data writing transistor T2 described above. For example, at least some of the sub-pixels refer to sub-pixels that execute a display function, rather than dummy sub-pixels.

[0104] As shown in FIGS. 3F and 3I, the pixel circuit further includes a first connection structure C1 connected to the gate electrode T3g of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor Cst. Both the data line Data and the first connection structure C1 extend entirely along the first direction D1. The data line Data includes an overlapping portion D0, and the first connection structure C1 is at least partially opposed to the overlapping portion D0 of the data line Data, that is, the overlapping portion D0 of the first connection structure C1 and the data line Data are at least partially opposed to each other in the second direction D2. The second direction D2 is parallel to the base substrate 200 and perpendicular to the first direction D1. For example, the entire overlapping portion D0 and the first connection structure C1 are arranged to face each other in the second direction D2. The overlapping portion D0 of the first connection structure C1 and the data line Data are insulated from each other, and the overlapping portion D0 of the first connection structure C1 and the data line Data constitute the first electrode plate and the second electrode plate of the parasitic capacitance Cgd, respectively. The ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01. From this, according to experiments, when the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor is less than 0.01, the loss of the voltage (i.e., the data signal) charged in the storage capacitor Cgd is at most 1% (a deviation of 1%), and the loss of the OLED driving current is at most 1% (a deviation of 1%). It has been found that the deviation of the emission luminance can be controlled within a small range. By controlling the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor within this range, the parasitic capacitance Cgd can be reduced while realizing a high PPI, and the influence of the jump voltage of the data line during the display process on the driving voltage of the driving transistor T3 can be significantly reduced, realizing a higher display quality.

[0105] Taking one sub-pixel as an example, for instance, as shown in FIG. 3K, in at least one embodiment, the size S (Pixel Pitch) of the sub-pixel 100 in the second direction D2 is greater than 50 μm, and the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.005. According to experiments, in a display substrate having sub-pixels of this size, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.005, significantly reducing the influence of the jump voltage of the data line Data on the drive voltage of the drive transistor T3 during the display process, realizing a high PPI and achieving a better display effect. In particular, in a large display substrate or display panel exceeding 55 inches, while achieving a high PPI, the effect of reducing the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 during the display process is particularly remarkable.

[0106] For example, as shown in FIG. 3K, in at least one embodiment, the size S of one sub-pixel 100 in the second direction D2 is 68 μm or less, and the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is 0.003 or more. According to experiments, in a display substrate having sub-pixels of this size, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst can be made 0.003 or more. In this case, during the display process, the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 is significantly reduced, and at the same time, a high PPI is achieved and a better display effect is obtained. In particular, in a large display substrate or display panel exceeding 55 inches, while achieving a high PPI, the effect of reducing the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 during the display process is particularly remarkable.

[0107] For example, as shown in FIG. 3K, in at least one embodiment, the size S of one sub-pixel 100 in the second direction D2 is less than 50 μm, and the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is greater than 0.005 and less than 0.006. According to experiments, in a display substrate having sub-pixels of this size, the size of a single sub-pixel is small and a high PPI is achieved. In this case, the influence of the jump voltage of the data line Data on the drive voltage of the drive transistor T3 becomes large, and since the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is greater than 0.004 and less than 0.006, during the display process, it is possible to reduce the influence of the jump voltage of the data line Data on the drive voltage of the drive transistor T3 while realizing a high PPI, achieving these two requirements and obtaining a better display effect. In particular, in a large display substrate or display panel with a size exceeding 55 inches, the effect of reducing the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 during the display process is particularly remarkable.

[0108] FIG. 5 is a schematic plan view of at least two adjacent sub-pixels of a display substrate provided according to an embodiment of the present invention. FIG. 6 is a schematic view after removing the first power line based on FIG. 5. For example, as shown in FIGS. 5 to 6, a plurality of sub-pixels 100 include a first sub-pixel P1 and a second sub-pixel P2 adjacent to each other in the second direction D2. In one sub-pixel, for example, the first sub-pixel P1, the first connection structure C1 includes a first portion C11 extending along the first direction D1 and a second portion C12 extending along the second direction, and the second portion is connected to the first portion C11. An edge of the first portion C11 close to the overlapping portion D0 of the data line Data is the first edge 1a, the first portion C11 has a second edge 1b away from the overlapping portion D0 of the data line Data, and an edge of the overlapping portion D0 of the data line Data close to the first connection structure C1 is the third edge 1c. For the adjacent first sub-pixel P1 and second sub-pixel P2, the distance between the orthographic projection of the second edge 1b of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data of the second sub-pixel P2 on the base substrate 200 is the first distance L1, that is, the distance (round number 6) in FIGS. 4A and 6. The distance between the first edge 1a of the first connection structure C1 of the first sub-pixel P1 and the first edge 1c of the overlapping portion D0 of the data line Data of the first sub-pixel P1 is the second distance L2, that is, the distance (round number 7) in FIG. 6. The ratio of the first distance L1 to the second distance L2 is greater than 14. In this way, on the one hand, it can be ensured that the first connection structure C1 of this sub-pixel is sufficiently separated from the data line Data of the adjacent sub-pixel, and the distance L1 is greater than 14 times the distance L2 between the first connection structure C1 of this sub-pixel and the data line Data of this sub-pixel. Thereby, the parasitic capacitance Cgd formed in the first connection structure C1 of this sub-pixel by the data line Data of the adjacent sub-pixel is significantly reduced. As a result, during the display process, the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 is significantly reduced, and the display quality is improved.

[0109] For example, the above definitions of the first distance L1 and the second distance L2 are applicable to any sub-pixel within the pixel array of the display substrate. Therefore, the following description of the first distance L1 in the second sub-pixel P2 is the same.

[0110] When comparing the display substrate shown in FIG. 4B with the display substrate provided by an embodiment of the present application shown in FIGS. 5 to 6 of the present invention, in the display substrate shown in FIG. 4B, data lines Data1' and Data2' are respectively provided at positions close to the left and right sides of the first connection structure C1' of the sub-pixel. As a result, a large parasitic capacitance is also generated in the first connection structure C1' and the Data1' and Data2' on its left and right sides, which has a very large impact on the display quality. However, in the display substrate provided by an embodiment of the present application shown in FIGS. 5 to 6 of the present invention, since the ratio of the first distance L1 to the second distance L2 is greater than 14, this problem can be better avoided.

[0111] For example, in at least one embodiment, the size S of one sub-pixel 100 in the second direction D2 is less than 50 μm, and the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5. According to experiments, in a display substrate where the size S of the sub-pixel is less than 50 μm, the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5, reducing the parasitic capacitance Cgd and achieving a high PPI. In particular, in a large display substrate or display panel exceeding 55 inches, while achieving a high PPI, the effect of reducing the influence of the jump voltage on the data line Data on the drive voltage of the drive transistor T3 during the display process is particularly remarkable.

[0112] For example, in at least one embodiment, the size S of one sub-pixel 100 in the second direction D2 is greater than 50 μm, for example, 50 μm < size S < 68 μm, and the ratio of the first distance L1 to the first distance L1 is greater than 15.5. According to experiments, in a display substrate where the size S of the sub-pixel is less than 50 μm, the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5. While reducing the parasitic capacitance Cgd and achieving a high PPI, especially in a large display substrate or display panel exceeding 55 inches, it has been found that the effect of reducing the influence of the jump voltage on the data line Data on the driving voltage of the driving transistor T3 during the display process while achieving a high PPI is particularly remarkable.

[0113] For example, in the embodiments shown in FIGS. 5 to 6, the first connection structure C1 of the first sub-pixel P1 is positioned between the data line Data1 of the first sub-pixel P1 and the data line Data1 of the second sub-pixel P2 in the second direction D2. In FIGS. 5 to 6, the data line Data2 located on the left side of the data line Data1 of the first sub-pixel P1 and adjacent thereto is the data line of a sub-pixel (not shown in its entirety) adjacent to the left side of the first sub-pixel P1. The data line Data2 located on the right side of the data line Data1 of the second sub-pixel P2 and adjacent thereto is the data line of a sub-pixel (not shown in its entirety) adjacent to the right side of the second sub-pixel P2. For example, the distance between the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the data line Data of the first sub-pixel P1 on the base substrate 200 is smaller than the size of one sub-pixel 100 in the second direction D2, and the distance between the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the data line Data of the second sub-pixel P2 on the base substrate 200 is larger than the size of one sub-pixel 100 in the second direction D2. For example, at least the first connection structure C1 and the data line Data of the adjacent first sub-pixel P1 and second sub-pixel P2 are symmetric (mirror symmetric) with respect to the symmetry axis extending along the first direction. In this way, by making the ratio of the first distance L1 to the second distance L2 as large as possible, that is, by making the distance between the data line Data of the second sub-pixel P1 and the first connection structure of the first sub-pixel P1 as large as possible, the length in the first direction is utilized to the maximum extent to design the layout of the pixel circuit and realize a higher PPI.

[0114] Alternatively, in other embodiments, for example, the distance between the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the data line Data of the first sub-pixel P1 on the base substrate 200 is smaller than the size S of one sub-pixel in the second direction D2, and the distance between the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the data line Data of the second sub-pixel P2 on the base substrate 200 is smaller than the size S of one sub-pixel 100 in the second direction D2. That is, at least the first connection structure C1 and the data line Data of the adjacent first sub-pixel P1 and second sub-pixel P2 are asymmetric (non-mirror symmetric) with respect to the axis extending along the first direction. The embodiments of the present invention do not limit the specific positions of each structure of the pixel circuit as long as the relationship between the above-mentioned first distance L1 and second distance L2 is satisfied.

[0115] For example, as shown in FIGS. 5 to 6, the edge of the gate electrode T3g of the driving transistor T3 of the first sub-pixel P1 close to the overlapping portion D0 of the data line Data of the second sub-pixel P2 is the fourth edge 1d, and the distance between the second edge 1b of the first sub-pixel P1 and the third edge 1c of the second sub-pixel P2 is equal to the sum of the distance between the second edge 1b of the first sub-pixel P1 and the fourth edge 1d of the first sub-pixel P1 and the distance between the fourth edge 1d of the first sub-pixel P1 and the third edge 1c of the second sub-pixel P2.

[0116] For example, referring to FIG. 4A, the first connection structure C1 and the data line Data are arranged in different layers, and the orthographic projection of the first connection structure C1 on the base substrate 200 does not overlap with the orthographic projection of the overlapping portion D0 of the data line Data on the base substrate 200. Alternatively, in some other embodiments, the first connection structure C1 and the data line Data are arranged in different layers, and the orthographic projection of the first connection structure C1 on the base substrate 200 at least partially overlaps with the orthographic projection of the overlapping portion D0 of the data line Data on the base substrate 200.

[0117] Figure 4C is a schematic diagram of a parallel plate capacitor with opposing electrodes. Figure 4D is a schematic diagram of a parallel plate capacitor with offset electrodes. Referring to Figure 4C, a parallel plate capacitor with opposing electrodes means that two electrode plates of a parallel plate capacitor, such as electrode 1 and electrode 2, face each other, that is, the opposing surfaces of electrode 1 and electrode 2 are parallel to each other, and the orthographic projections of electrode 1 and electrode 2 on a plane parallel to the opposing surfaces overlap. Referring to Figure 4D, a parallel plate capacitor with offset electrodes means that the opposing surfaces of two electrode plates of a parallel plate capacitor, such as electrode 1 and electrode 2, are parallel to each other, and the orthographic projections of electrode 1 and electrode 2 on a plane parallel to the opposing surfaces partially overlap or do not overlap. The capacitance value of the parasitic capacitance within the scope of protection of the claims of the present invention shall follow the calculation method described later in the specification.

[0118] In the case of the parallel plate capacitor with opposing electrodes shown in Figure 4C and the parallel plate capacitor with offset electrodes shown in Figure 4D, the parallel plate capacitor C formed by electrode 1 and electrode 2 as the two electrode plates of the two capacitors satisfies Equation (1). [Equation 1] C = ε × A / d

[0119] In the formula, A represents the overlapping surface area of the two electrodes 1 and 2, and d represents the distance traveled by the power lines. According to Equation (1), in the embodiment shown in Figure 4A, C gd represents the capacitance value of the parasitic capacitance Cgd, and C gd satisfies Equation (2). [Equation 2] Cgd = ε × A / d = ε PI × (W sd1 × w sd1 ) / (t 2 PLN1 + d 2 sd1 ) 1 / 2

[0120] Referring to Figure 4A, ε PI represents the dielectric constant of the medium between the overlapping portion D0 of the data line Data and the first connection structure C1.

[0121] A represents the equivalent overlapping area between the overlapping portion D0 of the data line Data and the first connection structure C1. As shown in FIG. 4D, in a parallel plate capacitor where the electrodes are arranged with a shift, the equivalent overlapping area is the area of the surface where electrode 1 and electrode 2 face each other and the power lines are evenly distributed. For example, when the orthographic projection of the overlapping portion D0 of the data line Data on the base substrate 200 and the orthographic projection of the first connection structure C1 on the base substrate 200 do not overlap or at least partially overlap, the overlapping portion D0 of the data line Data and the first connection structure C1 are equivalent to electrode 1 and electrode 2 in FIG. 4D, respectively. d represents the distance that the power line moves. W sd1 represents the width of the first connection structure C1 in the second direction D2, that is, the distance (round number 5). w sd1 represents the length of the first connection structure C1 in the first direction D1. t PLN1 represents the distance between the first connection structure C1 and the data line Data in the direction perpendicular to the base substrate 200. d sd1 represents the distance between the first edge 1a of the first connection structure C1 and the third edge 1c of the data line Data in one sub-pixel, that is, the second distance L2.

[0122] Hereinafter, as an example, the parasitic capacitance Cgd formed by the first connection structure C1 and the overlapping portion D0 of the data line Data adjacent to each other within the sub-pixel is calculated. Other parallel plate capacitors can also refer to this calculation method.

[0123] For example, in one example, referring to FIGS. 4A and 6, when FIG. 4A is taken as the cross-sectional view of the second sub-pixel P2, S = 51.4 μm (greater than 50 μm) and Cst = 42 fF. Each distance is as follows. (Circle number 1) represents the distance between the data line Data1 of the first sub-pixel P1 and the data line Data2 of a sub-pixel adjacent to the first sub-pixel P1 and asymmetric to the first sub-pixel P1 (the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other form one repeating unit, and the sub-pixel adjacent to the first sub-pixel P1 on the side away from the second sub-pixel P2 of the first sub-pixel P1 belongs to another repeating unit). For example, (circle number 1) = 3.4 μm. (Circle number 2) represents the distance between the data line Data1 in the second sub-pixel P2 and the edge of the gate electrode T3g of the driving transistor T3 that is close. For example, (circle number 2) = 1.4 μm. (Circle number 3) represents the width of the gate electrode T3g of the driving transistor T3 in the second direction D2. For example, (circle number 3) = 11.5 μm. (Circle number 4) represents the distance between the first edge 1a of the first connection structure C1 on the gate electrode T3g of the driving transistor T3 of the second sub-pixel P2 and the edge of the gate electrode T3g of the driving transistor T3 close to the data line Data1 of the second sub-pixel. For example, (circle number 4) = 4 μm. (Circle number 5) represents the width of the first connection structure C1 of the gate electrode T3g of the driving transistor T3 in the second direction D1. For example, (circle number 5) = 5.4 μm. (Circle number 6) represents the distance between the second edge 1b of the first connection structure C1 and the third edge 1c of the overlapping part D0 of the data line Data1 of the first sub-pixel P1 in one sub-pixel, for example, the second sub-pixel P2, that is, the above-mentioned first distance L1. For example, in this example, (circle number 6) = (circle number 2) + (circle number 4) = 5.4 μm. (Round number 7) represents the distance between the orthographic projection of the first edge 1a of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data1 of the second sub-pixel P2 on the base substrate 200, that is, the second distance L2. For example, in this example, since the line width Data Width of one data line Data1 (for example, the line widths of multiple data lines are basically the same) = 2.5μm, (round number 7) = 2×S - (round number 1) - 2×Data Width (line width of the data line, for example, the line widths of multiple data lines are basically the same) - (round number 6) - (round number 5) = 2×51.4 - 3.4 - 2×2.5 - 5.4 - 5.4 = 83.6μm.

[0124] Therefore, (round number 7) / (round number 6) = 15.48, that is, L2 / L1 = 15.48, satisfying that the ratio of the first distance L1 to the second distance L2 is greater than 14.

[0125] Based on the above sizes, for example, ε PI = 4.0, t PLN1 = 1.24μm, d sd1 = L2 = (round number 6) = 5.4μm, W sd1 = 5.4μm, w sd1 = 5.4μm.

[0126] For example, as shown in FIG. 5, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are mirror-symmetric with respect to the symmetry axis extending along the first direction, since the first connection structure C1 of the sub-pixel forms the parasitic capacitance Cgd only with the data line Data located on one side thereof in the second direction D2, the calculated Cgd = 0.186fF is much smaller than Cst = 42fF, and Cgd / Cst = 4.4×10 -3 and the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.005.

[0127] For example, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are non-mirror-symmetric, for example, in the second direction D2, at positions where the distances to the first connection structure C1 on both sides of the first connection structure C1 of one sub-pixel are basically equal, data lines Data are respectively provided, and the parasitic capacitance formed is about twice the parasitic capacitance during mirror design, that is, Cgd = 2×0.186 fF = 0.11 fF, Cgd / Cst = 8.8×10 -3 is. Compared with the non-mirror design, when other conditions are the same, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst in the mirror design is smaller. In this case, the influence of the jump voltage on the data line Data of the display panel on the drive voltage of the drive transistor T3 is reduced, and the display effect is better.

[0128] For example, in another example, referring to FIGS. 4A and 6, when FIG. 4A is taken as a cross-sectional view of the second sub-pixel P2, S = 45.2 μm (smaller than 50 μm) and Cst = 42 fF. According to the same design rules, the following distances are calculated based on the ratio of the value of S in this example to the value of S in the example of S = 51.4, and thus the distances are as follows. (Round number 1) represents the distance between the data line Data1 of the first sub-pixel P1 and the data line Data2 of the sub-pixel adjacent to the first sub-pixel P1 and asymmetric with the first sub-pixel P1 (the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other form one repeating unit, and the sub-pixel adjacent to the first sub-pixel P1 on the side away from the second sub-pixel P2 of the first sub-pixel P1 belongs to another repeating unit). For example, (round number 1) = 3.4×45.2 / 51.4 = 3 μm. (Round number 5) represents the width of the first connection structure C1 of the gate electrode T3g of the drive transistor T3 in the second direction D1. For example, (round number 5) = 5.4×45.2 / 51.4 = 4.75 μm. (Circle number 6) represents the distance, i.e., the first distance L1, between the second edge 1b of the first connection structure C1 and the third edge 1c of the overlapping portion D0 of the data line Data1 of the first sub-pixel P1 in one sub-pixel, for example, the second sub-pixel P2. For example, in this example, (circle number 6) = 5.4×45.2 / 51.4 = 4.75 μm. (Circle number 7) represents the distance, i.e., the second distance L2, between the orthographic projection of the first edge 1a of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data1 of the second sub-pixel P2 on the base substrate 200. For example, in this example, since the line width Data Width of one data line Data1 (for example, the line widths of a plurality of data lines are basically the same) = 2.5 μm, (circle number 7) = 2×S - (circle number 1) - 2×Data Width - (circle number 6) - (circle number 5) = 2×45.2 -3 - 2×2.5 - 4.75 - 4.75 = 73.9 μm.

[0129] Therefore, (circle number 7) / (circle number 6) = 15.56, i.e., L2 / L1 = 15.56, satisfying that the ratio of the first distance L1 to the second distance L2 is greater than 14.

[0130] Based on the above sizes, for example, ε PI = 4.0, t PLN1 = 1.05 μm, d sd1 = L2 = (circle number 6) = 5.4×45.2 / 51.4 = 4.75 μm, W sd1 = 5.4×45.2 / 51.4 = 4.75 μm, w sd1 = 4.75 μm.

[0131] For example, as shown in FIG. 5, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other is mirror-symmetric with respect to the axis of symmetry along which the data line Data extends in the first direction, since the first connection structure C1 of the sub-pixel forms a parasitic capacitance Cgd only with the data line Data located on one side thereof in the second direction D2, the calculated Cgd = 0.168 fF is much smaller than Cst = 29.2 fF, and Cgd / Cst = 5.75×10 -3 results in a ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst being greater than 0.005.

[0132] For example, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are non-mirror-symmetric, for example, in the second direction D2, at positions where the distances from both sides of the first connection structure C1 of one sub-pixel to the first connection structure C1 are basically equal, data lines Data are respectively provided, and the formed parasitic capacitance is about twice the parasitic capacitance during mirror design, that is, Cgd = 2×0.168 fF = 0.33 fF, Cgd / Cst = 10×10 -3 results. Compared with non-mirror design, when other conditions are the same, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst in mirror design is smaller. In this case, the influence of the jump voltage on the data line Data of the display panel on the drive voltage of the drive transistor T3 is reduced, and the display effect is better.

[0133] For example, in yet another example, referring to FIGS. 4A and 6, when FIG. 4A is taken as a cross-sectional view of the second sub-pixel P2, S = 68 μm and Cst = 51.4 fF. Each distance is as follows. (Round number 1) represents the distance between the data line Data1 of the first sub-pixel P1 and the data line Data2 of a sub-pixel adjacent to the first sub-pixel P1 and asymmetric with the first sub-pixel P1 (the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other form one repeating unit, and the sub-pixel adjacent to the first sub-pixel P1 on the side away from the second sub-pixel P2 of the first sub-pixel P1 belongs to another repeating unit). For example, (round number 1) = 5.3 μm. (Round number 2) represents the distance between the data line Data1 in the second sub-pixel P2 and the adjacent edge of the gate electrode T3g of the driving transistor T3. For example, (round number 2) = 2.9 μm. (Round number 3) represents the width of the gate electrode T3g of the driving transistor T3 in the second direction D2. For example, (round number 3) = 12 μm. (Round number 4) represents the distance between the first edge 1a of the first connection structure C1 on the gate electrode T3g of the driving transistor T3 in the second sub-pixel P2 and the edge of the gate electrode T3g of the driving transistor T3 close to the data line Data1 of the second sub-pixel. For example, (round number 4) = 4.3 μm. (Round number 5) represents the width of the first connection structure C1 of the gate electrode T3g of the driving transistor T3 in the second direction D1. For example, (round number 5) = 7.5 μm. (Round number 6) represents the distance between the second edge 1b of the first connection structure C1 and the third edge 1c of the overlapping part D0 of the data line Data1 of the first sub-pixel P1 in one sub-pixel, for example, the second sub-pixel P2, that is, the above-mentioned first distance L1. For example, in this example, (round number 6) = (round number 2) + (round number 4) = 7.2 μm. (Round number 7) represents the distance between the orthographic projection of the first edge 1a of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data1 of the second sub-pixel P2 on the base substrate 200, that is, the second distance L2. For example, in this example, since the line width Data Width of one data line Data1 (for example, the line widths of multiple data lines are basically the same) = 2.4μm, (round number 7) = 2×S - (round number 1) - 2×Data Width (line width of the data line, for example, the line widths of multiple data lines are basically the same) - (round number 6) - (round number 5) = 2×68 - 5.3 - 2×2.4 - 7.2 - 4.3 = 114.4μm.

[0134] Therefore, (round number 7) / (round number 6) = 15.9, that is, L2 / L1 = 15.9, satisfying that the ratio of the first distance L1 to the second distance L2 is greater than 14.

[0135] Based on the above sizes, for example, ε PI = 4.0, t PLN1 = 1.24μm, d sd1 = L2 = (round number 6) = 7.2μm, W sd1 = 7.5μm, w sd1 = 4.3μm.

[0136] For example, as shown in FIG. 5, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are mirror-symmetric with respect to the symmetry axis extending along the first direction, since the first connection structure C1 of the sub-pixel forms the parasitic capacitance Cgd only with the data line Data located on one side thereof in the second direction D2, the calculated Cgd = 0.155fF is much smaller than Cst = 51.4fF, and Cgd / Cst = 3×10 -3That is, when S = 68 μm, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is equal to 0.003. When S is less than 68 μm, that is, when the width of a single sub-pixel is small, in order to achieve a high PPI, the space limitation becomes large. Therefore, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst satisfies being less than 0.003.

[0137] For example, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are non-mirror-symmetrical, for example, in the second direction D2, at positions where the distances to the first connection structure C1 on both sides of the first connection structure C1 of one sub-pixel are substantially equal, data lines Data are respectively provided, and the formed parasitic capacitance is about twice the parasitic capacitance during mirror design. That is, Cgd = 2×0.155 fF = 0.31 fF, Cgd / Cst = 6×10 -3 It becomes like this. Compared with non-mirror design, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst in the mirror design when the above other conditions are the same is smaller. In this case, the influence of the jump voltage on the data line Data of the display panel on the driving voltage of the driving transistor T3 becomes smaller, and the display effect is better.

[0138] For example, in yet another example, referring to FIGS. 4A and 6, when FIG. 4A is taken as a cross-sectional view of the second sub-pixel P2, S = 49.3 μm (smaller than 50 μm) and Cst = 44.8 fF. Each distance is as follows. (Circle number 1) represents the distance between the data line Data1 of the first sub-pixel P1 and the data line Data2 of a sub-pixel adjacent to the first sub-pixel P1 and non-symmetrical to the first sub-pixel P1 (the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other form one repeating unit, and the sub-pixel adjacent to the first sub-pixel P1 on the side away from the second sub-pixel P2 of the first sub-pixel P1 belongs to another repeating unit). For example, (circle number 1) = 3.3 μm. (Round number 2) represents the distance between the adjacent edges of the data line Data1 and the gate electrode T3g of the driving transistor T3 in the second sub-pixel P2. For example, (round number 2) = 12.5 μm. (Round number 3) represents the width of the gate electrode T3g of the driving transistor T3 in the second direction D2. For example, (round number 3) = 11.7 μm. (Round number 4) represents the distance between the first edge 1a of the first connection structure C1 on the gate electrode T3g of the driving transistor T3 in the second sub-pixel P2 and the edge of the gate electrode T3g of the driving transistor T3 close to the data line Data1 of the second sub-pixel. For example, (round number 4) = 3.3 μm. (Round number 5) represents the width of the first connection structure C1 of the gate electrode T3g of the driving transistor T3 in the second direction D1. For example, (round number 5) = 6 μm. (Round number 6) represents the distance between the edge of the first connection structure in one sub-pixel that is away from the overlapping portion of the data line of the sub-pixel and the edge of the overlapping portion of the data line of the sub-pixel adjacent to the sub-pixel. In this example, (round number 6) = 2 μm. (Round number 7) represents the distance between the orthographic projection of the first edge 1a of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data1 of the second sub-pixel P2 on the base substrate 200, that is, the second distance L2. For example, in this example, since the line width Data Width of one data line Data1 (for example, the line widths of multiple data lines are basically the same) = 2.4 μm, (round number 7) = 28.3 μm.

[0139] Therefore, (round number 7) / (round number 6) = 14.15, that is, L2 / L1 = 14.15, satisfying that the ratio of the first distance L1 to the second distance L2 is greater than 14.

[0140] Based on the above sizes, for example, ε PI = 4.0, t PLN1 = 1.36 μm, d sd1 = L2 = (round number 6) = 4 μm, W sd1=6 μm, w sd1 becomes 9 μm.

[0141] For example, as shown in FIG. 5, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are mirror-symmetrical with respect to the symmetry axis extending along the first direction, the first connection structure C1 of the sub-pixel forms a parasitic capacitance Cgd only with the data line Data located on one side thereof in the second direction D2. Therefore, the calculated Cgd = 0.24 fF is much smaller than Cst = 44.8 fF, and Cgd / Cst = 5.4×10 -3 and, that is, when S is less than 50 μm, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is greater than 0.005 and less than 0.006. When S is less than 50 μm, that is, when the width of a single sub-pixel is smaller, the space limitation for realizing a high PPI becomes greater. Therefore, it satisfies that the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.003.

[0142] For example, when the first connection structure C1 of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other and the data line Data are non-mirror-symmetrical, for example, at positions in the second direction D2 where the distances from both sides of the first connection structure C1 of one sub-pixel to the first connection structure C1 are basically equal, data lines Data are respectively provided, and the formed parasitic capacitance is about twice the parasitic capacitance during mirror design, that is, Cgd = 2 * 0.24 fF = 0.48 fF, Cgd / Cst = 10.8×10 -3 and. Compared with the non-mirror design, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst in the mirror design when the other above conditions are the same is smaller. In this case, the influence of the jump voltage on the data line Data of the display panel on the driving voltage of the driving transistor T3 becomes smaller, and the display effect is better.

[0143] In the above embodiment, as an example, the first connection structure C1 and the data line Data are arranged in different layers. Naturally, in some other embodiments, the first connection structure C1 may be arranged in the same layer as the data line Data, and the overlapping portion D0 between the first connection structure C1 and the data line Data faces each other in the second direction D2. The present invention is not limited to the case where the first connection structure C1 and the data line Data are arranged in different layers as long as the ratio of the first distance L1 to the second distance L2 is greater than 14.

[0144] FIG. 4E is yet another schematic cross-sectional view of a display substrate provided according to an embodiment of the present invention. For example, in at least one embodiment, as shown in FIG. 4E, the first electrode plate Cst1 of the storage capacitor Cst has an upper surface T01 away from the base substrate 200 and a side surface S01 intersecting the upper surface T01. The second electrode plate Cst2 of the storage capacitor Cst includes an intermediate portion CM and an edge portion CP. The orthographic projection of the intermediate portion CM on the base substrate 200 at least partially overlaps the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base substrate 200. The intermediate portion CM includes a bottom surface B01 facing the upper surface T01 of the first electrode plate Cst1 of the storage capacitor Cst. The edge portion CP at least partially surrounds the intermediate portion CM, is connected to the intermediate portion CM, and includes a bottom surface B02 close to the base substrate 200 and an inner side surface S02 intersecting the bottom surface B02. The inner side surface S02 faces the side surface S01 of the first electrode plate Cst1 of the storage capacitor Cst. The orthographic projection of the inner side surface S02 on a reference plane perpendicular to the base substrate 200 at least partially overlaps the orthographic projection of the side surface S01 of the first electrode plate Cst1 of the storage capacitor Cst facing the inner side surface S02 on the reference plane. The distance S1 between the inner side surface S02 of the edge portion CP and the side surface of the first electrode plate Cst1 of the storage capacitor Cst facing the inner side surface S02 is smaller than the distance S2 between the bottom surface of the intermediate portion CM and the upper surface of the first electrode plate Cst1 of the storage capacitor Cst. Thereby, a larger capacitance value of the storage capacitor Cst can be achieved by utilizing limited space, the charge storage capacity of the storage capacitor Cst is improved, the ratio of the parasitic capacitance Cgd formed by the overlapping portion D0 of the first connection structure C1 and the data line Data to the storage capacitance Cs is reduced, the influence of the parasitic capacitance Cgd on the display effect is mitigated, and the display effect is improved.

[0145] To clearly explain the structural features of the sub-pixel, the structure of each layer of the sub-pixel will be introduced below with examples.

[0146] For example, in conjunction with FIGS. 3A to 3I and FIG. 4A, the display substrate 10 is disposed on the base substrate 200 and includes a stacked body of a first semiconductor layer Active1, a first conductive layer Gate1, a second conductive layer Gate2, a second semiconductor layer Active2, a third conductive layer Gate3, an interlayer insulating layer ILD, a fourth conductive layer SD1, a first planarization layer PLN1, and a fifth conductive layer SD2, which are sequentially arranged in a direction away from the base substrate 200.

[0147] As shown in FIG. 3A, the first signal line includes a first scan signal line Scan(P)(n), a light emission control line EM(P)(n), and a second reset scan signal line Scan(P)(n + 1). For example, the first scan signal line Scan(P)(n), the light emission control line EM(P)(n), and the second reset scan signal line Scan(P)(n + 1) are located in the first conductive layer Gate1 and extend generally along the second direction D2. The driving transistor T3 includes a gate electrode T3g. For example, the gate electrode T3g of the driving transistor T3 is also located in the first conductive layer Gate1. For example, the gate electrode T3g of the driving transistor T3 forms a continuous integral structure with the first electrode plate Cst1 of the capacitor. Thus, the first scan signal line Scan(P)(n), the light emission control line EM(P)(n), the second reset scan signal line Scan(P)(n + 1), the gate electrode T3g of the driving transistor T3, and the first electrode plate Cst1 of the storage capacitor Cst are arranged in the same layer. The portion of the first scan signal line Scan(P)(n) overlapping the first semiconductor layer Active1 constitutes the gate electrode T4g of the fourth transistor T4. The two portions of the light emission control line EM(P)(n) overlapping the first semiconductor layer Active1 respectively constitute the gate electrode T5g of the fifth transistor T5 and the gate electrode T6g of the sixth transistor T6. The fifth transistor T5 and the sixth transistor T6 function as light emission control transistors. The fifth transistor T5 is the first light emission control transistor, and the sixth transistor T6 is the first light emission control transistor. The portion of the second reset scan signal line Scan(P)(n + 1) overlapping the first semiconductor layer Active1 constitutes the gate electrode T7g of the seventh transistor T7, and the seventh transistor T7 functions as a second reset transistor. Therefore, the first semiconductor layer Active1 includes the active layer A3 of the driving transistor T3, the active layer A4 of the fourth transistor T4, the active layer A5 of the fifth transistor T5, the active layer A6 of the sixth transistor T6, and the active layer A7 of the seventh transistor T7. Therefore, the gate electrode T3g of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor Cst are located on the side away from the base substrate 200 of the active layer A3 of the driving transistor T3.

[0148] For example, the third transistor T3 functions as a driving transistor T3 of the pixel circuit, and the fourth transistor T4 functions as a data writing transistor T4 of the pixel circuit. The driving transistor T3 is configured to control the light emission of the light emitting device 20, and the data line Data is connected to the first pole of the data writing transistor T4 and is configured to provide a data signal to the data writing transistor T4. The data writing transistor T4 is configured to write the data signal Vd to the gate electrode T3g of the driving transistor T3 in response to a first scanning signal applied to its gate electrode. For example, the data writing transistor T2 is configured to transmit the data signal Vd to the driving transistor T1 under the control of the first scanning signal Ga1, the first scanning signal Ga1 is transmitted by the first scanning signal line Scan(P)(n), and the data signal Vd is transmitted by the second signal line.

[0149] The reference signs Data, Data1, and Data2 in the present application refer to data lines in different embodiments or different sub-pixels. Specifically, reference may be made to the corresponding drawings.

[0150] As shown in FIG. 3B, for example, the first signal line further includes a second scanning signal line Scan(N)(n) and a first reset scanning signal line Scan(N)(n - 1). For example, the second scanning signal line Scan(N)(n) and the first reset scanning signal line Scan(N)(n - 1) are located in the second conductive layer Gate2. The portion of the second scanning signal line Scan(N)(n) overlapping with the second semiconductor layer Active2 constitutes the gate electrode T2g of the second transistor T2. The second transistor T2 functions as a compensation transistor. The portion of the first reset scanning signal line Scan(N)(n - 1) overlapping with the second semiconductor layer Active2 constitutes the gate electrode T1g of the first transistor T1. The first transistor T1 functions as a first reset transistor. Therefore, the second semiconductor layer Active2 includes the active layer A1 of the first transistor T1 and the active layer A2 of the second transistor T2.

[0151] For example, the active layers A1 to A7 of the first to seventh transistors referred to herein refer to the portions of the semiconductor layers constituting the first to seventh transistors that overlap the gate electrodes of the respective transistors.

[0152] The second scanning signal line Scan(N)(n) functions as a compensation scanning signal line, and the second scanning signal line Scan(N)(n) is configured to apply the second scanning signal Ga2 (i.e., the compensation scanning signal) to the gate electrode T2g of the compensation transistor T2. The compensation transistor T2 is configured to perform threshold compensation of the driving transistor T3 in response to the second scanning signal Ga2.

[0153] For example, as shown in FIG. 3B, the display substrate 10 further includes a first reset signal line Vini_N1. For example, the first reset signal line Vini_N1 is located in the second conductive layer Gate2. The first reset scanning signal line Scan(N)(n - 1) is configured to supply the first reset scanning signal, i.e., the first reset control signal Rst1, to the gate electrode T1g of the first reset transistor T1. The first pole T1s of the first reset transistor T1 is electrically connected to the gate electrode T3g of the driving transistor T3, and the second pole T1d of the first reset transistor T1 is electrically connected to the first reset signal line Vini_N1 and is configured to receive the first reset signal, for example, the first reset voltage Vinit1. The first reset transistor T1 is configured to write the first reset voltage Vinit1 to the gate electrode T3g of the driving transistor T3 in response to the first reset control signal Rst1.

[0154] As shown in FIG. 3F, the display substrate 10 further includes a second reset signal line Vini_OLED. For example, the second reset signal line Vini_OLED is located in the fourth conductive layer SD1. The second reset scan signal line Scan(P)(n+1) is configured to provide a second reset scan signal Rst2 to the gate electrode T7g of the second reset transistor T7. The first pole T7s of the second reset transistor T7 is electrically connected to the first display electrode 21 of the light-emitting device 20. The second pole T7d of the second reset transistor T7 is electrically connected to the second reset signal line Vini_OLED and is configured to receive a second reset signal, for example, a second reset voltage Vinit2. The second reset transistor T7 is configured to write the second reset signal to the first display electrode 21 of the light-emitting device 20 in response to the second reset scan signal Rst2.

[0155] For example, as shown in FIG. 3B, the active layer A2 of the compensation transistor T2 and the active layer A1 of the first reset transistor T1 form an integrally formed structure AL1 extending along the first direction D1, that is, the active layer A1 of the first reset transistor T1 extends along the first direction D1, or the active layer A2 of the compensation transistor T2 extends along the first direction D1. For example, as shown in FIG. 3C, the orthographic projection of the first semiconductor layer Active1 on the base substrate 200 does not overlap with the orthographic projection of the second semiconductor layer Active2 on the base substrate 200, and the transistors formed based on the first semiconductor layer Active1 and the second semiconductor layer Active2 do not interfere with each other.

[0156] For example, the material of the first semiconductor layer Active1 is different from that of the second semiconductor layer Active2. For example, the material of the first semiconductor layer Active1 includes, but is not limited to, silicon-based materials (such as amorphous silicon a-Si, polycrystalline silicon p-Si, etc.). For example, the material of the first semiconductor layer Active1 is low-temperature polysilicon (LTPS). For example, the material of the second semiconductor layer Active2 is an oxide semiconductor such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), AZO, IZTO, etc. Of course, the types of the materials of the first semiconductor layer Active1 and the second semiconductor layer Active2 are not limited to the above types, and the embodiments of the present invention are not limited thereto. Therefore, the active layers located in the first semiconductor layer Active1 and the second semiconductor layer Active2 are made of different materials and are arranged in different layers. For example, the active layer A1 of the first reset transistor T1 and the active layer A3 of the driving transistor T3 are made of different materials and are arranged in different layers.

[0157] For example, in at least one embodiment, in the case of the 7T1C pixel circuit shown in FIG. 2B, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 for resetting the light emitting device are P-type transistors that form active layers with LTPS materials, have high mobility, and have a more stable source voltage, so they are suitable for driving organic light-emitting diodes such as OLEDs. The first reset transistor T1 and the compensation transistor T2 for resetting the driving transistor T3 are N-type transistors that form active layers using oxide semiconductor materials, and because the leakage current is lower, the voltage stability of the driving transistor T3 and the storage capacitor Cst can be maintained better. Of course, in other embodiments, the types of each transistor of the pixel circuit and the material of the active layer are not limited to the above examples, and the embodiments of the present invention do not limit this.

[0158] Referring to FIGS. 3B and 5, the plurality of sub-pixels 100 includes a third sub-pixel P3. The signal line Scan(N)(n + 1) is the first reset scan signal line of the third sub-pixel P3, and the signal line Vini_N1’ is the first reset signal line of the third sub-pixel P3. The third sub-pixel P3 and the second sub-pixel P2 are adjacent in the first direction D1. For example, the complete pixel circuit shown in FIGS. 3A to 3K is the pixel circuit of the second sub-pixel P2 and pertains to a part of the structure of the pixel circuit of the sub-pixel adjacent to the second sub-pixel P2, for example, the third sub-pixel P3. The second scan signal line Scan(N)(n), the first reset scan signal line Scan(N)(n - 1), and the first reset signal line Vini_N1 in FIG. 3B all belong to the second sub-pixel P2.

[0159] For example, as shown in FIGS. 3F and 3G, a portion located in one sub-pixel 100 of the second reset signal line Vini_OLED extends along the second direction D2 and has a horizontal portion VS1 having a first end and a second end facing each other in the second direction D2, and a first vertical portion VS2 connected to the first end of the horizontal portion VS1 in the second direction D2 and extending along the first direction D1. As shown in FIG. 5, taking the second sub-pixel P2 and the third sub-pixel P3 as examples of two adjacent sub-pixels in the first direction D1, in FIGS. 3F and 3G, the orthographic projection of the horizontal portion VS1 of the second reset signal line Vini_OLED of the second sub-pixel P2 on the base substrate 200 at least partially overlaps with the orthographic projection of the first reset scan signal line Scan(N)(n + 1) of the third sub-pixel on the base substrate 200.The first vertical portion VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 and the active layer of the first reset transistor of the third sub-pixel P3 are arranged at intervals in the second direction D2. That is, the first vertical portion VS2 forms an integral structure A31 composed of the active layer of the compensation transistor and the active layer of the first reset transistor in the second semiconductor layer Active2, and is arranged at intervals in the second direction D2. (Since the pixel circuit structure of each sub-pixel is a repeating unit, the integral structure A31 in the third sub-pixel P3 is located below in FIG. 3G and can be set to the position in the sub-pixel of the integral structure AL in the second sub-pixel P2.) The first vertical portion VS2 extending along the first direction D1 of the second reset signal line Vini_OLED avoids the second semiconductor layer Active2. That is, the orthographic projection of the first vertical portion VS2 on the base substrate 200 does not overlap with the orthographic projection of the second semiconductor layer Active2 on the base substrate 200, avoiding signal interference between the two, and avoiding the influence of the second reset signal line Vini_OLED on the active layer A2 of the compensation transistor T2. The compensation transistor T2 using an oxide semiconductor material as the active layer has a stable high open-state current and a lower leakage current. The voltage of the first node N1 connected to the gate electrode of the driving transistor T3 and the storage capacitor Cst is more stable, leakage is less likely to occur, the driving current of the driving transistor T3 is more stable, the light-emitting efficiency of the light-emitting device 20 is more stable, and the display quality of the display device using the display panel is improved. In particular, it is remarkable when the positions of the second reset signal line Vini_OLED and the second semiconductor layer Active2 are relatively close in the direction perpendicular to the main surface of the base substrate 200. The feature that "the orthographic projection of the horizontal portion VS1 of the second reset signal line Vini_OLED on the base substrate 200 at least partially overlaps with the orthographic projection of the first reset scan signal line Scan(N)(n + 1) of the third sub-pixel P3 on the base substrate 200" can reduce the occupied area of the scan signal line and improve the aperture ratio of the display substrate.For example, as shown in FIGS. 3F to 3G, the first vertical portion VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 is spaced apart in the second direction D2 from the integrated structure AL1 for forming the active layer A1 of the first reset transistor T1 of the third sub-pixel P3. That is, the first vertical portion VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 avoids the active layer A1 of the first reset transistor T1 of the third sub-pixel P3. By utilizing the limited space, the positional relationship design between the pixel circuit structures of a plurality of sub-pixels is optimized, and a compact arrangement and a high PPI are achieved.

[0160] For example, as shown in FIG. 3I, the planar pattern of the sub-portion of the second reset signal line Vini_OLED corresponding to one sub-pixel 100 is in an inverted "Z" shape. The "Z" shaped sub-portion not only achieves the above-mentioned effect of avoiding the second semiconductor layer Active2, but also includes a U-shaped groove in the "Z" shaped sub-portion. The horizontal portion VS1 of the second reset signal line Vini_OLED forms the bottom of the U-shaped groove, and other wirings can be arranged in the U-shaped groove, so that the space can be reasonably utilized and the structure can be made more compact.

[0161] For example, as shown in FIG. 3I, a sub - portion of the second reset signal line Vini_OLED located in one sub - pixel 100 further includes a second vertical portion VS3. The second vertical portion VS3 is connected to the second end of the horizontal portion VS1 in the second direction D2, extends along the first direction D1. The active layer A7 of the second reset transistor T7 is located between the first vertical portion VS2 and the second vertical portion VS3. In the same sub - pixel 100, in the second direction D2, the distance between the first vertical portion VS2 of the second reset signal line Vini_OLED and the data line Data is greater than the distance between the second vertical portion VS3 of the second reset signal line Vini_OLED and the data line Data. The distance between the active layer of the second reset transistor T7 of the third sub - pixel P3 and the first vertical portion VS2 of the second reset signal line Vini_OLED of the second sub - pixel P2 is smaller than the distance between the active layer of the second reset transistor T7 of the third sub - pixel P3 and the second vertical portion VS3 of the second reset signal line Vini_OLED of the second sub - pixel P2. Thereby, the first vertical portion VS2 of the second reset signal line Vini_OLED avoids the second semiconductor layer Active2, rationally utilizes the limited space, and avoids over - dense wiring of the signal lines.

[0162] As shown in FIG. 3B, the second electrode plate Cst2 of the storage capacitor Cst is located in the second conductive layer Gate2 and is arranged in the same layer as the second scan signal line Scan(N)(n) and the first reset scan signal line Scan(N)(n). The second scan signal line Scan(N)(n) is, that is, a compensation scan signal line. Therefore, the second electrode plate Cst2 of the storage capacitor Cst is located on the side away from the base substrate 200 of the gate electrode T3g of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor Cst, is arranged in the same layer as the compensation scan signal line and the second electrode plate Cst2 of the storage capacitor Cst, the first reset signal line Vini_N1 and the second electrode plate Cst2 of the storage capacitor Cst are arranged in the same layer, and the active layer A2 of the compensation transistor T2 is located in the second semiconductor layer Active2. Therefore, it is on the side away from the base substrate 200 of the second electrode plate Cst2 of the storage capacitor Cst.

[0163] As shown in FIGS. 3F to 3G, the second reset signal line Vini_OLED is located in the fourth conductive layer SD1. Therefore, the second reset signal line Vini_OLED is located on the side away from the base substrate 200 of the active layer A2 of the compensation transistor T2.

[0164] FIG. 7A is a schematic cross-sectional view from a first perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K in sequence. FIG. 7B is a schematic cross-sectional view from a second perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K in sequence. For example, referring to FIGS. 3E and 7A to 7B, the gate electrodes T2g of the compensation transistor T2 and the gate electrode T1g of the first reset transistor T1 both have a dual-gate structure. The gate electrode T2g of the compensation transistor T2 includes a first gate electrode T2g1 and a second gate electrode T2g2. The gate electrode T1g of the first reset transistor T1 includes a first gate electrode T1g1 and a second gate electrode T1g2. The orthographic projection of the first gate electrode T2g1 of the compensation transistor T2 on the base substrate 200 overlaps with the orthographic projection of the second gate electrode T2g2 of the compensation transistor T2 on the base substrate 200, and the orthographic projection of the first gate electrode T1g1 of the first reset transistor T1 on the base substrate 200 overlaps with the orthographic projection of the second gate electrode T1g2 of the first reset transistor T1 on the base substrate 200.

[0165] For example, referring to FIGS. 3E and 7A - 7B, the first gate electrode T1g1 of the first reset transistor T1 and the first gate T2g1 of the compensation transistor T2 are located in the second conductive layer Gate2, and the second gate electrode T2g2 of the first reset transistor T1 and the second gate electrode T2g2 of the compensation transistor T2 are located in the third conductive layer Gate3. In a direction perpendicular to the main surface of the base substrate 200, the second semiconductor layer Active2 where the active layer A2 of the compensation transistor T2 and the active layer A1 of the first reset transistor T1 are located is positioned between the second conductive layer Gate2 and the third conductive layer Gate3. The first gate electrode T2g1 of the compensation transistor T2 and the first gate electrode T1g1 of the first reset transistor T1 are arranged in the same layer as the second electrode plate Cst2 of the storage capacitor Cst. The second gate electrode T2g2 of the compensation transistor T2 and the second gate electrode T1g2 of the first reset transistor T1 are located on the side away from the base substrate 200 of the active layer A2 of the compensation transistor T2 and the active layer A1 of the first reset transistor T1, and are located on the side closer to the base substrate 200 of the second reset signal line Vini_OLED.

[0166] As shown in FIG. 3D, the third conductive layer Gate3 further includes a dual - gate reset scan signal line Scan(N)(n - 1)' and a dual - gate compensation scan signal line Scan(N)(n)'. As shown in FIG. 3E, the portion of the dual - gate reset scan signal line Scan(N)(n - 1)' overlapping with the first semiconductor layer Active1 constitutes the second gate electrode T1g2 of the first reset transistor T1, and the portion of the dual - gate compensation scan signal line Scan(N)(n)' overlapping with the first semiconductor layer Active1 constitutes the second gate electrode T2g2 of the compensation transistor T2.

[0167] The orthographic projection of the dual-gate reset scan signal line Scan(N)(n-1)' on the main surface of the base substrate 200 basically overlaps with the orthographic projection of the first reset scan signal line Scan(N)(n-1) on the main surface of the base substrate 200, and the orthographic projection of the dual-gate compensation scan signal line Scan(N)(n)' on the main surface of the base substrate 200 basically overlaps with the orthographic projection of the second scan signal line Scan(N)(n), that is, the compensation scan signal line, on the main surface of the base substrate 200. In this way, the additional pixel area occupied by the dual-gate reset scan signal line Scan(N)(n-1)' and the dual-gate compensation scan signal line Scan(N)(n)' provided to realize the dual-gate structure can be reduced, and the aperture ratio of the display substrate can be improved.

[0168] For example, as shown in FIG. 3F, the first connection structure C1 is located in the fourth conductive layer SD1, the first connection structure C1 and the second reset signal line Vini_OLED are arranged in the same layer, and the second electrode plate Cst2 of the storage capacitor Cst is located on the side away from the base substrate 200.

[0169] When the first connection structure C1 and the data line Data are arranged in different layers, for example, in the embodiments shown in FIGS. 3A to 3I and FIG. 4A, the data line Data is located on the side away from the base substrate 200 of the first connection structure C1. Alternatively, in other embodiments, the data line Data can be located on the side close to the base substrate 200 of the first connection structure C1.

[0170] Referring to FIG. 4A, the interlayer insulating layer ILD of the display substrate 10 includes a first sub-insulating layer GI1 positioned between the first semiconductor layer Active1 and the first conductive layer Gate1, and a second sub-insulating layer ILD0 positioned between the first conductive layer Gate1 and the first conductive layer Gate1. Referring to FIG. 7A, the interlayer insulating layer ILD further includes a third sub-insulating layer ILD1 positioned between the second conductive layer Gate2 and the second semiconductor layer Active2, a fourth sub-insulating layer GI2 positioned between the second semiconductor layer Active2 and the third conductive layer Gate3, and a fifth sub-insulating layer ILD2 positioned between the third conductive layer Gate3 and the fourth conductive layer SD1.

[0171] The display substrate 10 further includes a sixth sub-insulating layer, i.e., the first planarization layer PLN1, positioned between the fourth conductive layer SD1 and the fifth conductive layer SD2, and a second planarization layer PLN2 positioned between the fifth conductive layer SD2 and the first display electrode 21. The first planarization layer PLN1 provides a flat surface for the fifth conductive layer SD2 disposed thereon, facilitates the pattern design of the fifth insulating layer SD2, reduces the manufacturing difficulty of the fifth insulating layer SD2, and improves the yield. The second planarization layer PLN2 provides a flat surface for the first display electrode 21 disposed thereon, facilitates the pattern design of the first display electrode 21, reduces the manufacturing difficulty of the first display electrode 21, and improves the yield.

[0172] For example, as shown in FIG. 4A, the display substrate 10 further includes a pixel definition layer PDL. From the opening of the pixel definition layer PDL, a part of the first display electrode of each sub-pixel 100 located in the light-emitting region is exposed, and the main body of the pixel definition layer PDL covers the edge of the first display electrode.

[0173] For example, as shown in FIG. 4A, the display substrate 10 is located on the main surface of the base substrate 200 and further includes a barrier layer 02 located on the side of the Active layer of the first semiconductor layer closer to the base substrate 200. For example, the barrier layer 02 is in contact with the base substrate 200. The barrier layer 02 can protect the base substrate and prevent damage and corrosion to the base substrate during the process of forming subsequent film layers. For example, the display substrate 10 further includes a buffer layer 01 located on the side of the barrier layer 02 away from the base substrate 200 to further protect the base substrate.

[0174] Referring to FIGS. 3B, 3K, and 4A, the second electrode plate Cst2 of the storage capacitor Cst has a first via hole V1 that exposes the first electrode plate Cst1 of the storage capacitor Cst, and the first connection structure C1 passes through the first via hole V1 and is connected to the first electrode plate Cst1 of the storage capacitor Cst. The first via hole V1 penetrates the second sub-insulating layer ILD0 along a direction perpendicular to the main surface of the base substrate 200. The display substrate further includes a via hole V9 that communicates with the first via hole V1 and penetrates the second sub-insulating layer ILD0, the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2, and the fifth sub-insulating layer ILD2 along a direction perpendicular to the main surface of the base substrate 200, and the first connection structure C1 is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst through the via hole V9 and the first via hole V1.

[0175] As shown in FIG. 3F, the first connection structure C1 includes a first portion C11 extending along a first direction D1 and a second portion C12 extending along a second direction D2. The second portion C11 of the first connection structure C1 is connected to the first portion C11 of the first connection structure. For example, the second portion C11 of the first connection structure C1 constitutes an integrally formed structure continuous with the first portion C11 of the first connection structure.

[0176] As shown in FIGS. 3F and 3I, the active layer A2 of the compensation transistor T2 is located on the side away from the data line Data of the first connection structure C1, and the second portion C12 of the first connection structure C1 is connected to the active layer A2 of the compensation transistor T2. For example, one end of the first portion C11 of the first connection structure C1, which is away from the second portion C12 in the first direction D1, is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst through the via hole V9 and the first via hole V1. The second portion C12 of the first connection structure C1 is connected to the active layer A2 of the compensation transistor T2 through the second via hole V10, and the second via hole V10 penetrates the fourth sub-insulating layer GI2 and the fifth sub-insulating layer ILD2 along the direction perpendicular to the main surface of the base substrate 200 (see FIG. 4A).

[0177] For example, referring to FIGS. 3K and 4A, in each sub-pixel 100 that executes a display function, a first power supply line VDD is connected to a first voltage terminal vdd and is configured to provide a first power supply voltage VDD to a pixel circuit. For example, the first power supply line VDD extends along a first direction D1. The pixel circuit is positioned between the first power supply line VDD and a second electrode plate Cst2 of a storage capacitor Cst in a direction perpendicular to the main surface of the base substrate 200, and further includes a second connection structure C2 that connects the first power supply line VDD and the second electrode plate Cst2 of the storage capacitor Cst. For example, the second connection structure C2 includes a horizontal portion C21 that extends along a second direction D2 and a vertical portion C22 that is connected to the horizontal portion C21 and extends along the first direction D1. The orthographic projection of the first power supply line VDD on the base substrate 200 overlaps the orthographic projection of the horizontal portion C21 of the second connection structure C2 on the base substrate 200, and the orthographic projection of the first power supply line VDD on the base substrate 200 does not overlap the orthographic projection of another structure arranged in the same layer as the second connection structure C2 on the base substrate 200. In this way, on the one hand, by using the overlapping portion between the horizontal portion C21 of the second connection structure C2 and the first power supply line VDD, the horizontal portion C21 of the second connection structure C2 is electrically connected to the first power supply line VDD, and through the second connection structure C2, it is easily realized to connect the first power supply line VDD and the second electrode plate Cst2 of the storage capacitor Cst.On the other hand, the conductive layer where the second connection structure C2 is located and the conductive layer where the first power line VDD is located are relatively close in the direction perpendicular to the main surface of the base substrate 200. For example, since they are adjacent conductive layers to each other, if there are too many structures in the conductive layer where the second connection structure C2 is located that overlap the first power line VDD in the direction perpendicular to the main surface of the base substrate 200, that is, the orthographic projection in the direction perpendicular to the main surface of the base substrate 200 of many structures in the conductive layer where the second connection structure C2 is located overlaps the orthographic projection in the direction perpendicular to the main surface of the base substrate 200 of the first power line VDD, it will cause interference to the first power voltage VDD transmitted by the first power line VDD, making the first power voltage VDD unstable and affecting the display effect of the display substrate. Therefore, the orthographic projection of the first power line VDD on the base substrate 200 does not overlap the orthographic projection on the base substrate 200 of other structures arranged in the same layer as the second connection structure C2, avoiding the instability of the first power voltage VDD and improving the display effect of the display substrate.

[0178] For example, as shown in FIG. 3K, the vertical portion C22 is basically aligned with the first connection structure C1 in the first direction, and the orthographic projection of the horizontal portion C21 on the base substrate 200 extends from the orthographic projection of the vertical portion C22 on the base substrate 200 along the first direction D1 to the orthographic projection of the first power line VDD on the base substrate 200. Thereby, the extending tendency of the second connection structure C2 is designed corresponding to the extending tendencies of the first power voltage VDD and the first connection structure C1, rationally utilizing the limited space to realize a neat and compact wiring design, contributing to improving the manufacturing yield of the pixel structure and achieving a high PPI.

[0179] For example, as shown in FIG. 4A, the first insulating layer PLN1 is located between the first power supply line VDD and the second connection structure C2, and the second insulating layer (including the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2, and the fifth sub-insulating layer ILD2) is located between the second connection structure C2 and the second plate Cst2 of the storage capacitor Cst. The horizontal portion C21 of the second connection structure C2 is connected to the first power supply line VDD through a third via hole V3 penetrating the first insulating layer PLN1, and the vertical portion C22 of the second connection structure C2 is connected to the second plate Cst2 of the storage capacitor Cst through a fourth via hole V4 (i.e., the fourth via hole V4 penetrates the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2, and the fifth sub-insulating layer ILD2) penetrating the second insulating layer. In this way, the first power supply line VDD is connected through the vertical portion C22 of the second connection structure C2 extending along the first direction D1 and the horizontal portion C21 of the second connection structure C2 extending along the second direction D2, and the first power supply line VDD and the second plate Cst2 of the storage capacitor Cst are electrically connected by a plurality of connection structures and a plurality of via holes, reducing the risk of disconnection by a single via hole penetrating a thicker insulating layer, and arranging the position and shape of the second connection structure C2, as well as the relationship between the second connection structure C2 and the first power supply line VDD, skillfully to electrically connect the first power supply line VDD and the second plate Cst2 of the storage capacitor Cst, realizing a compact pixel structure.

[0180] For example, in the embodiment shown in FIG. 4A, the first power supply line VDD and the data line Data are arranged in the same layer. For example, both the first power supply line VDD and the data line Data are located in the fifth conductive layer SD2, and the second connection structure C2 and the first connection structure C1 are arranged in the same layer. Both the second connection structure C2 and the first connection structure C1 are located in the fourth conductive layer SD. Therefore, by reasonably arranging the positional relationship between auxiliary connection structures such as the second connection structure C2 and the first connection structure C1 and the first power supply line VDD and the data line Data, the manufacturing of each layer of the display substrate can be facilitated, and the above pixel circuit can be realized.

[0181] For example, the first light emission control transistor T5 of the pixel circuit is connected to the first pole and the first voltage terminal of the driving transistor T3, and in response to the first light emission control signal applied to the gate electrode T5g of the first light emission control transistor T5, it is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first pole T3s of the driving transistor T3. As described above, the first semiconductor layer Active1 includes the active layer A3 of the driving transistor T3, the active layer A4 of the data writing transistor T4, and the active layer A5 of the first light emission control transistor T5. FIG. 7C is a schematic cross-sectional view along the active layer directions of the fifth transistor, the third transistor, and the sixth transistor in FIG. 3K in sequence, that is, a schematic cross-sectional view along the line A1 - A2 in FIG. 3K. Referring to FIGS. 3K and 7C, the horizontal portion C21 of the second connection structure C2 is connected to the first semiconductor layer Active1 through the fifth via hole V5.

[0182] For example, the horizontal portion C21 of the second connection structure C2 has a first end and a second end that face each other in the second direction D2. The first end of the horizontal portion C21 is located on the side of the first power supply line VDD close to the vertical portion C22 and is connected to the vertical portion C22. The second end of the horizontal portion C21 is located on the side of the first power supply line VDD away from the vertical portion C22 and is connected to the first semiconductor layer Active1 through the fifth via hole V5. By skillfully arranging the position and shape of the second connection structure C2 and the relationship between the second connection structure C2 and the first power supply line VDD, the first power supply line VDD and the second electrode plate Cst2 of the storage capacitor Cst are electrically connected to realize a compact pixel structure.

[0183] Referring to FIGS. 3K and 7A-7B, one sub-pixel 100 further includes a third connection structure C3. The data line Data is connected to the first semiconductor layer Active1 via a via hole V2 including, for example, a first sub-via hole V21 penetrating through the first sub-insulating layer GI1, the second sub-insulating layer ILD0, the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2, and the fifth sub-insulating layer ILD2, and a second sub-via hole V22 penetrating through the first planar layer PLN1. The data line Data is connected to the third connection structure C3 via the second sub-via hole V22, and the third connection structure C3 is connected to the first semiconductor layer Active1 via the first sub-via hole V21, thereby connecting the data line Data and the first semiconductor layer Active1.

[0184] FIG. 7C is a schematic cross-sectional view along the active layer direction of the fifth transistor, the third transistor, and the sixth transistor in FIG. 3K, that is, a schematic cross-sectional view along line A1-A2 in FIG. 3K. FIG. 7D is a schematic cross-sectional view along the active layer direction of the third transistor and the sixth transistor in FIG. 3K, that is, a schematic cross-sectional view along line B1-B2 in FIG. 3K. Referring to FIGS. 3K and 7C-7D, one sub-pixel 100 further includes a fourth connection structure C4 and a fifth connection structure C5. For example, the fourth connection structure C4 is located in the fifth conductive layer SD2, and the fifth connection structure C5 is located in the fourth conductive layer SD1. The first display electrode 21 is located on the surface of the second planarization layer PLN2 away from the base substrate 200, and is connected to the first semiconductor layer Active1 through the fourth connection structure C4 and a via hole. For example, the first display electrode 21 is connected to the fourth connection structure C4 through a via hole V8 located in the second planarization layer PLN2, and the fourth connection structure C4 is connected to the fifth connection structure C5 through a via hole V7 located in the first planarization layer PLN2. The fifth connection structure C5 is connected to the first semiconductor layer Active1 through a via hole V6 that penetrates the first sub-insulating layer GI1, the second sub-insulating layer ILD0, the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2, and the fifth sub-insulating layer ILD2. In this way, through a plurality of connection structures and a plurality of via holes, the first display electrode 21 and the first semiconductor layer Active1 are electrically connected, that is, electrically connected to the second pole T6d of the second light-emitting transistor T6, thereby reducing the risk of disconnection caused by a single via hole penetrating a thick insulating layer.

[0185] In the display substrate 10 provided by an embodiment of the present invention, the base substrate 200 may be a rigid substrate such as a glass substrate or a silicon substrate, or may be formed of a flexible material excellent in heat resistance and durability such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cyclic olefin polymer (COP), and cyclic olefin copolymer (COC).

[0186] For example, as the materials of the first to fifth conductive layers, gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of combinations of the above metals, or transparent conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO) can be included.

[0187] For example, the first insulating layer and the second insulating layer are inorganic insulating layers, and the materials thereof include at least one of silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon oxynitrides, or include metal oxynitride insulating materials such as aluminum oxide and titanium nitride. For example, the pixel definition layer PDL, the first planarization layer PLN1, and the second planarization layer PLN2 may be organic insulating materials such as polyimide (PI), acrylate, epoxy resin, and polymethyl methacrylate (PMMA). The embodiments of the present disclosure are not limited thereto.

[0188] In at least one embodiment, examples of the materials and thicknesses of the above layers of the display substrate 10 are shown in Table 1 below. Of course, the materials of the above each film layer and the thicknesses in the direction perpendicular to the main surface of the base substrate are not limited to those shown in Table 1.

[0189]

Table 1

[0190] For example, the light-emitting device has a top-emission type structure. The first display electrode 21 has reflectivity, and the second display electrode 21 has transparency or semi-transparency. For example, the first display electrode 21 is a material having a high work function as an anode. For example, it has an ITO / Ag / ITO laminated structure. The second display electrode is a material having a low work function as a cathode. For example, it is a semi-transparent metal or metal alloy material, such as an Ag / Mg alloy material.

[0191] Naturally, the materials and thicknesses of the above-mentioned each film layer are not limited to the examples in Table 1, and those skilled in the art can design according to specific products.

[0192] In some other embodiments, for example, FIG. 8 is another schematic plan view of a display substrate provided according to an embodiment of the present invention. As shown in FIG. 8, the first display electrode of the first sub-pixel P1 covers the boundary between the first sub-pixel P1 and the second sub-pixel P2. A part of the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and a part of the orthographic projection of the first connection structure C1 of the second sub-pixel P2 on the base substrate 200 are both located within the orthographic projection of the first display electrode 21 of the first sub-pixel P1 on the base substrate 200. In this case, the first display electrode is located in the boundary region between two adjacent sub-pixels, covers a part of the first connection structure of each of the two adjacent sub-pixels, meets the electrode arrangement method of specific requirements, and obtains a better display effect.

[0193] In some other embodiments, for example, the orthographic projection of the entire first connection structure C1 on the base substrate 200 can be located within the orthographic projection of the first display electrode 21 of the light-emitting device 20 on the base substrate 200. The plurality of sub-pixels includes a first sub-pixel P1 and a second sub-pixel P2 that are adjacent to each other in the second direction D2. The first display electrode 21 of the first sub-pixel P1 covers the boundary between the first sub-pixel P1 and the second sub-pixel P2. The orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the first connection structure C1 of the second sub-pixel P2 on the base substrate 200 are both located within the orthographic projection of the first display electrode 21 of the first sub-pixel P1 on the base substrate 200. FIG. 9 is a schematic cross-sectional view of a display substrate including a first connection structure and a first display electrode provided according to an embodiment of the present invention. For example, as shown in FIG. 9, a part of the orthographic projection of the first connection structure C1 on the main surface of the base substrate 200 is located within the orthographic projection of the first display electrode 21 of the light-emitting device 20 on the main surface of the base substrate 200, and another part of the orthographic projection of the first connection structure C1 on the main surface of the base substrate 200 is not located within the orthographic projection of the first display electrode 21 of the light-emitting device 20 on the main surface of the base substrate 200. That is, a part of the first connection structure C1 is covered by the first display electrode 21, and another part of the first connection structure C1 is not covered by the first display electrode 21.

[0194] FIG. 10 is a schematic cross-sectional view of a display substrate including a first connection structure and a first display electrode provided according to an embodiment of the present invention. For example, in the embodiments shown in FIGS. 3K and 10, in one sub-pixel 100, the orthographic projection of the entire first connection structure C1 on the base substrate 200 is located within the orthographic projection of the first display electrode 21 on the base substrate 200.

[0195] For example, as shown in FIG. 10, the orthographic projection of the first display electrode 21 of the sub-pixel 100 on the main surface of the base substrate 200 overlaps with a part of the orthographic projection of the data line Data of the sub-pixel 100 on the main surface of the base substrate 200. In the sub-pixel 100, the orthographic projection of the edge of the first display electrode 21, which is far from the data line Data and close to the first connection structure C1, on the base substrate 200 is basically aligned with the edge of the first connection structure C1 that is far from the data line Data. Here, "basically aligned" is not limited to being absolutely aligned. For example, if the alignment error between the two basically aligned edges is within 3% of the width of the first connection structure C1 in the second direction D2, it is considered that the two edges are basically aligned.

[0196] For example, FIG. 11 is yet another schematic plan view of a display substrate provided according to an embodiment of the present invention. As shown in FIG. 11, the light-emitting material of the light-emitting device 20 of the first sub-pixel P1 emits green light. That is, in the direction perpendicular to the base substrate 200, the light-emitting layer of the sub-pixel P1 where the first display electrode 21 covering a part of the first connection structure C1 of the first sub-pixel P1 and the first connection structure C1 of the second sub-pixel P2 is located emits green light. Compared with light-emitting materials of other colors such as the light-emitting material of an organic light-emitting diode, the green light-emitting material is not the most sensitive to voltage changes. Due to the jump of the data voltage transmitted by the data line near the first connection structure C1, a certain degree of jump occurs in the signal on the first connection structure C1. Since the first display electrode is located in the boundary region between adjacent sub-pixels and partially covers the first connection structures C1 of two adjacent sub-pixels and is close to the first connection structure C1, in the arrangement method of the first display electrodes of a plurality of sub-pixels 100, by the solution that the light-emitting layer of the sub-pixel where the first display electrode 21 covering the first connection structure C1 of adjacent sub-pixels 100 (for example, the first sub-pixel P1 and the second sub-pixel P2) is located emits green light, the influence of the voltage jump of the first connection structure C1 on the light-emitting device where the first display electrode is located can be minimized.

[0197] For example, as shown in FIG. 11, the orthographic projection on the base substrate 200 of the edge of the first display electrode 21 of the first sub-pixel P1 that is away from the second sub-pixel P2, and the orthographic projection on the base substrate 200 of the edge of the first connection structure C1 of the first sub-pixel P1 that is close to the data line Data of the first sub-pixel P1 are basically aligned. The orthographic projection on the base substrate 200 of the edge of the first display electrode 21 of the first sub-pixel P1 that is close to the second sub-pixel P2, and the orthographic projection on the base substrate 200 of the edge of the first connection structure C1 of the second sub-pixel P2 that is close to the data line Data of the second sub-pixel P2 are basically aligned. Here, "basically aligned" is not limited to being absolutely aligned. For example, if the alignment error between the above two basically aligned edges is within 3% of the width of the first connection structure C1 in the second direction D2, the two edges are considered to be basically aligned.

[0198] FIG. 12 is yet another schematic plan view of a display substrate provided according to an embodiment of the present invention. For example, as shown in FIG. 12, the first display electrode 21 of the light-emitting device 20 has a first end and a second end that face each other in the second direction D2. The first display electrode 21 of the first sub-pixel P1 covers the boundary between the first sub-pixel P1 and the second sub-pixel P2, and the orthographic projection of the first end of the first display electrode 21 of the first sub-pixel P1 on the base substrate 200 protrudes toward the orthographic projection of the second via hole V2 of the first sub-pixel P1 on the base substrate 200 in the second direction D2 and has a first protruding portion 21A that tapers. The orthographic projection of the second end of the first display electrode 21 of the first sub-pixel P1 on the main surface of the base substrate 200 protrudes toward the orthographic projection of the second via hole V2 of the second sub-pixel P2 on the main surface of the base substrate 200 in the second direction D2 and has a second protruding portion 21B that tapers. The orthographic projections of the first protruding portion 21A and the second via hole V2 of the first sub-pixel P1 on the main surface of the base substrate 200 face each other in the second direction D2. The orthographic projections of the second protruding portion 21B and the second via hole V2 of the second sub-pixel P2 on the main surface of the base substrate 200 face each other in the second direction D2. The light-emitting material of the light-emitting device 20 of the first sub-pixel P1 emits blue light. Compared with light-emitting materials of other colors, such as the light-emitting material of an organic light-emitting diode, the blue light-emitting material is sensitive to voltage changes. Both ends of the first display electrode 21 of the sub-pixel where the light-emitting device 20 using the blue light-emitting material is located, which are close to the data lines Data1 located on both sides thereof in the second direction D2, protrude so as to taper. Thereby, the influence of the jump of the data voltage on the data lines Data1 located on both sides of the first display electrode 21 on the voltage of the first display electrode 21 can be reduced. For example, the first protruding portion 21A and the second protruding portion 21B are symmetrically designed so that the display effects on both sides of the first display electrode 21 in the second direction D2 are more uniform.

[0199] In the first sub-pixel P1 and the second sub-pixel P2, each of the second vias is used to connect the data line and the first semiconductor layer, and can include two sub-vias that do not communicate with each other. Reference can be made to the aforementioned first sub-via and second sub-via. However, in different sub-pixels, the positions of the two sub-vias included in the second via do not necessarily have to be the same. For example, as shown in FIG. 12, the first sub-via V21 of the second via V2 of the first sub-pixel P1 and the first sub-via V21 of the second via V2 of the second sub-pixel P2 have basically the same corresponding positions within their respective sub-pixels. The second sub-via V22 of the second via V2 of the first sub-pixel P1 corresponds to the position of the data line Data1 of the first sub-pixel P1, and the second sub-via V22 of the second via V2 of the second sub-pixel P2 corresponds to the position of the data line Data1 of the second sub-pixel P2. The data line Data1 of the first sub-pixel P1 and the data line Data1 of the second sub-pixel P2 are symmetric with respect to the symmetry axis extending along the first direction D1. The distance between the first sub-via V21 and the second sub-via V22 of the first sub-pixel P1 is smaller than the distance between the first sub-via V21 and the second sub-via V22 of the second sub-pixel P2.

[0200] FIG. 13 is yet another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention. For example, as shown in FIG. 13, the second electrode plate Cst2 of the storage capacitor Cst includes a first portion Cst21 located on a first side in a second direction D2 of the first via hole V1, and a second portion Cst22 located on a second side in the second direction D2 of the first via hole V1. A first side of the first via hole V1 faces its second side, and the second portion Cst22 of the second electrode plate Cst2 is located on a side closer to the data line Data of the first portion Cst21 of the second electrode plate Cst2. In the second direction D2, a front projection of an edge E1 of the first connection structure C1 close to the second portion Cst22 of the second electrode plate Cst2 of the storage capacitor Cst (i.e., the second edge 1b of the first connection structure C1 described above) on the base substrate 200, a front projection of an edge E2 of the first display electrode 21 close to the first connection structure C1 on the base substrate 200, and a front projection of an edge E3 of the second portion of the second electrode plate Cst2 close to the first connection structure C1 on the base substrate 200 overlap (are basically aligned). Thereby, the parasitic capacitance formed by the first display electrode 21 and the first connection structure C1 can be reduced, and it also contributes to the planarization of the fourth conductive layer SD1.

[0201] For example, in at least one embodiment, at least one of the overlapping portion D0 of the data line Data and the first connection structure C1 includes a recess, and a recess of either one of the overlapping portion D0 of the data line Data and the first connection structure C1 is recessed in a direction away from the other of the overlapping portion D0 of the data line Data and the first connection structure C1 in the second direction D2.

[0202] Exemplarily, FIG. 14A is a schematic diagram of a first connection structure and a data line in a display substrate provided according to an embodiment of the present invention. As shown in FIG. 14A, for example, an overlapping portion of the data line Data includes a first recess R1, and the first recess R1 is recessed in a direction away from the first connection structure C1 in the second direction D2. A portion of the first connection structure C1 facing the data line Data is formed in a straight strip shape. Thereby, the first recess R1 increases the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and reduces the capacitance value of the parasitic capacitance formed by the overlapping portion D0 of the data line Data and the first connection structure C1.

[0203] For example, in FIG. 14A, since the data line Data and the first connection structure C1 are arranged in different layers, the pattern of the data line Data can be laid out using a film layer different from the first connection structure C1. Design space limitations of the first recess R1 due to the first connection structure C1 and the like are avoided, and sufficient space is ensured for the design of the first recess R1. For example, the first connection structure C1 is located in the fourth conductive layer SD1 described above, and the data line Data is located in the fifth conductive layer SD2 described above. Alternatively, in other embodiments, the connection structure C1 can be located in the fifth conductive layer SD2 described above, and the data line Data can be located in the fourth conductive layer SD1 described above. Of course, the first connection structure and the data line can also be arranged in two other different conductive layers, but the present invention does not impose specific restrictions on the layers in which the first connection structure and the data line are arranged.

[0204] Exemplarily, FIG. 14B is a schematic diagram of a first connection structure and a data line in another display substrate provided according to an embodiment of the present invention. As shown in FIG. 14B, for example, the first connection structure C1 includes a second recess R2, and the second recess R2 is recessed in a direction away from the overlapping portion D0 of the data line Data in the second direction D2, and the overlapping portion D0 of the data line Data is formed in a straight strip shape. Therefore, the second recess R2 increases the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and reduces the capacitance value of the parasitic capacitance formed by the overlapping portion D0 of the data line Data and the first connection structure C1.

[0205] Similarly, for example, since the data line Data and the first connection structure C1 are arranged in different layers, the pattern of the first connection structure C1 can be laid out using a film layer different from the data line Data. The design space limitation of the second recess R2 due to structures such as the data line Data is avoided, and sufficient space for the design of the second recess R2 is ensured. For example, the first connection structure C1 is located in the fourth conductive layer SD1 described above, and the data line Data is located in the fifth conductive layer SD2 described above. Alternatively, in other embodiments, the connection structure C1 can be located in the fifth conductive layer SD2 described above, and the data line Data can be located in the fourth conductive layer SD1 described above. Of course, the first connection structure and the data line can also be arranged in two other different conductive layers, but the present invention does not impose specific restrictions on the layers in which the first connection structure and the data line are arranged.

[0206] Exemplarily, FIG. 14C is a schematic diagram of a first connection structure and a data line in still another display substrate provided according to an embodiment of the present invention. As shown in FIG. 14C, for example, the overlapping portion D0 of the data line Data includes a first recess R1 that is recessed in a direction away from the first connection structure C1 in the second direction D2. The first connection structure C1 includes a second recess R2 that is recessed in a direction away from the overlapping portion D0 of the data line Data in the second direction D2. In this way, the portion of the first connection structure C1 facing the data line Data forms a linear strip shape. Thereby, the first recess R1 and the second recess R2 further increase the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and further reduce the capacitance value of the parasitic capacitance formed by the overlapping portion D0 of the data line Data and the first connection structure C1.

[0207] For example, in FIG. 14C, the data line Data and the first connection structure C1 are arranged in different layers, avoiding the design space limitation between the first recess R1 and the second recess R2, and there is sufficient space in different layers to meet the design of the first recess R1 and the second recess R2. For example, the first connection structure C1 is located in the fourth conductive layer SD1 described above, and the data line Data is located in the fifth conductive layer SD2 described above. Alternatively, in other embodiments, the connection structure C1 can be located in the fifth conductive layer SD2 described above, and the data line Data can be located in the fourth conductive layer SD1 described above. Of course, the first connection structure and the data line can also be arranged in two other different conductive layers, but the present invention does not impose specific restrictions on the layers in which the first connection structure and the data line are arranged.

[0208] At least one embodiment of the present invention further provides a display device including any display substrate provided by the embodiments of the present invention. FIG. 15 is a schematic diagram of a display device provided by at least one embodiment of the present invention. As shown in FIG. 15, a display device 10-1 provided by at least one embodiment of the present invention includes any display panel 10 provided by the embodiments of the present invention. The display device 10-1 may be, for example, a device having a display function such as an organic light-emitting diode display device, or other types of devices. The embodiments of the present disclosure are not limited thereto.

[0209] Regarding the structure, function, and technical effects of the display device provided by the embodiments of the present invention, reference can be made to the corresponding description of the display substrate 10 provided by the above embodiments of the present invention, and details will not be repeated here.

[0210] For example, the display device 10-1 provided by at least one embodiment of the present invention may be any product or component having a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0211] The above description is only an exemplary embodiment of the present invention and is not used to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Description of Reference Numerals

[0212] 10 Display substrate 20 Light-emitting device 100 Sub-pixel 200 Base substrate Cst Storage capacitor C1 First connection structure T3 Driving transistor T4 Data writing transistor

Claims

1. In a base substrate provided with a plurality of pixels arranged in an array, each of at least some of the plurality of pixels includes a plurality of subpixels, at least some of the plurality of subpixels includes a pixel circuit, and the pixel circuit is A base substrate comprising a light-emitting device, a storage capacitor, a drive transistor, and a data writing transistor, wherein each of the drive transistor and the data writing transistor comprises an active layer, a gate electrode, a first electrode, and a second electrode, and the drive transistor is configured to control the light-emitting device to emit light, A data line connected to the first pole of the data writing transistor and configured to provide a data signal to the data writing transistor, wherein the data writing transistor is configured to write the data signal to the gate electrode of the drive transistor in response to a first scanning signal applied to the gate electrode of the data writing transistor, A first connection structure connected to the gate electrode of the drive transistor and the first plate of the storage capacitor, wherein both the data line and the first connection structure extend along a first direction, the data line includes an overlapping portion, the first connection structure and the overlapping portion of the data line are at least partially opposite each other in a second direction, the second direction is parallel to the base substrate and perpendicular to the first direction, A display board in which the first connection structure and the overlapping portion of the data lines are insulated from each other, the first connection structure and the overlapping portion of the data lines constitute a first electrode plate and a second electrode plate of a parasitic capacitance, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.

01.

2. The display substrate according to claim 1, wherein the size of the subpixel in the second direction is greater than 50 μm, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is less than 0.

005.

3. The display substrate according to claim 2, wherein the size of the subpixel in the second direction is 68 μm or less, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is 0.003 or more.

4. The display substrate according to claim 1, wherein the size of the subpixel in the second direction is less than 50 μm, and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.005 and less than 0.

006.

5. The first connection structure includes a first portion extending along the first direction, the edge of the first portion of the first connection structure near the overlapping portion of the data lines is the first edge, the first portion of the first connection structure further has a second edge away from the overlapping portion of the data lines, and the edge of the overlapping portion of the data lines near the first connection structure is the third edge. The display substrate according to claim 1, wherein the plurality of subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, each of the first subpixel and the second subpixel includes the pixel circuit, the distance between the orthographic projection on the base substrate of the second edge of the first connection structure of the first subpixel and the orthographic projection on the base substrate of the third edge of the overlapping portion of the data lines of the second subpixel is a first distance, the distance between the first edge of the first connection structure of the first subpixel and the third edge of the overlapping portion of the data lines of the first subpixel is a second distance, and the ratio of the first distance to the second distance is greater than 14.

6. The display substrate according to claim 5, wherein the size of the subpixel in the second direction is less than 50 μm, and the ratio of the first distance to the second distance is greater than 14 and less than 15.

5.

7. The display substrate according to claim 5, wherein the size of the subpixel in the second direction is greater than 50 μm, and the ratio of the first distance to the second distance is greater than 15.

5.

8. The plurality of subpixels, the first connection structure of the first subpixel, is located between the data line of the first subpixel and the data line of the second subpixel in the second direction. The distance between the orthographic projection of the first connection structure of the first subpixel on the base substrate and the orthographic projection of the data line of the first subpixel on the base substrate is smaller than the size of one of the subpixels in the second direction. The display substrate according to claim 5, wherein the distance between the orthographic projection of the first connection structure of the first subpixel on the base substrate and the orthographic projection of the data line of the second subpixel on the base substrate is smaller than the size of one of the subpixels in the second direction.

9. The first connection structure of the first subpixel is located between the data line of the first subpixel and the data line of the second subpixel in the second direction. The distance between the orthographic projection of the first connection structure of the first subpixel on the base substrate and the orthographic projection of the data line of the first subpixel on the base substrate is smaller than the size of one of the subpixels in the second direction. The display substrate according to claim 5, wherein the distance between the orthographic projection of the first connection structure of the first subpixel on the base substrate and the orthographic projection of the data line of the second subpixel on the base substrate is greater than the size of one of the subpixels in the second direction.

10. The edge of the gate electrode of the drive transistor of the first subpixel that is close to the overlapping portion of the data lines of the second subpixel is the fourth edge. The display substrate according to claim 5, wherein the distance between the second edge of the first subpixel and the third edge of the second subpixel is equal to the sum of the distance between the second edge of the first subpixel and the fourth edge and the distance between the fourth edge of the first subpixel and the third edge of the second subpixel.

11. The first connection structure and the data lines are arranged in different layers, and the orthographic projection of the first connection structure on the base substrate overlaps at least partially with the orthographic projection of the data lines on the base substrate in a direction perpendicular to the base substrate. Alternatively, the display substrate according to claim 10, wherein the first connection structure and the data lines are arranged on different layers, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the overlapping portion of the data lines on the base substrate do not overlap in a direction perpendicular to the base substrate.

12. The display substrate according to claim 10, wherein the first connection structure and the data line are arranged on the same layer, and the overlapping portion of the first connection structure and the data line faces each other in a second direction.

13. The display board according to claim 1, wherein at least one of the overlapping portion of the data lines and the first connection structure includes a recess, and the recess of either the overlapping portion of the data lines or the first connection structure is recessed in the second direction toward a direction away from the other of the overlapping portion of the data lines or the first connection structure.

14. The display substrate according to claim 13, wherein the overlapping portion of the data lines includes a first recess that is recessed in the second direction toward a direction away from the first connection structure, and the portion of the first connection structure facing the data lines is in the shape of a straight strip.

15. The display substrate according to claim 13, wherein the first connection structure includes a second recess that is recessed in the second direction away from the overlapping portion of the data lines, and the overlapping portion of the data lines forms a linear strip shape.

16. The display board according to claim 13, wherein the overlapping portion of the data lines includes a first recess that is recessed in the second direction toward a direction away from the first connection structure, and the first connection structure includes a second recess that is recessed in the second direction toward a direction away from the overlapping portion of the data lines.

17. Further including a first reset scan signal line, a second reset scan signal line, a first reset signal line, and a second reset signal line, The aforementioned pixel circuit is A first reset transistor including an active layer, wherein the first reset scan signal line is configured to provide a first reset scan signal to the gate electrode of the first reset transistor, the first electrode of the first reset transistor is electrically connected to the gate electrode of the drive transistor, the second electrode of the first reset transistor is electrically connected to the first reset signal line to receive a first reset signal, and the first reset transistor is configured to write the first reset signal to the gate electrode of the drive transistor in response to the first reset scan signal. The device further includes a second reset transistor, the second reset scan signal line being configured to provide a second reset scan signal to the gate electrode of the second reset transistor, the first pole of the second reset transistor being electrically connected to a first indicator electrode of the light-emitting device, the second pole of the second reset transistor being electrically connected to the second reset signal line being configured to receive a second reset signal, and the second reset transistor being configured to write the second reset signal to the first indicator electrode of the light-emitting device in response to the second reset scan signal. The active layer of the first reset transistor extends along the first direction, and the first reset scan signal line extends along the second direction. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, and the plurality of sub-pixels further include a third sub-pixel adjacent to the second sub-pixel in the first direction. The portions of the second reset signal line located at each of the plurality of sub-pixels include a horizontal portion extending along the second direction and having a first end and a second end facing each other in the second direction, and a first vertical portion connected to the first end of the horizontal portion and extending along the first direction. The orthographic projection of the horizontal portion of the second reset signal line of the second sub-pixel on the base substrate and the orthographic projection of the first reset scan signal line of the third sub-pixel on the base substrate at least partially overlap, and the first vertical portion of the second reset signal line of the second sub-pixel and the active layer of the first reset transistor of the third sub-pixel are arranged at intervals in the second direction. The display substrate according to claim 1.

18. The planar pattern of the sub-part of the second reset signal line corresponding to one sub-pixel forms an inverted "Ji" shape, and the "Ji" shaped sub-part includes a U-shaped groove, and the horizontal portion of the second reset signal line functions as the bottom of the U-shaped groove. The display substrate according to claim 17.

19. Further includes a compensation scan signal line. The pixel circuit is Further includes a compensation transistor including an active layer, a gate electrode, a first electrode, and a second electrode. The scan signal line is configured to apply a second scan signal to the gate electrode of the compensation transistor, and the compensation transistor is configured to perform threshold compensation on the drive transistor in response to the second scan signal. The active layer of the compensation transistor and the active layer of the first reset transistor form an integral structure. The display substrate according to claim 17.

20. The portion of the second reset signal line located at one of the sub-pixels further includes a second vertical portion connected to the second end of the horizontal portion and extending along the first direction. The active layer of the first reset transistor of the third sub-pixel is located between the first vertical portion and the second vertical portion of the second reset signal line of the second sub-image. In the same subpixel, in the second direction, the distance between the first vertical portion and the data line is greater than the distance between the second vertical portion and the data line. The display substrate according to claim 17, wherein the distance between the active layer of the first reset transistor of the third subpixel and the first vertical portion of the second reset signal line of the second subpixel is smaller than the distance between the active layer of the first reset transistor of the third subpixel and the second vertical portion of the second reset signal line of the second subpixel.

21. The gate electrode of the drive transistor and the first electrode plate of the storage capacitor are arranged in the same layer to form an integrated structure, and the second reset scan signal line and the gate electrode of the drive transistor are arranged in the same layer. The gate electrode of the drive transistor and the first plate of the storage capacitor are located on the side of the active layer of the drive transistor that is away from the base substrate. The second plate of the storage capacitor is located on the side of the gate electrode of the drive transistor and the first plate of the storage capacitor that is away from the base substrate, and the compensation scanning signal line and the second plate of the storage capacitor are arranged on the same layer. The active layer of the compensation transistor is located on the side of the second electrode plate of the storage capacitor that is away from the base substrate. The display board according to claim 19, wherein the second reset signal line is located on the side of the active layer of the compensation transistor away from the base substrate.

22. The active layer of the first reset transistor and the active layer of the drive transistor are formed of different materials and arranged in different layers. The display board according to claim 21, wherein the first reset signal line and the second electrode plate of the storage capacitor are arranged in the same layer.

23. Both the gate electrode of the compensation transistor and the gate electrode of the first reset transistor have a dual-gate structure, and the gate electrode of the compensation transistor includes a first gate electrode and a second gate electrode. The gate electrode of the first reset transistor includes a first gate electrode and a second gate electrode, The display substrate according to claim 22, wherein the orthographic projection of the first gate electrode of the compensation transistor on the base substrate and the orthographic projection of the second gate electrode of the compensation transistor on the base substrate overlap, and the orthographic projection of the first gate electrode of the first reset transistor on the base substrate and the orthographic projection of the second gate electrode of the first reset transistor on the base substrate overlap.

24. The display substrate according to claim 23, wherein the first gate electrode of the compensation transistor and the first gate electrode of the first reset transistor are arranged in the same layer as the second electrode plate of the storage capacitor, and the second gate electrode of the compensation transistor and the second gate electrode of the first reset transistor are located on the side of the active layer of the compensation transistor and the active layer of the first reset transistor that is away from the base substrate, and are located on the side of the second reset signal line that is closer to the base substrate.

25. The material of the active layer of the first reset transistor is an oxide semiconductor. The display substrate according to claim 22, wherein the material of the active layer of the drive transistor and the data writing transistor is low-temperature polysilicon.

26. The first connection structure is located on the side of the second electrode plate of the storage capacitor away from the base substrate, The second plate of the storage capacitor has a first via hole that exposes the first plate of the storage capacitor, the first connection structure is connected to the first plate of the storage capacitor by passing through the first via hole, the second plate of the storage capacitor includes a first portion located on the first side in the second direction of the first via hole and a second portion located on the second side in the second direction of the first via hole, the first side of the first via hole faces the second side of the first via hole, and in one of the plurality of subpixels, the second portion of the second plate is located on the side of the first portion of the second plate that is closer to the data line, The display substrate according to claim 21, wherein the orthographic projection on the base substrate of the edge of the first connection structure that is close to the second portion of the second electrode plate of the storage capacitor in the second direction, the orthographic projection on the base substrate of the edge of the first display electrode that is close to the first connection structure, and the orthographic projection on the base substrate of the edge of the second portion of the second electrode plate that is close to the first connection structure overlap.

27. The first connection structure and the second reset signal line are arranged on the same layer. The display board according to claim 21, wherein, when the first connection structure and the data line are arranged in different layers, the data line is located on the side of the first connection structure away from the base substrate, or the data line is located on the side of the first connection structure closer to the base substrate.

28. The first connecting structure includes a first portion extending along the first direction and a second portion extending along the second direction and connected to the first portion. The display substrate according to claim 19, wherein in one of the plurality of subpixels, the active layer of the compensation transistor is located on the side of the first connection structure away from the data line, and the second portion of the first connection structure is connected to the active layer of the compensation transistor.

29. The orthographic projection of the entire first connection structure on the base substrate is located within the orthographic projection of the first display electrode of the light-emitting device on the base substrate. The display substrate according to claim 1, wherein the plurality of subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, each of the first subpixel and the second subpixel includes the pixel circuit, the first display electrode of the first subpixel covers the boundary between the first subpixel and the second subpixel, and the orthographic projection of the first connection structure of the first subpixel on the base substrate and the orthographic projection of the first connection structure of the second subpixel on the base substrate are both located within the orthographic projection of the first display electrode of the first subpixel on the base substrate.

30. The display substrate according to claim 29, wherein the orthographic projection on the base substrate of the edge of the first display electrode of the first subpixel that is far from the second subpixel overlaps with the orthographic projection on the base substrate of the edge of the first connection structure of the first subpixel that is close to the data line of the first subpixel, and the orthographic projection on the base substrate of the edge of the first display electrode of the first subpixel that is close to the second subpixel overlaps with the orthographic projection on the base substrate of the edge of the first connection structure of the second subpixel that is close to the data line of the second subpixel.

31. A portion of the orthographic projection of the base substrate of the first connection structure is located within the orthographic projection of the first display electrode of the light-emitting device on the base substrate. The display substrate according to claim 1, wherein the plurality of subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, each of the first subpixel and the second subpixel includes the pixel circuit, the first display electrode of the first subpixel covers the boundary between the first subpixel and the second subpixel, and both a portion of the orthographic projection of the first connection structure of the first subpixel on the base substrate and a portion of the orthographic projection of the first connection structure of the second subpixel on the base substrate are located within the orthographic projection of the first display electrode of the first subpixel on the base substrate.

32. The display substrate according to claim 31, wherein the light-emitting material of the light-emitting device of the first subpixel emits green light.

33. The first plate of the storage capacitor has an upper surface that is separated from the base substrate and a side surface that intersects with the upper surface. The second plate of the aforementioned storage capacitor is The orthographic projection on the base substrate at least partially overlaps with the orthographic projection on the base substrate of the first plate of the storage capacitor, and includes an intermediate portion including the bottom surface facing the top surface of the first plate of the storage capacitor, The intermediate portion is at least partially surrounded and connected to the intermediate portion, and includes an edge portion that includes a bottom surface near the base substrate and an inner surface intersecting the bottom surface, wherein the inner surface faces the side surface of the first plate of the capacitor, and the orthographic projection of the inner surface on a reference plane perpendicular to the base substrate at least partially overlaps with the orthographic projection of the side surface of the first plate of the storage capacitor facing the inner surface on the reference plane. The display board according to claim 1, wherein the distance between the inner surface of the edge portion and the side surface of the first electrode plate of the storage capacitor facing the inner surface is smaller than the distance between the bottom surface of the intermediate portion and the top surface of the first electrode plate of the storage capacitor.

34. The first display electrode of the light-emitting device has a first end and a second end that face each other in the second direction. The display substrate includes a first semiconductor, the first semiconductor layer includes the active layer of the drive transistor and the active layer of the data writing transistor, and the data lines are connected to the first semiconductor layer via second via holes. The plurality of subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, each of the first subpixel and the second subpixel includes the pixel circuit, the first display electrode of the first subpixel covers the boundary between the first subpixel and the second subpixel, the orthographic projection on the base substrate of the first end of the first display electrode of the first subpixel has a first projection that tapers toward the orthographic projection on the base substrate of the second via hole of the first subpixel in the second direction, the orthographic projection on the base substrate of the second end of the first display electrode of the first subpixel has a second projection that tapers toward the orthographic projection on the base substrate of the second via hole of the second subpixel in the second direction, the orthographic projections on the base substrate of the first projection and the second via hole of the first subpixel face each other in the second direction, the orthographic projections on the base substrate of the second projection and the second via hole of the second subpixel face each other in the second direction. The display substrate according to claim 1, wherein the light-emitting material of the light-emitting device of the first subpixel emits blue light.

35. The gate electrode of the drive transistor and the first plate of the storage capacitor are arranged in the same layer to form an integrated structure, the gate electrode of the drive transistor and the first plate of the storage capacitor are located on the side of the active layer of the drive transistor away from the base substrate, and the second plate of the storage capacitor is located on the side of the gate electrode of the drive transistor and the first plate of the storage capacitor away from the base substrate. The aforementioned display board is It further includes a first power line connected to a first voltage terminal and configured to supply a first power supply voltage to the pixel circuit, extending along a first direction, The aforementioned pixel circuit is The present invention further includes a second connection structure positioned between the first power line and the storage capacitor in a direction perpendicular to the base substrate, and connecting the first power line and the second plate of the storage capacitor, wherein the second connection structure includes a horizontal portion extending along the second direction and a vertical portion connected to the horizontal portion and extending along the first direction. The display board according to claim 1, wherein the orthographic projection of the first power line on the base board overlaps with the orthographic projection of the horizontal portion of the second connection structure on the base board, and the orthographic projection of the first power line on the base board does not overlap with the orthographic projection of other structures arranged on the same layer as the second connection structure on the base board.

36. The display board according to claim 35, wherein the vertical portion is basically aligned with the first connection structure in the first direction, and the orthographic projection of the horizontal portion on the base substrate extends from the orthographic projection of the vertical portion on the base substrate along the first direction to the orthographic projection of the first power line on the base substrate.

37. A first insulating layer located between the first power line and the second connection structure, The display board according to claim 35, further comprising a second insulating layer positioned between the second connection structure and the second plate of the storage capacitor, wherein the horizontal portion of the first power line is connected to the second connection structure via a third via hole penetrating the first insulating layer, and the vertical portion of the second connection structure is connected to the second plate of the storage capacitor via a fourth via hole penetrating the second insulating layer.

38. The display board according to claim 35, wherein the first power line and the data line are arranged on the same layer, and the second connection structure and the first connection structure are arranged on the same layer.

39. The aforementioned pixel circuit is The present invention further includes a first light-emitting transistor connected to the first pole and the first voltage terminal of the drive transistor, and configured to apply a first power supply voltage at the first voltage terminal to the first pole of the drive transistor in response to a first light-emitting control signal applied to the gate electrode of the first light-emitting transistor, The display substrate according to claim 35, wherein the display substrate includes a first semiconductor layer, the first semiconductor layer includes the active layer of the drive transistor, the active layer of the data writing transistor, and the active layer of the first light-emitting transistor, and the horizontal portion of the second connection structure is connected to the first semiconductor layer via a fifth via hole.

40. The display substrate according to claim 39, wherein the horizontal portion of the second connection structure has a first end and a second end facing each other in the second direction, the first end of the horizontal portion is located on the side of the first power line closer to the vertical portion and connected to the vertical portion, and the second end of the horizontal portion is located on the side of the first power line further away from the vertical portion and connected to the first semiconductor layer via the fifth via hole.

41. A display device comprising a display board according to any one of claims 1 to 40.

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