Multiplication type spectrum spread generator
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2023-07-28
- Publication Date
- 2026-07-21
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
Technical Field
[0001] A phase-locked loop (PLL) is a circuit that provides an output signal having a phase related to the phase of the input signal of the PLL. The phase of the output signal having a certain relationship with respect to the phase of the input signal makes the frequency of the output signal have a certain relationship with respect to the frequency of the input signal. For example, the output frequency is a multiple of the input frequency.
Summary of the Invention
[0002] In some examples, the circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, and the input of the control circuit is coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, and the input of the modulation circuit is coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input is coupled to the output of the modulation circuit, and the oscillator output is coupled to the second input of the PFD.
[0003] In some examples, the PLL includes an input, an output, a PFD, a control circuit, a modulation circuit, and an oscillator. The PFD is coupled to the input of the PLL and is operable to receive a reference signal having a reference signal frequency and compare the reference signal with a feedback signal having a feedback signal frequency, and in response, provide a first control signal. The control circuit is coupled to the PFD, receives the first control signal, and is operable to provide a second control signal having a current value determined based on the first control signal. The modulation circuit is coupled to the control circuit and is operable to modulate the second control signal to provide a modulated control signal whose value changes within one period of the reference signal. The oscillator is coupled between the modulation circuit and the output of the PLL, and the oscillator is operable to provide a signal having an output frequency proportional to the value of the second control signal, and at the rising edge of the reference signal, the second control signal has a value sufficient to make the output frequency equal to the reference signal frequency.
[0004] In some examples, a method includes receiving a reference signal having a reference signal frequency, comparing the reference signal frequency with the frequency of a feedback signal, providing a first control signal having a value based on the result of the comparison, providing a second control signal that is proportional to the reference signal frequency and has a value based on the first control signal, modulating the second control signal based on a modulation signal to form a modulated signal, and providing a signal having a frequency proportional to the modulated control signal.
Brief Description of the Drawings
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Figure 1
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Figure 2
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Figure 3
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[0010] In the drawings, the same reference numerals or other reference signs are used to indicate (functionally and / or structurally) identical or similar features.
Embodiments for Carrying Out the Invention
[0011] A PLL can be useful in various circuits, systems, or devices where signal synchronization is beneficial. For example, a PLL can be useful in clock synchronization, demodulation, frequency generation, or other applications such as communication, digital device control (e.g., clock generation). Based on the frequency (F IN) of a received signal such as a reference clock (CLK IN) or other reference signal, the PLL provides an output signal having a frequency (F PLL) that is a multiple of F IN.
[0012] A PLL can be useful for the operation of a DC-DC power converter. However, the operation of a DC-DC power converter can generate electromagnetic interference (EMI) based on the frequency of the F PLL (e.g., the switching frequency of the DC-DC power converter). Some use cases of DC-DC power converters can be sensitive to the generation of EMI or can be subject to restrictions on the generated EMI due to government regulations, industry standards, etc. Although it may be difficult to completely prevent EMI generation, several techniques can reduce or otherwise mitigate EMI. One such approach is spread spectrum clocking (SSC). SSC modulates the output signal of the PLL (CLK PLL) to have a frequency within a predetermined range centered around F PLL. Such modulation prevents or mitigates EMI concentration in the F PLL and instead disperses the radiated EMI among frequencies within a certain range around the F PLL as determined based on SSC. To limit the generated EMI to a specific amount, a specific F When a PLL is provided, there may be an ideal or optimal modulation frequency and amplitude for SSC modulation. In at least one application environment, this modulation frequency is about 120 kilohertz (kHz). Some use cases of the PLL may include boundary conditions that result in the SSC modulation frequency being outside the bandwidth of the PLL. In at least some examples, the bandwidth of the PLL can be about 10 times or less of F IN or less.
[0013] This description includes various examples of PLLs that can be configured to provide a PLL. At least some of such examples include circuit elements (e.g., analog, digital, or combinations thereof) suitable for performing such modulation to provide a PLL. In some examples, the amplitude of the modulation signal is not adjusted by the PLL but may be unaffected by changes in process, voltage, or temperature (PVT). At least some implementations of the PLL include an oscillator. The oscillator can be de-tuned to generate frequency modulation. De-tuning can be implemented by modulating a control signal of the oscillator, such as the value of the current provided to the oscillator to cause the PLL to provide a PLL. For example, the oscillator can be de-tuned according to a modulation signal (I ssm) determined according to F<^ ssc which may be an integer multiple of F IN. The PLL can be adjusted based on the average of F PLL over one clock cycle of CLK REF. In this way, the CLK PLL can be adjusted in the positive and negative directions with respect to the F PLL (e.g., in one example, by equal amounts in the positive and negative directions, in other words, more or less than the F PLL by a specific amount). can be modulated according to the ssc, and the modulation is F PLL and F does not affect the average of the ssc and is not within the PLL bandwidth. Thus, it can be said that the modulation is invisible to the PLL.
[0014] FIG. 1 is a block diagram of system 100 in various examples. In some implementations, system 100 can obtain advantages from the implementation of a PLL. Therefore, system 100 includes a device 102 that includes a PLL 104, a circuit 106, and a circuit 108. Device 102 can be any suitable device that can obtain advantages from a PLL as described herein, such as PLL 104, including a computer system, a router, a smartphone, a wearable device, an audio and / or video device, a component of a transport vehicle, etc. PLL 104 can be implemented according to any suitable technique including analog and / or digital components and can be implemented in a single integrated circuit or in multiple integrated circuits coupled together. Also, PLL 104 may be implemented on the same integrated circuit as at least some components of other circuits, such as circuit 106, circuit 108, and / or other circuits not shown in FIG. 1. Circuit 106 provides CLK IN to PLL 104. In some examples, CLK IN is received by circuit 106 as an input from another component or is provided by a user, and circuit 106 provides CLK IN to PLL 104. In other examples, CLK IN can be received by the system 100 from a user and / or can be generated by the system 100, and is generated by the circuit 106 or provided in some other way based on one or more other signals. The circuit 106 can be implemented according to any suitable technique including analog and / or digital components, for example, can include a processor, state machine, logic circuit, digital circuit, memory, analog circuit, software, and / or any combination thereof, suitable for implementing at least the operations or functions attributed to the circuit 106 herein. The circuit 108 receives the output signal (CLK PLL) of the PLL 104. In some examples, the circuit 108 operates at least partially in accordance with the CLK PLL (e.g., can be clocked in accordance with the CLK PLL, can synchronize another signal or process it in some other way based on the CLK PLL, etc.). As described herein, the CLK PLL has a frequency F PLL that has a certain relationship such as an integer relationship with F_IN (which is, for example, the frequency of the received clock signal CLK IN). As used herein, an integer relationship between two values means that one value is multiplied by an integer to obtain the other value, or one value is divided by an integer to obtain the other value. The circuit 108 can be implemented according to any suitable technique including analog and / or digital components, for example, can include a processor, state machine, logic circuit, digital circuit, memory, analog circuit, software, and / or any combination thereof, suitable for implementing at least the operations or functions attributed to the circuit 108 herein.
[0015] The PLL 104 can be operable to receive the CLK IN, operate on the CLK IN to form a signal CLK REF having a frequency F ref. F ref is F has an integer relationship with IN. For example, PLL104 divides F ref by F IN such that CLK IN is divided (frequency-divided) by IN to form CLK REF. PLL104 compares the frequency and phase of CLK REF with the frequency and phase of a feedback signal having an integer relationship with CLK PLL. Based on the comparison, PLL104 provides a control signal for controlling an oscillator (not shown) within PLL104. In at least some examples, the control signal is a current-based control signal (I ctrl0). The control signal determines I ssm based on F ssm and CLK IN, and adds a modulation signal to I ctrl0 to form a second control signal (I ctrl), which may be provided to a modulation circuit (not shown) within PLL104. In at least some examples, I ssm is represented in terms of current. PLL104 controls the oscillator based on I ctrl to provide CLK PLL104. In some examples, PLL104 further operates (e.g., multiplies (frequency-multiplies) or divides (frequency-divides)) the output signal of the oscillator before providing the operated signal as CLK PLL.
[0016] FIG. 2 is a block diagram of PLL104 in various examples. PLL104 includes a divider 202, a divider 204, a phase frequency detector (PFD) 206, a control circuit 208, a modulation circuit 210, an oscillator 212, a control circuit 216, and a divider 218. Divider 202, divider 204, and divider 218 can be of any suitable technology, including digital and / or analog components operable to divide a signal, such as to reduce the frequency of the output signal of the divider relative to the frequency of the input signal received by the divider. PFD 206 can be of any suitable technology, including digital and / or analog components operable to receive a plurality of signals and compare the frequency and / or phase values of the signals to determine an output value. The output value of PFD 206 can indicate that a control signal for controlling oscillator 212 should increase in value or decrease in value. In some examples, control circuit 216 can be any suitable control circuit operable to receive an input signal and provide a DACCODE based on the received input signal. In some examples, the input signal to control circuit 216 is CLK IN. Control circuit 216 can include, for example, a processor, a state machine, logic circuitry, digital circuitry, memory, analog circuitry, software, and / or any combination thereof, suitable for performing at least the operations or functions attributed to control circuit 216 herein.
[0017] The control circuit 208 can be of any suitable technology including digital and / or analog components that are operable to receive a signal and provide a control signal based on the received signal. In some examples, the control circuit 208 is implemented as or includes a charge pump capable of providing a control signal having a current value determined based on the output value of the PFD 206. The modulation circuit 210 can be of any suitable technology including digital components such as transistors, resistors, amplifiers, etc. and / or analog components that are operable to receive a control signal from the control circuit 216 and control the oscillator 212 to provide an output signal having a frequency proportional to the value of the control signal (e.g., a frequency proportional to the current value of the control signal, etc.). The oscillator 212 can be of any suitable technology including digital components and / or analog components that are operable to provide a signal having a certain frequency that is proportional to or otherwise determined according to the value of the input signal received by the oscillator 212. In some examples, the oscillator 212 has a ring oscillator architecture and / or includes a bulk acoustic wave device (BAW). In some examples, the oscillator 212 is operable to provide its output signal as CLK It is provided to other circuits that provide a PLL. The control circuit 216 can be of any suitable technology including digital and / or analog components that is operable to receive an input signal of the PLL 104, or other signals, and provide a digital (or other) control signal to the modulation circuit 210. For example, a digital signal can control the value of the modulation signal of the modulation circuit 210 by means of a multiplying digital-to-analog converter (DAC) 220 or the like. For example, the control circuit 216 can include a counter such as a digital up / down counter (not shown) suitable for determining and providing the DACCODE as a digital signal. The divider 218 can be coupled between the output of the oscillator 212 and the input of the PFD 206 and can be operable to provide a feedback signal that is a scaled representation of the output signal of the oscillator 212 (e.g., having a lower or divided frequency) to the PFD 206.
[0018] In an example of the operation of the PLL 104, a clock signal CLK IN (having the frequency of F_IN) is received at the input of the PLL 104. In an example of the PLL 104 including the divider 202 and the divider 204, CLK_IN is divided by the divider 202 and the divider 204 to form CLK_REF having the frequency of F ref. In one example, the dividing circuit 202 is a divide-by-two circuit and the dividing circuit 204 is a divide-by-sixteen circuit. Although two dividers are shown in FIG. 2, in various examples, dividers each having any suitable division value can be implemented. The PFD 206 receives CLK REF and compares CLK REF with the output of the divider 218. Based on the comparison, the PFD 206 provides a control signal to the control circuit 208. For example, in response to F ref being greater than the frequency of the output signal of the divider 218, the PFD 206 provides a control signal to the control circuit 208 that is operable to increase the value of the control signal provided to control the oscillator 212 to the control circuit 208. Similarly, F In response to ref being less than the frequency of the output signal of frequency divider 218, PFD 206 provides a control signal to control circuit 208 operable to cause control circuit 208 to decrease the value of the control signal provided to control oscillator 212. PFD 206 may perform the phase and / or frequency comparison according to any suitable hardware architecture, software process, or combination thereof.
[0019] Based on the control signal provided by the PFD 206, the control circuit 208 may be operable to provide a control signal for controlling the oscillator 212. For example, the control circuit 208 may receive the output signal of the PFD 206 and provide a control signal having a value proportional to the value of the output signal of the PFD 206. In some examples, the control signal provided by the control circuit 208 has a current that is proportional to or otherwise related to the value of the output signal of the PFD 206. For example, the control circuit 208 may include a charge pump of any suitable architecture that receives the output signal of the PFD 206 and provides a control signal having a current value that has a relationship to the value of the output signal of the PFD 206. The control signal provided by the control circuit 208 may be a charge pump of any suitable architecture that receives the output signal of the PFD 206 and provides a control signal having a current value that has a relationship to the value of the output signal of the PFD 206. This is shown in Figure 2 as ctrl0.
[0020] The modulation circuit 210 is Receive ctrl0 and I The current I For example, in various implementations, the modulation circuit 210 provides I Modulate ctrl0 to I ctrl. The modulation of ctrl0 may, in some instances, be performed as described above in this specification for SSCs, such as F PLL and / or F Provides mitigation of EMI generation at PLL harmonics. To modulate ctrl0, DAC 220 receives DACCODE from control circuit 216. Control circuit 216 may modulate CLK according to any suitable process. IN and / or F Provide a DACCODE based on IN, the scope of which is not limited herein. For example, the control circuit 216 may determine and provide the DACCODE based on the shape for modulation, such as having values suitable for forming a sine wave approximation, a triangular wave approximation, a rectangular wave approximation, or any other suitable modulation pattern. Based on the DACCODE, the DAC 220 may be operable to provide an I ssm. In some examples, the I ssm is a current having a value proportional to the value of the DACCODE. The modulation circuit 210 may be operable to sum I ctrl0 and I ssm to provide an I ctrl. In some examples, this sum is through a direct connection between the output of the control circuit 208 and the DAC 220 (e.g., the sum of the currents at a node in the modulation circuit 210). In other examples, the modulation circuit 210 receives both I ctrl0 and I ssm and includes a circuit structure or component (not shown) that provides an I ctrl as the sum of I ctrl0 and I ssm.
[0021] The modulation circuit 210 provides an I ctrl to the oscillator 212. The oscillator 212 may be operable to provide an output signal having a frequency proportional to the value of the I ctrl. For example, the frequency of the output signal of the oscillator 212 may be proportional to or have another relationship with the current value of the I ctrl. In some examples, the oscillator 212 has a ring oscillator architecture, and in other examples, the oscillator 212 has any suitable architecture for providing a signal having a frequency that has a programmed or predictable relationship with the value of the I ctrl.
[0022] In some examples, PLL 104 includes an additional divider (not shown) following oscillator 212, such that the output signal of oscillator 212 is divided by the divider to frequency F CLK with PLL can form a PLL. The division can be by any suitable division value based on the application environment of PLL 104, such as a division value of 4. The output signal of oscillator 212 can be divided by divider 218 to form a feedback signal for providing to PFD 206 as described above. Divider 218 can divide by any suitable division value based on the application environment of PLL 104.
[0023] I ctrl0 and I I according to both ssm By controlling the generation of ctrl, CLK PLL (and thus F PLL) can be modulated around the programmed frequency or target frequency for the output by PLL 104. F By modulating the PLL, F the peak value of the EMI generated and / or radiated based on the PLL can be reduced. However, based on the control made according to DACCODE, CLK At each rising clock edge of REF, F PLL can have a value approximately equal to the programmed frequency or target frequency for the output by PLL 104, making the modulation effectively transparent to PLL 104.
[0024] FIG. 3 is a schematic diagram of modulation circuit 210 in various examples. In some examples, modulation circuit 210 includes transistor 302, transistor 304, transistor 306, transistor 308, transistor 310, transistor 312, transistor 314, DAC 316, amplifier 318, and resistor 320. In some examples, at least some of the various transistors of modulation circuit 210 are field effect transistors (FETs) such as metal oxide semiconductor FETs (MOSFETs).
[0025] In the exemplary architecture of the modulation circuit 210, the transistor 302 is an n-channel MOSFET (nMOSFET) and has a drain operable to receive I ctrl (such as by being coupled to the output of the control circuit 208), and a source coupled to ground 322. The transistor 304 has a gate coupled to the gate and drain of the transistor 302, a source coupled to ground 322, and a drain coupled to the oscillator 212 (e.g., I (such that Ctrl can be provided at the drain of transistor 304). In at least some examples, transistors 302 and 304 form a current mirror such that a scaled amount of current flowing through transistor 302 also flows through transistor 304. For example, if transistors 302 and 304 are the same size (e.g., channel width and channel length), the current flowing through transistor 302 is equal to the current flowing through transistor 304. In other ways, the scaled current may be proportional to the size difference of the transistors. Transistor 306 has a gate coupled to the gate of transistor 302, a source coupled to ground 322, and a drain. In at least some examples, transistors 302 and 306 form a current mirror such that a scaled amount of current flowing through transistor 302 also flows through transistor 306. Transistor 308 is a p-channel transistor (pMOSFET) and has a gate coupled to the drains of transistor 306 and transistor 308, and a source coupled to power supply 324. Transistor 310 has a gate coupled to the drains of transistor 306 and transistor 308, a drain, and a source coupled to power supply 324. In at least some examples, transistors 308 and 310 form a current mirror such that a scaled amount of the current flowing through transistor 310 is based on the amount of current flowing through transistor 308. Transistor 312 has a gate connected to the drain of transistor 306, a drain, and a source connected to power supply 324. In at least some examples, transistors 308 and 312 form a current mirror such that a scaled amount of the current flowing through transistor 312 is based on the amount of current flowing through transistor 308. In some examples, the ratio of the current mirror is 1:1, but in other examples, the ratio is 1:X, where X is related to the size difference of the transistors forming the current mirror. Transistor 314 has a gate, a drain connected to the drain of transistor 312, and a source.
[0026] The DAC 316 has a first terminal coupled to the drain of the transistor 312, a second terminal coupled to the ground 322, a control terminal coupled to the control circuit 216, and an output terminal. The DAC 316 can be of any suitable architecture such as a resistor DAC. The amplifier 318 has a first input terminal (such as a non-inverting input) coupled to the output terminal of the DAC 316, an output terminal coupled to the gate of the transistor 314, and a second input terminal (such as an inverting input) coupled to the source of the transistor 314. The resistor 320 is coupled between the source of the transistor 314 and the ground 322. In some examples, the DAC 316, the amplifier 318, the transistor 314, and the resistor 320 collectively form the DAC 220 of FIG. 2.
[0027] In an example of the operation of the modulation circuit 210, the current I ctrl0 can be received as a control signal from a PLL control loop (e.g., as the output of the control circuit 208). The modulation circuit 210 mirrors (and, in some examples, scales) I ctrl0 via the transistors 302, 304, and 312 and provides it at the output of the modulation circuit 210 (e.g., at the drain of the transistor 304). The modulation circuit 210 also mirrors (and, in some examples, scales) I ctrl0 via the transistors 302, 306 and 308, 310 and applies it to the DAC 316. For example, the current I Ctrl0 flows through transistor 302 and is mirrored to flow through transistor 306. Through their connection, the current flowing through transistor 306 also flows through transistor 308. The current flowing through transistor 308 is mirrored and flows to DAC316 through transistor 310. In some examples, DAC316 is a resistor ladder. For example, DAC316 can be a resistor ladder with 17 taps, and the resistor ladder includes a plurality of switches coupled between each tap of the resistor ladder and the first input terminal of amplifier 318. Each of these switches can be controlled according to each bit of DACCODE. In other examples, the number of taps of the resistor ladder, and thus the accuracy of DAC316, can correspond to the number of unique values possible based on the number of bits included in DACCODE.
[0028] Based on the value of DACCODE, DAC316 provides a certain value (e.g., tap voltage) at the first input terminal of amplifier 318. Amplifier 318 and transistor 314 provide the tap voltage at the source of transistor 314 such that the tap voltage is provided across resistor 320. The voltage across resistor 320 generates current I_ssm, which can be added to I_ctrl0 at the output of modulation circuit 210 based on node addition. In some examples, modulation circuit 210 provides I ssm to have a value approximately equal to the value of the DACCODE value multiplied by a fraction of I ctrl0. As described above, combining I ctrl0 with I ssm facilitates modulation of PLL104 while promoting PLL104 to provide a signal having the average frequency of the F PLL and reducing the formation of EMI at the F PLL or its harmonics. PLL or its harmonics.
[0029] For example, as described above, oscillator 212 can be a current controlled oscillator (CCO). I_ctrl0 can be a base current for controlling oscillator 212 and can determine, specify, or program in some other way the average CCO frequency for oscillator 212. I_ctrl is the CCO control current derived from I ctrl0 and I ssm. I ssm is a modulation current as described above, which is derived from I ctrl0 and depends on the component ratios of PLL104 (e.g., the ratio of the current mirrors of PLL104 as described above) and the value of DACCODE, and thus has a well-controlled amplitude. For example, I ssm can be determined based on Equation 1 below, where K is a scaling factor determined by the size (and thus the current mirror ratio) of the transistors (e.g., 302, 304, 306, 308, 310, 312) of PLL104. I ssm = K × DACCODE × I ctrl0 (1)
[0030] FIG. 4 is a timing diagram 400 of signals in various examples. In at least some examples, the signals represented in FIG. 400 are signals of PLL104 as described above or are related to PLL104. Thus, components or signals of PLL104 can be referred to as described above with reference to other figures in this specification. Timing diagram 400 includes CLK IN, CLK REF, and F PLL. CLK IN and CLK REF are shown in FIG. 4 with a horizontal axis representing time and a vertical axis representing voltage (e.g., binary values - logic high and logic low). F PLL is shown in FIG. 4 with a horizontal axis representing time and a vertical axis representing frequency.
[0031] As shown in timing diagram 400, CLK IN is CLK CLK can be divided to form REF. As shown in FIG. 400, IN is CLK It can be divided by 32 to form REF (for example, divider 202 is a divide-by-2 circuit and divider 204 is a divide-by-16 circuit). In other examples, any other appropriate divisor can be used (for example, based on the division values of divider 202 and divider 204). As further shown in FIG. 400, F_PLL is CLK It can be modulated so as to have approximately the nominal value or target value at each rising edge of REF, but F PLL changes from the nominal value by +ΔF at 1 / 4 of the period of CLK and changes from the nominal value by -ΔF at 3 / 4 of the period of REF. The change of F PLL (for example, the modulation of F PLL) can be controlled based on the value of DACCODE so that F PLL can be gradually stepped to different values at the rising clock edge of CLK IN. In this way, SSC can be implemented so that EMI generation based on F PLL or its harmonics can be mitigated. In timing diagram 400, it has a triangular wave approximation shape, and CLK has a maximum positive deviation at about 1 / 4 of the period of REF and CLK has a maximum negative deviation at about 3 / 4 of the period of REF as shown, but in various examples, F PLL (for example, based on the modulation pattern provided according to DACCODE) can have any other appropriate shape with a maximum positive deviation or a maximum negative deviation at any appropriate point of the period of CLK REF.
[0032] FIG. 5 is a flowchart of a method 500 of operating a PLL in various examples. In at least some examples, the PLL is PLL 104. Thus, components or signals of PLL 104 can be referenced as described above with reference to other figures herein. In some examples, the PLL is operable to provide a signal (e.g., a clock signal, etc.) for synchronizing the operation of some other components. As described elsewhere herein, in some situations, EMI can be generated at the operating frequency of the PLL or at various harmonics of the operating frequency. To mitigate the occurrence of such EMI, method 500 includes modulating the operating frequency of the PLL to implement SSC.
[0033] In operation 502, a reference signal is received as an input signal. In some examples, the input signal is CLK_IN as described above herein and has a frequency of F IN. In some examples, the input signal can be divided (to reduce the value of F IN) and can form CLK REF having a frequency of F ref.
[0034] In operation 504, F ref is compared to the frequency of the feedback signal. In some examples, the feedback signal can be the output signal (frequency F CLK having a PLL PLL, etc.) of an oscillator of the PLL, such as oscillator 212, or a scaled representation of the output signal. The comparison can be performed by a PFD, such as PFD 206, in some examples. Based on the comparison, a first control signal can be provided indicating whether F ref is greater than or less than the feedback signal.
[0035] In operation 506, a second control signal is provided. In some examples, the second control signal can be provided to have a current or other characteristic proportional to F PLL. The comparison of operation 504 is F In response to indicating that ref is greater than the feedback signal, the value of the second control signal can be increased to increase the frequency of the oscillator output signal. The comparison of operation 504 is F In response to indicating that ref is less than the feedback signal, the value of the second control signal can be decreased to decrease the frequency of the oscillator output signal.
[0036] In operation 508, the second control signal is modulated to form an SSC control signal. The SSC control signal, in some examples, is CLK Within one period of REF, F The frequency of the oscillator output signal to the PLL can be modulated to increase or decrease. The frequency of the oscillator output signal, in some examples, is F Increased or decreased from the PLL by ΔF. In at least some examples, the modulation can be controlled based on DACCODE as described above. In some implementations, operation 508 can be repeated for each received rising edge of CLK_IN.
[0037] In operation 510, a signal having a frequency proportional to the SSC control signal is provided. In some examples, the signal can instead have a frequency that is not proportional to the SSC control signal but has a certain relationship. In at least some examples, the oscillator can be operable to provide the signal as the oscillator output signal. The modulation of the second control signal to form the SSC control signal, in some examples, is F While facilitating a PLL that provides a signal having the average frequency of the PLL, F Mitigates the formation of EMI in the PLL or its harmonics.
[0038] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, when Device A generates a signal to control Device B to perform a certain action, in a first example, Device A is coupled to Device B, or in a second example, when intervening component C does not substantially change the functional relationship between Device A and Device B, Device A is coupled to Device B via intervening component C such that Device B is controlled by Device A via the control signal generated by Device A.
[0039] A device "configured" to perform a certain task or function can be configured by a manufacturer during manufacturing to perform that task or function (e.g., programming and / or wired connection), and / or can be configured (or reconfigured) by a user after manufacturing to perform such functions and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the construction and / or layout of hardware components, via the interconnection of the device, or via a combination thereof. A circuit or device described herein as including certain components may instead be coupled to those components and adapted to form the described circuit or device.
[0040] As used herein, terms such as "terminal" and "node", "interconnection", "pin", "ball", and "lead" are used interchangeably. Unless otherwise specified, these terms are generally used to mean an interconnection between, or a termination of, device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components. While in one example of the described elements, some are included in a circuit and others are outside that circuit, in other examples additional or fewer features may be incorporated into the circuit. Also, some or all of the features shown as being outside the circuit may be included in the circuit and / or some of the features shown as being inside the circuit may be incorporated outside the circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board. Although a particular transistor is described herein for use, other transistors (or equivalent devices) may be used instead, with little or no change to the remaining circuit elements. For example, metal-oxide-semiconductor FETs ("MOSFETs") (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of, or in combination with, the devices described herein. The transistor may be a depletion-mode device, drain-extended device, enhancement-mode device, natural transistor, or other type of device-structure transistor. Also, the device may be implemented within / on a silicon substrate (Si), silicon carbide substrate (SiC), gallium nitride substrate (GaN), or gallium arsenide substrate (GaAs).
[0041] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings of this description. Unless otherwise specifically stated, "about", "approximately", or "substantially" preceding a value means + / - 10% of the stated value, and when the value is zero, it is a reasonable range of values near zero.
[0042] Within the scope of the claims of the present invention, modifications can be made to the described examples, and other examples are also possible.
Claims
1. It is a circuit, A phase frequency detector (PFD) having a first input, a second input and an output, wherein the PFD is operable to receive a reference signal extracted from an input signal at the first input, A first control circuit having an input coupled to the output of the PFD and an output, A second control circuit having an input and an output, wherein the second control circuit is operable to receive the input signal at the input, A modulation circuit having a first input coupled to the output of the first control circuit, a second input coupled to the output of the second control circuit, and an output, An oscillator having an input coupled to the output of the modulation circuit and an output coupled to the second input of the PFD, A circuit that includes this.
2. The circuit according to claim 1, The modulation circuit includes a multiplicative digital-to-analog converter (DAC).
3. The circuit according to claim 2, A circuit in which the second control circuit is further operable to control the DAC to modulate the signal received by the modulation circuit in order to form a modulated signal.
4. The circuit according to claim 3, The aforementioned reference signal has a reference signal frequency, The PFD is further operable to receive a feedback signal having a feedback signal frequency at the second input and compare the reference signal frequency with the feedback signal frequency to provide a first control signal indicating whether the reference signal frequency is greater than or less than the feedback signal frequency.
5. The circuit according to claim 4, The control circuit is operable to receive the first control signal and provide a second control signal based on the first control signal. A circuit having a first value, wherein the second control signal increases in response to the first control signal indicating that the reference signal frequency is greater than the feedback signal frequency, and decreases in response to the first control signal indicating that the reference signal frequency is less than the feedback signal frequency.
6. The circuit according to claim 5, A circuit in which the first value is the current of the second control signal.
7. The circuit according to claim 5, The modulation circuit is operable to modulate the second control signal to form a modulated signal, and the modulated signal is a circuit that changes the current within one period of the reference signal such that the output signal of the oscillator changes the frequency within one period of the reference signal and has a certain value of the reference signal frequency at each pair of rising edges of the reference signal.
8. The circuit according to claim 7, The modulation circuit is further operable to modulate the second control signal with respect to the reference signal by equal amounts in the positive and negative directions during one period of the reference signal, such that the output signal of the oscillator has the average frequency of the reference signal frequency during one period of the reference signal.
9. It is a phase-locked loop (PLL), Input and Output and, A phase frequency detector (PFD) having a first input, a second input, and an output coupled to the input of the PLL, wherein the PFD is operable to provide a first control signal in response to receiving a reference signal having a reference signal frequency and a feedback signal having a feedback signal frequency, and comparing the reference signal and the feedback signal, A first control circuit having an input coupled to the output of the PFD and an output, the first control circuit being operable to receive the first control signal and to provide a second control signal having a current value determined based on the first control signal, A second control circuit having an input coupled to the input of the PLL and an output, A modulation circuit having a first input coupled to the output of the first control circuit, a second input coupled to the output of the second control circuit, and an output, wherein the modulation circuit is operable to modulate the second control signal to provide a modulated control signal whose value changes within one period of the reference signal, An oscillator having an input coupled to the output of the modulation circuit and an output coupled to the output of the PLL, the oscillator being operable to provide a signal having an output frequency proportional to the value of the second control signal, Includes, A phase-locked loop (PLL) in which, at the rising edge of the reference signal, the second control signal has a value sufficient to make the output frequency equal to the reference signal frequency.
10. A PLL according to claim 9, A PLL wherein the modulation circuit is further operable to modulate the second control signal by a first amount in the positive direction and a second amount in the negative direction during one period of the reference signal, such that the signal has the average frequency of the reference signal frequency taken over one period of the reference signal.
11. A PLL according to claim 9, A PLL in which the first control signal indicates whether the reference signal frequency is greater than or less than the feedback signal frequency.
12. A PLL according to claim 11, The second control signal has a first value, A PLL, wherein the first control circuit is further operable to increase the first value in response to the first control signal indicating that the reference signal frequency is greater than the feedback signal frequency, and to decrease the first value in response to the first control signal indicating that the reference signal frequency is less than the feedback signal frequency.
13. The PLL according to claim 12, The first value is the current value, The modulation circuit is further operable to modulate the second control signal to provide the modulated control signal, and to sum the second control signal with the modulated signal, in a PLL.
14. The PLL according to claim 12, The modulation circuit, The second control signal is copied to form the first copied signal. The second control signal is copied and scaled to form a second copied signal. To provide the modulated signal, the second copied signal is applied to a digital-to-analog converter (DAC). The modulated signal is added to the first copied signal in order to form the modulated second control signal. A PLL that is further operable to provide the modulated second control signal.
15. A PLL according to claim 14, The DAC includes a resistor ladder having multiple taps, wherein the selected tap of the resistor ladder determines the value of the modulated signal, and the PLL.
16. It is a method, Receiving a reference signal having a reference signal frequency, wherein the reference signal is extracted from an input signal; The aforementioned reference signal frequency is compared with the frequency of the feedback signal, To provide a first control signal having a value based on the results of the comparison, To provide a second control signal having a value proportional to the reference signal frequency based on the first control signal, Modulating the second control signal based on a modulated signal in order to form a modulated control signal, wherein the modulated signal is based on the input signal and the first control signal, To provide a signal having a frequency proportional to the modulated control signal, Methods that include...
17. The method according to claim 16, A method for modulating the second control signal, comprising modulating the second control signal by equal amounts in the positive and negative directions within one period of the reference signal.
18. The method according to claim 16, A method for modulating the second control signal, which includes modulating the second control signal by adding the second control signal to the modulated signal in order to form the modulated control signal.
19. The method according to claim 18, A method for providing a digital code to a digital-to-analog converter (DAC) in order to provide the modulated signal, further comprising providing a digital code such that the digital code changes within one period of the reference signal to change the modulated control signal in the positive and negative directions during the period of the reference signal.
20. The method according to claim 16, A method further comprising providing the feedback signal based on the signal having a frequency proportional to the modulated control signal.