Display substrate and display device

Abstract

A display substrate and a display device, in which a display region has a bottom edge extending along a horizontal direction and a left edge extending along a vertical direction, the display region includes a left display region and a right display region, the left display region includes a first edge display region and a first intermediate display region extending along the left edge, the horizontal direction intersects with the vertical direction, a frame region surrounds at least a portion of the display region, a first power supply voltage lead provides a first power supply voltage and is located in the frame region, the first power supply voltage lead includes a bottom lead extending along a portion of the bottom edge corresponding to the first edge display region and does not extend along a portion of the bottom edge corresponding to the first intermediate display region, the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, the edge voltage line is directly connected to the bottom lead to provide the first power supply voltage to sub-pixels located in the first edge display region, and the intermediate voltage line is separated from the bottom lead.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202210898307.2 filed on July 28, 2022, and all the content disclosed in the above Chinese patent application is incorporated herein by reference as part of this application.

[0002] At least one embodiment of the present disclosure relates to a display substrate and a display device.

Background Art

[0003] Compared with conventional liquid crystal displays (LCDs), organic light-emitting diode (OLED) display products have the advantages of self-emission, wide color gamut, high contrast, light weight and thinness, and thus are widely applied in fields such as mobile phones and tablet computers.

[0004] Generally, it is necessary to draw out multiple types of signal lines in the display area, such as data lines, to the fanout region, and then connect them to an integrated circuit (IC) through the fanout region. The fanout region is located in a frame region that does not execute the display function. As people continuously pursue the visual effect of display products, narrow borders and full-screen displays are gradually becoming the development trend of current OLED display products.

Summary of the Invention

Means for Solving the Problems

[0005] At least one embodiment of the present disclosure provides a display board comprising a display area, a non-display area, a first power supply voltage lead, and a first power supply voltage line. The display area has subpixels and has a lower edge extending along the transverse direction and a left edge extending along the vertical direction, wherein the transverse direction intersects the vertical direction, and the boundary line extending along the vertical direction divides the display area into a left display area and a right display area, the left display area comprising a first edge display area extending along the left edge and a first intermediate display area adjacent to the right display area located in the first edge display area, the non-display area comprising a frame area surrounding at least a portion of the display area, and the first power supply voltage lead is configured to provide a first power supply voltage. The first power supply voltage lead is located in the frame region and includes a lower lead that extends along the portion of the lower edge corresponding to the first edge display region, but does not extend along the portion of the lower edge corresponding to the first intermediate display region, and the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, wherein the edge voltage line is directly connected to the lower lead to provide the first power supply voltage to the subpixel located in the first edge display region, and the intermediate voltage line is separated from the lower lead.

[0006] For example, in a display board according to at least one embodiment of the present disclosure, the first power supply voltage line includes a vertical voltage line extending along the vertical direction and a horizontal voltage line extending along the horizontal direction, wherein the vertical voltage line is located on a different layer from the horizontal voltage line, the vertical voltage line includes an edge vertical voltage line located in the first edge display area, the horizontal voltage line includes an edge horizontal voltage line located in the first edge display area and intersecting the edge vertical voltage line, the edge vertical voltage line and the edge horizontal voltage line constitute the edge voltage line, the first power supply voltage lead further includes a left lead extending along the left edge of the display area, the edge vertical voltage line is directly connected to the lower lead, and the edge horizontal voltage line is directly connected to the left lead.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the subpixel includes a drive transistor, a light-emitting device, and a data transistor, the drive transistor is configured to control the magnitude of the drive current flowing through the light-emitting device, the light-emitting device is configured to receive the drive current and to emit light when driven by the drive current, the data transistor is configured to write a data signal to the gate of the drive transistor in response to a first control signal, the data line is configured to transmit the data signal to the subpixel, the display area includes a lower display area and an upper display area, the lower display area is close to the lower edge, the upper display area is located vertically away from the lower edge of the lower display area, the lower display area includes a first area and a second area, the first area is horizontally The display area includes a first sub-region approaching the left edge in the direction and a second sub-region moving away from the left edge, and the data lines passing through the first and second sub-regions include a first connecting line extending vertically within the first sub-region and a second connecting line extending horizontally within the second sub-region, the first connecting line being installed on the same layer as the vertical voltage lines and the second connecting line being installed on the same layer as the horizontal voltage lines, the first and second connecting lines of the same data line being electrically connected by a first connecting hole, the first sub-region being located in the first intermediate display area, at least a portion of the second sub-region being located in the intermediate display area, the first sub-region having a left endpoint that is closest to the left edge of the display area in the horizontal direction, and a straight line extending vertically and passing through the left endpoint being the boundary line between the first edge display area and the first intermediate display area.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the boundary line passes through the second region and approaches the left edge of the display region. 3 A sub-region and a third distance away from the left edge of the display region. 4The lower display area is divided into sub-regions, the first sub-region being located in the first edge display region, the second sub-region being located in the first intermediate display region, the lower display region further including a third region, the third region being located in the first edge display region and laterally on the side of the second region away from the first region, the edge lateral voltage line includes a lower edge lateral voltage line located in the third region, the edge vertical voltage line passes through the third region and intersects the lower edge lateral voltage line at a first intersection, the left end of the lower edge lateral voltage line is electrically connected to the left lead, the right end of the lower edge lateral voltage line opposite its left end and the second connecting line in the second region are cut by the first fracture surface, and the edge The voltage lines include a plurality of vertical edge voltage lines and a plurality of horizontal edge voltage lines, the plurality of vertical edge voltage lines and the plurality of horizontal edge voltage lines intertwining with each other to form a grid, the grid including a plurality of first intersections, and at each position of some of the plurality of first intersections, one vertical edge voltage line is electrically connected to one lower horizontal edge voltage line via a first via.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of edge vertical voltage lines are electrically connected to the plurality of edge horizontal voltage lines via a plurality of first vias, the planar pattern consisting of the positions of the plurality of first vias is a connecting line segment located in the third region, and the extension direction of the connecting line segment is the Lateral direction and the above Vertical They both intersect.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the third region is the second region approaching the left edge in the lateral direction of the second region. 1 This is a corner region defined by the edge, the left edge, and the lower edge.

[0011] For example, in a display board according to at least one embodiment of the present disclosure, the frame region includes a frame corner region surrounding the corner region, and a grid-like auxiliary first power supply voltage line is installed in the frame corner region, and the grid-like auxiliary first power supply voltage line includes a plurality of vertical auxiliary voltage lines and a plurality of horizontal auxiliary voltage lines. Multiple vertical auxiliary voltage lines extend along the vertical direction and are installed on the same layer as the vertical voltage lines, with the first end of each of the multiple vertical auxiliary voltage lines in the vertical direction directly connected to the first power supply voltage lead, and the second end of each of the multiple vertical auxiliary voltage lines opposite to its first end in the vertical direction electrically connected to one of the edge vertical voltage lines passing through the corner region; Multiple horizontal auxiliary voltage lines extend along the horizontal direction and are installed on the same layer as the multiple vertical auxiliary voltage lines, with one end of each of the multiple horizontal auxiliary voltage lines in the horizontal direction directly connected to the first power supply voltage lead, and the second end of each of the multiple horizontal auxiliary voltage lines opposite to its first end in the horizontal direction electrically connected to one of the edge vertical voltage lines.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the lateral direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel rows include a plurality of edge pixel rows approaching the lower edge, the plurality of lateral auxiliary voltage lines correspond one-to-one with the plurality of edge pixel rows, each of the plurality of edge pixel rows includes an edge subpixel closest to the left edge, the plurality of edge vertical voltage lines include an outermost edge vertical voltage line of an edge subpixel passing through each of the edge pixel rows, the second end of each of the plurality of lateral auxiliary voltage lines is electrically connected to an outermost edge vertical voltage line passing through the corresponding edge pixel row and is electrically connected via a first edge via to an edge lateral voltage line passing through the corresponding edge pixel row.

[0013] For example, in a display board according to at least one embodiment of the present disclosure, the lateral voltage lines further include a plurality of first lateral voltage lines, the plurality of first lateral voltage lines are arranged in the vertical direction and located in the upper display area, the left end of the first lateral voltage lines is electrically connected to the left lead, the edge lateral voltage lines further include an upper edge lateral voltage line located in the upper display area, the upper edge lateral voltage line is part of one of the first lateral voltage lines, the vertical voltage lines further include a plurality of intermediate vertical voltage lines, which are arranged in the horizontal direction and pass through a portion of the first intermediate display area and through the upper display area along the vertical direction, Multiple intermediate vertical voltage lines, multiple edge vertical voltage lines, and multiple first horizontal voltage lines are intertwined to form a grid, the multiple edge vertical voltage lines and the multiple first horizontal voltage lines intersect at multiple auxiliary intersections within the first edge display area, one edge vertical voltage line is electrically connected to one first horizontal voltage line via an auxiliary via at each position of some of the auxiliary intersections, and the multiple edge vertical voltage lines are electrically connected to the multiple first horizontal voltage lines via multiple auxiliary vias, and the planar pattern consisting of the positions of the multiple auxiliary vias is an auxiliary line segment located in the first edge display area.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the extension direction of the auxiliary line segment is the same as the extension direction of the connecting line segment, the display substrate includes a plurality of the auxiliary line segments, and the connecting line segment and the plurality of auxiliary line segments are arranged at intervals from each other along the longitudinal direction.

[0015] For example, in a display board according to at least one embodiment of the present disclosure, the display area further includes an upper edge opposite to the lower edge, the first power supply voltage lead further includes an upper lead extending along the upper edge, the upper lead being electrically connected to the left lead, the upper end of the edge vertical voltage line being connected to the upper lead, the lower end opposite to the upper end of the edge vertical voltage line being directly connected to the lower lead, the vertical voltage line includes an intermediate vertical voltage line located in the first intermediate display area, and the intermediate vertical voltage line includes a first vertical voltage line and a second vertical voltage line. The first longitudinal voltage line passes sequentially along the longitudinal direction through the upper display area and at least a portion of the second area, the upper end of the first longitudinal voltage line is electrically connected to the upper lead, the lower end of the first longitudinal voltage line opposite its upper end and the first connecting line in the first sub-area are cut by the second fracture surface, the second longitudinal voltage line passes sequentially along the longitudinal direction through the upper display area and the first area, the transverse voltage line includes an intermediate transverse voltage line located in the first area, the intermediate transverse voltage line and the second connecting line in the second area are cut by the third fracture surface, the second longitudinal voltage line and the intermediate transverse voltage line intersect at a second intersection, and the second longitudinal voltage line is electrically connected to the intermediate transverse voltage line via a second via at the second intersection.

[0016] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of first lateral voltage lines and the plurality of second vertical voltage lines intersect at a plurality of third intersections, and at each of at least some of the plurality of third intersections, one of the first lateral voltage lines is electrically connected to one of the second vertical voltage lines via a third via.

[0017] For example, in a display board according to at least one embodiment of the present disclosure, the display area further includes a right edge opposite to the left edge, the first power lead further includes a right lead extending along the right edge, the right lead is electrically connected to the upper lead, each of the plurality of first lateral voltage lines penetrates the upper display area along the lateral direction, and the right end of each of the plurality of first lateral voltage lines opposite its left end is electrically connected to the right lead.

[0018] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of intermediate vertical voltage lines and the plurality of first horizontal voltage lines intersect each other at a plurality of fourth intersections within the upper display area, and at each of some of the fourth intersections, one of the intermediate vertical voltage lines is electrically connected to one of the first horizontal voltage lines via a fourth via, and the planar pattern consisting of the positions of the plurality of fourth vias is a polyline.

[0019] For example, in a display board according to at least one embodiment of the present disclosure, the polyline includes a plurality of sub-polylines extending from the left edge to the right edge, each of the plurality of sub-polylines includes a plurality of polyline portions whose ends are connected to the ends, the plurality of polyline portions includes a first line segment extending along a first direction and a second line segment extending along a second direction, the first direction intersects with the second direction, and both the first and second directions intersect with the horizontal and vertical directions, the first end of the first line segment and the first end of the second line segment intersect at the upper vertex, the plurality of vertices of the plurality of sub-polylines are located on the second vertical voltage line, and the fourth via at the vertex position is all the second via.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, each of the plurality of sub-lines exhibits a W-shape.

[0021] For example, in a display board according to at least one embodiment of the present disclosure, the W-shaped sub-bend includes a first line segment, a second line segment, a third line segment, and a fourth line segment, wherein the first and second line segments are located between the third and fourth line segments, the third line segment is connected to the first line segment, the fourth line segment is connected to the second line segment, the first line segment is substantially parallel to the fourth line segment, and the second line segment is substantially parallel to the third line segment.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the vertical direction is perpendicular to the horizontal direction, the included angle formed by the first line segment and the horizontal direction is 45°, and the included angle formed by the second line segment and the horizontal direction is 45°.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, in the vertical direction, the auxiliary line segment is located between the third line segments of two adjacent sub-fold lines.

[0024] For example, in a display substrate according to at least one embodiment of the present disclosure, the connection line segment, the auxiliary line segment, and the third line segment are substantially parallel to each other.

[0025] For example, in a display substrate according to at least one embodiment of the present disclosure, the second vertical voltage line divides the first region into the first sub-region and the second sub-region, and the structure of the first sub-region and the structure of the second sub-region are substantially axisymmetric with respect to the second vertical voltage line. The lower display region includes a fourth region, and the structure of the fourth region and the structure of the second region are substantially axisymmetric with respect to the second vertical voltage line. The data line passing through the first region and the fourth region includes a third connection line extending along the vertical direction in the second sub-region and a fourth connection line extending along the horizontal direction in the fourth region. The third connection line is installed in the same layer as the vertical voltage line, the fourth connection line is installed in the same layer as the horizontal voltage line, the third connection line and the fourth connection line of the same data line are electrically connected by a second connection hole, and the right end of the intermediate horizontal voltage line located in the first region facing the left end thereof and the fourth connection line in the fourth region are cut by a fourth broken surface.

[0026] For example, in the display substrate according to at least one embodiment of the present disclosure, the display substrate includes a plurality of the first connection lines, a plurality of the second connection lines, a plurality of the third connection lines, and a plurality of the fourth connection lines. The plurality of the first connection lines and the plurality of the second connection lines are electrically connected by a plurality of the first connection holes respectively. The plurality of the third connection lines and the plurality of the fourth connection lines are electrically connected by a plurality of the second connection holes respectively. The planar pattern formed by the plurality of the first connection holes is a fifth line segment, and the fifth line segment is the boundary between the first region and the second region. The planar pattern formed by the plurality of the second connection holes is a sixth line segment, and the sixth line segment is the boundary between the first region and the fourth region. The lower display region further includes a fifth region, and the structure of the fifth region and the structure of the third region are substantially axisymmetric with respect to the second longitudinal voltage line. The planar pattern of a plurality of fifth vias symmetric to the plurality of the first vias in the fifth region is a seventh line segment. The planar pattern formed by connecting the connection line segment, the fifth line segment, the sixth line segment, and the seventh line segment in sequence is the same as the planar pattern of each sub-folded line among the plurality of sub-folded lines.

[0027] For example, in the display substrate according to at least one embodiment of the present disclosure, the planar shape of the first region is a first triangle, the planar shape of the second region is a second triangle. The first side of the first triangle approaching the left edge in the horizontal direction is at least partially overlapped with the first side of the second triangle departing from the left edge of the display region in the horizontal direction. Two lower vertices of the first triangle are located at the lower edge of the display region. The left vertex of the two lower vertices of the first triangle approaching the left edge is the left end point of the first sub-region. The first triangle is an isosceles triangle, and the second longitudinal voltage line is substantially the perpendicular bisector of the base of the isosceles triangle.

[0028] For example, in a display substrate according to at least one embodiment of the present disclosure, the frame region includes a left frame region extending along the left edge, a plurality of auxiliary connection lines extending in the lateral direction are provided in the left frame region, the plurality of auxiliary connection lines are provided on the same layer as the edge vertical voltage lines, the display region includes a pixel array, the pixel array includes a plurality of pixel rows extending in the lateral direction and a plurality of pixel columns extending in the vertical direction, the plurality of pixel columns include an edge pixel column closest to the left edge, the plurality of edge vertical voltage lines include an outer edge vertical voltage line passing through the edge pixel column, the left end of each of the plurality of auxiliary connection lines in the lateral direction is electrically connected to the left lead, the right end of each of the plurality of auxiliary connection lines opposite to its left end in the lateral direction is electrically connected to the outer edge vertical voltage line and is electrically connected via a second edge via to the left end of a corresponding first lateral voltage line.

[0029] For example, in a display substrate according to at least one embodiment of the present disclosure, the right display region includes a second edge display region extending along the right edge and a second intermediate display region located on the side of the second edge display region approaching the left display region, wherein the second edge display region and the first edge display region are symmetric with respect to an axis of symmetry extending along the vertical direction, and the second intermediate display region and the first intermediate display region are axially symmetric with respect to a second vertical voltage line.

[0030] For example, in a display board according to at least one embodiment of the present disclosure, the display board further includes a second power supply voltage line configured to provide the subpixels with a second power supply voltage different from the first power supply voltage, wherein the vertical voltage line is located on the same layer as the data lines in the upper display area, and the horizontal voltage line is located on the same layer as the second power supply voltage line.

[0031] At least one embodiment of the present disclosure further provides a display device including any one type of display substrate according to the embodiments of the present disclosure. [Brief explanation of the drawing]

[0032] To more clearly explain the technical concepts of the embodiments of the present invention, the drawings of the embodiments are briefly described below. However, it is clear that the drawings described below only relate to a part of the embodiments of the present invention and do not limit the present invention.

[0033] [Figure 1] This is a schematic overall plan view of a display substrate according to an embodiment of the present disclosure. [Figure 2] This is a partially enlarged schematic diagram of Figure 1, including the lower display area and a portion of the upper display area. [Figure 3A] This is a partially enlarged schematic diagram of region R1 in Figure 2. [Figure 3B] This is a schematic diagram of the partial film layer in region R1 in Figure 2. [Figure 3C] This is a schematic diagram of the partial film layer in region R1 in Figure 2. [Figure 3D] This is a schematic diagram of the partial film layer in region R1 in Figure 2. [Figure 4] This is a partially enlarged schematic diagram including regions R2 and R3 in Figure 1. [Figure 5A] This is a partially enlarged schematic diagram of region R2 in Figure 4. [Figure 5B] Figure 4 is a schematic diagram of the partial film layer in region R2. [Figure 5C] Figure 4 is a schematic diagram of the partial film layer in region R2. [Figure 5D] Figure 4 is a schematic diagram of the partial film layer in region R2. [Figure 6A] This is a partially enlarged schematic diagram of region R3 in Figure 1. [Figure 6B] Figure 1 is a schematic diagram of the partial film layer in region R3. [Figure 6C] Figure 1 is a schematic diagram of the partial film layer in region R3. [Figure 6D] Figure 1 is a schematic diagram of the partial film layer in region R3. [Figure 7A] This is a partially enlarged schematic diagram of region R4 in Figure 1. [Figure 7B] Figure 1 is a schematic diagram of the partial film layer in region R4. [Figure 7C]Figure 1 is a schematic diagram of the partial film layer in region R4. [Figure 7D] Figure 1 is a schematic diagram of the partial film layer in region R4. [Figure 8A] This is a partially enlarged schematic diagram of region R5 in Figure 1. [Figure 8B] Figure 1 is a schematic diagram of the partial film layer in region R5. [Figure 8C] Figure 1 is a schematic diagram of the partial film layer in region R5. [Figure 9] This is a partially enlarged schematic diagram of region R6 in Figure 1. [Figure 10] This is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure. [Figure 11A] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11B] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11C] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11D] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11E] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11F] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11G] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11H] This is a schematic diagram showing different film layers in a pixel circuit. [Figure 11I] Figures 11A to 11F are schematic diagrams of the layered structure of the film layers shown. [Figure 12] This is a schematic diagram of a display board according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0034] To clarify the purpose, technical proposal, and advantages of the embodiments of the present invention, the technical proposal of the embodiments of the present invention will be described clearly and completely below with reference to the drawings of the embodiments. Clearly, the embodiments described are a part of the embodiments of the present invention, not all of them. Any other embodiments that a person skilled in the art can obtain without inventive work based on the embodiments of the present invention described are all within the scope of the protection of the present invention.

[0035] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art within the field to which this invention pertains. The terms “first,” “second,” and similar terms used in the patent application and claims of this invention do not indicate any order, number, or importance, but merely distinguish different components. Similar terms such as “equipment” or “includes” indicate that the element or component described before the term covers the elements or components and equivalents listed after the term, but do not exclude other elements or components. Terms such as “inside,” “outside,” “above,” and “below” refer only to relative positions, and if the absolute position of the described object changes, the relative position may change accordingly.

[0036] The drawings in this disclosure are not strictly drawn to actual proportions, and the number of lateral voltage lines, vertical voltage lines, and vias on the display board are not limited to those shown in the drawings. The specific dimensions and number of each structure may be determined as needed. The drawings described in this disclosure are merely schematic diagrams of the structure.

[0037] The terms “parallel,” “perpendicular,” and “same” used in this disclosure all include both strictly “parallel,” “perpendicular,” and “same,” as well as terms with a certain degree of error, such as “approximately parallel,” “approximately perpendicular,” and “approximately same,” indicating that the values ​​are within an acceptable range of deviation for a given value as determined by a person skilled in the art, taking into account errors related to measurement and the measurement of a particular quantity (e.g., limitations of the measurement system). For example, “approximately” may indicate that the values ​​are within one or more standard deviations, or within 10% or 5% of the given value.

[0038] Unless otherwise specified in the following description of the embodiments of this disclosure, the component may be one, more than one, or may be understood to be at least one. "At least one" means one or more, and "more than one" means at least two.

[0039] In the embodiments of this disclosure, "identical layer" refers to the relationship between multiple film layers formed from the same material through the same step (e.g., a one-step patterning process). Here, "identical layer" does not necessarily mean that the multiple film layers have the same thickness or the same height in the cross-sectional view of the multiple film layers.

[0040] The terms used in this disclosure to indicate direction, such as "vertical," "horizontal," "up," "down," "left," and "right," are merely for indicating relative positional relationships. If the absolute position of the described object changes, the relative positional relationships may also change accordingly, and are not limited to the directions shown in the drawings of the specification. For example, "upper edge," "lower edge," "left edge," and "right edge" are not limited to the top, bottom, left, and right shown in the drawings, but only need to satisfy their limited relative positional relationships. Similarly, "left display area" and "right display area" are not limited to the left and right in the drawings of this specification, but only need to satisfy their limited relative positional relationships. above and under It's not limited to that; it's sufficient to satisfy that limited relative positional relationship.

[0041] At least one embodiment of the present disclosure provides a display board comprising a display area, a non-display area, a first power supply voltage lead, and a first power supply voltage line. The display area has a lower edge extending laterally and a left edge extending vertically, wherein the laterally intersects the vertically, and the boundary line extending vertically divides the display area into a left display area and a right display area, the left display area comprising a first edge display area extending along the left edge and a first intermediate display area adjacent to the right display area located in the first edge display area, the non-display area comprising a frame area surrounding at least a portion of the display area, and the first power supply voltage lead is configured to provide a first power supply voltage. The first power supply voltage lead is configured and located in the frame region, and the first power supply voltage lead includes a lower lead that extends along the portion of the lower edge corresponding to the first edge display region, but does not extend along the portion of the lower edge corresponding to the first intermediate display region, and the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, wherein the edge voltage line is directly connected to the lower lead to provide the first power supply voltage to the subpixel located in the first edge display region, and the intermediate voltage line is separated from the lower lead.

[0042] At least one embodiment of the present disclosure further provides a display device including any one type of display substrate according to the embodiments of the present disclosure.

[0043] Exemplary, Figure 1 is a schematic overall plan view of a display board according to an embodiment of the present disclosure, and Figure 2 is a partially enlarged schematic view of Figure 1 including the lower display area and the partially upper display area. For example, as shown in Figure 1, a display board 10 according to at least one embodiment of the present disclosure includes a display area 1, a frame area 2, a first power supply voltage lead 4 and a first power supply voltage line vss. The display area 1 has subpixels installed and has a lower edge 1a extending along the horizontal direction X and a left edge 1b extending along the vertical direction Y, with the horizontal direction intersecting the vertical direction, for example, the horizontal direction being perpendicular to the vertical direction, and of course, in another embodiment the horizontal direction may not be perpendicular to the vertical direction. The display area 1 includes a left display area 11 and a right display area 12 arranged in the horizontal direction X. For example, a dividing line ML extending along the vertical direction Y divides the display area 1 into a left display area 11 and a right display area 12. For example, if the dividing line ML is the vertical bisector of the lower edge 1a, the left display area 11 and the right display area 12 are made symmetrical, and the display effect of the entire display board 10 is uniform, but this is not limited to the case where the dividing line ML is the vertical bisector of the lower edge 1a. The left display area 11 includes a first edge display area 11P extending along the left edge 1b and a first intermediate display area 11M approaching the right display area 12 located at the first edge display area 11P, and the frame area 2 is a non-display area that surrounds at least a part of the display area 1. For example, the display board 10 may further include a pad 3 located on the side of the lower edge 1a away from the display area 1, and a first power supply voltage lead 4 is configured to provide a first power supply voltage VSS by being connected to the pad 3, and is located within the frame area 2, and the first power supply voltage lead 4 includes a lower lead 41 that extends along the portion of the lower edge 1a corresponding to the first edge display area 11P, but does not extend along the portion of the lower edge 1a corresponding to the first intermediate display area 11M, and the first power supply voltage line vss includes an edge voltage line LP located in the first edge display area 11P and an intermediate voltage line LM located in the first intermediate display area 11M, wherein the edge voltage line LP contacts and is electrically connected to the lower lead 41 to provide the first power supply voltage VSS to the subpixel located in the first edge display area 11P, and the intermediate voltage line LM is separated from the lower lead 41, i.e., the intermediate voltage line LM is not directly connected to the lower lead 4 from the pad 3.Thus, in the display board 10 according to the embodiment of this disclosure, the edge voltage line provides a VSS signal to the subpixels of the first edge display area 11P by contacting and electrically connecting with the lower lead 41, and the intermediate voltage line LM is separated from the lower lead 41, i.e., does not make contact, but provides a VSS signal to the first intermediate display area 11M by connecting with the left lead 42 or the upper lead 43 or another first power supply voltage line vss. In other words, the first power supply voltage lead 4 drawn from the pad 3 located on the side away from the display area of ​​the lower edge 1a is not directly connected to the first intermediate display area 11M, i.e., the intermediate voltage line LM is not connected to the pad 3 by the frame area 2 and is not directly connected to the first power supply voltage line vss, and the first power supply voltage VSS is obtained via the edge voltage line without obtaining the first power supply voltage VSS by the pad 3. This reduces the wiring installed in the fanout area and further reduces the fanout area, thereby reducing the width of the lower frame and realizing an even narrower frame.

[0044] For example, the edge voltage line LP is directly connected to the lower lead 41, that is, the edge voltage line LP and the lower lead 41 are in contact with each other, and there is no other structure between the edge voltage line LP and the lower lead 41 that acts as a medium connecting them. For example, the edge voltage line LP is installed in the same layer as the lower lead 41 and forms a continuous, integrally molded structure. In such a case, the material of the edge voltage line LP and the lower lead 41 may be the same and may be formed by the same patterning process. In this way, the structure and manufacturing process of the display substrate can be simplified.

[0045] Naturally, in other embodiments, the edge voltage line LP and the lower lead 41 may be located on different layers, and they may be in contact with each other by vias. It should be explained that in this disclosure, the term “direct connection” means that two structures that are connected to each other (e.g., the edge voltage line LP and the lower lead 41 are directly connected) are in contact with each other, and there is no other structure between the two connected structures acting as a medium connecting them. For example, the two directly connected structures may be a continuous, integrally molded structure, in which case the material of the two directly connected structures is the same, and the manufacturing process of the display substrate can be simplified by forming the two structures using the same patterning process, or the material of the two directly connected structures may be different, for example, the two directly connected structures may both be conductive signal lines, and they may each use materials suited to their respective functions to meet the demands for different performance, such as different conductivity.

[0046] For example, as shown in Figure 1, the first power supply voltage line vss includes a vertical voltage line YL extending along the vertical direction Y and a horizontal voltage line XL extending along the horizontal direction X, wherein the vertical voltage line YL is located on a different layer from the horizontal voltage line XL, the vertical voltage line YL includes an edge vertical voltage line YLP located in the first edge display area 11P, and the horizontal voltage line XL includes an edge horizontal voltage line XLP located in the first edge display area 11P and intersecting the edge vertical voltage line YLP, the edge vertical voltage line YLP and the edge horizontal voltage line XLP constitute the edge voltage line LP, and the first power supply voltage lead 4 further includes a left lead 42 extending along the left edge 1b of the display area 1, the edge vertical voltage line YLP is directly connected to the lower lead 41 and the edge horizontal voltage line XLP is directly connected to the left lead 42. For example, the edge vertical voltage line YLP penetrates the entire display area vertically through the first edge display area 11P, thereby providing the first power supply voltage VSS to the subpixels of the entire first edge display area 11P. In this way, the edge vertical voltage line YLP is directly connected to the lower lead 41 that is close to it, which allows for space saving and contributes to reducing the outer frame area of ​​the lower edge 1a.

[0047] For example, if the first power supply voltage pin 4a is installed on pad 3, the lower lead 41 is electrically connected to the first power supply voltage pin 4a, and the first power supply voltage pin 4a is located at the first end of pad 3 approaching the first edge display area 11P in the lateral direction X, then by sequentially and directly connecting the first power supply voltage pin 4a, the lower lead 41, and the edge vertical voltage line YLP of the first edge display area 11P in close proximity, the wiring of the lower frame can be effectively reduced, and the frame area outside the lower edge 1a can be made smaller.

[0048] For example, as shown in Figure 1, in some embodiments, a second first power supply voltage pin 4b may be further installed on pad 3, the second first power supply voltage pin 4b being located at the second end approaching the right edge 1d, i.e., approaching the second edge display area 12P in the lateral direction X of pad 3, the structure relating to the first power supply voltage line vss of the second edge display area 12P and the first edge display area 11P is axially symmetric with respect to an axis of symmetry extending along the vertical direction Y, and the second first power supply voltage pin 4b is directly connected to the edge vertical voltage line in the second edge display area 12P, similar to the first first power supply voltage pin 4a and the first power supply voltage line vss in the first edge display area 11P, thereby providing the first power supply voltage VSS to the subpixels of the second edge display area 12P.

[0049] Figure 6A is a figure 1 Figures 6B to 6D are schematic diagrams of a partial enlargement of region R3 in Figure 3. For example, as shown in Figures 1 and 6A, the lower end approaching the lower lead 41 of the edge longitudinal voltage line YLP is directly connected to the lower lead 41. For example, the upper end of the edge longitudinal voltage line YLP opposite its lower end is directly connected to the upper lead 43, thereby more reliably providing the first power supply voltage VSS via the edge longitudinal voltage line YLP.

[0050] For example, as shown in Figure 1, referring to the equivalent circuit diagram of the pixel circuit shown in Figure 8, the display board 10 further includes a data line data, and the sub-pixel includes a drive transistor T3, a light-emitting element and a data transistor T4, the drive transistor T3 is configured to control the magnitude of the drive current flowing through the light-emitting element, the light-emitting element is configured to receive the drive current and to emit light when driven by the drive current, the data transistor T4 is configured to write a data signal DATA to the gate of the drive transistor T3 in response to a first control signal, the data line data is configured to transmit the data signal DATA to the sub-pixel, the display area 1 includes a lower display area 14 and an upper display area 13, the lower display area 14 is close to the lower edge 1a and the upper display area 13 is located on the side away from the lower edge 1a of the lower display area 14 in the vertical direction, and the lower display area 14 is the first area The region includes a region (1) and a second region (2), the first region (1) includes a first sub-region A that approaches the left edge 1b in the lateral direction X and a second sub-region B that moves away from the left edge 1b, the data line data passing through the first sub-region A and the second region (2) includes a first connection line DL1 extending along the vertical direction Y within the first sub-region A, a second connection line DL2 extending along the lateral direction X within the second region (2), and a fifth connection line DL5 located within the upper display region 13 and extending along the vertical direction Y, the fifth connection line DL5 being installed on the same layer as the first connection line DL1, the first connection line DL1 being installed on the same layer as the vertical voltage line YL, the second connection line DL2 being installed on the same layer as the lateral voltage line XL, the first connection line DL1 and the second connection line DL2 of the same data line data being electrically connected by a first connection hole VC1, and the fifth connection line DL5 and the second connection line DL2 of the same data line data being connected by a third connection hole VC3 by They are electrically connected. This forms a single transmission channel for each data line, such as the data signal DATA shown by the three arrows in Figure 1. For example, multiple data lines are each connected to pad 3 by multiple data signal leads CL, which are electrically connected to an integrated circuit IC on pad 3, thereby providing the data signal DATA to the data line.

[0051] For example, the first sub-region A is located in the first intermediate display region 11M, and at least a portion of the second region (2) is located in the first intermediate display region 11M. The first sub-region A has a left endpoint PO that is closest to the left edge 1b of the display region 1 in the horizontal direction X, and a straight line extending along the vertical direction Y and passing through the left endpoint PO is the boundary line IL between the first edge display region 11P and the first intermediate display region 11M. That is, the region between this straight line and the left edge 1b is the first edge display region 11P. The first sub-region A is located in the first intermediate display region 11M.

[0052] For example, as shown in Figures 1-2, the boundary line IL passes through the second region (2) and approaches the left edge 1b of the display region 1. 3 Sub-region A and the part away from the left edge 1b of display region 1 4 The area is divided into sub-area A and sub-area B, with the first sub-area A located in the first edge display area 11P and the second sub-area B located in the first intermediate display area 11M.

[0053] Figure 3A is a partially enlarged schematic diagram of region R1 in Figure 2, and Figures 3B-3D show region R in Figure 2. 1 This is a schematic diagram of a partial film layer. Referring to Figures 1-2 and 3A-3D, or Figures 1 and 6A-6D, the lower display area 14 further includes a third area (3), the third area (3) is located in the first edge display area 11P and is located on the side of the second area (2) away from the first area (1) in the lateral direction X, the edge lateral voltage line XLP includes the lower edge lateral voltage line XLP1 located in the third area (3), the edge longitudinal voltage line YLP passes through the third area (3) and intersects with the lower edge lateral voltage line XLP1 at the first intersection P1, the left end of the lower edge lateral voltage line XLP1 is electrically connected to the left lead 42, and the right end of the lower edge lateral voltage line XLP1 opposite its left end and the second connecting line DL2 in the second area (2) are severed by the first fracture surface OP1. The first fracture surface OP1 may be shown in Figures 1-2, and Figures 3A-3B are partial schematics showing only a limited number of pixels, and therefore do not show the first fracture surface OP1. Edge voltage linesThe structure includes multiple vertical edge voltage lines YLP and multiple horizontal edge voltage lines XLP, which intertwine to form a grid. The grid includes multiple first intersections P1, and at some of the positions of the first intersections P1, one vertical edge voltage line YLP is electrically connected to one lower horizontal edge voltage line XLP1 via a first via V1, thereby resulting in multiple first vias V1 at multiple first intersections P1. In this way, multiple vertical edge voltage lines YLP and multiple lower horizontal edge voltage lines XLP1 are electrically connected in a grid-like structure in the third region (3), reducing the resistance to transmit the first power supply voltage VSS in the third region (3) of the first power supply voltage line vss, and resulting in a relatively low voltage drop on the grid-like first power supply voltage line vss composed of the vertical edge voltage lines YLP and lower horizontal edge voltage lines XLP1 in the third region (3).

[0054] For example, Figure 3 The film layer shown in B and the figure 3 A first insulating layer exists between the film layer shown in C, and a first via V1 penetrates the first insulating layer. The first connection structure C1 passing through the first via V1 electrically connects the vertical edge voltage line YLP and the horizontal lower edge voltage line XLP1.

[0055] For example, all first power supply voltage lines vss (vertical voltage lines YL) located in display area 1 and extending along the vertical Y direction are placed on the same layer as the data lines data in the upper display area 13, the horizontal voltage lines XL located in display area 1 are placed on the same layer as the second power supply voltage lines, and all first power supply voltage lines vss (horizontal voltage lines XL) extending along the X direction are located on the side of the vertical voltage lines YL that is closer to the base substrate. For example, the vertical voltage lines YL are located on the following sixth conductive layer 580, and the horizontal voltage lines XL are located on the following fifth conductive layer 570. Of course, in other embodiments, the voltage lines YL and horizontal voltage lines XL may be placed on different metal layers, and the first insulating layer may be placed between the two metal layers.

[0056] Figures 3A and 3B show three example first vias V1, but the number of first vias V1 is not limited.

[0057] For example, referring to Figures 1-2, multiple vertical edge voltage lines YLP are electrically connected to multiple horizontal edge voltage lines XLP via multiple first vias V1, and the planar pattern consisting of the positions of the multiple first vias V1 is a connecting line segment SC located in the third region (3) (the dotted line in the third region (3) in Figure 1 represents the connecting line segment SC), and the extension direction of the connecting line segment SC intersects both the horizontal X and vertical Y directions. Here, "planar pattern consisting of the positions of the multiple first vias V1" refers to the overall pattern formed by arranging the positions of the multiple first vias V1.

[0058] For example, in the embodiments shown in Figures 1 and 2, the connecting line segment SC is a straight line segment, thereby maintaining the shape of the following W-shaped polyline. Naturally, in other embodiments, the connecting line segment SC may be a curved line segment if necessary.

[0059] For example, as shown in Figure 1, the third region (3) is a corner region defined by the first side SL1 approaching the left edge 1b in the lateral direction X of the second region (2), the left edge 1b, and the bottom edge 1a. Third region (3) teeth, The corner area and In order to realize a design in which the data line data originally passes through the second region (2) and the first region (1) (Fanout in pixel, FIP technology), the first fracture surface OP1 is installed within the corner region, thereby floating the first power supply voltage signal. The wire By providing access, it is possible to prevent signal interference caused by floating wires, such as electrostatic interference due to the tendency of static electricity to accumulate on floating wires.

[0060] The planar pattern of the multiple third connection holes VC3 of the fifth connection line DL5 and the second connection line DL2, which connect multiple data lines data respectively, is a line segment, for example a straight line segment, and this line segment may be the first side SL1 of the second region (2) and the boundary line between the third region (3) and the second region (2).

[0061] For example, referring to Figures 1-2, the frame region 2 includes a frame corner region 20 surrounding the corner region (3), and auxiliary first power supply voltage lines vss exhibiting a grid pattern are installed in the frame corner region 20. In this way, the voltage drop of the first power supply voltage lines within the first edge display region 11P can be significantly reduced.

[0062] Figure 4 is a partially enlarged schematic diagram including regions R2 and R3 in Figure 1, where region R2 includes the frame corner region 20. Figure 5A is a partially enlarged schematic diagram of region R2 in Figure 4, and Figures 5B to 5D are schematic diagrams of the partial film layer of region R2 in Figure 4. Referring to Figures 4 and 5A to 5D, the grid-like auxiliary first power supply voltage lines vss include multiple vertical auxiliary voltage lines YAL and multiple horizontal auxiliary voltage lines XAL. Multiple vertical auxiliary voltage lines YAL extend along the vertical Y direction and are installed on the same layer as the vertical voltage line YL, with the first end of each of the multiple vertical auxiliary voltage lines YAL in the vertical Y direction directly connected to the first power supply voltage lead 4 (for example, the lower lead 41, or the corner lead connecting the lower lead 41 and the left lead 42), and the second end of each of the multiple vertical auxiliary voltage lines YAL opposite to its first end in the vertical Y direction electrically connected, for example, directly connected, to a single edge vertical voltage line YLP passing through the corner region (3). Multiple lateral auxiliary voltage lines XAL extend along the lateral direction X and are installed on the same layer as multiple vertical auxiliary voltage lines YAL. One end of each of the multiple lateral auxiliary voltage lines XAL in the lateral direction X is directly connected to the first power supply voltage lead 4 (for example, the left lead 42, or the corner lead connecting the lower lead 41 and the left lead 42), and the second end of each of the multiple lateral auxiliary voltage lines XAL opposite its first end in the lateral direction X is electrically connected to a single edge vertical voltage line YLP. As shown in Figure 5D, multiple vertical auxiliary voltage lines YAL are installed on the same layer as multiple lateral auxiliary voltage lines, for example, on the same layer as the vertical voltage line YL, and by simultaneously forming the vertical auxiliary voltage line YAL, lateral auxiliary voltage lines, and vertical voltage line YL using the same patterning process, the structure and manufacturing process of the display board can be simplified.

[0063] For example, referring to Figures 5A to 5D, the display area 1 includes a pixel array, the pixel array includes multiple pixel rows extending along the horizontal direction X and multiple pixel columns extending along the vertical direction Y, the multiple pixel rows include multiple edge pixel rows PXR approaching the lower edge 1a, multiple horizontal auxiliary voltage lines XAL correspond one-to-one with the multiple edge pixel rows PXR, each of the multiple edge pixel row PXR includes an edge sub-pixel P closest to the left edge 1b, multiple edge vertical voltage lines YLP include the outermost edge vertical voltage line YLP0 passing through each edge pixel row PXR of the edge sub-pixel P, and the second end of each of the multiple horizontal auxiliary voltage lines XAL is electrically connected to the outermost edge vertical voltage line YLP0 passing through the corresponding edge pixel row PXR, for example, directly connected, and the second end of each of the multiple horizontal auxiliary voltage lines XAL is electrically connected via a first edge via VP1 to an edge horizontal voltage line XLP passing through the corresponding edge pixel row PXR. As shown in Figure 5C, the second end of the lateral auxiliary voltage line XAL is electrically connected to the edge lateral voltage line XLP of the corresponding edge pixel row PXR by the first edge connection structure CP1 passing through the first insulating layer. Figures 5A to 5D show the connection relationship between one lateral auxiliary voltage line XAL and the corresponding edge pixel row PXR that is closest to the lower edge 1a. The connection status of the other edge pixel row PXRs is similar; however, in this embodiment, the length of the lateral auxiliary voltage line XAL corresponding to each edge pixel row PXR differs to accommodate the shape of the corner region. In other embodiments, if necessary, the length of the lateral auxiliary voltage line XAL of each edge pixel row PXR may be designed to accommodate the pixel arrangement of the display substrate.

[0064] For example, as shown in Figures 1 and 5A to 5B, the second power supply voltage lead 4b-1 is located in the lower frame region surrounding the lower edge 1a and is electrically connected to the second power supply voltage pin 4b. The second power supply voltage line passing through multiple pixel rows is electrically connected to the second power supply voltage lead 4b-1, thereby providing the second power supply voltage VDD to the pixels of the multiple pixel rows.

[0065] For example, as shown in Figure 1, the lateral voltage line XL further includes multiple first lateral voltage lines XLU, which are arranged in the vertical direction Y and located in the upper display area 13, with the left end of the first lateral voltage line XLU electrically connected to the left lead 42, and the edge lateral voltage line XLP further includes the upper edge lateral voltage line XLP2 located in the upper display area 13, with the upper edge lateral voltage line XLP2 being part of one first lateral voltage line XLU. The vertical voltage line YL further includes multiple intermediate vertical voltage lines YLM, and multiple Intermediate vertical voltage line YLM These are arranged in the horizontal direction X and pass through a part 11M of the first intermediate display area and the upper display area 13 along the vertical direction Y, and multiple intermediate vertical voltage lines YLM, multiple edge vertical voltage lines YLP, and multiple first horizontal voltage lines XLU intertwine to form a grid, thereby reducing the resistance of the first power supply voltage line vss and reducing the voltage drop on the first power supply voltage line vss.

[0066] Multiple edge vertical voltage lines YLP and multiple first horizontal voltage lines XLU intersect multiple auxiliary intersection points AP within the first edge display area 11P, and at each position of some of the auxiliary intersection points AP, one edge vertical voltage line YLP is electrically connected to one first horizontal voltage line XLU via auxiliary via AV within the first edge display area 11P, and multiple edge vertical voltage lines YLP are electrically connected to multiple first horizontal voltage lines XLU via multiple auxiliary via AV, and the planar pattern consisting of the positions of the multiple auxiliary via AV is an auxiliary line segment SA located in the first edge display area 11P, the end of the auxiliary line segment SA away from the left edge 1b is suspended, that is, via patterns without this are connected to the end of the auxiliary line segment SA away from the left edge 1b, and the auxiliary line segment SA is different from the third line segment S3 of the following W-shaped polyline. In this way, the resistance of the first power supply voltage line vss within the first edge display area 11P can be reduced more effectively, thereby reducing the voltage drop of the first power supply voltage line vss within the first edge display area 11P.

[0067] The structure in which one edge vertical voltage line YLP is electrically connected to one first horizontal voltage line XLU via auxiliary via AV within the first edge display area 11P at the position of auxiliary line segment SA is similar to the structure of area R1 shown in Figures 3A to 3D, and you may also refer to Figures 3A to 3D, but a detailed explanation is omitted here.

[0068] For example, referring to Figure 1, the extension direction of the auxiliary line segment SA is the same as the extension direction of the connecting line segment SC, and for example, the lengths of the auxiliary line segment SA and the connecting line segment SC are also the same, thereby maintaining uniformity in the arrangement of connection points connected via vias and preventing uneven defects from occurring on the display board. For example, the display board 10 includes a plurality of auxiliary line segments SA, and the connecting line segment SC and the plurality of auxiliary line segments SA are arranged at intervals from each other along the vertical direction Y.

[0069] For example, as shown in Figure 1, the display area 1 further includes an upper edge 1c opposite to the lower edge 1a, and the first power supply voltage lead 4 further includes an upper lead 43 extending along the upper edge 1c, the upper lead 43 being electrically connected to the left lead 42, the upper end of the edge vertical voltage line YLP being connected to the upper lead 43, and the lower end of the edge vertical voltage line YLP opposite its upper end being directly connected to the lower lead 41.

[0070] Figure 7A is a partially enlarged schematic diagram of region R4 in Figure 3, and Figures 7B-7D are schematic diagrams of partial film layers of region R4 in Figure 3. For example, as shown in Figure 1, the longitudinal voltage line YL includes an intermediate longitudinal voltage line YLM located in the first intermediate display region 11M, and the intermediate longitudinal voltage line YLM includes the first longitudinal voltage line YLM1 and the second longitudinal voltage line YML2. The first longitudinal voltage line YLM1 passes sequentially along the longitudinal direction Y through the upper display region 13 and at least a portion of the second region (2). Referring to Figures 1 and 7A-7D, the upper end of the first longitudinal voltage line YLM1 is electrically connected to the upper lead 43, and the lower end of the first longitudinal voltage line YLM1 opposite its upper end and the first connecting line DL1 in the first sub-region A are severed by the second fracture surface OP2, and Figures 7A and 7D partially show the two second fracture surfaces OP2 located in region (2). The second longitudinal voltage line YML2 passes sequentially along the longitudinal direction Y through the upper display area 13 and the first area (1), the transverse voltage line XL includes the intermediate transverse voltage line XLM located in the first area (1), the intermediate transverse voltage line XLM and the second connecting line DL2 in the second area (2) are cut by the third fracture surface OP3, and as shown in Figures 1-2, the right end of the intermediate transverse voltage line XLM located in the first area (1) opposite its left end and the fourth connecting line DL4 in the fourth area (4) are cut by the fourth fracture surface OP4. Thus, both ends of each of the multiple intermediate transverse voltage lines XLM in the transverse direction X are cut from the corresponding second connecting line D2 and the corresponding fourth connecting line DL4, respectively.

[0071] As shown in the figure, the second vertical voltage line YML2 and the intermediate horizontal voltage line XLM intersect at the second intersection P2, and the second vertical voltage line YML2 is electrically connected to the intermediate horizontal voltage line XLM at the second intersection P2 via the second via V2.

[0072] For example, the second vertical voltage line YML2 is electrically connected to multiple intermediate horizontal voltage lines XLM, each arranged vertically, via multiple second vias V2 arranged vertically in the Y direction. The portion shown in Figures 7A to 7D has three second vias V2, but this does not represent that a display board has only three second vias V2. For example, each of the multiple intermediate horizontal voltage lines XLM is connected to the second vertical voltage line YML2 via the second via V2, thereby transmitting the first power supply voltage VSS to each pixel in the first region (1). For example, as shown in Figure 7B, the second vertical voltage line YML2 and the intermediate horizontal voltage line XLM are connected by a second connection structure C2 passing through the second via V2.

[0073] For example, as shown in Figure 1, multiple first lateral voltage lines XLU and second vertical voltage lines YML2 located in the upper display area 13 intersect at multiple third intersections P3, and at least some of the positions of the multiple third intersections P3, one first lateral voltage line XLU is electrically connected to the second vertical voltage line YML2 via a third via V3. This electrically connects the intermediate lateral voltage line XLM and the second vertical voltage line YLM2 via the second via V2. The second vertical voltage line YLM2 is electrically connected to the first lateral voltage line XLU via the third via V3, which in turn electrically connects the first lateral voltage line XLU to the first power supply voltage lead 4 (left lead 42). As a result, the first lateral voltage line XLU provides the first power supply voltage VSS to the second vertical voltage line YML2, and the second vertical voltage line YML2 provides the first power supply voltage VSS to the intermediate lateral voltage line XLM. This makes it possible to provide the first power supply voltage VSS to pixels within the first region (1) without directly connecting the first power supply voltage line located in the first region (1) to the first power supply voltage lead from the pad 3 in the frame region surrounding the lower edge 1b. As can be seen from Figures 1, 6A, and 6D, the lower lead 41 is not connected to the intermediate vertical voltage line YLM located in the first intermediate display area 11M and the second intermediate display area 12M, but is directly connected only to the edge vertical voltage line YLP located in the first edge display area 11P.

[0074] For example, both the second via V2 and the third via V3 penetrate the first insulating layer.

[0075] For example, the first power supply voltage lead 4 is installed on the same layer as the vertical voltage line YLP, and the first power supply voltage lead 4 and the vertical voltage line YLP are made of the same material and form a continuous, integrated molded structure. They may also be formed by the same patterning process, simplifying the structure and manufacturing process of the display board.

[0076] For example, as shown in Figure 1, the display area 1 further includes a right edge 1d opposite the left edge 1b, the first power lead further includes a right lead 44 extending along the right edge 1d, the right lead 44 is electrically connected to the upper lead 43, each of the multiple first lateral voltage lines XLU penetrates the upper display area 13 along the lateral direction X, and the right end opposite the left end of each of the multiple first lateral voltage lines XLU is electrically connected to the right lead 44, thereby simultaneously transmitting the first power supply voltage VSS from the left and right ends of the first lateral voltage lines XLU to the display area 1, improving the signal transmission speed and contributing to improved display quality of the display board.

[0077] For example, multiple intermediate vertical voltage lines YLM and multiple first horizontal voltage lines XLU within the upper display area 13 are connected in a grid pattern by intersecting each other at multiple fourth intersection points P4 within the upper display area 13. Resistance of the first power supply voltage line vss This contributes to reducing the voltage drop. At each position of some of the fourth intersections P4, one intermediate vertical voltage line YLM is electrically connected to one first transverse voltage line XLU via a fourth via V4, thereby connecting multiple first transverse voltage lines XLU extending along the transverse X direction and the intermediate vertical voltage line YLM extending along the vertical Y direction in the upper display area 13 in a grid pattern, thereby reducing the resistance of the first power supply voltage line vss located in this part of the upper display area 13 and reducing the voltage drop on the first power supply voltage line vss.

[0078] The planar pattern consisting of the positions of multiple fourth vias V4 is a polyline (dotted line), which matches the shape of a W-shaped polyline composed of the boundary SL1 (dotted line) between the second region (2) and the third region (3), the boundary of the fourth region (4) between the second region (2) and the first region (1), i.e., the fifth line segment S5 (dotted line), the boundary between the first region (1) and the fourth region (4), i.e., the sixth line segment S6 (dotted line), and the boundary SL3 (dotted line) between the fourth region (4) and the fifth region (5) (at least all of these are polylines). This contributes to maintaining uniformity in the arrangement of connection points connected via vias in the lower display region 14 and the upper display region 13, thereby preventing uneven display defects from occurring on the display board.

[0079] The structure in which one intermediate vertical voltage line YLM is electrically connected to one first horizontal voltage line XLU via a fourth via V4 is similar to the structure of region R1 shown in Figures 3A to 3D, and you may also refer to Figures 3A to 3D, but a detailed explanation is omitted here.

[0080] For example, as shown in Figure 1, the polyline includes multiple sub-polylines extending from the left edge 1b to the right edge 1d, each of the multiple sub-polylines includes multiple polyline portions whose ends are connected to each other, each polyline portion includes a first line segment S1 (dotted line) extending along a first direction and a second line segment S2 (dotted line) extending along a second direction, the first direction intersects with the second direction, and both the first and second directions intersect with the horizontal direction X and the vertical direction Y, the first end of the first line segment S1 overlaps with the first end of the second line segment S2, for example the first end of the first line segment S1 and the first end of the second line segment S2 intersect at the upper vertex TP, multiple vertices of the multiple sub-polylines are located on the second vertical voltage line YML2, and the fourth via V4 at each vertex position is the second via V2.

[0081] For example, as shown in Figure 1, each of the multiple sub-bend lines exhibits a W-shape. In Figure 1, the single dotted line showing a W-shape represents one sub-bend line.

[0082] For example, a W-shaped sub-polyline includes a first line segment S1 (dotted line) and a second line segment S2 (dotted line), and a third line segment S3 (dotted line) and a fourth line segment S4 (dotted line), where the first line segment S1 and the second line segment S2 are located between the third line segment S3 and the fourth line segment S4, the third line segment S3 is connected to the first line segment S1, the fourth line segment S4 is connected to the second line segment S2, the first line segment S1 is approximately parallel to the fourth line segment S4, and the second line segment S2 is approximately parallel to the third line segment S3.

[0083] For example, the vertical direction is perpendicular to the horizontal direction, the angle between the first line segment S1 and the horizontal direction is 45°, and the angle between the second line segment S2 and the horizontal direction is 45°, so that the intermediate vertical voltage line YLM is connected to the first horizontal voltage line XLU at as many intersections as possible via the fourth via V4, in order to ensure that the W-shaped wiring is maintained.

[0084] For example, in the vertical direction Y, auxiliary line segment SA is located between the third line segment S3 of two adjacent sub-bricklines.

[0085] For example, by having the connecting line segment SC, auxiliary line segment SA, and third line segment S3 be approximately parallel to each other, the uniformity of the arrangement of connection points connected via vias to each position in the first edge display area 11P is maintained, thereby preventing uneven display defects from occurring on the display board.

[0086] For example, as shown in Figure 2, the second vertical voltage line YML2 divides the first region (1) into a first sub-region A and a second sub-region B, and the structure of the first sub-region A and the structure of the second sub-region B are approximately axially symmetric with respect to the second vertical voltage line YML2, the lower display region 14 includes a fourth region (4), and the structure of the fourth region (4) and the structure of the second region (2) are approximately axially symmetric with respect to the second vertical voltage line YML2, and the data line data passing through the first region (1) and the fourth region (4) is connected by a third connecting line DL3 extending along the vertical Y direction to the second sub-region B and a third connecting line extending along the horizontal X direction to the fourth region (4) The system includes four connection lines DL4 and a sixth connection line DL6 that extends along the vertical direction Y located in the upper display area 13. The sixth connection line DL6 is installed on the same layer as the first connection line DL1, the third connection line DL3 is installed on the same layer as the vertical voltage line YL, and the fourth connection line DL4 is installed on the same layer as the horizontal voltage line XL. The same data line data is electrically connected by the second connection hole VC2 between the third connection line DL3 and the fourth connection line DL4, and by the fourth connection hole VC4 between the sixth connection line DL6 and the fourth connection line DL4, thereby forming a data signal transmission channel on the data line data.

[0087] For example, the display board 10 includes multiple first connection lines DL1, multiple second connection lines DL2, multiple third connection lines DL3, and multiple fourth connection lines DL4, the multiple first connection lines DL1 and the multiple second connection lines DL2 are electrically connected by multiple first connection holes VC1, the multiple third connection lines DL3 and the multiple fourth connection lines DL4 are electrically connected by multiple second connection holes VC2, and the planar pattern consisting of the multiple first connection holes VC1 is the fifth line segment S5, and the fifth line The segment S5 is the boundary between the first region (1) and the second region (2), the planar pattern consisting of multiple second connection holes VC2 is the sixth line segment S6, the sixth line segment S6 is the boundary between the first region (1) and the fourth region (4), the lower display region 14 further includes the fifth region (5), the structure of the fifth region (5) and the structure of the third region (3) are approximately axially symmetric with respect to the second longitudinal voltage line YML2, and the planar pattern of multiple fifth vias V5 that are symmetric with respect to multiple first vias V1 in the fifth region (5) is the seventh line segment S7. As shown in Figure 1, the planar pattern formed by sequentially connecting the connecting line segment SC (dotted line), the fifth line segment S5 (dotted line), the sixth line segment S6 (dotted line), and the seventh line segment S7 (dotted line) is the same as the planar pattern of each of the multiple sub-polylines (for example, a W-shaped sub-polyline). This maintains uniformity in the arrangement of connection points connected via vias in the lower display area 14 and the upper display area 13, thereby preventing uneven display defects from occurring on the display board.

[0088] For example, as shown in Figure 1, the boundary line between the second region (2) and the third region (3) is the first side SL1 of the second region (2), and the angle between the first line segment S1 and the transverse direction X is smaller than the angle between the first side SL1 and the transverse direction X.

[0089] For example, as shown in Figures 1 and 2, the planar shape of the first region (1) is the first triangle, and the planar shape of the second region (2) is the second triangle, and the left edge 1b is adjacent to the first triangle in the lateral direction X. 1The side (i.e., the second connection line SL2) overlaps with at least a portion of the first side (i.e., the second connection line SL2) that moves away from the left edge 1b of the display area 1 in the horizontal direction X of the second triangle, the two lower vertices DP1 and DP2 of the first triangle are located at the lower edge 1a of the display area 1, the left vertex approaching the left edge 1b of the two lower vertices of the first triangle is the left endpoint PO of the first sub-area A, the first triangle is an isosceles triangle, and the second vertical voltage line YML2 is approximately the perpendicular bisector of the base of the isosceles triangle. By arranging in this way, the arrangement of data lines and first power supply voltage lines throughout the entire display area 1 can be made uniform and consistent, thereby preventing uneven defects from occurring on the display board.

[0090] Figure 8A is a figure 1 Figure 8B-8C is a schematic diagram of a partially enlarged portion of region R5 in Figure 3, and the schematic diagrams of the partial film layer of region R5 in Figure 3 are shown. For example, referring to Figure 1 and Figures 8A-8C, frame region 2 includes the left frame region 2a extending along the left edge 1b, and the left frame region 2 a Multiple auxiliary connection lines ACLs are installed along the horizontal direction X, and these multiple auxiliary connection lines ACLs are installed on the same layer as the edge vertical voltage lines YLP. Display area 1 includes a pixel array, which includes multiple pixel rows extending along the horizontal direction X and multiple pixel columns extending along the vertical direction Y. For example, multiple auxiliary connection lines ACLs correspond one-to-one with multiple first horizontal voltage lines XLU, and correspond one-to-one with multiple pixel rows in the upper display area 13. Multiple pixel rows include the edge pixel row PXC0 closest to the left edge 1b, multiple edge vertical voltage lines YLP include the outer edge vertical voltage line YLP-1 passing through the edge pixel row PXC0, the left end of each of the multiple auxiliary connection lines ACL in the lateral direction X is electrically connected to the left lead 42, for example, directly, the right end of each of the multiple auxiliary connection lines ACL opposite its left end in the lateral direction X is electrically connected to the outer edge vertical voltage line YLP, and is electrically connected to the left end of the corresponding first lateral voltage line XLU via the second edge via VP2. For example, as shown in Figures 8A and 8B, the right end of each of the multiple auxiliary connection lines ACL in the lateral direction X is connected via the second edge via VP2 to a third connection configuration C3 located at the left end of the corresponding first lateral voltage line XLU. ru.

[0091] For example, the auxiliary connecting wire ACL is installed in the same layer as the left lead 42, and for instance, both are made of the same material, forming a continuous, integrally molded structure. Of course, the materials of both may be different.

[0092] Here, taking the situation in the left frame region 2a as an example, multiple auxiliary connection lines ACLs are also installed in the right frame region opposite to the left frame region in the horizontal direction X. The connection method between the auxiliary connection lines ACLs in the right frame region and the right end of the first horizontal voltage line XLU is the same as the connection method between the auxiliary connection lines ACLs in the left frame region 2a and the left end of the first horizontal voltage line XLU, and a detailed explanation is omitted here.

[0093] For example, referring to Figure 1, the right display area 12 includes a second edge display area 12P extending along the right edge 1d, and a second intermediate display area 12M located on the side of the second edge display area 12P approaching the left display area 11. The second edge display area 12P and the first edge display area 11P are symmetric with respect to an axis of symmetry extending along the vertical direction Y, and the second intermediate display area 12M and the first intermediate display area 11M are axisymmetric with respect to the second vertical voltage line YML2. The first intermediate display area 11M and the second intermediate display area 12M constitute an intermediate display area, the second sub-area B is located in the second intermediate display area 12M, and the first area (1) is located in the intermediate display area.

[0094] For example, the first power supply voltage lead 4 is another lower lead that extends along the portion of the lower edge 1a corresponding to the second edge display area 12P. 45 The configuration further includes, for example, an edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P is electrically connected by contacting another lower lead 45, for example, the two are directly connected, i.e., the second edge display area 12P ni The edge voltage line providing the first power supply voltage VSS and another lower lead 451 are in contact with each other, and there is no other structure acting as a medium connecting the edge voltage line providing the first power supply voltage VSS in the second edge indicator region 12P and the other lower lead 45. For example, the edge voltage line providing the first power supply voltage VSS in the second edge indicator region 12P is located on the same layer as the other lower lead 45 and constitutes a continuous, integrally molded structure.

[0095] Naturally, in other embodiments, the edge voltage line providing the first power supply voltage VSS in the second edge indicator area 12P may be located on a different layer from another lower lead 45, and both may be in contact with each other via vias.

[0096] For example, the display board 10 further includes a second power supply voltage line vdd (not shown in Figure 1), which is configured to provide a sub-pixel with a second power supply voltage different from the first power supply voltage VSS, for example, with the polarities of the first power supply voltage VSS and the second power supply voltage VDD being reversed. For example, the first power supply voltage VSS may be at a low level and the second power supply voltage VDD may be at a high level. Of course, the first power supply voltage VSS may be at a high level and the second power supply voltage VDD may be at a low level.

[0097] For example, the vertical voltage line YL is placed on the same layer as the data line data in the upper display area 13, and the horizontal voltage line XL is placed on the same layer as the second power supply voltage line.

[0098] Figure 10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure, Figures 11A to 11H are schematic diagrams of different film layers in the pixel circuit, and Figure 11I is a schematic diagram of the stacking of the film layers shown in Figures 11A to 11F. The dotted line frame in Figure 11A represents the region of one subpixel.

[0099] In some examples, as shown in Figure 10, the display board further includes a plurality of subpixels, at least some of which include a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120.

[0100] For example, as shown in Figures 10 to 11I, the pixel circuit includes multiple transistors and at least one capacitor. For example, the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset control transistor T7, a third reset transistor T8, and a memory capacitor C.

[0101] For example, as shown in Figures 10 to 11I, the display board has reset power signal lines 561, 551 and 554, scan signal lines 552, 531 and 523, second power voltage line vdd, reset control signal lines 522, 532 and 553, light emission control signal line 521, and data lines 200 It also includes.

[0102] For example, as shown in Figures 10 to 11I, the first pole of the threshold compensation transistor T2 is electrically connected to the first pole of the drive transistor T3, the second pole of the threshold compensation transistor T2 is electrically connected to the gate of the drive transistor T3, and the gate of the threshold compensation transistor T2 is electrically connected to the scan signal lines 531 and 552 to receive the compensation control signal, the first pole of the first reset control transistor T7 is electrically connected to the reset power signal line 561 to receive the reset signal Vinit2, the second pole of the first reset control transistor T7 is electrically connected to the first electrode of the light-emitting element (i.e., the N4 node), and the gate of the first reset control transistor T7 is electrically connected to the reset control signal line 522 to receive the reset control signal Reset(N+1), the first pole of the third reset transistor T8 is electrically connected to the reset power signal line 551 to receive the reset signal Vref, the second pole of the third reset transistor T8 is electrically connected to the second pole of the drive transistor T3, and the gate of the third reset transistor T8 is electrically connected to the reset control signal line 522, and the data write transistor The first pole of transistor T4 is electrically connected to the second pole of drive transistor T3, and the second pole of data writing transistor T4 is electrically connected to data line 200 (data line data) to receive the data signal Data, and the gate of data writing transistor T4 is electrically connected to scan signal line 523 to receive the scan signal Gate, the first pole of memory capacitor C is electrically connected to the second power supply voltage line vdd, and the second pole of memory capacitor C is electrically connected to the gate of drive transistor T3, and the first pole of second reset transistor T1 is electrically connected to reset power supply signal line 554 to receive the reset signal Vinit1, the second pole of second reset transistor T1 is electrically connected to the gate of drive transistor T3, and the gate of second reset transistor T1 is electrically connected to reset control signal lines 553 and 532 to receive the reset control signal Reset(N), the gate of first light emission control transistor T6 is electrically connected to light emission control signal line 521 to receive the light emission control signal EM, and the first pole of first light emission control transistor T6 is electrically connected to the first pole of drive transistor T3,The second pole of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 120, and the first pole of the second light-emitting control transistor T5 is electrically connected to the second power supply voltage line vdd, thereby receiving the first power supply signal VDD. The second pole of the second light-emitting control transistor T5 is electrically connected to the second pole of the drive transistor T3, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line 521, thereby receiving the light-emitting control signal EM. The second electrode of the light-emitting element 120 is connected to the voltage terminal VS, S Electrically connected 。

[0103] It should be noted that, in the embodiments of this disclosure, each pixel circuit may be an 8T1C (i.e., 8 transistors and 1 capacitor) structure as shown in Figure 10, but may also be a structure containing a further number of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and the embodiments of this disclosure are not limited thereto.

[0104] Figure 11A shows the active semiconductor pattern 510. For example, as shown in Figure 11A, the active semiconductor pattern 510 may be used to fabricate the active layers of the drive transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, first reset control transistor T7, and third reset control transistor T8 in order to form the channel region of the transistors. The active semiconductor pattern 510 includes the active layer pattern (channel region) and doped region pattern (source / drain region) of the transistors in each subpixel, and the active layer pattern and doped region pattern of the transistors in the same pixel circuit are installed integrally.

[0105] For example, the active semiconductor pattern 510 may include a low-temperature polycrystalline silicon layer formed integrally, and the source region and drain region can be made conductive by doping or the like to realize electrical connection between each structure. For example, the source region and drain region may be regions doped with p-type impurities.

[0106] Figure 11B shows a first conductive layer pattern 520 located on the side of the active semiconductor pattern 510 away from the base substrate. For example, as shown in Figure 11B, the first conductive layer pattern 520 includes a reset control signal line 522, a scan signal line 523, one pole of a capacitor 524, and a light emission control signal line 521. For example, the first conductive layer pattern 520 may also include the gates of a drive transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset control transistor T7, and a third reset control transistor T8.

[0107] What needs to be explained is that in Figure 11A, each dotted rectangular frame represents the portion where the active semiconductor pattern 510 and the first conductive layer pattern 520 overlap, i.e., the channel region. As the channel region of each transistor, the active semiconductor layers on both sides of each channel region are made conductive by a process such as ion doping to become the first and second poles of each transistor. The source electrode and drain electrode of a transistor may be structurally symmetrical, and therefore, there may be no physical distinction between the source electrode and the drain electrode. In the embodiments of this disclosure, in order to distinguish transistors, it is explained that, in addition to the gate as a control electrode, one electrode is directly the first pole and the other electrode is the second pole, and therefore, the first and second poles of all or some transistors in the embodiments of this disclosure are interchangeable as needed.

[0108] For example, as shown in Figures 11B and 11I, the gate of the data writing transistor T4 may be the overlapping portion of the scan signal line 523 and the active semiconductor pattern 510, the gate of the first light emission control transistor T6 may be the first overlapping portion of the light emission control line 521 and the active semiconductor pattern 510, and the gate of the second light emission control transistor T5 may be the second overlapping portion of the light emission control line 521 and the active semiconductor pattern 510. The gate of the third reset transistor T8 is the first overlapping portion of the reset control line 522 and the active semiconductor pattern 510, and the gate of the first reset control transistor T7 is the second overlapping portion of the reset control line 522 and the active semiconductor pattern 510.

[0109] Figure 11C shows the second conductive layer pattern 530 on the side of the first conductive layer pattern 520 that is away from the base substrate. For example, as shown in Figure 11C, the second conductive layer pattern 530 includes a scan signal line 531, a second pole 533 of capacitor C, and a reset control signal line 532.

[0110] Figure 11D shows the active layer pattern 540 on the side of the second conductive layer pattern 530 that is away from the base substrate. For example, as shown in Figure 11D, the active layer pattern 540 includes the channel region of the second reset transistor T1 and the threshold compensation transistor T2. For example, when the active layer in the second reset transistor T1 and the threshold compensation transistor T2 uses an oxide semiconductor, transistors using oxide semiconductors have good hysteresis characteristics and low leakage current, as well as relatively low mobility. Therefore, transistors using oxide semiconductors can be used to replace the low-temperature polycrystalline silicon material in transistors, forming a low-temperature polycrystalline silicon-oxide (LTPO) pixel circuit, achieving low leakage current and contributing to improved gate voltage stability of the transistor.

[0111] For example, as shown in Figures 11C, 3D and 11I, the gate of the second reset transistor T1 may be in the area where the reset control signal line 532 and the active layer pattern 540 overlap, and the gate of the threshold compensation transistor T2 may be in the area where the scan signal line 531 and the active layer pattern 540 overlap.

[0112] Figure 11E shows the third conductive layer 550 on the side of the active layer pattern 540 that is away from the base substrate. For example, as shown in Figure 11E, the third conductive layer 550 includes a reset power signal line 554, a reset control signal line 553, a scan signal line 552, and a reset power signal line 551.

[0113] For example, as shown in Figures 11C to 11F and Figure 11I, the reset control signal line 553 overlaps with the channel region of the second reset transistor T1, the second reset transistor T1 includes double gates located on both sides of the active layer, and the scan signal line 552 overlaps with the channel region of the threshold compensation transistor T2, the threshold compensation transistor T2 includes double gates located on both sides of the active layer, and the threshold compensation transistor T2 is a double gate transistor.

[0114] For example, the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors. The data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, the first reset control transistor T7, and the third reset control transistor T8 may be P-type transistors.

[0115] Figure 11F shows a fourth conductive layer 560 located on the side of the third conductive layer 550 away from the base substrate. For example, as shown in Figure 11F, the fourth conductive layer 560 includes a reset power signal line 561, connection parts 568, 569, 563, 567, 562, 564, 565, and 566.

[0116] For example, as shown in Figures 10 to 11I, the connector 568 has both ends connected to the reset power signal line 551 and its center connected to the first pole of the third reset transistor T8; the connector 569 connects the data line data to the second pole of the data writing transistor T4; the connector 563 is for electrically connecting the first pole of the data writing transistor T4 to the second pole of the third reset transistor T8 so as to introduce the reset signal Vref to the N2 node; and the connector 567 is for electrically connecting the first pole of the drive transistor T3 to the first pole of the threshold compensation transistor T2. The center of the connection part 562 is connected to the second power supply voltage line vdd (for example, Figure 11H, i.e., the second power supply voltage line vdd), both ends of the connection part 562 are connected to one pole 533 of the capacitor, one end of the connection part 564 is connected to the second pole 533 of the memory capacitor C, the other end of the connection part 564 is connected to the first pole of the second light emission control transistor T5, the connection part 565 is for electrically connecting the first electrode of the light-emitting element and the second pole of the first light emission control transistor T6, and the connection part 566 is for electrically connecting the reset power supply signal line 554 and the first pole of the second reset transistor T1.

[0117] Figure 11G shows a fifth conductive layer 570 located on the side of the fourth conductive layer 560 away from the base substrate. For example, as shown in Figure 11G, the fifth conductive layer 570 includes a connector 573, a connector 575, a second power supply voltage line 572 (transmitting the second power supply voltage VDD), a connector 574, and a lateral voltage line XL (e.g., an intermediate lateral voltage line XLM). For example, the fifth conductive layer 570 further includes a fourth connector line.

[0118] For example, as shown in Figures 10 to 11G, the connection part 573 is for electrically connecting to the data line data, and for example, the data line data is electrically connected by the connection part 573 to several connection lines installed on a different layer from the data line data that extends along the horizontal direction X in the display area 1, thereby transmitting the data signal DATA to the connection lines. The connection part 575 is a spare pad, and the first connection line may be electrically connected to the second connection line by the spare pad, or the vertical voltage line may be electrically connected to the horizontal voltage line by the spare pad. For example, the electrical connection between the connection part 574 and the connection part 565 realizes the electrical connection between the second pole of the first light-emitting control transistor T6 and the first electrode of the light-emitting element. For example, the second power supply voltage line 572 is electrically connected to the second power supply voltage line vdd.

[0119] Figure 11H shows the sixth conductive layer 580 located on the side of the fifth conductive layer 570 away from the base substrate. For example, as shown in Figure 11H, the sixth conductive layer 580 includes data lines data, a second power supply voltage line vdd, a fifth connection line 450, and connection parts 584 and 585.

[0120] For example, connection parts 584 and 585 are electrically connected to the first electrodes of different light-emitting elements.

[0121] For example, as shown in Figures 11G and 11H, the data line data includes a relay pad 290, and the data line data is connected to the connection section 573 by the relay pad 290, thereby electrically connecting to several connection lines located on a different layer from the data line data that extends along the horizontal direction X in the display area 1, thereby transmitting the data signal DATA to the connection lines. For example, each of the vertical voltage lines YL includes a relay pad 459, and the vertical voltage lines YL are connected to the relay pad 459 ri The connecting portion 575 may be electrically connected to the corresponding horizontal voltage line XL which is to be electrically connected to the vertical voltage line YL, thereby achieving an electrical connection between the vertical voltage line YL and the horizontal voltage line XL.

[0122] As shown in Figure 12, at least one embodiment of the present disclosure further provides a display device 100, which includes any one type of display substrate 10 relating to at least one embodiment of the disclosure.

[0123] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

Claims

1. A display board, A display area having subpixels and a lower edge extending along the horizontal direction and a left edge extending along the vertical direction, wherein the horizontal direction intersects the vertical direction, and the display area includes a left display area and a right display area arranged in the horizontal direction, and the left display area includes a first edge display area extending along the left edge and a first intermediate display area approaching the right display area located in the first edge display area, A non-display area including a frame area surrounding at least a portion of the aforementioned display area, A first power supply voltage lead configured to provide a first power supply voltage, located in the frame region, wherein the first power supply voltage lead includes a lower lead extending along the portion of the lower edge corresponding to the first edge indicator region, and the first power supply voltage lead does not extend along the portion of the lower edge corresponding to the first intermediate indicator region, A display board comprising a first power supply voltage line including an edge voltage line located at the edge of the first edge display area and an intermediate voltage line located in the first intermediate display area, wherein the edge voltage line is electrically connected to the lower lead by contact with it, thereby providing the first power supply voltage to the sub-pixel located in the first edge display area, and the intermediate voltage line is separated from the lower lead.

2. The first power supply voltage line includes a vertical voltage line extending along the vertical direction and a horizontal voltage line extending along the horizontal direction, wherein the vertical voltage line and the horizontal voltage line are installed on different layers. The vertical voltage lines include vertical voltage lines located in the first edge display area, and the horizontal voltage lines include horizontal voltage lines located in the first edge display area and intersecting the vertical voltage lines, and the vertical voltage lines and the horizontal voltage lines constitute the edge voltage lines. The display board according to claim 1, wherein the first power supply voltage lead further includes a left lead extending along the left edge of the display area, the edge vertical voltage line being directly connected to the lower lead, and the edge horizontal voltage line being directly connected to the left lead.

3. The subpixel further includes a data line, and the subpixel includes a drive transistor, a light-emitting device, and a data transistor, wherein the drive transistor is configured to control the magnitude of the drive current flowing through the light-emitting device, the light-emitting device is configured to receive the drive current and to emit light when driven by the drive current, the data transistor is configured to write a data signal to the gate of the drive transistor in response to a first control signal, and the data line is configured to transmit the data signal to the subpixel. The display area includes a lower display area and an upper display area, wherein the lower display area is close to the lower edge, and the upper display area is located on the side away from the lower edge of the lower display area in the vertical direction. The lower display area includes a first area and a second area, the first area includes a first sub-area approaching the left edge in the lateral direction and a second sub-area moving away from the left edge, the data lines passing through the first sub-area and the second area include a first connecting line extending vertically within the first sub-area and a second connecting line extending horizontally within the second area, the first connecting line being installed on the same layer as the vertical voltage lines and the second connecting line being installed on the same layer as the horizontal voltage lines, the first connecting line and the second connecting line of the same data line being electrically connected by a first connecting hole, the first sub-area being located in the first intermediate display area and at least a portion of the second area being located in the first intermediate display area. The display substrate according to claim 2, wherein the first sub-region has a left endpoint that is closest to the left edge of the display region in the lateral direction, and a straight line extending along the vertical direction and passing through the left endpoint is the boundary line between the first edge display region and the first intermediate display region.

4. The boundary line passes through the second region and divides the second region into a third sub-region approaching the left edge of the display region and a fourth sub-region moving away from the left edge of the display region, the first sub-region being located in the first edge display region and the second sub-region being located in the first intermediate display region. The aforementioned lower display area is, The third region is located in the first edge display region and is located laterally on the side of the second region away from the first region, The lateral edge voltage line includes the lower lateral edge voltage line located in the third region, the longitudinal edge voltage line passes through the third region and intersects with the lower lateral edge voltage line at a first intersection, the left end of the lower lateral edge voltage line is electrically connected to the left lead, and the right end of the lower lateral edge voltage line opposite its left end and the second connecting line in the second region are severed by the first fracture surface. The edge voltage line includes a plurality of vertical edge voltage lines and a plurality of horizontal edge voltage lines, the plurality of vertical edge voltage lines and the plurality of horizontal edge voltage lines intertwine with each other to form a grid, and the grid includes a plurality of first intersections, The display board according to claim 3, wherein at each position of some of the first intersections among the plurality of first intersections, one vertical edge voltage line is electrically connected to one horizontal lower edge voltage line via a first via.

5. The display board according to claim 4, wherein the plurality of vertical edge voltage lines are electrically connected to the plurality of horizontal edge voltage lines via a plurality of first vias, the planar pattern consisting of the positions of the plurality of first vias is a connecting line segment located in the third region, and the extending direction of the connecting line segment intersects both the horizontal and vertical directions.

6. The display substrate according to claim 4, wherein the third region is a corner region of the second region defined by the first side approaching the left edge in the lateral direction, the left edge, and the lower edge.

7. The frame region includes a frame corner region surrounding the corner region, and a grid-like auxiliary first power supply voltage line is installed in the frame corner region, and the grid-like auxiliary first power supply voltage line is, A plurality of vertical auxiliary voltage lines extending along the aforementioned vertical direction and installed on the same layer as the aforementioned vertical voltage line, wherein the first end of each of the plurality of vertical auxiliary voltage lines in the aforementioned vertical direction is directly connected to the first power supply voltage lead, and the second end of each of the plurality of vertical auxiliary voltage lines facing its first end in the aforementioned vertical direction is electrically connected to one of the edge vertical voltage lines passing through the corner region, The display board according to claim 6, comprising a plurality of lateral auxiliary voltage lines extending along the lateral direction and installed in the same layer as the plurality of vertical auxiliary voltage lines, wherein one end of each of the plurality of lateral auxiliary voltage lines in the lateral direction is directly connected to the first power supply voltage lead, and the second end of each of the plurality of lateral auxiliary voltage lines facing its first end in the lateral direction is electrically connected to one of the edge vertical voltage lines.

8. The display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel rows include a plurality of edge pixel rows approaching the lower edge, the plurality of horizontal auxiliary voltage lines correspond one-to-one with the plurality of edge pixel rows, each of the plurality of edge pixel rows includes an edge subpixel closest to the left edge, and the plurality of edge vertical voltage lines include the outermost edge vertical voltage lines of the edge subpixel passing through each of the edge pixel rows. The display board according to claim 7, wherein the second end of each of the plurality of lateral auxiliary voltage lines is electrically connected to the outermost vertical voltage line passing through the corresponding edge pixel row, and is electrically connected via the first edge via to the edge lateral voltage line passing through the corresponding edge pixel row.

9. The aforementioned lateral voltage line is, The above further includes a plurality of first horizontal voltage lines arranged in the vertical direction and located in the upper display area, the left end of each of the first horizontal voltage lines being electrically connected to the left lead, the edge horizontal voltage line further includes an upper edge horizontal voltage line located in the upper display area, and the upper edge horizontal voltage line is part of one of the first horizontal voltage lines, The aforementioned vertical voltage lines are, The aforementioned intermediate vertical voltage lines are arranged in the horizontal direction and further include a plurality of intermediate vertical voltage lines that pass through a portion of the first intermediate display area and the upper display area along the vertical direction, and the plurality of intermediate vertical voltage lines, the plurality of edge vertical voltage lines and the plurality of first horizontal voltage lines are intertwined to form a grid. The plurality of vertical edge voltage lines and the plurality of first horizontal voltage lines intersect at a plurality of auxiliary intersections within the first edge display area, and at each position of some of the auxiliary intersections, one of the vertical edge voltage lines is electrically connected to one of the first horizontal voltage lines via an auxiliary via, and the plurality of vertical edge voltage lines are electrically connected to the plurality of first horizontal voltage lines via a plurality of auxiliary vias. The display board according to claim 5, wherein the planar pattern consisting of the positions of the plurality of auxiliary vias is an auxiliary line segment located in the first edge display area, and the end of the auxiliary line segment that is separated from the left edge is suspended.

10. The extension direction of the auxiliary line segment is the same as the extension direction of the connecting line segment. The display board according to claim 9, wherein the display board includes a plurality of auxiliary line segments, and the connecting line segment and the plurality of auxiliary line segments are arranged at intervals from each other along the vertical direction.

11. The display area further includes an upper edge opposite to the lower edge, and the first power supply voltage lead further includes an upper lead extending along the upper edge, the upper lead being electrically connected to the left lead. The upper end of the edge vertical voltage line is connected to the upper lead, and the lower end of the edge vertical voltage line opposite to its upper end is directly connected to the lower lead. The aforementioned vertical voltage lines include intermediate vertical voltage lines located in the first intermediate display region, and the aforementioned intermediate vertical voltage lines are A first vertical voltage line that passes sequentially through the upper display area and at least a portion of the second area along the vertical direction, wherein the upper end of the first vertical voltage line is electrically connected to the upper lead, and the lower end of the first vertical voltage line opposite to its upper end and the first connecting line in the first sub-area are cut by the second fracture surface, The display board according to claim 9, comprising: a second vertical voltage line passing sequentially through the upper display area and the first area along the vertical direction, wherein the horizontal voltage line includes an intermediate horizontal voltage line located in the first area, the intermediate horizontal voltage line and the second connecting line in the second area are cut by a third fracture surface, the second vertical voltage line and the intermediate horizontal voltage line intersect at a second intersection, and the second vertical voltage line is electrically connected to the intermediate horizontal voltage line at the second intersection via a second via.

12. The display board according to claim 11, wherein the plurality of first transverse voltage lines and the plurality of second vertical voltage lines intersect at a plurality of third intersections, and at each position of at least some of the plurality of third intersections, one of the first transverse voltage lines is electrically connected to one of the second vertical voltage lines via a third via.

13. The display area further includes a right edge opposite to the left edge, and the first power lead further includes a right lead extending along the right edge, the right lead being electrically connected to the upper lead. The display board according to claim 11, wherein each of the plurality of first lateral voltage lines penetrates the upper display area along the lateral direction, and the right end of each of the plurality of first lateral voltage lines opposite its left end is electrically connected to the right lead.

14. The plurality of intermediate vertical voltage lines and the plurality of first horizontal voltage lines intersect each other at a plurality of fourth intersections within the upper display area, and at each of some of the fourth intersections, one intermediate vertical voltage line is electrically connected to one of the first horizontal voltage lines via a fourth via. The display board according to claim 13, wherein the planar pattern consisting of the positions of the plurality of fourth vias is a polyline.

15. The polyline includes a plurality of sub-polylines extending from the left edge to the right edge, and each of the plurality of sub-polylines includes a plurality of polyline portions whose ends are connected to each other. Each of the aforementioned multiple broken line portions includes a first line segment extending along a first direction and a second line segment extending along a second direction, wherein the first direction intersects the second direction, and both the first and second directions intersect the horizontal and vertical directions, and the first end of the first line segment and the first end of the second line segment intersect at the upper vertex. The display board according to claim 14, wherein multiple vertices of the multiple sub-bellipses are located on the second vertical voltage line, and all of the fourth vias at the vertex positions are the second vias.

16. The display board according to claim 15, wherein each of the multiple sub-bend lines exhibits a W-shape.

17. The W-shaped sub-bend includes the first line segment and the second line segment, and the third line segment and the fourth line segment, wherein the first and second line segments are located between the third and fourth line segments, the third line segment is connected to the first line segment, and the fourth line segment is connected to the second line segment. The first line segment is approximately parallel to the fourth line segment, The display board according to claim 16, wherein the second line segment is substantially parallel to the third line segment.

18. The display board according to claim 17, wherein the vertical direction is perpendicular to the horizontal direction, the angle between the first line segment and the horizontal direction is 45°, and the angle between the second line segment and the horizontal direction is 45°.

19. The display board according to claim 17, wherein the auxiliary line segment is located between the third line segments of two adjacent sub-bend lines in the vertical direction.

20. The display board according to claim 19, wherein the connecting line segment, the auxiliary line segment, and the third line segment are substantially parallel to each other.

21. The second longitudinal voltage line divides the first region into a first sub-region and a second sub-region, and the structure of the first sub-region and the structure of the second sub-region are substantially axially symmetric with respect to the second longitudinal voltage line. The lower display area includes a fourth area, the structure of the fourth area and the structure of the second area are substantially axially symmetric with respect to the second longitudinal voltage line, the data line passing through the first area and the fourth area includes a third connecting line extending longitudinally into the second sub-area and a fourth connecting line extending transversely into the fourth area, the third connecting line is installed on the same layer as the longitudinal voltage line, the fourth connecting line is installed on the same layer as the transverse voltage line, and the third and fourth connecting lines of the same data line are electrically connected by a second connecting hole. The display substrate according to claim 15, wherein the right end opposite to the left end of the intermediate lateral voltage line located in the first region and the fourth connecting line in the fourth region are cut by the fourth fracture surface.

22. The display board includes a plurality of first connection lines, a plurality of second connection lines, a plurality of third connection lines, and a plurality of fourth connection lines, wherein the plurality of first connection lines and the plurality of second connection lines are electrically connected by a plurality of first connection holes, and the plurality of third connection lines and the plurality of fourth connection lines are electrically connected by a plurality of second connection holes. The planar pattern consisting of the plurality of first connection holes is a fifth line segment, and the fifth line segment is the boundary between the first region and the second region. The planar pattern consisting of the plurality of second connection holes is a sixth line segment, and the sixth line segment is the boundary between the first region and the fourth region. The lower display region further includes a fifth region, the structure of the fifth region and the structure of the third region are substantially axially symmetric with respect to the second longitudinal voltage line, and the planar pattern of the plurality of fifth vias symmetric with respect to the plurality of first vias in the fifth region is a seventh line segment. The display board according to claim 21, wherein the planar pattern formed by sequentially connecting the connecting line segment, the fifth line segment, the sixth line segment, and the seventh line segment is the same as the planar pattern of each of the multiple sub-polylines.

23. The planar shape of the first region is a first triangle, the planar shape of the second region is a second triangle, the first side of the first triangle approaching the left edge in the lateral direction overlaps with at least a portion of the first side of the second triangle moving away from the left edge of the display region in the lateral direction, the two lower vertices of the first triangle are located at the lower edge of the display region, and the left vertex of the two lower vertices of the first triangle approaching the left edge is the left endpoint of the first sub-region. The display board according to claim 21, wherein the first triangle is an isosceles triangle and the second vertical voltage line is approximately the perpendicular bisector of the base of the isosceles triangle.

24. The frame region includes a left frame region extending along the left edge, and a plurality of auxiliary connection lines extending along the horizontal direction are installed in the left frame region, and the plurality of auxiliary connection lines are installed on the same layer as the vertical voltage lines of the edge. The display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel columns include an edge pixel column closest to the left edge, and the plurality of edge vertical voltage lines include an outer edge vertical voltage line passing through the edge pixel column. The display board according to claim 9, wherein the left end of each of the plurality of auxiliary connection lines in the lateral direction is electrically connected to the left lead, the right end of each of the plurality of auxiliary connection lines opposite to its left end in the lateral direction is electrically connected to the outer edge vertical voltage line, and is electrically connected to the left end of the corresponding first lateral voltage line via a second edge via.

25. The right display area includes a second edge display area extending along the right edge and a second intermediate display area located on the side of the second edge display area approaching the left display area. The display substrate according to claim 13, wherein the second edge display region and the first edge display region are symmetric with respect to an axis of symmetry extending along the vertical direction, and the second intermediate display region and the first intermediate display region are axially symmetric with respect to a second vertical voltage line.

26. The aforementioned display board is The system further includes a second power supply voltage line configured to provide the subpixel with a second power supply voltage different from the first power supply voltage, The display board according to claim 2, wherein the vertical voltage lines are installed on the same layer as the data lines in the upper display area, and the horizontal voltage lines are installed on the same layer as the second power supply voltage lines.

27. A display device comprising a display board according to any one of claims 1 to 26.

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