High-Performance Hybrid Bonded Interconnect System

Abstract

A high performance hybrid bonded interconnect structure and a method for fabricating the same are disclosed. The interconnect structure can include a first plurality of die stacks bonded to a carrier. A protective layer can be provided over at least a portion of the first plurality of die stacks and the second plurality of die stacks. A bridging layer having conductive interconnects can provide electrical communication between the plurality of die stacks.

Description

[Technical Field]

[0001] TECHNICAL FIELD The technical field relates to high performance three-dimensional bonded structures and methods for forming high performance three-dimensional bonded structures. [Background technology]

[0002] In semiconductor device packaging equipment, stacking of integrated circuits is used in many applications. For example, three-dimensional (3D) integration techniques often utilize packages in which two or more integrated device dies are stacked on top of each other and electrically connected to each other. Conventional methods for fabricating 3D integrated devices can limit product yield due to stresses exerted on both the die and the substrate during assembly. Therefore, there continues to be a need for improved systems and methods for stacking integrated device dies. Summary of the Invention

[0003] In one embodiment, the bonded structure may include a carrier and a first plurality of die stacks, each die stack including a plurality of dies, each die stack of the first plurality of die stacks being bonded to the carrier, and the bonded structure may further include a protective layer disposed on at least a portion of the first plurality of die stacks, and a bridging layer including a non-conductive bridge layer and a lateral conductive interconnect, the lateral conductive interconnect providing or enabling electrical communication between the first plurality of die stacks.

[0004] In some embodiments, the bonded structure can further include a plurality of contact features at least partially embedded in the non-conductive bridge layer, with the lateral conductive interconnect providing electrical communication between at least two of the plurality of contact features. In some embodiments, the bonded structure can further include at least one die stack directly bonded to the bridging layer without an adhesive. In some embodiments, the bonded structure can further include a second plurality of die stacks directly bonded to the bridging layer and a bridging element directly bonded to the second plurality of die stacks. In some embodiments, the bonded structure can further include at least one test pad at least partially embedded in the bridging layer, with the test pad in electrical communication with the first plurality of die stacks and the second plurality of die stacks. In some embodiments, the bonded structure can further include a bridging element directly bonded to the bridging layer without an adhesive. In some embodiments, the bonded structure can further include a cavity disposed between the first die stack and the second die stack. In some embodiments, each die stack of the first plurality of die stacks comprises a first die bonded to a second die without an adhesive. In some embodiments, a first non-conductive bonding layer of at least one die stack of the plurality of die stacks is directly bonded to a second non-conductive bonding layer of the carrier without an intervening adhesive, and a first contact feature of at least one die stack of the plurality of die stacks is directly bonded to a second contact feature of the carrier without an intervening adhesive. In some embodiments, the material of the protective layer is the same as the material of the bridging layer.

[0005] In another embodiment, the bonded structure may include a first die stack including a first plurality of dies, a second die stack including a second plurality of dies, a protective layer disposed around at least lateral sides of the first and second die stacks and between the first die stack and the second die stack, and a bridging layer disposed on the first die stack, the second die stack, and the protective layer, wherein the bridging layer provides electrical communication between the first die stack and the second die stack.

[0006] In some embodiments, the first plurality of dies in the first die stack are direct hybrid bonded to one another. In some embodiments, the second plurality of dies in the second die stack are direct hybrid bonded to one another. In some embodiments, the first die stack and the second die stack are direct hybrid bonded to the carrier. In some embodiments, the first die stack and the second die stack are direct hybrid bonded to a bridging element. In some embodiments, the bonded structure can further include a third die stack including a third plurality of dies, the third die stack being direct hybrid bonded to the bridging layer, and the bonded structure can further include a fourth die stack including a fourth plurality of dies, the fourth die stack being direct hybrid bonded to the bridging layer. In some embodiments, the bonded structure can further include bridging elements bonded to the third die stack and the fourth die stack. In some embodiments, the bonded structure may further include at least one test pad embedded in the bridging layer, the test pad configured to be in electrical communication with the first die stack, the second die stack, the third die stack, and the fourth die stack.

[0007] In another embodiment, a method of forming a bonded structure is disclosed. The method may include direct bonding a first plurality of stacks to a carrier, each stack of the first plurality of stacks including at least one die in contact with the carrier, and the method may further include depositing a protective layer on at least a portion of the plurality of stacks, planarizing the protective layer, and forming a non-conductive bridging layer having a non-conductive bridge layer and lateral conductive interconnects, the lateral conductive interconnects providing electrical communication between the first plurality of stacks.

[0008] In some embodiments, the method may further include forming a first plurality of contact features at least partially embedded in a non-conductive bridging layer, wherein the lateral conductive interconnect provides electrical communication between the first plurality of stacks. In some embodiments, planarizing the protective layer exposes the contact features of the plurality of stacks. In some embodiments, each stack comprises at least a first die bonded to a second die. In some embodiments, the method may further include bonding the second plurality of stacks to a non-conductive bridging layer. In some embodiments, each stack of the second plurality of stacks is configured in electrical communication with a respective stack of the first plurality of stacks. In some embodiments, a non-conductive bridging element is directly bonded to the second plurality of stacks. In some embodiments, the bridging element is directly bonded to the non-conductive bridging layer. In some embodiments, depositing the protective layer further includes forming a cavity between the first stack and the second stack. In some embodiments, the non-conductive bridging layer further includes test pads configured to be in electrical communication with the first plurality of stacks.

[0009] In another embodiment, the bonded structure may include a carrier and a first die stack including a first top die and a first bottom die, wherein the first bottom die of the first die stack is bonded to the carrier, and the bonded structure may further include a bridging layer including a non-conductive layer and a conductive interconnect, wherein the bridging layer is attached to the first top die of the first die stack, and the bonded structure further includes a second die stack including a second bottom die bonded (e.g., direct hybrid bonded) to an upper surface of the bridging layer, wherein the conductive interconnect of the bridging layer provides electrical communication between the first die stack and the second die stack.

[0010] In some embodiments, the bonded structure may further include a third die stack bonded to the carrier, with the bridging layer being deposited on a third top die of the third die stack.

[0011] In another embodiment, a bonded structure may include a carrier including a non-conductive layer and conductive features at least partially embedded in the non-conductive layer, and a first die stack including a first top die and a first bottom die, wherein the first top die and first bottom die of the first die stack each have a corresponding non-conductive layer and conductive features, respectively, and the first bottom die of the first die stack is bonded to the carrier, and the bonded structure may further include a bridging layer including the non-conductive layer and a conductive interconnect, the bridging layer being attached to the first top die of the first die stack, and the bonded structure may further include a second die stack including a second bottom die directly hybrid bonded to an upper surface of the bridging layer, and the conductive interconnect of the bridging layer provides electrical communication between the first die stack and the second die stack.

[0012] In some embodiments, the bonded structure may further include a third die stack bonded to the carrier, with the bridging layer disposed on a third top die of the third die stack. In some embodiments, the conductive interconnects of the bridging layer comprise printed wires. In some embodiments, the bonded structure may further include wire bonds connecting the first die stack and the second die stack.

[0013] For purposes of outlining the present disclosure and the advantages achieved over the prior art, certain objects and advantages of the present disclosure are described herein. Not all such objects and advantages may be achieved in any particular embodiment. Thus, for example, one skilled in the art will recognize that the present invention can be embodied or practiced in a way that achieves or optimizes one advantage or group of advantages taught herein without necessarily achieving other objects and advantages that may be taught or suggested herein.

[0014] All of these embodiments are within the scope of the invention disclosed herein. These and other embodiments will be readily apparent to those skilled in the art from the following detailed description of the preferred embodiments, which proceeds with reference to the accompanying figures, but the invention is not limited to any particular preferred embodiment disclosed. [Brief explanation of the drawings]

[0015] [Figure 1A] 1 is a schematic diagram of a microelectronic structure according to a conventional design; [Figure 1B] 1 is a schematic diagram of a microelectronic structure according to a conventional design; [Figure 2A] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2B] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2C] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2D]1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2E] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2F] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 2G] 1A-1D illustrate schematically an exemplary method for manufacturing a microelectronic device. [Figure 3A] 1A-1D illustrate a method of forming a microelectronic structure according to one embodiment. [Figure 3B] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3C] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3D] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3E] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3F] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3G] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 3H] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 4A] 1A-1D illustrate a method of forming a microelectronic structure according to one embodiment. [Figure 4B] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 4C] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 4D] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 4E] 10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. [Figure 4F]10A-10C illustrate a method of forming a microelectronic structure according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Various embodiments disclosed herein enable multiple arrays or stacks of singulated integrated device dies (e.g., semiconductor devices, integrated circuit devices, etc.) to be attached to a carrier (e.g., a package substrate, a wafer, another integrated device die, a substrate, etc.) by direct bonding and to be in electrical communication with one another. Forming multiple stacks (e.g., arrays) of direct-bonded dies on a carrier can induce significant stress in the carrier material. Stress in the carrier material can reduce device planarity and adversely affect device yield during downstream production steps. Furthermore, electrical communication between individual dies in a first stack and individual dies in a second stack can be challenging because the only communication or communication path between the first stack and the second stack is through the carrier. Thus, communication between two dies in adjacent die stacks can experience delays or signal delays.

[0017] In some embodiments, one or more protective layers may be formed. Protective materials may be deposited on and around the die stack to reduce the stress the stack induces in the carrier material and improve carrier planarity. Additionally, various embodiments disclosed herein facilitate efficient electrical communication between individual dies in the stack through the use of bridging layers and / or bridging elements. Bridging layers and / or bridging elements may be fabricated on top of multiple stacks, allowing one stack to electrically communicate with another stack through the bridging layers or elements. In some embodiments, a bonded bridging die (e.g., a semiconductor device, an integrated circuit device, etc.) may electrically connect a first die stack to a second die stack. In some embodiments, a non-conductive (e.g., dielectric) bridging layer may be formed (e.g., deposited) and patterned with electrical contacts or traces to electrically connect multiple adjacent die stacks to one another.

[0018] Thus, in various embodiments, a first die may be bonded (e.g., using a hybrid direct bonding technique, such as DBI® technology used by Xperi, Inc. of San Jose, California) to a bonding surface of a carrier, e.g., a substrate (e.g., a wafer, printed circuit board, etc.). In some embodiments, a first stack of dies may be formed by direct bonding a series of dies on top of the first die. In some embodiments, each die of the stack is in electrical communication with every other die in the stack. Through-substrate vias (TSVs) may provide vertical electrical communication between vertically adjacent dies in the stack. In some embodiments, a second stack of dies may be bonded to the carrier laterally adjacent to the first stack of dies. As with the first stack of dies, each individual die in the second stack of dies may be in electrical communication with each other die in the second stack of dies. In various embodiments, one or more protective support materials may be applied to the first and second die stacks. In some embodiments, the support material may be planarized using a conventional polishing or etching process, such as a chemical mechanical polishing (CMP) process. In some embodiments, one or more bridging layers may be applied to the first and second die stacks. In some embodiments, electrical contact structures and / or traces may be formed on, in, and / or within the one or more bridging layers such that the top die in the first stack is in electrical communication with the top die in the second stack via the bridging layer.

[0019] Another advantage of forming bonded stack structures according to the disclosed embodiments is that efficient direct bonding can be used to fabricate larger and more complex 3D stack structures while maintaining low intra-carrier stress and reducing signal path lengths while optimizing production yield. After deposition of the bridging layer, in some embodiments, further stacks can be direct bonded on top of the bridging dielectric layer. In some embodiments, a bridging element (e.g., a bridging die) can additionally or alternatively be provided to bridge the topmost die of adjacent stacks. In some embodiments, further stacks bonded on top of the bridging dielectric layer or bridging die can be in electrical communication with the first and second die stacks via the bridging dielectric layer or bridging die.

[0020] 1A and 1B schematically illustrate a conventional bonded structure on a carrier (e.g., a wafer, a printed circuit board, etc.). Conventionally, a first stack of dies 101 (e.g., a semiconductor device, an integrated circuit device, etc.) is attached to a carrier 103 (e.g., a substrate, a wafer, another integrated device die, etc.) by a carrier bonding layer 115. In some configurations, the stack 101 may be attached with an adhesive, such as solder. In other configurations, the stack 101 may be directly hybrid bonded to the carrier 103 without an adhesive. In various embodiments, the carrier 103 may be a wafer, a singulated integrated device die, a semiconductor interposer, a reconfigurable element, etc. The carrier bonding layer 115 may have a plurality of electrically conductive (or conductive) contacts 117 at least partially embedded therein. Although illustrated as a single layer, the carrier bonding layer 115 may include one or more dielectric layers. A second stack of dies 105 may be attached to the carrier 103 laterally adjacent to the first die stack 101. In some configurations, the stack 101 may be attached with an adhesive, e.g., solder. In other configurations, the stack 105 may be direct hybrid bonded to the carrier 103 without an adhesive.

[0021] Both the first die stack 101 and the second die stack 105 may include multiple individual dies 107 bonded together. For example, in FIG. 1A , the first die stack 101 is comprised of five individual dies 107 bonded together. The first die 109 may have a front-side bonding layer 111 and a back-side bonding layer 113. Both the front-side bonding layer 111 and the back-side bonding layer 113 may be comprised of one or more dielectric layers, and both the front-side dielectric layer 111 and the back-side dielectric layer 113 may have a plurality of conductive contacts 117 at least partially embedded therein. A second die 119, comprised of the front-side bonding layer 111 and the back-side bonding layer 113, may be bonded to the first die 109, and may have a plurality of conductive contacts at least partially embedded in the layers 111, 113. Another die 107 may be bonded to the first die 109 and the second die 119 to form the first stack 101. A second stack 105 similar to the first stack may be formed in a laterally adjacent position on the carrier 103. Each die 107 of the second stack 105 may have a front-side bonding layer 111 and a back-side bonding layer 113 and a plurality of conductive contacts 117 that may be partially embedded in the front-side bonding layer 111 and the back-side bonding layer 113. Like the first stack 101, the second stack 105 may include a stack of dies 107, where a first die 119 of the second stack 105 is attached (e.g., direct hybrid bonded) to the carrier 103, a second die 121 of the second stack 105 is bonded (e.g., direct hybrid bonded) to the first die 119, and so on. This stacked bonding configuration may be repeated until the desired number of dies are bonded to the second stack 105. Each die (or in some configurations, the cache die except for the uppermost (top) die) may have through-substrate vias (TSVs) (not shown) to provide vertical electrical communication between vertically adjacent dies.As the number of dies in the first stack 101 and the second stack 105 increases, the stress on the carrier 103 also increases, and the communication path length between the dies in the first stack 101 and the second stack 105 also increases.

[0022] 1B schematically illustrates a first stack 101 and a second stack 105 bonded to a carrier 103. In the configuration of FIG. 1B, stresses on the carrier 103 may be large, which may result in significant bending (unflatness) of the carrier 103. Furthermore, the signal path between the top die (e.g., the 15th die 125) of the second stack 105 and the top die (e.g., the 15th die 127) of the first stack 101 is long. For example, for a 50 μm thick direct-bonded die, the electrical path between the 15th die 127 of the first stack 101 and the bonding layer 115 of the carrier 105 is approximately 700 μm (50×14 dies). From the above, the electrical path between the fifteenth die 127 of the first stack 101 and the fifteenth die 125 of the second stack 105 is greater than 1400 μm, taking into account lateral traces in the carrier's bonding layer. The long signal path 123 can cause significant delays and slow signal processing when communicating between distal dies, e.g., dies 125 and 127. Furthermore, electrical communication between the second stack 105 and the first stack 101 travels along the signal path 123 through the carrier 103. Furthermore, no lateral support exists to support the first stack 101 and the second stack 105. This lack of lateral support can reduce downstream yields of end products using devices with large first stacks 101 and second stacks 105.

[0023] 2A-2G schematically illustrate an exemplary process for forming multiple stacks of dies (e.g., semiconductor devices, integrated circuit devices, etc.) on a carrier 201 (e.g., a wafer, substrate, die, etc.). FIG. 2A schematically illustrates the carrier 201 having a first stack 201 and a second stack 211, each including one die 207, 213. In some embodiments, the carrier 201 includes a bonding layer 203 (e.g., one or more dielectric layers) having conductive contacts 205 at least partially embedded therein. While schematically illustrated as a single layer, it should be understood that the bonding layer 203 may be comprised of multiple dielectric layers. A plurality of electrical contacts 205 may be at least partially embedded in the bonding layer 203. The first die 207 of the first stack 209 and the first die 213 of the second stack 211 may be direct hybrid bonded to the carrier 201. The first die 207 of the first stack 209 and the first die 213 of the second stack 211 may have a front-side bonding layer 215 and a back-side bonding layer 217. Both the front-side bonding layer 215 and the back-side bonding layer 217 may include one or more dielectric layers or sublayers. A plurality of conductive contacts 205 may be at least partially embedded in both the front-side bonding layer 215 and the back-side bonding layer 217. Although not shown, a plurality of through-substrate vias (TSVs) may provide electrical communication between the contacts 205 of the front-side bonding layer 215 and the contacts 205 of the back-side bonding layer 217.

[0024] 2B , a pair of second dies 219, 221 (e.g., semiconductor devices, integrated devices, etc.) may be direct hybrid bonded to the first die 207 of the first stack 209 and the first die 213 of the second stack 211, respectively. In some embodiments, the pair of second dies 209, 221 each have a front-side bonding layer 223 and a back-side bonding layer 225. In some embodiments, one or both of the front-side bonding layer 223 and the back-side bonding layer 225 may be a dielectric layer having the conductive contacts 205 at least partially embedded therein. While shown as a single layer 223, 225, it should be understood that the layer 223, 225 may include multiple dielectric layers or sublayers. The pair of second dies 219, 221 may be direct hybrid bonded to the pair of first dies 207, 213 by the bonding layers 217, 223, respectively. Although not shown, a plurality of through substrate vias (TSVs) may provide electrical communication between contacts 205 of front-side bonding layer 223 and contacts 225 of back-side bonding layer 225 .

[0025] 2C , a pair of third dies 227, 229 may be directly bonded to the pair of second dies 219, 221, respectively. In some embodiments, the pair of third dies 227, 229 each have a front-side bonding layer 231 and a back-side bonding layer 223. In some embodiments, one or both of the front-side bonding layer 231 and the back-side bonding layer 233 may be a dielectric layer having the conductive contacts 205 at least partially embedded therein. While shown as a single layer 231, 233, it should be understood that the layers 231, 235 may include multiple dielectric layers. In some embodiments, the plurality of conductive contacts 205 may be at least partially embedded in one or both of the front-side bonding layer 231 and the back-side bonding layer 233. The front-side bonding layer 231 of the pair of third dies 227, 229 may be bonded to the back-side bonding layer 225 of the pair of second dies 219, 221, respectively. Although not shown, a plurality of through-substrate vias (TSVs) may provide electrical communication between the contacts 205 of the front-side bonding layer 231 and the contacts 205 of the back-side bonding layer 233.

[0026] Additional paired dies 241, 243 may be added to the stack in a manner similar to that shown in Figures 2A-2C. The additional dies 241, 243 may be bonded to the dies in the first stack 209 and the second stack 211. Any suitable number of dies may be provided in each stack 209, 211. Each stack 201, 211 may contain the same or a different number of stacked dies. The more dies 241, 243 that may be bonded to the first stack 209 and the second stack 211, the longer the electrical communication paths 244 (e.g., signal paths) between the die 245 in the first stack 209 and the die 247 in the second stack 211. Longer electrical communication paths 244 may result in slower inter-stack processing speeds. Furthermore, because the first stack 209 can only communicate with the second stack 211 through the carrier 201, signal paths remain long, and signal speeds slow as more dies 241, 243 are added to the first stack 209 and second stack 211. For example, the top die of the first stack 209 communicates with the top die of the second stack 211 via TSVs formed through the die located below it in the first stack 209, traces provided in the carrier 201, and TSVs formed through the die located below it in the second stack 211. The long signal paths 244 between the two top dies (and between the other dies in the stacks 209, 211) introduce lags and delays that can degrade electrical performance.

[0027] 2E, a protective layer 245 may be deposited on and around the first stack 209 and the second stack 211, as well as on the exposed portions of the carrier dielectric layer 203. The protective layer 245 may include a coating or molding compound that provides some lateral support to the first stack 209 and the second stack 211 during singulation or planarization. For example, the protective layer 245 may be comprised of an organic polymer, such as an epoxy. In other embodiments, the protective layer 245 may be comprised of one or more inorganic dielectrics (e.g., silicon oxide). Additionally, in some embodiments, the protective layer 245 may be comprised of a stack of multiple layers (e.g., inorganic and organic dielectric layers).

[0028] 2F, the first stack 209 and the second stack 211 may be singulated. During singulation, the protective layer 245 may provide some lateral support and protection to the first stack 209 and the second stack 211. However, due to the stresses that the first stack 209 and the second stack 211 create in the carrier 201, the carrier 201 may be subjected to significant stresses during singulation, which may result in cracking and reduced yield.

[0029] 2G, singulated module 250 can be made from multiple stacked dies. The module may consist of a single stack of die 252 or multiple stacks of die 254 mounted (e.g., bonded) to carrier 201. In module 250 containing multiple stacks of die 254, all communication between adjacent stacks of die 252 occurs through carrier 201. Furthermore, because there is little or no lateral support between the multiple stacks of die 254, carrier 201 may deform or develop defects, such as cracks, due to stresses resulting from the multiple stacks of die 254. Deformation of carrier 201 may reduce the efficiency and yield of devices fabricated using module 250 containing multiple stacks of die 252 or 254.

[0030] Figures 3A-3H illustrate a method of forming a microelectronic structure according to one embodiment. Figure 3A illustrates a pair of stacks 301, 303, each of which comprises multiple bonded dies 305 bonded (e.g., direct hybrid bonded) to a carrier 307. Unless otherwise noted, the embodiment of Figure 3A and the method of fabricating Figure 3A may be the same as or generally similar to the same components and structures of Figures 2A-2D. For example, the steps for fabricating the structure of Figure 3A may be the same as or substantially similar to the steps described above in connection with Figures 2A-2D.

[0031] 3B shows a first protective layer 309 disposed on the stacks 301 and 303. The first protective layer 309 may be disposed (e.g., deposited) on the carrier 307, the first stack 301, and the second stack 303. Depositing the first protective layer 309 may form an empty cavity 310 (e.g., no material or no protective layer 310) between the first stack 301 and the second stack 303. The first protective layer 309 may be made of a material with a low thermal expansion coefficient. The first protective layer 309 may be made of an organic or inorganic non-conductive material. In some embodiments, the first protective layer 309 may be made of a silicon-containing dielectric layer, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, or a silicate. In some embodiments, the first protective layer 309 may be composed of multiple layers of different dielectrics. For example, a nitrogen-containing dielectric layer may be coated on the surfaces of the stacked dies 301 and 303 and the exposed bonding surface of the carrier 307. An oxygen-containing dielectric layer may be coated on the nitrogen-containing dielectric layer. In some embodiments, the first protective layer may include a particulate composite material. Depending on the nature of the first protective material 309, the exposed surfaces of the stacked dies 301 and 303 and the carrier may be treated with a nitrogen-containing plasma prior to coating the first protective layer 309. In some embodiments, for example, the first protective layer 309 may include an encapsulant or molding compound, such as a non-conductive epoxy. In some embodiments, using a material with a low thermal expansion coefficient may be advantageous to reduce stress on the carrier 307. In some embodiments, the first protective layer may have a coefficient of thermal expansion of less than 20 ppm / ° C., less than 15 ppm / ° C., or less than 10 ppm / ° C. In some embodiments, the first protective layer 309 may be comprised of a porous material, or the first protective layer 309 may be comprised partially of a porous material. In some embodiments, the substrate of the top die of the stack 301, 303 may have embedded through-substrate vias (TSVs) (not shown).In this case, portions of the top die substrate may be selectively removed to expose the protruding TSVs along with their encapsulating liners. A first protective layer 309 may be formed on the exposed surface of the top die substrate and the top surface of the carrier 307. In some embodiments, upon selective removal of portions of the top die substrate, a temporary protective layer may be formed on the exposed top surface of the carrier. After formation of the protruding TSVs, the carrier and bonded die stack 301, 303 may be cleaned to remove undesired defect-forming material and the temporary protective layer protecting the carrier surface. The cleaned surface may then be coated with the first protective layer 309.

[0032] During operation, the first stack 301 and the second stack 303 may generate heat. Due to the low thermal expansion coefficient of the first protective layer 309, the heat generated by the first stack 301 and the second stack 303 (or the devices in the carrier 307) does not impose as much stress on the carrier 307 or the stacked devices 301, 303 as it would on the similar structures shown in FIGS. 2A-2D . This reduced stress provided by the low thermal expansion coefficient can also reduce the effects of heat or pressure applied during downstream processing steps (e.g., deposition of another layer, chemical mechanical polishing (CMP), etc.). The first protective layer 309 can provide lateral support for the stacks 301, 303. In some embodiments, the lateral support of the stacks 301, 303 can prevent the stacks 301, 303 from being damaged during subsequent processing steps, such as planarization or etching.

[0033] FIG. 3C illustrates planarizing the first protective layer 309. Chemical mechanical polishing (CMP) or other suitable methods can be used to planarize the first protective layer 309. The planarization step can include polishing the first protective layer 309 deposited on the backside bonding surface of the top die of the stack 301, 303 to expose or form a flat, smooth bonding surface and recessed conductive pads. In other embodiments, the planarization process can polish away portions of the first protective layer 309, thereby forming a residual flat, smooth layer of the first protective layer on the bonding surface of the top die of the stack 301, 303. In some embodiments having recessed protruding TSVs in the protective layer 309, as described above, planarizing the first protective layer 309 can remove portions of the first protective layer 302 and portions of the protruding TSVs to expose the conductive layer within the TSVs. The first protective layer 309 can provide lateral support to the stacks 301, 303 so that planarization of the first protective layer 309 does not impair or adversely affect the functionality of the stacks 301, 303 and carrier 307.

[0034] FIG. 3D illustrates the deposition of the second protective layer 311. The second protective layer 311 may be made of a material with a low coefficient of thermal expansion, such as an inorganic dielectric. The second protective layer 311 may be made of a semiconductor-containing dielectric layer, such as a silicon-containing dielectric layer, including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. In some embodiments, the second protective layer 311 may be made of multiple layers of different dielectrics. For example, a nitrogen-containing dielectric layer may be coated on the surfaces of the stacked dies 301 and 303 and the exposed bonding surface of the carrier 307. An oxygen-containing dielectric layer may be coated on the nitrogen-containing dielectric layer. In some embodiments, the second protective layer may include a particulate composite material. Depending on the nature of the second protective material 311, the exposed surfaces of the first protective layer 309 on the stacked dies 301, 303 and the carrier 307 may be treated with a nitrogen-containing plasma prior to coating with the second protective layer 311. The second protective layer 311 may be provided (e.g., deposited) on and around the pair of stacks 301, 303 and the first protective layer 309. The second protective layer 311 may provide additional lateral support to the stacks 310, 303 and reduce stress in the carrier in a manner similar to the first protective layer 309. The second protective layer 311 may also fill voids (e.g., empty vertical spaces) between the first stack 301 and the second stack 303. The second protective layer 311 may include an organic or inorganic non-conductive material. In some embodiments, for example, the second protective layer 311 may include an encapsulant or molding compound, such as a non-conductive epoxy.

[0035] 3E illustrates how the second protective layer 311 may be planarized. Chemical mechanical polishing (CMP) and other suitable methods may be used to planarize the second protective layer 311. The second protective layer 311 may provide lateral support to the functional stacks 301, 303 so that planarization of the second protective layer 311 does not impair or adversely affect the functionality of the functional stacks 301, 303. In some embodiments, the second protective layer 311 may not be provided. In such embodiments, the first protective layer 309 may fill the gap 310 between the first and second stacked dies 301, 303 and may be suitable for subsequent processing operations after planarization of the layer 309.

[0036] FIG. 3F illustrates the deposition of a bridging layer 312, including a non-conductive bridge layer 313, on the backside of the first and second stacks 301, 303 and the first and second protective layers 309, 311. The non-conductive bridge layer 313 may comprise a non-conductive layer (e.g., a dielectric layer). Although illustrated as a single layer, the bridge layer 313 may comprise multiple dielectric layers or sublayers. In some embodiments, the non-conductive bridge layer 313 may comprise an inorganic dielectric, such as silicon oxide, silicon nitride, or the like. The bridge layer 313 may be a bridging layer deposited on both the first and second stacks 301, 303. Thus, the non-conductive bridge layer 313 may not constitute a separate element attached, stuck, or bonded to the stacks 301, 303. Alternatively, the non-conductive bridge layer 313 may be deposited on the top die 304, some portions of the first protective layer 309 (e.g., some portions of the first protective layer 309 arranged around each stack 301, 303), and some portions of the second protective layer 311 (e.g., some portions of the second protective layer 311 arranged between some portions of the first protective layer 309 between the stacks 301, 303).

[0037] 3G illustrates the formation of conductive structures 315 and conductive interconnect layer 314 within non-conductive bridge layer 313. In some embodiments, bridging layer 312 may comprise non-conductive bridge layer 313 with conductive interconnect layer 314. Conductive structures 315 may be at least partially patterned within non-conductive bridge layer 313, and these conductive structures may be in electrical communication with first stack 301 and second stack 303. Another electrical interconnect layer 314 may be patterned on non-conductive bridge layer 313 or may be at least partially patterned within non-conductive bridge layer 313. Electrical interconnect layer 314 may be configured to electrically connect first stack 301 to second stack 303. In some embodiments, electrical connections between the first stack 301 and the second stack 303 through the electrical interconnect layer 314 provide two or more electrical communication paths 317 between the dies 319 in adjacent stacks 301, 303. In some embodiments, the dies 319 in the second stack 303 can communicate with the dies 319 in the first stack 301 either through the carrier 307 or through the electrical interconnect layer 314. For example, some dies 319 (e.g., dies in the upper portions of the stacks 301, 303) can communicate with each other through TSVs in their respective stacks 301, 303 and the interconnect layer 314. Other dies 319 (e.g., dies in the lower portions of the stacks 301, 303) can communicate with each other through TSVs in their respective stacks 301, 303 and traces (not shown) in the carrier 307. In some embodiments, signal speeds can be increased and energy consumption can be reduced by providing more than one electrical communication path 317 from the second stack 303 to the first stack 301. It should be recognized that while two adjacent stacks 301, 303 are shown in Figures 3A-3G, in some embodiments, three or more adjacent stacks 301, 303 can be provided on the carrier 307.For example, two, three, four, five, or more die stacks may be provided on the carrier, at least partially encapsulated by protective layers 309, 311 and electrically connected by bridging layers 312. In some embodiments, the bridging layer may comprise a planarizing non-conductive layer 309, 311 that fills the gap 310 between the first conductive die stack 301 and the second conductive die stack 303. In this embodiment, the conductive structures 315 and the conductive interconnect layer 314 may be formed in the non-conductive bridge layer 309 or 311. The conductive structures 315 may be at least partially patterned in the non-conductive bridge layer 309 or 311, and these conductive structures may be in electrical communication with the first stack 301 and the second stack 303. A separate electrical interconnect layer 314 may be patterned on the non-conductive bridge layer 309 or 311 or may be at least partially patterned in the non-conductive bridge layer 309 or 311.

[0038] In some embodiments, instead of using a deposited conductive interconnect layer 314, wire bonds may be used to form bridges, thereby electrically connecting each conductive structure 315 to adjacent die stacks. In some embodiments, the conductive interconnect layer 314 may be composed of printed conductive nanometal particles. In some embodiments, the printed (e.g., deposited) conductive interconnect layer 314 may be composed of silver nanoparticles. After the formation of the printed (e.g., deposited) circuit, the nanoparticles of the circuit may be densified by heat treatment, for example, in an oven, or by rapid thermal annealing lamps as in RTP, or by laser annealing. In some embodiments, the printed circuit may be densified in a microwave oven, preferably at temperatures below 180° C., which are commonly used oven processing temperatures. In some embodiments, the electrical resistivity of the printed conductive interconnect layer 314 may be less than 5 μΩ cm, less than 4 μΩ cm, or less than 3 μΩ cm.

[0039] 3H illustrates bonding of the third stack 321 and the fourth stack 323, which may be formed on top of the interconnect layer 314 or the bridging layer 312. Like the first stack 301 and the second stack 303, the third stack 321 and the fourth stack 323 may be formed by bonding (e.g., direct hybrid bonding) the dies 325 to each other as described above. While both the third stack 321 and the fourth stack 323 are illustrated as consisting of five dies 325, it should be understood that both the third stack 321 and the fourth stack 323 may consist of six or more dies 325 or four or fewer dies 325. In some embodiments, the non-conductive bridge layer 309, 311, or 314 may have test pads 431, as shown in FIG. 4F, for testing electrical yield, connectivity, electrical resistance, and other desired electrical functionality between, for example, the various dies and stacks (including the circuitry in carrier 307) of FIG. 3H. Electrical testing may be performed to characterize device yield and known good die prior to singulation. In some embodiments, the structure shown in FIG. 3H may be singulated into multiple devices as described above.

[0040] 4A-4F illustrate another embodiment that enables the formation of a 3D stack of stacks 403 with multiple electrical communication routes. Unless otherwise specified, the components in FIGS. 4A-4F may be substantially similar to the components in FIGS. 3A-3H. For example, as described above, as shown in FIG. 4A, a carrier 401 (e.g., a wafer, substrate, etc.) may have multiple stacks 403 bonded to a surface of the carrier 401. As described above, a first protective layer 405 may be deposited on and around the multiple stacks 403. The first protective layer 405 may be planarized, and a second protective layer 407 may be deposited on the first protective layer 405, if desired. As described above, in some embodiments, the second protective layer 407 may be planarized. A bridging layer 410 may be formed on top of the plurality of stacks 403 and the first and second protective layers 405 and 407, or on the first planarizing protective layer 405. The bridging layer 410 may include a non-conductive bridging layer 409 (e.g., a dielectric layer) and a plurality of electrical contacts or contact features 412. In other embodiments, a portion of the first protective layer 405 may serve as the bridging layer 410 (e.g., a portion of the protective layer 405 may remain deposited on the stack and patterned with a conductor). The non-conductive bridging layer 409 may include one or multiple dielectric layers or sublayers. As described above, the electrical interconnect structure 411 may be patterned on or at least partially embedded in the non-conductive bridging layer 409. The electrical interconnect structure 411 may include a plurality of electrical vias and traces and may be configured to electrically connect the plurality of stacks 403 together. Unlike in Figure 3H, a bridging die 413 may be bonded (e.g., direct hybrid bonded) to the dielectric bridging layer 409. In such an embodiment, the bridging layer 410 may serve as a bonding layer that may be pre-processed for direct bonding as described herein.In some embodiments, the bonding die 413 may be direct hybrid bonded to the bonding surface of the bridging layer 410. In other embodiments, the bridging die 413 may be attached to the bridging layer 410 with an adhesive (e.g., with solder). The bridging die 413 may comprise a semiconductor device, wafer, or other semiconductor device or element. In some embodiments, the bridging die 413 has a bonding layer 415, which may include one or more dielectric layers or sublayers. In some embodiments, the bonding layer 415 may be deposited on the bridging layer 410 and directly bonded to a corresponding bonding surface or layer of the die 413. In some embodiments, the bonding layer 415 may be formed on the die 413 and then directly bonded to the bridging layer 410. A series of electrical contact structures 417 may be at least partially patterned on or within the bonding layer 415. The bridging die 413 can provide additional support to the plurality of stacks 403 and can add additional desired functionality to the 3D microstructure 400. The bridging die 411 can be in electrical communication or contact with the plurality of stacks 403 as well as the carrier 401.

[0041] As shown in FIG. 4B , in some embodiments, a carrier 401 may have a plurality of stacks 403 bonded to a surface of the carrier 401. As described above, a first protective layer 405 may be deposited on and around the plurality of stacks 403. The first protective layer 405 may be planarized, and a second protective layer 407 may be deposited on the first protective layer 405, if desired. As described above, in some embodiments, the second protective layer 407 may be planarized. A bridging element 413 may be bonded to the plurality of stacks 403. The bridging element 413 (e.g., a wafer), semiconductor element, integrated circuit device, etc. may have a bonding layer 415. The bonding layer 415 may include one or more dielectric layers or sublayers. A plurality of contact features 416 may be at least partially embedded within the bonding layer 415. Unlike in FIG. 4A, in FIG. 4B the bridging element 413 may allow electrical communication between the multiple stacks 403 via conductive features in the bonding layer of the bridging element 413 .

[0042] As shown in FIG. 4C, a structure such as that described in FIG. 3H may be provided according to the method described above. After fabricating a structure such as that described in FIG. 3H, a second plurality of stacks 417, each having one or more dies 419, may be bonded on top of the bridging layer 410. The bridging layer 410 may include a non-conductive bonding layer 409 (e.g., a dielectric layer) and a plurality of contact features 412. A bridging die 413 having a bonding layer 415 may be bonded (e.g., direct hybrid bonded) to the second plurality of stacks 417. While illustrated as a single layer, the bonding layer 415 may include one or more dielectric layers or sublayers. A contact structure 421 may be partially patterned on or in the bonding layer 415. The first plurality of stacks 403 may be in electrical communication with each other by the dielectric bridging layer 409 or the carrier 401. The second plurality of stacks 417 may be in electrical communication with each other through a dielectric bridging layer 409 and / or a bridging die 413. The second plurality of stacks 417 may be in electrical communication with the first plurality of stacks through a dielectric bridging layer 409. As shown in Figure 4C, the bridging die 413 may fill gaps 418 between adjacent stacks 417.

[0043] As shown in FIG. 4D , in some embodiments, a microstructure similar to that of FIG. 4B can be prepared using substantially the same methods and components. However, unlike FIG. 4D , after bonding the plurality of stacks 403 to the carrier 401, a first protective layer 405 can be deposited on and over the plurality of stacks 403 and the carrier 401. The first protective layer 405 can be planarized using CMP or another suitable method, as described above. After planarizing the protective layer 405, a bridging bonding layer can be deposited on the plurality of stacks 403 and the first protective layer 405, but in this case, no second protective layer is deposited. Depositing the bridging bonding layer 409 can form a cavity 423 between the plurality of stacks 403. The cavity 423, or inner die cavity, can further enhance the flexibility of the carrier 401. The cavities 423 allow the microstructure to move slightly to relieve stresses that build up between the stacks 403 and on the carrier 401. In some embodiments, the bridging bonding layer may be omitted or may be fabricated on the surface of the bridging die 413. The bridging die 413 may be bonded onto the dies 401, 403 to allow communication between the bonded dies and the entire carrier 403.

[0044] As shown in FIG. 4E , in some embodiments, a structure substantially similar to FIG. 3A with substantially the same components can be fabricated. The structure includes a carrier 401 and multiple dies 403. After bonding the multiple die stack 403, a first protective layer 409 can be deposited on and around the die stack 403. Unlike FIG. 3A , where the first protective layer 409 is then covered with a second protective layer, in FIG. 4E , a second protective layer is not provided. Instead, in FIG. 4E , a bridging layer 410 made of the same material as the first protective layer 409 can be provided on the protective layer 409. The bridging layer 410 can have multiple contact structures 425 patterned on or within the bridging layer 410. Similarly, a bridging interconnect structure 411 can be at least partially formed within the bridging layer 410. In some embodiments, the redistribution layer or contact structure can be made of copper. In some embodiments, multiple stacks 403 may be in electrical communication with other stacks via bridging interconnect structures 411 or carriers 401 .

[0045] As shown in FIG. 4F, in some embodiments, a structure similar to that of FIG. 4C is provided. As described above, a first plurality of stacks 403 may be bonded (e.g., direct hybrid bonded) to a carrier 401. A first protective layer 405 may be deposited on and around the plurality of stacks 403. In some embodiments, the first protective layer 405 may be planarized. A second protective layer 407 may then be deposited on the first protective layer 405. The second protective layer 407 may be planarized, and a bridging bonding layer 409 may be bonded to the plurality of stacks 403. In some embodiments, the first protective layer 405, the second protective layer 407, and the bridging layer 409 may be composed of the same dielectric material or may be composed of different dielectric materials. In some embodiments, the first or second protective layer may include a bridging layer. In this case, the second plurality of die stacks 419 may be bonded to the bridging bonding layer 409, and a bridging die 413 may be bonded to the second plurality of die stacks 419. However, unlike in Figure 4C, in Figure 4F test pad structures 431 may be patterned in the bridging bonding layer 419 and electrically connected to the electrical interconnect structures 411 and both the first plurality of die stacks 403 and the second plurality of die stacks 419, as well as the carrier 401. The test pad structures 413 allow manual or automated probes to test the functionality of any of the first plurality of die stacks 403, the second plurality of die stacks 419, the carrier 401, or the bridging die 413.

[0046] In some embodiments, the stacked structure of FIG. 4F may be encapsulated and the encapsulation may be planarized. The planarized surface may be attached to another carrier (not shown) to expose the backside of carrier 401. The backside of the carrier may be prepared for bonding to another substrate, such as bridging layer 409 of the substrate shown in FIG. 4E. The resulting structure may have two or more bonding layers. Bridging layer 409 may serve as an interposer to interconnect arrays of stacked dies on both sides of bridging layer 409. Methods for preparing the backside of carrier 401 include thinning, polishing, and exposing embedded conductors within carrier 401. In some embodiments, a flat, planar bonding surface with embedded conductors may be formed on the backside of carrier 401. In some embodiments, the backside of carrier 401 may comprise a solderable mass or alloy mass. Similarly, solderable or alloy masses may be provided as conductive features on the bridging layer 409 depending on design parameters.

[0047] Direct bonding example Various embodiments disclosed herein relate to direct-bonded structures in which two elements can be directly bonded to each other without an intervening adhesive. A direct hybrid bonded structure has two elements that can be directly bonded to each other without an intervening adhesive. Two or more semiconductor elements (e.g., integrated device dies, wafers, etc.) can be stacked or bonded to each other to form a bonded structure. Conductive features of a first element can be electrically connected to corresponding conductive features of a second element. Any suitable number of elements can be stacked within the bonded structure. For example, a third element can be stacked on the second element, a fourth element can be stacked on the third element, etc. Additionally or alternatively, one or more additional elements can be stacked laterally adjacent to each other along the first element. In some embodiments, the laterally stacked additional element can be half the size of the second element.

[0048] In some embodiments, the elements are directly bonded to one another without adhesive. In various embodiments, a non-conductive material or dielectric can serve as the first bonding layer of a first element, which can be directly bonded, without adhesive, to a corresponding non-conductive field region that serves as the second bonding layer of a second element. The non-conductive bonding layers can be applied to the respective front surfaces (front sides) of the devices. Active devices and / or circuitry can be patterned and / or otherwise provided within or on the device portions. The active devices and / or circuitry can be provided at or near the front surface of the device portion and / or at or near the opposite back surface of the device portion. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive bonding layer of the first element can be directly bonded to the corresponding non-conductive bonding layer of the second element using dielectric-dielectric bonding techniques. For example, non-conductive or dielectric-dielectric bonds can be formed without adhesives using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of which are incorporated herein by reference for all purposes. It should be appreciated that in various embodiments, the conductive bonding layer may be comprised of a non-conductive material, such as a dielectric, e.g., silicon oxide, or an undoped semiconductor material, e.g., undoped silicon. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, e.g., silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, e.g., silicon carbide, silicon oxycarbonitride, low-K dielectrics, SICOH dielectrics, silicon carbonitride, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content.

[0049] In various embodiments, direct hybrid bonds can be formed without an intervening adhesive. For example, non-conductive bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to plasma and / or etching agents to activate these surfaces. In some embodiments, the surfaces can be terminated with species after or during activation (e.g., during the plasma and / or etching process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces, and the termination process can provide additional chemical species at the bonding surfaces that improve bonding energy during direct bonding. In some embodiments, activation and termination are performed in the same step (e.g., using a plasma to both activate and terminate the surfaces). In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. Additionally, in some embodiments, the bonding surface may be exposed to a fluorine-containing plasma. Additionally, in some embodiments, the bonding surface may be exposed to fluorine. For example, one or more fluorine peaks may be present near the layers and / or bonding interface. Thus, in a direct-bonded structure, the bonding interface between two non-conductive materials (e.g., bonding layers) may comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface. Additional examples of activation and / or termination treatments can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference in its entirety and incorporated herein for all purposes.

[0050] In various embodiments, the conductive contact pads of a first component may also be directly bonded to corresponding conductive contact pads of a second component. For example, hybrid bonding techniques may be used to provide conductor-to-conductor direct bonds along a bonding interface that includes covalently direct-bonded non-conductive-non-conductive (dielectric-dielectric) surfaces that have been pretreated as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and dielectric-to-dielectric hybrid bonds may be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference in its entirety for all purposes.

[0051] For example, non-conductive (e.g., dielectric) bonding surfaces (e.g., inorganic dielectric surfaces) can be pretreated as described above and then directly bonded to one another without an intervening adhesive. Conductive contact features (e.g., contact pads that can be at least partially surrounded by a non-conductive dielectric field region in the bonding layer) can also be directly bonded to one another without an intervening adhesive. In various embodiments, the conductive contact features can comprise separate pads at least partially embedded within a non-conductive field region. In some embodiments, the conductive contact features can comprise the exposed contact surface of a through-substrate via (TSV). In some embodiments, the conductive contact features can each be recessed below the outer (e.g., upper) surface of the dielectric field region or non-conductive bonding layer, e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, or can be recessed within a range of, e.g., 2 nm to 20 nm, or 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses in the opposing elements may be sized so that the overall gap between the opposing contact pads is less than 15 nm or less than 10 nm. The non-conductive bonding layers may be directly bonded together at room temperature, in some embodiments, without a contact agent, after which the bonded structure may be annealed. During annealing, the conductive features may expand and contact each other, thereby forming a metal-to-metal direct bond. Beneficially, Direct Bond Interconnect (DBI®) technology, commercially available from Xperi, Inc. of San Jose, California, may be used to connect high density pads together across the direct bond interface (e.g., at small or fine pitches for regular arrays). In some embodiments, the pitch of the pads, e.g., conductive traces embedded within the bonding surface of one of the bonded elements, may be less than 40 microns, less than 10 microns, or even less than 2 microns.For some applications, the ratio of the pitch of the bond pads 106a, 106b to one of the bond pad dimensions (e.g., diameter) is less than 5, or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonded elements may be in the range of 0.3 microns to 20 microns, such as 0.3 microns to 3 microns. In various embodiments, the contact pads and / or traces may be made of copper, although other metals may be suitable.

[0052] Thus, in a direct bonding process, a first element can be directly bonded to a second element without an intervening adhesive. In some configurations, the first element can comprise a singulated element, such as a singulated integrated device die. In other configurations, as shown, the first element can comprise a carrier or substrate (e.g., a wafer) containing a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die. In other configurations, the second element can comprise a carrier or substrate (e.g., a wafer). The embodiments disclosed herein can be used with wafer-to-wafer, die-to-die, or die-to-wafer bonding techniques. In a wafer-to-wafer (W-W) process, two or more wafers can be directly bonded together (e.g., direct hybrid bonding) and then singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush with one another and may include indicia indicative of the singulation process (e.g., saw marks if a saw-based singulation process is used).

[0053] As described herein, a first element and a second element can be directly bonded to each other without adhesive, which differs from a vapor deposition process. In one application, the width of the first element in the bonded structure is approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure may differ from the width of the second element. Similarly, the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element. Thus, the first and second elements may comprise non-vapor-deposited elements. Furthermore, unlike vapor-deposited layers, direct-bonded structures may contain defect regions along the bond interface 118 where nanoscale voids (nanovoids) exist. Nanovoids may form due to activation of the bonding surface (e.g., exposure to plasma). As mentioned above, the bond interface may contain a concentration of material resulting from activation and / or a final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS). In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can replace OH groups on a hydrolyzed (OH-terminated) surface with NH molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond comprises a covalent bond, which is stronger than a van der Waals bond. The bonding layers 108a, 108b may also further have a polished surface that is planarized to a high degree of smoothness.

[0054] In various embodiments, metal-to-metal bonds between the contact pads may be bonded such that copper grains grow into each other across the bonding interface. In some embodiments, the copper may have grains oriented along the 111 crystal plane to enhance copper diffusion across the bond interface. The bonding interface may extend substantially all the way to at least a portion of the bonded contact pad, such that there is substantially no gap between the non-conductive bonding layers at or near the bonded contact pad. In some embodiments, a barrier layer may be provided under the contact pad (which may comprise, for example, copper). However, in other embodiments, there may not be a barrier layer under the conductive features, as described, for example, in U.S. Pat. No. 11,195,748, which is incorporated by reference in its entirety and incorporated herein by reference for all purposes.

[0055] Beneficially, the hybrid bonding techniques described herein enable very fine pitches between adjacent contact pads and / or small pad sizes. For example, in various embodiments, the pitch p (i.e., the edge-to-edge or center-to-center distance) between adjacent conductive features may be in the range of 0.5 to 50 microns, 0.75 to 25 microns, 1 to 25 microns, 1 to 10 microns, or 1 to 5 microns. Furthermore, the larger lateral dimension (e.g., pad diameter) may also be small (e.g., in the range of 0.25 to 30 microns, 0.25 to 5 microns, or 0.5 to 5 microns).

[0056] Unless the context clearly requires otherwise, throughout the specification and claims, terms such as "comprise," "comprising," "include," and "including" are to be construed in an inclusive sense, i.e., "including, but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as used generally herein, means two or more elements that are directly connected to each other or that are connected to each other by one or more intermediate elements. Similarly, the term "coupled," as used generally herein, means two or more elements that are directly connected to each other or that are connected to each other by one or more intermediate elements. Additionally, as used herein, the terms "herein," "above," "below," and words of similar import refer to this application as a whole, and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element may be directly located on or over the second element, such that the first and second elements are in direct contact, or the first element may be indirectly located on or over the second element, such that one or more elements are interposed between the first and second elements. Where the context permits, terms in the above Detailed Description using the singular or plural may also include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0057] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood differently within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions, and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are present in any required way for one or more embodiments.

[0058] While certain embodiments have been described, these embodiments are provided by way of example only and do not limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, while blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention, as defined by the appended claims and their equivalents, is intended to cover such forms or modifications as fall within the scope and spirit of the invention.

Claims

1. A bonded structure, Having a carrier, The system has a first plurality of die stacks, each die stack containing a plurality of dies, and each die stack among the first plurality of die stacks is bonded to the carrier. Furthermore, the first plurality of die stacks has a protective layer attached to at least a portion thereof, wherein the upper surface of the protective layer is coplanar with the upper surface of the uppermost die of the first plurality of die stacks and is adjacent to the first plurality of die stacks. Furthermore, it has a bridging layer comprising a non-conductive bridge layer and a lateral conductive interconnect, which is attached to the first plurality of die stacks without adhesive. The lateral conductive interconnect provides electrical communication between the first plurality of die stacks in the bonded structure.

2. The nonconductive bridge layer further comprises a plurality of contact feature portions that are at least partially embedded within it. The bonded structure according to claim 1, wherein the lateral conductive interconnect provides electrical communication between at least two of the plurality of contact feature portions.

3. The bonded structure according to claim 1, further comprising at least one die stack directly bonded to the bridging layer without adhesive.

4. The bonded structure according to claim 1, further comprising a plurality of second die stacks directly bonded to the bridging layer and a bridging element directly bonded to the plurality of second die stacks.

5. The bonded structure according to claim 4, further comprising at least one test pad at least partially embedded in the bridging layer, wherein the test pad is in electrical contact with the first plurality of die stacks and the second plurality of die stacks.

6. The bonded structure according to claim 1, further comprising a bridging element directly bonded to the bridging layer without adhesive.

7. The bonded structure according to claim 6, further comprising a cavity provided between a first die stack and a second die stack.

8. The bonded structure according to claim 1, wherein each die stack of the first plurality of die stacks is made by bonding a first die to a second die without adhesive.

9. The first nonconductive bonding layer of at least one die stack among the plurality of die stacks is directly bonded to the second nonconductive bonding layer of the carrier without an intervening adhesive. The bonded structure according to claim 1, wherein the first contact feature portion of at least one die stack among the plurality of die stacks is directly bonded to the second contact feature portion of the carrier without the intervening adhesive.

10. The bonded structure according to claim 1, wherein the material of the protective layer is the same as the material of the bridging layer.

11. A bonded structure, A first die stack including a first number of dies, A second die stack including a second set of dies, A protective layer provided around at least the lateral sides of the first and second die stacks and between the first die stack and the second die stack, the protective layer having an upper surface that is coplanar with the upper surface of the uppermost die of the first plurality of die stacks, A bonded structure comprising a first die stack, a second die stack, and a bridging layer bonded to the protective layer without adhesive, wherein the bridging layer provides electrical communication between at least one die of the first die stack and at least one die of the second die stack.

12. The bonded structure according to claim 11, wherein the first plurality of dies in the first die stack are directly hybrid bonded to one another.

13. The bonded structure according to claim 11, wherein the second plurality of dies in the second die stack are directly hybrid bonded to one another.

14. The bonded structure according to claim 11, wherein the first die stack and the second die stack are directly hybrid bonded to a carrier.

15. The bonded structure according to claim 11, wherein the first die stack and the second die stack are directly hybrid bonded to a bridging element.

16. The present invention further comprises a third die stack including a third plurality of dies, the third die stack being directly hybrid bonded to the bridging layer, The bonded structure according to claim 15, further comprising a fourth die stack including a fourth plurality of dies, wherein the fourth die stack is directly hybrid bonded to the bridging layer.

17. The bonded structure according to claim 16, further comprising a bridging element bonded to the third die stack and the fourth die stack.

18. The bonded structure according to claim 17, further comprising at least one test pad embedded in the bridging layer, wherein the test pad is configured to be in electrical contact with the first die stack, the second die stack, the third die stack, and the fourth die stack.

19. A method for forming a bonded structure, wherein the method is The process includes the step of directly bonding a first plurality of stacks to a carrier, wherein each stack of the first plurality of stacks includes at least one die in contact with the carrier. The step includes applying a protective layer to at least a portion of the plurality of stacks, The step includes flattening the protective layer, The process includes the step of forming a non-conductive bridge layer and a non-conductive bridging layer having a lateral conductive interconnect, The lateral conductive interconnect provides electrical communication between the first plurality of stacks.

20. The step further includes forming a first plurality of contact feature portions that are at least partially embedded in the nonconductive bridge layer, The method according to claim 19, wherein the lateral conductive interconnect provides electrical communication between at least two of the plurality of contact feature portions.

21. The method according to claim 19, wherein the contact feature portion of the plurality of stacks is exposed by flattening the protective layer.

22. The method according to claim 19, wherein each stack comprises at least a first die bonded to a second die.

23. The method according to claim 19, further comprising the step of bonding a second plurality of stacks to the nonconductive bridging layer.

24. The method according to claim 23, wherein each of the second plurality of stacks is configured to be in electrical contact with each of the first plurality of stacks.

25. The method according to claim 19, wherein a non-conductive bridging element is directly bonded to the second plurality of stacks.

26. The method according to claim 19, wherein the bridging element is directly bonded to the non-conductive bridging layer.

27. The method according to claim 19, wherein the step of applying the protective layer further includes the step of forming a cavity between the first stack and the second stack.

28. The method according to claim 19, wherein the nonconductive bridging layer further comprises a test pad configured to be in electrical contact with the first plurality of stacks.

29. A bonded structure, Having a carrier, It has a first die stack including a first top die and a first bottom die, the first bottom die of the first die stack being bonded to the carrier, It has a bridging layer including a non-conductive layer and a conductive interconnect, the bridging layer is adhered to the first top die of the first die stack, The second die stack includes a second bottom die that is directly hybrid bonded to the upper surface of the bridging layer, The conductive interconnect of the bridging layer provides electrical contact between the first die stack and the second die stack in the bonded structure.

30. The bonded structure according to claim 29, further comprising a third die stack bonded to the carrier, wherein the bridging layer is adhered to a third top die of the third die stack.

31. A bonded structure, A carrier comprising a non-conductive layer and a conductive feature portion at least partially embedded in the non-conductive layer, The present invention has a first die stack comprising a first top die and a first bottom die, wherein the first top die and the first bottom die of the first die stack each have a corresponding non-conductive layer and a conductive feature portion, and the first bottom die of the first die stack is bonded to the carrier. Furthermore, it has a protective layer that is on the same plane as the upper surface of the first top die and has an upper surface adjacent to the first die stack, It has a bridging layer including a non-conductive layer and a conductive interconnect, the bridging layer being adhered to the first top die of the first die stack without adhesive, The second die stack includes a second bottom die that is directly hybrid bonded to the upper surface of the bridging layer, The conductive interconnect of the bridging layer provides electrical contact between the first die stack and the second die stack in the bonded structure.

32. The bonded structure according to claim 31, further comprising a third die stack bonded to the carrier, wherein the bridging layer is adhered to a third top die of the third die stack.

33. The bonded structure according to claim 31, wherein the conductive interconnect of the bridging layer is made of printed wire.

34. The bonded structure according to claim 31, further comprising a wire bond connecting the first die stack and the second die stack.

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