Selective deposition of liner and barrier films to reduce resistance in semiconductor devices

Abstract

The semiconductor device includes a field effect transistor (FET) having a source / drain (S / D) structure and an interconnect structure in contact with the S / D structure. The interconnect structure has a barrier film on a surface of the interconnect structure that separates the interconnect structure from a material surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S / D structure. A second portion of the barrier film covers a second interface between the interconnect structure and a dielectric material adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film.

Description

[Technical Field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-Provisional Patent Application No. 17 / 882,821, filed August 8, 2022, the entire text of which is incorporated herein by reference.

[0002] The present disclosure generally describes embodiments relating to semiconductor devices and manufacturing processes. [Background technology]

[0003] The background information provided herein is intended to provide a general overview of the contents of the present disclosure. Works of the present inventors referenced in this background section, along with aspects described therein that would not otherwise be admitted as prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0004] Transistors, such as field-effect transistors (FETs), are fundamental elements of microelectronics and integrated circuits. Efforts are ongoing to scale down or shrink transistors and other semiconductor devices to increase density and improve processing performance. Traditionally, transistors are formed in one plane, with wiring / metallization formed above the plane of the active device. In recent years, three-dimensional (3D) processing has been developed that utilizes a vertical axis to improve transistor density. For example, a new device architecture known as a complementary FET (CFET) may include alternating stacked transistors. Summary of the Invention

[0005] Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a field effect transistor (FET) having a source / drain (S / D) structure and an interconnect structure in contact with the S / D structure. The interconnect structure has a barrier film on a surface of the interconnect structure that separates the interconnect structure from a material surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S / D structure. A second portion of the barrier film covers a second interface between the interconnect structure and a dielectric material adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier film.

[0006] In one embodiment, the second portion of the barrier film covers a surface of a via structure of the interconnect structure. The via structure can connect the interconnect structure to a power rail. In some examples, the first portion of the barrier and the second portion of the barrier are formed using the same material.

[0007] Aspects of the present disclosure further provide a method for manufacturing a semiconductor device, which may include forming a trench structure through a dielectric material to expose an S / D structure of a FET, selectively forming a first barrier film overlying a surface of a silicide layer of the exposed S / D structure to seal the exposed S / D structure, conformally forming a second barrier film on an interior surface of the trench structure, the second barrier film overlying the first barrier film, and filling a conductive material into the trench structure to form an interconnect structure for the S / D structure.

[0008] In one example, selectively forming the first barrier film may include performing a selective deposition process in which the deposition of the first barrier film covering the surface of the silicide layer of the exposed S / D structure is selective to the dielectric material surrounding the trench structure. In one example, the first barrier film is thicker than the second barrier film. In one example, the trench structure includes a via structure at the bottom of the trench structure, and the inner surface of the via structure is covered with the second barrier film but not the first barrier film. In one example, the via structure reaches a buried power rail.

[0009] In one example, the silicide layer of the exposed S / D structure includes a layer of titanium, titanium silicide, nickel, nickel silicide, platinum, platinum silicide, ruthenium, or ruthenium silicide. The dielectric material surrounding the trench structure includes one of silicon oxide, silicon nitride, or silicon carbonitride (SiCN). The semiconductor device is a complementary field effect transistor (CFET).

[0010] Aspects of the present disclosure may further provide another semiconductor device. The semiconductor device may include a first S / D structure of a first FET and a first interconnect structure in contact with the first S / D structure. The first S / D structure includes a silicide layer on a first portion of a surface of the first S / D structure. The silicide layer may contact an interface between the first S / D structure and the first interconnect structure. The first S / D structure includes a contact etch stop layer (CESL) on a second portion of a surface of the S / D structure. The CESL is not present on the first portion of the surface of the S / D structure.

[0011] In one example, the semiconductor device may further include a first buried power rail. The first interconnect structure includes a first via interconnect structure connecting the first interconnect structure to the first buried power rail. In one example, the semiconductor device may further include a second S / D structure of a second FET formed on the first FET and a second interconnect structure contacting the second S / D structure. The second interconnect structure includes a second via connection structure connecting the second interconnect structure to the second buried power rail. The second via interconnect structure contacts a CESL of the first S / D structure. In one example, the silicide layer includes a layer of titanium (Ti), and the CESL includes a layer of silicon nitride (SiN). In one example, the semiconductor device is a CFET device.

[0012] Aspects of the present disclosure provide a method for manufacturing a semiconductor device. The method may include forming a first S / D structure including epitaxy and a CESL covering the S / D epitaxy, forming a pre-metal deposition (PMD) to embed the first S / D structure, forming a local interconnect trench and a first via at a bottom of the local interconnect trench, where a portion of the CESL of the first S / D structure is exposed in the local interconnect trench, removing the portion of the CESL of the first S / D structure exposed in the local interconnect trench to expose the epitaxy of the first S / D structure, forming a silicide layer on the exposed epitaxy, and filling the local interconnect trench and the first via with a conductive material to form a first interconnect structure for the first S / D structure. The first interconnect structure may contact the silicide layer.

[0013] In one embodiment, the local interconnect trench and the first via are formed by performing a dual damascene process. In one embodiment, the first via connects the first interconnect structure to a first buried power rail. In one embodiment, the method further includes forming a second interconnect structure for a second S / D structure stacked above the first S / D. The second interconnect structure includes a second via connecting the second interconnect structure to a second buried power rail. The second via contacts the remaining CESL of the first S / D structure. In one embodiment, the silicide layer includes a Ti layer and the CESL includes a SiN layer.

[0014] Various embodiments of the present disclosure, presented by way of example only, will now be described in detail with reference to the following drawings, in which like numerals refer to like elements. It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Brief explanation of the drawings]

[0015] [Figure 1]1 illustrates the results of incorporating atomic layer deposition of a barrier metal into a complementary field effect transistor (CFET) device 100. [Figure 2] A CFET device 200 is shown as a result of the selective deposition process. [Figure 3] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. [Figure 4] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. [Figure 5] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. [Figure 6] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. [Figure 7] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. [Figure 8] 3 illustrates a self-aligned metallization process for forming interconnect structures within a CFET device 300. DETAILED DESCRIPTION OF THE INVENTION

[0016] In the following disclosure, many different embodiments or examples are provided that implement different features of the provided subject matter. To simplify the disclosure, specific examples of elements and configurations are described below. It should be understood that these are merely examples and are not intended to limit the invention. For example, in the following description, a step of forming a first feature over or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact with each other. Additionally, the present disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations being discussed.

[0017] Additionally, spatial terms such as "bottom," "lower," "below," "upper," and the like may be used herein to facilitate describing the relationship of one element or feature to another element or feature as shown in the figures. Spatial terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be reoriented (rotated 90 degrees or at other orientations) and the spatially related descriptors used herein may be interpreted accordingly.

[0018] As traditional scaling methods such as contact poly pitch (CPP) (or transistor pitch) and metal pitch (routing track) reduction are reaching their fundamental limits, techniques for monolithic and sequential transistor stacking of devices have been proposed to continue device scaling through integration into three dimensions. Some devices fabricated with these new methods are called complementary field effect transistor (CFET) devices.

[0019] In monolithic gate-on-gate stack integration, complementary devices are sequentially formed one on top of the other within a single monolithic wafer. For example, appropriate source and drain epitaxy can be formed, followed by silicide formation and local interconnect metallization. A replacement metal gate process is then performed, which can form common and / or split gates. In sequential gate stack integration, for example, a bottom device is formed through source and drain epitaxy, silicide formation, bottom device local interconnect metallization, and bottom device replacement metal gate integration. A new wafer containing, for example, the nanosheet stack for the top device can then be placed on top of the bottom device. The same processes as described for the bottom device can then be performed. For example, top source and drain epitaxy can be formed, silicide formation can be performed, top interconnect metallization can be performed, and finally, top replacement gate formation and connection can be performed to form an optional common gate.

[0020] From the device integration perspective, both monolithic and sequential approaches to 3D integration face challenges regarding thermal processing.

[0021] In existing device fabrication processes, such as FinFET, lateral gate-all-around, or nanosheet processes, integration flows can be configured so that processes requiring high temperatures are primarily performed at the front-end-of-line (FEOL). Such integration flows avoid damage to materials (e.g., silicides or gate work function metals (WFMs)) that have physical constraints (e.g., recrystallization or agglomeration) at these temperatures. Changes in the WFM during thermal processing can alter the device threshold voltage. Agglomeration of metals, such as silicides, can cause significant voids and physical damage to the film, potentially resulting in poor connections between the respective contacts and the interconnect metal. Furthermore, integration flows can be performed at high temperatures performed at the FEOL, minimizing the diffusion of materials into the metal (e.g., dopants in source and drain contacts).

[0022] As an example, a typical integration process for a FINFET device involves the following high thermal processing steps: (a) Annealing of flowable oxide films used in shallow trench isolation formation can be included. For example, annealing can be performed at temperatures above 1000°C. In some examples, nanosheet processing is performed. Processing temperatures can be reduced to below 900°C to prevent Ge diffusion from the SiGe / silicon lattice in the initial fin structure. (b) Pre-cleaning of silicon fins prior to source and drain epitaxy deposition, which can be performed at temperatures ranging from 700°C to 780°C. (c) Formation of NMOS source and drain using in-situ doped silicon, which can be performed over a temperature range of 600°C to 750°C. (d) Formation of PMOS source and drain using in-situ doped silicon germanium, which can be performed at temperatures ranging from 525°C to 650°C. (e) Reliability annealing of high-k films in high-k metal gate (HKMG) stacks to eliminate charge traps, which can be performed at temperatures ranging from 700°C to 780°C. (f) Source and drain dopant activation annealing when implants are used to dope or co-dope the source and drain epitaxy, which can typically be performed at temperatures in the range of 800-1000°C in sub-millisecond processing.

[0023] In a standard FINFET device integration process flow, the above-mentioned high temperature processes can be incorporated before the deposition of high temperature sensitive materials. For example, in a replacement metal gate (RMG) process, many of these higher temperature processes can be performed before the deposition of the work function metal.

[0024] Considerable industry efforts have been made to reduce many of these high-temperature processes to incorporate wrap-around contact (WAC) devices and ultimately move toward 3D devices. However, many of these steps involve significant tradeoffs with lowering the thermal processing temperature. Lowering the thermal processing temperature can potentially limit device performance. For example, reducing the epitaxial growth of in-situ doped source and drain contacts significantly reduces the dopant levels in the source and drain regions. Similarly, lowering the reliability annealing temperature can be performed in conjunction with high-pressure processes in the presence of hydrogen. However, the actual impact on device performance in scaled libraries is unclear.

[0025] For a monolithic CFET device, as an example, the device integration flow includes the following processing steps: (a) NMOS source and drain epitaxy growth at a temperature ranging from 600 to 700°C, (b) NMOS silicide formation, (c) post-metal anneal at a temperature ranging from 450 to 650°C, (d) silicon pre-clean at a temperature ranging from 750 to 800°C, (e) PMOS source and drain epitaxy growth at a temperature ranging from 550 to 650°C, (f) PMOS silicide formation, (g) reliability anneal at a temperature ranging from 700 to 780°C, (h) source and drain activation at a temperature ranging from 800 to 1100°C, (i) replacement metal gate work function metal deposition, and (j) MO post-metal anneal (PMA) at a temperature of 450°C. For a sequential CFET device, the overall process is similar, except that the RMG module is performed twice, once after each local interconnect to the contact is formed and metallized.

[0026] In the example monolithic and sequential CFET integration process described above, a bottom device silicide is formed around the bottom device source and drain contacts, followed by metallization with the formation of the lower local interconnect. This precedes the formation of the top source and drain epitaxy, which is also typically performed at high temperatures. To remove native oxide from the silicon or silicon germanium, the silicon pre-clean can be replaced by a room-temperature gas-phase etching process rather than a thermal process. The actual growth of the source and drain epitaxy, in some instances, still requires temperatures above 500°C. Furthermore, the epitaxy growth incorporates doping species such as boron or phosphorus, and therefore the saturation of the in-situ doped species depends on the epitaxy growth temperature. In some embodiments of the present disclosure, such an in-situ doped epitaxy process can occur at temperatures below the condensation temperature of the silicide, which is typically on the order of 700°C.

[0027] One of the constraints on the epitaxy growth temperature of the source and drain is the effect on the silicide and local interconnect metal present in the bottom device during the formation of the source and drain on the top device. Local interconnect metals such as ruthenium (Ru) and other high refractive index metals can withstand temperatures up to 700°C. Commonly used silicide materials such as titanium (Ti) and nickel-platinum will agglomerate at these high temperatures. This agglomeration of metal can be seen both through extreme changes in sheet resistance in experiments and through cross sections through a STEM.

[0028] In another experiment, a Si / Si configuration, i.e., P / Ti / TiN / Ru stack, was prepared in which 40 Å of titanium was deposited over 400 Å of phosphorus-doped silicon (atomic concentration of phosphorus 7e20 cm-3), along with a thin TiN film (formed from the nitridation of the titanium deposition) and 30 Å of ruthenium metal. No agglomeration was observed at low temperatures, such as 500 °C. However, energy dispersive X-ray spectroscopy (EDS) studies show that both silicon and phosphorus are incorporated into the local interconnect metal.

[0029] Diffusion of silicon and phosphorus into the local interconnect metal can have a significant impact on the contact and local interconnect resistance. A further concern is that excessive silicon incorporation into the local interconnect can severely damage the source and drain contacts, causing further contact resistance problems.

[0030] Several types of barrier materials can be used to mitigate the diffusion of silicon and dopants from the source and drain into the local interconnect metal. For example, barrier materials for this application can include conductive materials or metals such as titanium nitride (TiN) and tantalum (TaN). Additional experiments show that such barrier films (also called liner films) having a specific thickness, e.g., on the order of 20 Å to 30 Å, can mitigate the migration of silicon and phosphorus into the local interconnect metal at temperatures of about 500°C for specific annealing times. Depending on the requirements of a specific application, different barrier materials (other than TiN and TaN) can be used, and different film thicknesses (other than 20 Å to 30 Å) can be employed.

[0031] Generally, barrier materials such as TiN and TaN have low conductance compared to metals such as ruthenium or cobalt used in local interconnects. This poses a significant problem for devices, particularly monolithic and sequential CFET devices, because local interconnects can be formed with vias connecting the interconnects to buried power rails. Formation of local interconnects and vias can incorporate, for example, a process called dual damascene.

[0032] For example, a barrier metal (such as TiN) may be deposited after the formation of the silicide, positioned to minimize diffusion of silicon and dopants from the source and drain contacts into the interconnect metal. In some examples, a dual damascene process is used, which involves, for example, atomic layer deposition of a barrier metal. The resulting barrier metal conformally covers not only the surface of the silicide, but also the interior surface regions of the local interconnect, and the via connects downward to the buried power rail while also forming a conformal barrier at the interface between the via and the buried power rail. Figure 1 shows the results of incorporating atomic layer deposition of a barrier metal into a CFET device 100.

[0033] A cross-sectional view of a CFET device 100 taken through two source or drain (S / D) structures (or S / Ds) 112, 122 is shown in Figure 1. The two S / D structures 112, 122 may correspond to two transistors stacked one on top of the other. For example, the upper transistor may be configured as a nanosheet channel, while the lower transistor may be configured as a fin structure channel.

[0034] For example, the top S / D 122 may be an NMOS-S / D formed by silicon epitaxy with phosphorus dopant (Si:P). The bottom 112 may be a PMOS-S / D formed by silicon germanium epitaxy with boron dopant (SiGe:B). Each S / D 112 or 122 may be covered with a silicide layer 113 or 123, respectively. For example, each silicide layer 113 or 123 may include a titanium (Ti) film on its outer surface.

[0035] A first interconnect structure 114 connects the bottom PMOS 110 to the buried VDD power rail 112. A second interconnect structure 124 connects the top NMOS-S / D 122 to the buried VSS power rail 120. The interconnect structures 114, 124 and power rails 110, 120 may be formed of, for example, ruthenium. Each interconnect structure 114 or 124 may have an upper portion (local interconnect) and a lower portion (via structure, or via 111 or 121). As shown, via 111 connects the upper portion (local interconnect) of interconnect structure 114 to the VDD power rail 110, and via 121 connects the upper portion (local interconnect) of interconnect structure 124 to the VSS power rail 120. Each interconnect structure 114 or 124 may be capped by an etch stop layer 116 or 126, respectively.

[0036] Conformal barrier films 115, 125 can be formed on the surface of each interconnect structure 114, 124, respectively. In one example, the barrier films 115, 125 can be made of titanium nitride (TiN). As shown, the barrier films 115, 125 can occupy space within each interconnect structure 114 or 124, thereby reducing the volume of ruthenium within the interconnect structure 114, 124. If the thickness of the barrier films 115, 125 were increased, the volume of ruthenium within the interconnect structure 114, 124 could decrease, leading to an increase in the resistance of each interconnect structure 114 or 124. Additionally, because barrier films 115, 125 exist between via 111 and VDD power rail 110 and between via 121 and VSS power rail 120, increasing the thickness of barrier films 115, 125 also creates resistance between each S / D structure 112 or 122 and the respective power rail 110 or 120.

[0037] As shown in FIG. 1, the inventors have recognized that incorporating a barrier metal throughout the local interconnect and the vias connecting to the power supply significantly impacts the resistance of the interconnect structure. The cumulative resistance as a function of barrier thickness can increase significantly as vias are scaled to smaller sizes. In some instances, a resistance greater than 200 ohms for the accumulated resistance from the contact to the buried rail is believed to hinder device performance. Therefore, while a barrier film can be utilized to minimize the diffusion of silicon and dopants from the source and drain into the interconnect metal, the inventors have discovered that the barrier need only overlie the silicide layer and not enter the entire local interconnect and via structure.

[0038] The present disclosure provides a method for selectively depositing a barrier metal over only the silicide, rather than conformally depositing it over the entire surface area of the local interconnect and via structures. FIG. 2 illustrates a CFET device 200 resulting from such a selective deposition method. The example CFET device 200 of FIG. 2 has a similar structure to the example CFET device 100 of FIG. 1, except that two barrier films, rather than one, are formed within each interconnect structure: barrier films 215a and 215b in interconnect structure 214, which replace barrier film 115 of FIG. 1, and barrier films 225a and 225b in interconnect structure 224, which replace barrier film 125 of FIG. 1. The other elements 210-214, 216, 220-224, and 226 of FIG. 2 are similar to elements 110-114, 116, 120-124, and 126 of FIG. 1.

[0039] In the CFET device 200, the barrier film 215a can be first selectively formed on the silicide layer 213 of the S / D structure 212 at a thicker thickness (e.g., in the range of 10-40 Å). The barrier film 215b can be later formed (before metallizing the interconnect structure 214) on the inner surface of the interconnect structure 214 at a thinner thickness (e.g., in the range of 2-5 Å). The barrier film 215a can be sufficiently thick to minimize silicon or dopant diffusion from the S / D structure 212. The barrier film 215b can be thin enough to minimize its effect on the resistance of the interconnect structure 214, but thick enough to mitigate diffusion between the interconnect metal and the surrounding dielectric material. The barrier films 225a, 225b can be formed in a manner similar to the barrier films 215a, 215b. The thicknesses mentioned above are merely examples and can be adjusted according to a particular process parameter configuration or desired device performance.

[0040] As explained in the above example, the barrier metal in the selective deposition process is deposited over only the exposed surfaces of the silicide in the open local interconnect structure, and not over the entire local interconnect structure and surface area of the via formed, for example, from a dual damascene process. The selective deposition process also does not deposit the barrier metal at the interface between the buried power rail and the connecting via, provided the selective deposition process is tunable specifically for the silicide.

[0041] Experiments based on CFET device 200 demonstrate the overall conductance improvement associated with the removal of barrier metal from the entire local interconnect and via surfaces. In fact, the improvement in via resistance scales equally well with the removal of barrier metal from the corresponding sidewalls, given the extreme difference in conductance between metals (such as ruthenium and cobalt) and barrier materials (such as TiN and TaN), as if the vias were equally large.

[0042] In some embodiments, the barrier metal film can be made of TiN, TaN, etc. The silicide material can be titanium, titanium silicide, nickel, nickel silicide, platinum, platinum silicide, ruthenium, ruthenium silicide, etc. The dielectric film that would be inside the interconnect and via structure in a dual damascene approach before metallization of the interconnect and via can be some type of pre-metal dielectric, such as silicon oxide, or a dielectric liner material, such as silicon nitride or silicon carbon nitride (SiCN). Therefore, the selective deposition of the barrier metal film over the silicide material can be selective to the dielectric film employed. In some embodiments, the selective deposition process can completely "seal" the silicide surface to minimize diffusion of dopant species, such as silicon, silicon germanium, or phosphorus, boron, or arsenic, from the source and drain regions into the interconnect metal. In some instances, the selective deposition process can partially cover the silicide surface. Small-scale diffusion may occur, but it will not significantly affect the performance of the CFET device.

[0043] In one embodiment, a diffusion barrier is formed on a silicide layer using area-selective deposition based on self-assembled monolayers (SAMs). For example, a trench structure (or trench) for accommodating interconnect structure 214 can be formed through a dielectric material to expose source / drain 212. A dielectric layer 213 can be formed overlying substrate 212. A SAM layer can be formed to cover the inner surface of interconnect structure 214 (i.e., the surface of the dielectric material) while leaving silicide layer 213 exposed. A deposition process (e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD)) can then be performed to form a barrier film 215a over silicide layer 213. Due to the SAM layer preventing the formation of a barrier film on the dielectric material, the barrier film can be formed only over silicide layer 213. The photoresist film can then be removed. A barrier film 215b can be conformally formed in the trench, covering the surface of the dielectric material and barrier film 215a. In other embodiments, selective deposition techniques other than SAM-based methods may be utilized.

[0044] In some embodiments, the subsequently formed barrier film 215b may not overlap the previously formed barrier film 215a. For example, the barrier film 215b may cover only the surface of the dielectric material surrounding the interconnect structure 214 by using a deposition process that is selective to the silicide layer 213. Depending on the selectivity of the deposition process, the barrier film 215b may or may not cover the interface between the via structure 211 and the buried power rail 210.

[0045] In some embodiments, the thick barrier film 215a can be formed over the inner surface of an upper portion (local interconnect) of the interconnect structure 214. For example, the via structure 211 below the local interconnect can be covered, for example, by filling with a material or depositing a film over the inner surface of the via 211. Deposition of a first barrier film is then performed within the trench of the interconnect structure 214. The inner surface of the via 211 can then be exposed. A second barrier film can be deposited over the inner surface of the trench. Because the upper portion of the interconnect structure 214 can have a larger size (e.g., a larger width or volume), the thick barrier film 215a may have a limited effect on the conductance of the overall interconnect structure 214.

[0046] In some embodiments, the barrier films 215a, 215b may be made of different materials and therefore may exhibit different diffusion protection characteristics. The use of different barrier film materials can provide increased flexibility depending on cost, process condition parameter configuration, and silicide layer and dielectric material properties.

[0047] Aspects of the present disclosure further provide a method for selective deposition of a contact etch stop layer (CESL) that promotes vertical self-alignment of interconnect structures for stacked logic devices, such as logic CFET devices. For example, as the size of CFET logic cells shrinks, interconnect structures (such as via-to-rail structures and via-to-contact (VCT) structures) can be placed in close proximity to complementary devices. Some mechanism for vertical self-alignment of interconnect structures that reduces the likelihood of shorts between via structures and complementary devices is needed. One solution is to thicken the CESL liner. However, simply increasing the CESL thickness without selective deposition would significantly change the contact resistance to the point where the CFET device would not achieve its expected performance (e.g., power, performance, and area (PPA)).

[0048] The present disclosure provides a mechanism for selective CESL deposition that enables vertical self-alignment of interconnect structures that can reduce or prevent short circuits between via structures and complementary devices. For example, a thick CESL can be selectively deposited over a portion of the surface of an S / D structure to prevent short circuits to adjacent via structures. The thick CESL will not overlie the interface between the S / D structure and each local interconnect, and therefore will not affect the S / D contact conductivity.

[0049] Figures 3-8 illustrate a self-aligned metallization process for forming interconnect structures within a CFET device 300. A series of intermediate stages in the fabrication of the CFET device 300 are shown in perspective (Figure 3) or cross-sectional views (Figures 4-8). A cross-section through a set of S / D structures is shown in each of Figures 3-8. During the self-aligned metallization process, a CESL is selectively deposited over the surface of the S / D contacts (S / D structures) to help prevent shorts and reduce local interconnect resistance.

[0050] In FIG. 3, silicon fin structures 303 are formed over a silicon substrate 301. Power rails 307 are embedded in shallow trench isolation (STI) silicon oxide 305 between the fin structures. Each power rail 307 can be fabricated from ruthenium (Ru) and can be covered with a cap layer 308, such as a layer of silicon carbide (SiC). An etch stop layer 306 (e.g., silicon oxide) can be deposited from the top to seal the power rails 307. A group of gate structures 321 traverse the fin structure 303. Each gate structure 321 can include a pair of gate spacers 321b that sandwich a dummy gate 321a with a cap 321c that overlies the gate spacer 321b and the dummy gate 321a.

[0051] The CFET device 300 may include two stages of FET transistors stacked in a direction perpendicular to the substrate 301. For example, the lower stage of the FET transistors may have a fin structure channel (an extension of the fin structure 303, not shown) between each pair of gate spacers 321b and embedded in each dummy gate 321a. The upper stage of the FET transistors may have a nanosheet channel between each pair of gate spacers 321b. As an example, the lower stage of the FET transistors may be a p-type FET, and the upper stage of the FET transistors may be an n-type FET. It should be noted that the architecture of the CFET device 300 is arbitrary. The present disclosure is not limited to any particular CFET device architecture.

[0052] In the example of FIG. 3 , a bottom PMOS-S / D structure 311 of a p-type FET is formed over the fin structure 303 in the space between adjacent gate structures 321. For example, the bottom S / D structure 311 can be epitaxially grown and have a lower portion 311a of SiGe and an upper portion 311b of SiGe:B. A contact etch stop layer (CESL) 312 (e.g., silicon nitride (SiN)) can be selectively deposited over the surface of the bottom S / D structure 311. The CESL 312 can have a desired thickness effective to prevent the S / D structure 311 from shorting to a metal interconnect formed during a subsequent self-aligned metallization process. NMOS cover spacers 322 can be formed over the upper portion of each sidewall of the gate spacer 321b to protect the upper nanosheet channel (not shown) during lower-level processing of the FET device.

[0053] In FIG. 4, a dual damascene process is performed to form via structures 403 and local interconnect trenches 405 for subsequent metallization. As a specific example, a sacrificial light absorbing material (SLAM)-assisted dual damascene process is used. For example, a pre-metal (PMD) silicon oxide (PMD oxide) 401 can first be filled into the trenches between the gate structures 321 to embed the S / D structures 311. A first etching process (not shown) can then be performed to form a via structure (or vias) through the PMD oxide 401 from top to bottom to reach the top surface of the power rail 307. The via structure can be formed by breaking through the cap layer 308. The substrate can then be coated with SLAM (the via structure can be filled with SLAM) and patterned with trench photoresist. A second etching process can then be performed to etch the SLAM filled into the via structures (not shown) along with the PMD oxide 401. As a result, trenches 405 can be formed with vias 403 disposed below each trench, exposing S / D structures 311. As shown, SLAM 404 remains at the bottom of the original via structures (now labeled via structures 403).

[0054] 5, a silicide layer (or silicide) 501 can be formed over the surfaces of the S / D structures (or S / D contacts) 311. For example, exposed portions of the CESL 311 of each S / D structure 312 can be removed to expose the epitaxy of each S / D structure 311. As a result, the remaining CESL 312 is now only on a portion of the surface of each S / D structure 311 and is embedded in the PMD oxide 401, forming a selective deposition of CESL 312.

[0055] Silicide 501 can be formed over the exposed epitaxy surface of each S / D structure 311. In one example, a titanium (Ti) film can be selectively formed over the exposed epitaxy to form silicide 501. A silicide-forming anneal can be performed to form the silicide compound of silicide 501. After the annealing process, in some examples, a layer of titanium can remain on the surface of silicide 501. In various embodiments, other metals, such as aluminum, copper, tungsten, tantalum, ruthenium, or cobalt, can be used in place of titanium.

[0056] In FIG. 6 , lower interconnect metallization is performed to form interconnect structure 602. For example, residual SLAM 404 can be removed from via 403. A barrier film or liner (shown here) can be formed over the interior surfaces of via 403 and trench 405. In some embodiments, the barrier film or liner can be formed using a two-step deposition technique disclosed herein. For example, a first SAM-assisted selective deposition can be performed to selectively form a first barrier film (e.g., TiN) over each silicide layer 501. Then, a second non-selective deposition can be performed to form a second barrier film on the interior surfaces of the trench and via structure. As a result of the above-described two-step deposition, the resistance of the interconnect structure can be reduced and diffusion from the S / D structure into the interconnect metal can be minimized. In some embodiments, a two-step deposition technique is not used. A single-step deposition, such as a CVD or ALD process, can be performed to form the barrier film.

[0057] A conductive material (such as ruthenium) can then be filled into trenches 405 and vias 403, followed by a recess formation process to lower the top surface of the conductive material to a desired level, so that local interconnects 602a and via interconnects 602b can be formed as upper and lower portions of each interconnect structure 602. A cap layer 603 can be formed over interconnect structures 602, followed by deposition of a PMD oxide to seal the interconnect structures.

[0058] In FIG. 7, an upper S / D structure 701 and an upper interconnect structure 702 are formed, followed by metal layer 1 (M1). For example, the PMD oxide above the bottom S / D structure 311 may be recessed. The NMOS cover spacer 322 may be removed to expose the channel of the upper FET device. The upper S / D structure 701 may be epitaxially grown. Processes similar to those used to form the lower interconnect structure 602 may then be performed to form the upper interconnect structure 702. For example, these processes may include deposition of a CESL over the S / D contacts, local interconnect trench and via formation, silicide formation, two-step barrier liner formation, and upper interconnect metallization.

[0059] After the formation of the upper interconnect structure 702, a gate replacement process can be performed to replace the dummy gate 321a with a real gate structure. After the real gate structure is formed, M1 metallization can be performed. For example, following the deposition of an etch stop layer on the substrate, a blanket dielectric layer 703 can be formed over the etch stop layer and planarized. Vias and trenches can be formed through the dielectric layer 703, the etch stop layer, and / or the PMD oxide and filled with a conductive material (such as tungsten, copper, aluminum, ruthenium, etc.) to form the M1 interconnect structure 704.

[0060] As shown, via structures 705 connecting each top S / D structure 701 to each buried power rail 307 are adjacent to several bottom S / D structures 311. Therefore, selectively placed vias 312 can function as an insulating layer that effectively prevents shorts between the S / D and via interconnects. In various embodiments, vias 312 can be configured to have a predetermined thickness effective to prevent shorts between the S / D structures and adjacent interconnect structures.

[0061] Figure 8 shows a cross section of the same CFET device 300 fabricated over a different set of S / D structures shown in Figures 3-7. Similarly, there are two stages in the FET device: a lower stage that is a p-type FET with a fin-shaped channel, and an upper stage that is an n-type FET with a nanosheet channel. Correspondingly, there are bottom S / D structures 801a-801d and top S / D structures 802a-802d, each with a respective interconnect structure 804.

[0062] 7, CESL 805 is selectively formed over a portion of the surface of each one of S / D structures 801a-801d and 802a-802d. A silicide layer 806 is formed on the portion of the surface of each S / D structure not covered by the CESL and connects to each interconnect structure 804. A barrier liner may be formed between silicide layer 806 and each interconnect structure 804.

[0063] 7, a first group of S / D structures 801a, 802a, and 802b are connected to buried power rail 307, and a second group of S / D structures 801b-801d and 802c-802d are connected to up to M1 interconnect structures 807 through via structures 803. S / D structures 801c-801d and 802c-802d are also connected to each other through respective local interconnect and via structures.

[0064] It should be noted that the techniques for selective deposition of barrier films or etch stop layers disclosed herein are not limited to the devices described in this disclosure. For example, the techniques can be applied to various semiconductor devices that may have architectures other than CFET architectures. For example, the various semiconductor devices can include, but are not limited to, planar devices, including FINFETs, nanosheet FETs, nanowire FETs, etc.; 3D devices, including FINFETs, nanosheet FETs, nanowire FETs, etc.; and junction or junctionless transistors. Additionally, materials such as barrier films / liners, local interconnect structures, via structures, silicides, S / D structures, CESLs, dielectric materials, caps, metals, etch stop layers, etc., can vary in various embodiments of the present disclosure. The inventive concepts disclosed herein are not limited to the materials described in this disclosure.

[0065] In the foregoing description, specific details have been disclosed, such as the particular configuration of the processing system and descriptions of the various elements and processes used within the system. However, it should be understood that the technology described herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific values, materials, and configurations have been disclosed to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and redundant description may be omitted.

[0066] To aid in understanding various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that the operations described are necessarily order dependent. In fact, the operations need not be performed in the order presented. The operations described may be performed in a different order than in the embodiments described. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0067] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may include, for example, a base substrate structure, such as a semiconductor wafer or reticle, or a layer on or overlying the base substrate structure, such as a thin film. Thus, a substrate is not limited to any particular base structure, lower layer, or upper layer, whether patterned or not, but is considered to include such layers or base structures, as well as any combination of layers and / or base structures. While this specification may refer to particular types of substrates, this is for illustrative purposes only.

[0068] While aspects of the present disclosure have been described in conjunction with specific embodiments offered as examples, alternatives, modifications, and variations can be made to these examples. Accordingly, the embodiments described herein are intended to be illustrative and not limiting. Changes may be made without departing from the scope of the claims set forth below.

Claims

1. A field-effect transistor (FET) having an S / D structure, the S / D structure comprising a silicide layer surrounding the entire surface of the S / D structure, The interconnection structure includes the S / D structure in contact with the S / D structure, The interconnection structure has a barrier film on its surface that separates the interconnection structure from the material surrounding it. The first portion of the barrier film covers the first interface between the interconnection structure and a portion of the silicide layer of the S / D structure. The second portion of the barrier film covers the second interface between the interconnection structure and the dielectric material adjacent to the interconnection structure. The first portion of the barrier film is thicker than the second portion of the barrier film. A semiconductor device in which the first portion of the barrier film does not contain the material of the second portion of the barrier film.

2. The semiconductor device according to claim 1, wherein the second portion of the barrier film covers the surface of the via structure of the interconnection structure.

3. The semiconductor device according to claim 2, wherein the via structure connects the interconnection structure to a power rail.

4. The first source / drain (S / D) structure of the first field-effect transistor (FET), The first interconnection structure is in contact with the first S / D structure, The first S / D structure includes a silicide layer on a first portion of the surface of the first S / D structure, and the silicide layer is in contact with the interface between the first S / D structure and the first interconnection structure. The first S / D structure includes a contact etching stop layer (CESL) that is in direct contact with a second portion of the surface of the first S / D structure, wherein the CESL is not present on the first portion of the surface of the first S / D structure. The silicide layer and the CESL cover the entire surface of the first S / D structure, forming a semiconductor device.

5. Further including the first embedded power rail, The semiconductor device according to claim 4, wherein the first interconnection structure includes a first via interconnection structure that connects the first interconnection structure to the first embedded power rail.

6. The second S / D structure of the second FET formed on the first FET, The present invention further includes a second interconnection structure in contact with the second S / D structure, The second interconnection structure includes a second via interconnection structure that connects the second interconnection structure to a second embedded power rail. The semiconductor device according to claim 5, wherein the second via interconnection structure is in contact with the CESL of the first S / D structure.

7. The semiconductor device according to claim 4, wherein the silicide layer includes a titanium (Ti) layer and the CESL includes a silicon nitride (SiN) layer.

8. The semiconductor device according to claim 4, wherein the semiconductor device is a complementary FET (CFET) device.

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