Ferroelectric Random Access Memory Cell

Abstract

An embodiment of the present invention provides a ferroelectric random access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source / drain region and an upper source / drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, the ferroelectric layer having two or more sections with different horizontal thicknesses between the bottom source / drain region and the upper source / drain region. A method for fabricating the FeRAM cell is also provided. (FIG. 24)

Description

[Background technology]

[0001] This application relates to semiconductor integrated circuit manufacturing, and more particularly to ferroelectric random access memory cells and methods of manufacturing the same.

[0002] Analog computing using emerging memories has been considered a promising option for artificial intelligence (AI) applications. For example, some recently commercialized ferroelectric random access memory (FeRAM) cells are used in memory applications, where each FeRAM cell holds one bit of one of two logic states (either logic "1" or logic "0"), depending on the polarization of the ferroelectric layer within the FeRAM cell.

[0003] In analog computing applications, it is desirable to have FeRAM cells where a single FeRAM cell can hold multiple logic states, which may be achieved by gradually changing the polarization of the FeRAM cell to provide a continuous value or multiple discrete values (instead of just two values, "1" or "0") as a function of programming voltage. However, it has proven extremely difficult, if not impossible, to achieve FeRAM cells with gradually changing polarization. Summary of the Invention

[0004] Embodiments of the present invention provide a ferroelectric random access memory (FeRAM) cell, for example, based on a ferroelectric vertical transport field effect transistor (Fe-VTFET). The FeRAM cell comprises a bottom source / drain region and a vertical channel between the source / drain regions; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, the ferroelectric layer having two or more sections with different horizontal thicknesses between the bottom source / drain region and the top source / drain region. The two or more sections of the ferroelectric layer may be programmed to have different combinations of polarization to provide multiple logic states.

[0005] In one embodiment, the FeRAM cell further comprises a gate metal surrounding the ferroelectric layer, wherein the gate metal has two or more horizontal thicknesses that complement the different horizontal thicknesses of the two or more sections of the ferroelectric layer, resulting in a uniform horizontal thickness measured from a vertical channel.

[0006] In another embodiment, the ferroelectric layer comprises a bottom section, a middle section, and a top section of three different horizontal thicknesses, the three different horizontal thicknesses being arranged in a stepped pattern.

[0007] In one embodiment, the top section of the ferroelectric layer is adapted to be programmed to have a polarization state that is different from the polarization state of the middle and bottom sections, hi another embodiment, the top and middle sections of the ferroelectric layer are adapted to be programmed to have a polarization state that is different from the polarization state of the bottom section.

[0008] In one embodiment, the ferroelectric layer of an FeRAM cell is composed of doped hafnium oxide. In another embodiment, the difference in lateral thickness between two of the two or more sections of the ferroelectric layer is at least 0.5 nm, allowing controllability in programming different sections of the ferroelectric layer to have different and / or desired polarizations.

[0009] An embodiment of the present invention further provides a method for forming a FeRAM cell, the method including: forming a vertical channel on a bottom epitaxial layer; forming a gate oxide on sides of the vertical channel; forming a first layer of ferroelectric material surrounding a first section of the vertical channel; forming a second layer of ferroelectric material surrounding a second section of the vertical channel and the first layer of ferroelectric material; forming a third layer of ferroelectric material surrounding a third section of the vertical channel and the second layer of ferroelectric material; forming a gate metal surrounding the third layer of ferroelectric material; and forming a top epitaxial layer on the vertical channel.

[0010] In one embodiment, forming the first layer of ferroelectric material includes forming a first conformal layer of ferroelectric material surrounding the vertical channel; covering a first portion of the first conformal layer of ferroelectric material with a first sacrificial material layer, the first portion having a vertical height corresponding to the first section of the vertical channel; and removing exposed portions of the first conformal layer of ferroelectric material not covered by the first sacrificial material layer.

[0011] In another embodiment, forming the second layer of ferroelectric material includes forming a second conformal layer of ferroelectric material surrounding the first layer of ferroelectric material and a portion of the vertical channel not covered by the first layer of ferroelectric material; covering a second portion of the second conformal layer of ferroelectric material with a second sacrificial material layer, the second portion having a vertical height corresponding to the sum of the first and second sections of the vertical channel; and removing exposed portions of the second conformal layer of ferroelectric material not covered by the second sacrificial material layer.

[0012] In a further embodiment, forming the third layer of ferroelectric material includes forming a third conformal layer of ferroelectric material surrounding the second layer of ferroelectric material and a portion of the vertical channel not covered by the second layer of ferroelectric material; covering the third portion of the third conformal layer of ferroelectric material with a third sacrificial material layer, the third portion having a vertical height corresponding to the sum of the first section, second section, and third section of the vertical channel; and removing the exposed portion of the third conformal layer of ferroelectric material not covered by the third sacrificial material layer.

[0013] An embodiment of the present invention further comprises forming a top spacer surrounding the remaining portion of the vertical channel after removing the exposed portion of the third conformal layer of ferroelectric material to expose the remaining portion of the vertical channel therebelow, and further comprising forming a bottom spacer above the bottom epitaxial layer surrounding the vertical channel before forming the gate oxide.

[0014] In one embodiment, forming the gate oxide includes exposing the vertical channel to an oxygen-containing environment to oxidize the side surfaces of the vertical channel. [Brief explanation of the drawings]

[0015] The present invention will be more fully understood and appreciated from the following detailed description of the embodiments thereof taken in conjunction with the accompanying drawings, in which:

[0016] [Figure 1] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 2] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 3]1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 4] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 5] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 6] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 7] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 8] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 9] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 10] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 11] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 12] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 13] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 14] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 15]1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 16] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 17] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 18] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 19] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 20] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 21] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 22] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 23] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention. [Figure 24] 1 is an illustration of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell in a manufacturing process according to an embodiment of the present invention.

[0017] [Figure 25] 1 is an illustration of a flowchart of a method for fabricating a FeRAM cell according to an embodiment of the present invention.

[0018] It will be understood that for purposes of simplicity and clarity, elements shown in the figures have not necessarily been drawn to scale. Further, where applicable, in the various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other instances, the grouping of certain elements in the functional block diagrams is for illustrative purposes only and may not necessarily imply that they are in or embodied in a single physical entity. DETAILED DESCRIPTION OF THE INVENTION

[0019] In the following detailed description and in the accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings are exemplary and schematic illustrations that are not drawn to scale. Furthermore, for ease of explanation, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not mean that the layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor processing steps, the descriptions provided herein are intended to be illustrative of the processes that may be required to form a functional semiconductor integrated circuit device. It is emphasized that this is not intended to be an all-inclusive list of steps, and rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, have purposely not been described herein for the sake of brevity.

[0020] It should be understood that the terms "about" or "substantially," as used herein with respect to thickness, width, percentage, range, etc., are meant to indicate closeness or approximation, but not exactness. For example, the terms "about" or "substantially," as used herein, mean that there may be a small margin of error, such as, by way of example only, 1% or less of the stated amount. Similarly, the terms "on," "above," or "on top of," as used herein to describe the positional relationship between two layers or structures, are intended to be interpreted broadly and should not be interpreted as excluding the presence of one or more intervening layers or structures.

[0021] To provide spatial context for different structural orientations of the semiconductor structures shown in the figures, XYZ Cartesian coordinates may be provided in some of the figures. As used herein, the terms "vertical" or "vertical direction" or "vertical height" refer to the Z direction of the Cartesian coordinate system shown in the figures, and the terms "horizontal" or "horizontal direction" or "lateral direction" as used herein refer to the X and / or Y directions of the Cartesian coordinate system shown in the figures.

[0022] Furthermore, although different reference numbers may be used across different drawings, the same or similar reference numbers are used throughout the drawings to indicate the same or similar features, elements, or structures, and thus, detailed descriptions of the same or similar features, elements, or structures may not be repeated for each of the drawings for brevity. Labeling of the same or similar elements in some drawings may also be omitted so as not to overcrowd the drawings.

[0023] FIG. 1 illustrates cross-sectional views of a FeRAM cell 10 during fabrication steps of the FeRAM cell 10 according to one embodiment of the present invention. More specifically, embodiments of the present invention provide for receiving a support structure, such as a semiconductor substrate 101, and forming an epitaxial layer on the semiconductor substrate 101. The semiconductor substrate 101 may be a bulk substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate, or may be a silicon-on-insulator (SOI) substrate or a silicon-germanium-on-insulator (SiGeOI) substrate. Other types of substrates may also be used as the support structure. The epitaxial layer may be an epitaxially grown Si layer, an epitaxially grown Ge layer, or an epitaxially grown SiGe layer. As illustrated in FIG. 1, the epitaxial layer may be formed as a bottom epitaxial layer 210 to operate or function as a bottom source / drain region of a vertical transistor operating as part of the FeRAM cell 10. The bottom epitaxial layer 210 may hereinafter be referred to as the bottom source / drain region.

[0024] An embodiment of the present invention further provides forming a vertical channel 310 on the bottom epitaxial layer 210. The vertical channel 310 may be formed of a silicon material, for example, by a lithographic patterning and etching process of a crystalline silicon layer on the bottom epitaxial layer 210 using a hard mask 301. In one embodiment, the vertical channel 310 may have a vertical height between about 15 nm and about 50 nm. The hard mask 301 may be silicon nitride (SiN) or other suitable material as a hard mask.

[0025] FIG. 2 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that shown in FIG. 1 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a bottom spacer 220 on the bottom epitaxial layer 210. The bottom spacer 220 surrounds the vertical channel 310 at its bottom and may be a layer of a dielectric material, such as SiN, silicon-oxide (SiO), or other low-K materials, such as SiOC, SiON, SiOCN, or SiBCN. Other suitable insulating materials may also be used to form the bottom spacer 220. The bottom spacer 220 may have a vertical thickness of approximately 5 nm to 15 nm.

[0026] 3 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 2 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a gate oxide 320 on the sides of the vertical channel 310. For example, one embodiment of the present invention may include exposing the vertical channel 310 to an oxygen-containing environment to oxidize the sides of the vertical channel 310, thereby forming a thin oxide layer on the sides of the vertical channel 310 to form the gate oxide 320. The oxidation process may be performed after the formation of the bottom spacer 220, so that only the portions of the sides of the vertical channel 310 between the hard mask 301 and the bottom spacer 220 may be oxidized to form the gate oxide 320.

[0027] 4 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 3 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a first conformal layer 410 of ferroelectric material surrounding the vertical channel 310. For example, in one embodiment, the first conformal layer 410 of ferroelectric material may be formed over the bottom spacer 220 and hard mask 301, on the sidewalls of the hard mask 301, and on the gate oxide 320 surrounding the vertical channel 310, for example, through a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other currently existing or future developed means. The first conformal layer 410 may have a thickness ranging from about 1 nm to about 5 nm.

[0028] 5 is an illustration of a cross-sectional view of the FeRAM cell 10 at a manufacturing step subsequent to that illustrated in FIG. 4 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for performing an anisotropic etching process, such as a reactive ion etching (RIE) process, to remove horizontal portions of the first conformal layer 410 of ferroelectric material. For example, the anisotropic etching process can remove portions of the first conformal layer 410 above the bottom spacer 220 and above the hard mask 301, leaving only vertical portions 411 of the first conformal layer 410 relative to the gate oxide 320.

[0029] 6 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 5 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a layer of sacrificial material, such as a first organic planarization layer (OPL) 510, over the FeRAM cell 10 being fabricated. For example, the first OPL 510 can cover the bottom spacers 220, the vertical portion 411 of the first conformal layer 410, and the top surface of the hard mask 301 such that the first OPL 510 has a height greater than the top surface of the hard mask 301.

[0030] 7 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 6 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for recessing first OPL 510 to expose a portion of vertical portion 411 of first conformal layer 410. For example, recessing first OPL 510 includes creating a first sacrificial material layer, such as modified first OPL 511 having a vertical height V1 that covers the lower portion of vertical portion 411 of first conformal layer 410. Recessing first OPL 510 may include etching the OPL material via an RIE process.

[0031] 8 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 7 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing exposed portions of vertical portion 411 of first conformal layer of ferroelectric material 410 that are not covered by modified first OPL 511, thereby forming first layer 412 of ferroelectric material having vertical height V1 that surrounds first section of vertical channel 310. First section of vertical channel 310 has corresponding vertical height V1, as shown in FIG.

[0032] 9 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 8, in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing the first sacrificial material layer of the modified first OPL 511 to expose the first layer of ferroelectric material 412. The first layer of ferroelectric material 412, like the thickness of the first conformal layer 410, can have a lateral thickness ranging from about 1 nm to about 5 nm.

[0033] 10 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that depicted in FIG. 9 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a second conformal layer of ferroelectric material 420 surrounding the exposed portion of the vertical channel 310 and the first layer of ferroelectric material 412. For example, the second conformal layer of ferroelectric material 420 can be formed on the top surface of the bottom spacer 220, on the top surface and sidewalls of the hard mask 301, on the gate oxide 320 surrounding the exposed portion of the vertical channel 310, and on the first layer of ferroelectric material 412, for example, through a CVD process, a PVG process, an ALD process, or any other suitable means. The second conformal layer 420 can have a thickness ranging from about 1 nm to about 5 nm.

[0034] 11 is an illustration of a cross-sectional view of the FeRAM cell 10 at a manufacturing step subsequent to that illustrated in FIG. 10 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for performing an anisotropic etching process, such as an RIE process, to remove horizontal portions of the second conformal layer of ferroelectric material 420 in steps similar to those illustrated in FIG. 5 . For example, the anisotropic etching process can remove the horizontal portions of the second conformal layer 420 over the bottom spacer 220 and over the hard mask 301, leaving only vertical portions 421 of the second conformal layer 420 relative to the gate oxide 320 and relative to the first layer of ferroelectric material 412.

[0035] 12 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 11 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a layer of sacrificial material, such as second OPL 520, over FeRAM cell 10 during fabrication. For example, second OPL 520 can cover bottom spacer 220, vertical portion 421 of second conformal layer 420, and the top surface of hard mask 301 such that second OPL 520 has a height greater than the top surface of hard mask 301.

[0036] 13 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that depicted in FIG. 12 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for recessing second OPL 520 to expose a portion of vertical portion 421 of second conformal layer 420 directly to gate oxide 320 and vertically above first layer of ferroelectric material 412. For example, recessing second OPL 520 may result in a modified second OPL 520 having a vertical height V2 that covers the bottom of vertical portion 421 of second conformal layer 420. The recessing of the second OPL 520 may include creating a second sacrificial material layer such as a second OPL 521. A bottom portion of the vertical portion 421 of the second conformal layer 420 covers the first layer of ferroelectric material 412 and a second section of the vertical channel 310 directly above the first section of the vertical channel 310. Recessing the second OPL 520 may include etching the OPL material via an RIE process.

[0037] 14 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 13 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing exposed portions of vertical portion 421 of second conformal layer of ferroelectric material 420 that are not covered by modified second OPL 521, thereby forming second layer of ferroelectric material 422 having vertical height V2 that surrounds second section of vertical channel 310 and first layer of ferroelectric material 412. The sum of the heights of second section of vertical channel 310 and first layer of ferroelectric material 412 corresponds to vertical height V2 of second layer of ferroelectric material 422, as illustrated in FIG. 14 .

[0038] 15 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 14, in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing the second sacrificial material layer of modified second OPL 521 to expose second layer of ferroelectric material 422. Second layer of ferroelectric material 422, like the thickness of second conformal layer 420, can have a lateral thickness ranging from about 1 nm to about 5 nm.

[0039] 16 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 15 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a third conformal layer of ferroelectric material 430 surrounding the exposed portion of the vertical channel 310 and the second layer of ferroelectric material 422. For example, the third conformal layer of ferroelectric material 430 can be formed on the top surface of the bottom spacer 220, on the top surface and sidewalls of the hard mask 301, on the gate oxide 320 surrounding the exposed portion of the vertical channel 310, and on the second layer of ferroelectric material 422, for example, through a CVD process, a PVD process, an ALD process, or any other suitable means. The third conformal layer 430 can have a thickness ranging from about 1 nm to about 5 nm.

[0040] 17 is an illustration of a cross-sectional view of FeRAM cell 10 at a manufacturing step subsequent to that illustrated in FIG. 16 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for performing an anisotropic etching process, such as an RIE process, to remove horizontal portions of third conformal layer 430 of ferroelectric material in steps similar to those illustrated in FIGS. 5 and 11 . For example, the anisotropic etching process can remove horizontal portions of third conformal layer 430 over bottom spacer 220 and over hard mask 301, leaving only vertical portions 431 of third conformal layer 430 relative to gate oxide 320 and second layer of ferroelectric material 422.

[0041] 18 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 17 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a layer of sacrificial material, such as third OPL 530, over FeRAM cell 10 during fabrication. For example, third OPL 530 can cover bottom spacer 220, vertical portion 431 of third conformal layer 430, and the top surface of hard mask 301 such that third OPL 530 has a height greater than the top surface of hard mask 301.

[0042] 19 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that depicted in FIG. 18 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for recessing third OPL 530 to expose a portion of vertical portion 431 of third conformal layer 430 directly to gate oxide 320 and vertically above second layer of ferroelectric material 422. For example, recessing third OPL 530 includes creating a third sacrificial material layer, such as modified third OPL 531 having vertical height V3, that covers the lower portion of vertical portion 431 of third conformal layer 430. The lower portion of vertical portion 431 of third conformal layer 430 covers second layer of ferroelectric material 422 and a third section of vertical channel 310 directly above the second section of vertical channel 310. Retreating the third OPL 530 may include etching the OPL material via an RIE process.

[0043] 20 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 19 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing exposed portions of vertical portion 431 of third conformal layer of ferroelectric material 430 that are not covered by modified third OPL 531, thereby forming third layer of ferroelectric material 432 having a vertical height V3 that surrounds third section of vertical channel 310 and second layer of ferroelectric material 422. The sum of the heights of third section of vertical channel 310 and second layer of ferroelectric material 422 corresponds to vertical height V3 of third layer of ferroelectric material 432, as illustrated in FIG. 20 .

[0044] 21 is an illustration of a cross-sectional view of FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 20, in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for removing the third sacrificial material layer of modified third OPL 531 to expose third layer of ferroelectric material 432. Third layer of ferroelectric material 432, like the thickness of third conformal layer 430, can have a lateral thickness ranging from about 1 nm to about 5 nm.

[0045] According to one embodiment, as demonstratively illustrated in FIG. 21 , first, second, and third layers 412, 422, and 432 of ferroelectric material can together form a ferroelectric layer 400 that surrounds the vertical channel 310 of the FeRAM cell 10. In other words, the ferroelectric layer 400 can have two or more sections with different horizontal thicknesses between the bottom epitaxial layer 210, which functions as the bottom source / drain region, and the top source / drain region 630 (see FIG. 24 ). These two or more sections of the ferroelectric layer 400 can be programmed to have different combinations of polarizations, thereby providing multiple logic states.

[0046] For example, the ferroelectric layer 400 may have a bottom section including a first vertical height 413 and a first horizontal thickness 414; a middle section having a second vertical height 423 and a second horizontal thickness 424; and a top section having a third vertical height 433 and a third horizontal thickness 434. Here, a distinction is made that the bottom, middle, and top sections of the ferroelectric layer 400 are distinct from the first, second, and third layers of ferroelectric material 412, 422, and 432. Also, the bottom, middle, and top sections of the ferroelectric layer 400 do not correspond to the first, second, and third sections of the vertical channel 310, which are related to the process of forming the first, second, and third layers of ferroelectric material 412, 422, and 432.

[0047] According to another embodiment, the bottom, middle, and top sections of the ferroelectric layer 400 may have three different horizontal thicknesses, and the three different horizontal thicknesses may be arranged in a stepped manner. For example, the bottom, middle, and top sections 413, 423, and 433 of the ferroelectric layer 400 may have a first horizontal thickness 414, a second horizontal thickness 424, and a third horizontal thickness 434, respectively, and the second horizontal thickness 424 may be greater than the third horizontal thickness 434 but less than the first horizontal thickness 414.

[0048] In one embodiment, the difference between the first horizontal thickness 414 and the second horizontal thickness 424 of the ferroelectric layer 400 (the difference between the first section 413 and the second section 423) or the difference between the second horizontal thickness 424 and the third horizontal thickness 434 (the difference between the second section 423 and the third section 433) may be at least 0.5 nm, may be greater than 1 nm, and in some embodiments may be as great as 5 nm. In other words, the difference in horizontal thickness between two of the first section, the second section, and the third section is at least 0.5 nm. This difference of at least 0.5 nm allows for controllability in programming different sections of the ferroelectric layer to have different and / or desired polarizations. In another embodiment, the ferroelectric layer 400 is made of or includes hafnium zirconium oxide (HZO) or a suitable perovskite oxide having the general formula ABO3.

[0049] According to another embodiment, the first vertical height 413 of the bottom section, the second vertical height 423 of the middle section, and the third vertical height 433 of the top section may be the same. In another embodiment, the first, second, and third vertical heights of the bottom, middle, and top sections 413, 423, and 433 may be different to balance and / or adjust differences in operating current in different states, as described in more detail below. More specifically, the second vertical height 423 of the middle section may be greater than the first vertical height 413 of the bottom section but less than the third vertical height 433 of the top section of the ferroelectric layer 400, taking into account the proximity of the respective volumes of ferroelectric material in the bottom, middle, and top sections to one another.

[0050] FIG. 22 is an illustration of a cross-sectional view of the FeRAM cell 10 at a fabrication step subsequent to that illustrated in FIG. 21 , in accordance with one embodiment of the present invention. More specifically, embodiments of the present invention provide for forming a gate metal 540 surrounding the third layer of ferroelectric material 432 and overlying the bottom spacer 220. As demonstratively illustrated in FIG. 22 , in one embodiment, the sum of the horizontal thicknesses of the gate metal 540 and the ferroelectric layer 400 remains substantially the same in different sections of the ferroelectric layer 400. In other words, the gate metal 540 may have multiple horizontal thicknesses that complement the horizontal thicknesses of the ferroelectric layer 400. For example, the bottom section of the ferroelectric layer 400 may have the greatest horizontal thickness, while the gate metal 540 surrounding the bottom section of the ferroelectric layer 400 may have the smallest horizontal thickness. Meanwhile, the top section of the ferroelectric layer 400 may have the smallest horizontal thickness, while the gate metal 540 surrounding the top section of the ferroelectric layer 400 may have the largest horizontal thickness, which may result in a uniform horizontal thickness measured from the vertical channel 310 to the outer sidewalls of the gate metal 540.

[0051] In one embodiment, the gate metal 540 may include, for example, tungsten (W), copper (Cu), ruthenium (Ru), and other suitable materials and may be formed, for example, through a CVD process, a PVD process, or an ALD process, and then recessed to have a height corresponding to the vertical height V3 of the third layer of ferroelectric material 432.

[0052] 23 is an illustration of a cross-sectional view of FeRAM cell 10 at a manufacturing step subsequent to that illustrated in FIG. 22, in accordance with one embodiment of the present invention. More specifically, Embodiments of the present invention provide for forming a top spacer 610 on top of the gate metal 540. The top spacer 610 may be deposited on top of the gate metal 540 to surround the remaining exposed portion of the vertical channel 310 and may comprise a dielectric material such as, for example, SiN, SiO, SiOC, SiON, SiOCN, SiBCN, and / or other suitable insulating materials.

[0053] FIG. 24 is an illustration of a cross-sectional view of the FeRAM cell 10 at a manufacturing step subsequent to that illustrated in FIG. 23 , in accordance with one embodiment of the present invention. More specifically, an embodiment of the present invention provides depositing an interlevel dielectric (ILD) layer 620 on the upper spacer 610. The ILD layer 620 may be deposited at a level above the hard mask 301. A CMP process may then be applied to planarize the upper surface of the ILD layer 620 and expose the hard mask 301. After the CMP process, the hard mask 301 may be selectively removed to expose the end faces of the underlying vertical channel 310. Then, upper epitaxial source / drain regions 630 may be formed through an epitaxial growth process. The upper source / drain regions may be, for example, epitaxial silicon-germanium (SiGe) regions.

[0054] According to one embodiment, during operation, the FeRAM cell 10 can be programmed to have multiple logic states. For example, in one embodiment, the top section of the ferroelectric layer 400 can be programmed to have a polarization state that is different from the polarization state of the middle and bottom sections. In another embodiment, the top and middle sections of the ferroelectric layer 400 can be programmed to have a polarization state that is different from the polarization state of the bottom section.

[0055] The polarization states of the bottom, middle, and top sections of the ferroelectric layer 400 may be controlled through a program voltage applied to the gate metal 540. For example, in a first example where a high voltage is applied to the gate metal 540, the bottom, middle, and top sections of the ferroelectric layer 400 are programmed to have one polarization state, resulting in the FeRAM generating the highest sense current. In a second example where a center voltage is applied to the gate metal 540, only the center and top sections of the ferroelectric layer 400 may be programmed to have one polarization state, while the center voltage may not be large enough to program the bottom section, resulting in the bottom section having a different polarization state than the center and top sections, thereby generating a smaller sense current than the first example. In a third example, where a low voltage is applied to the gate metal 540, only the top section of the ferroelectric layer 400 can be programmed to have one polarization state, while the low voltage may not be large enough to program the middle and bottom sections, resulting in the middle and bottom sections having a different polarization state than the top section, thereby generating a smaller sense current than in the first and second examples. In a fourth example, where no voltage is applied to the gate metal 540, the polarization states of the bottom, middle, and top sections remain different from the first example, and the FeRAM generates no sense current. It is clear from the above that embodiments of the present invention provide an FeRAM that can have multiple, e.g., four, logic states. However, embodiments of the present invention are not limited in this respect. For example, more or fewer different sections of the ferroelectric layer may be used to create a ferroelectric random access memory with more or fewer different logic states.

[0056] FIG. 25 is an illustration of a flow chart of a method for fabricating a ferroelectric random access memory (FeRAM) cell according to an embodiment of the present invention. The method includes the steps of: (901) forming a vertical channel on a bottom epitaxial layer, the bottom epitaxial layer forming bottom source / drain regions; (902) forming bottom spacers of a dielectric material on the bottom source / drain regions, the bottom spacers surrounding the bottom of the vertical channel; (903) forming a gate oxide on the side of the vertical channel, the gate oxide may be formed, for example, by an oxidation process of the side of the vertical channel; (904) forming a first layer of ferroelectric material surrounding a first section of the vertical channel; (905) forming a second layer of ferroelectric material surrounding a second section of the vertical channel and the first layer of ferroelectric material; (906) forming a third layer of ferroelectric material surrounding a third section of the vertical channel and the second layer of ferroelectric material; (907) forming a gate metal surrounding the third layer of ferroelectric material; and (908) forming top spacers of ferroelectric material and top epitaxial source / drain regions.

[0057] It should be understood that the exemplary methods described herein can be readily incorporated into other semiconductor process flows, semiconductor devices, and integrated circuits comprising various analog, digital, or mixed-signal circuits. In particular, integrated circuit dies can be fabricated with a variety of devices, such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention can be employed in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention may include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the techniques of the present invention.

[0058] Thus, at least a portion of one or more semiconductor structures described herein may be implemented in an integrated circuit. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips may be implemented in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with surface and / or buried interconnects). In either case, the chip may then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product such as a motherboard or a final product. The final product may be any product containing the integrated circuit chip, from a toy or other low-end application to a sophisticated computer product with a display, keyboard or other input device, and central processing unit.

[0059] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive, and the present invention is not limited to the disclosed embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical applications or technical improvements over commercially available technology, and to enable those skilled in the art to understand the embodiments disclosed herein. Numerous modifications, substitutions, changes, and equivalents will occur to those skilled in the art. Such modifications, alterations, and / or alternative embodiments can be made without departing from the scope of the present invention, and are all considered and deemed to be within the scope of the present invention herein. It is therefore to be understood that the appended claims are intended to cover all such modifications and alterations that fall within the scope of the present invention.

Claims

1. a vertical channel between the bottom source / drain region and the top source / drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide; Equipped with A ferroelectric random access memory (FeRAM) cell, wherein the ferroelectric layer has two or more sections with different horizontal thicknesses between the bottom source / drain region and the top source / drain region.

2. 2. The FeRAM cell of claim 1, further comprising a gate metal surrounding said ferroelectric layer, wherein said gate metal has two or more horizontal thicknesses that complement said different horizontal thicknesses of said two or more sections of said ferroelectric layer.

3. 10. The FeRAM cell of claim 1, wherein the ferroelectric layer comprises a bottom section, a middle section, and a top section of three different horizontal thicknesses, the three different horizontal thicknesses being arranged in a stepped pattern.

4. 4. The FeRAM cell of claim 3, wherein the top section of the ferroelectric layer is adapted to be programmed to have a polarization state different from the polarization states of the middle and bottom sections.

5. 4. The FeRAM cell of claim 3, wherein the top and middle sections of the ferroelectric layer are adapted to be programmed to have a polarization state different from a polarization state of the bottom section.

6. 10. The FeRAM cell of claim 1, wherein said ferroelectric layer comprises doped hafnium oxide.

7. 10. The FeRAM cell of claim 1, wherein the difference in horizontal thickness between two of said two or more sections of said ferroelectric layer is at least 0.5 nm.

8. a vertical channel between a bottom source / drain region and an upper source / drain region; a gate oxide surrounding the vertical channel; a ferroelectric layer surrounding the gate oxide; and A gate metal surrounding the ferroelectric layer Equipped with A ferroelectric random access memory (FeRAM) cell, wherein the ferroelectric layer has a bottom section, a middle section, and a top section arranged in a stepped manner.

9. 9. The FeRAM cell of claim 8, wherein the bottom section, the middle section, and the top section of the ferroelectric layer have a first horizontal thickness, a second horizontal thickness, and a third horizontal thickness, respectively, and the second horizontal thickness is greater than the third horizontal thickness but less than the first horizontal thickness.

10. 9. The FeRAM cell of claim 8, wherein the bottom section, the middle section, and the top section of the ferroelectric layer have a first vertical height, a second vertical height, and a third vertical height, respectively, the second vertical height being less than the third vertical height but greater than the first vertical height.

11. 9. The FeRAM cell of claim 8, wherein the top section of the ferroelectric layer is adapted to be programmed to have a first polarization state, and the middle and bottom sections of the ferroelectric layer are adapted to be programmed to have a second polarization state, the second polarization state being different from the first polarization state.

12. 9. The FeRAM cell of claim 8, wherein the top and middle sections of the ferroelectric layer are adapted to be programmed to have a first polarization state, and the bottom section of the ferroelectric layer is adapted to be programmed to have a second polarization state, the second polarization state being different from the first polarization state.

13. 9. The FeRAM cell of claim 8, wherein the top section, the middle section, and the bottom section of the ferroelectric layer have a lateral thickness difference of at least 0.5 nm.

14. 1. A method of forming a ferroelectric random access memory (FeRAM) cell, comprising: forming a vertical channel on the bottom epitaxial layer; forming a gate oxide on the sides of the vertical channel; forming a first layer of ferroelectric material surrounding a first section of the vertical channel; forming a second layer of ferroelectric material surrounding a second section of the vertical channel and the first layer of ferroelectric material; forming a third layer of ferroelectric material surrounding a third section of the vertical channel and the second layer of ferroelectric material; forming a gate metal surrounding the third layer of ferroelectric material; and forming an upper epitaxial layer over the vertical channel.

15. forming the first layer of ferroelectric material comprises: forming a first conformal layer of ferroelectric material surrounding the vertical channel; covering a first portion of the first conformal layer of ferroelectric material with a first sacrificial material layer, the first portion having a vertical height corresponding to the first section of the vertical channel; and removing exposed portions of the first conformal layer of ferroelectric material not covered by the first layer of sacrificial material.

15. The method of claim 14, comprising:

16. forming the second layer of ferroelectric material comprises: forming a second conformal layer of ferroelectric material surrounding the first layer of ferroelectric material and a portion of the vertical channel not covered by the first layer of ferroelectric material; covering a second portion of the second conformal layer of ferroelectric material with a second sacrificial material layer, the second portion having a vertical height corresponding to the sum of the first and second sections of the vertical channel; and 16. The method of claim 15, comprising removing exposed portions of the second conformal layer of ferroelectric material that are not covered by the second sacrificial material layer.

17. forming the third layer of ferroelectric material comprises: forming a third conformal layer of ferroelectric material surrounding the second layer of ferroelectric material and a portion of the vertical channel not covered by the second layer of ferroelectric material; covering a third portion of the third conformal layer of ferroelectric material with a third sacrificial material layer, the third portion having a vertical height corresponding to the sum of the first section, the second section, and the third section of the vertical channel; and 17. The method of claim 16, comprising removing exposed portions of the third conformal layer of ferroelectric material that are not covered by the third sacrificial material layer.

18. 20. The method of claim 17, further comprising, after removing the exposed portion of the third conformal layer of ferroelectric material to expose a remainder of the vertical channel therebelow, forming a top spacer surrounding the remainder of the vertical channel.

19. 15. The method of claim 14, wherein forming the gate oxide comprises exposing the vertical channel to an oxygen-containing environment to oxidize the side surfaces of the vertical channel.

20. 15. The method of claim 14, further comprising forming a bottom spacer on the bottom epitaxial layer surrounding the vertical channel before forming the gate oxide.

21. A computer program comprising program code adapted to perform the steps of the method according to any one of claims 14 to 20 when the computer program is run on a computer.

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