Carbon mold for DRAM capacitors

Abstract

A memory device and a method for forming the memory device are described. A method for forming an electronic device using carbon as a removable mold material for forming a DRAM capacitor is described. A dense, high-temperature (above 500°C) PECVD carbon material is used instead of oxide as the removable mold material, e.g., core material. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide an electronic device that includes carbon as a removable molding material in the formation of DRAM capacitors. [Background technology]

[0002]

[0002] Manufacturing DRAM is a competitive business. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but must be periodically reprogrammed or "refreshed" to maintain this voltage for more than a very short period of time. DRAM memory circuits are manufactured by replicating billions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0003] There is a continuing need to reduce the size of individual DRAM cells and increase memory cell density to allow more memory to be packed onto a single memory chip, especially at densities above 8 gigabits. Reducing cell size is subject to limitations such as the need to route both bit and word lines through the cell, the size of the cell capacitor, and the compatibility of array and non-array devices.

[0004] A significant barrier to further shrinking the size of DRAMs is maintaining sufficient cell capacitance with good leakage and low density of cell-to-cell shorts. The average spacing between cells is 15 to 20 nm to accommodate high-k dielectrics and have at least a 10 nm margin for cell-to-cell leakage.

[0005] Another challenge in scaling DRAM size is the small capacitor pitch on a hexadecimal layout, which is equal to the bitline (BL) pitch. Fixing the gap between holes so that high aspect ratio (HAR) etching meets the final minimum gap of 12 nm means that hole size shrinks rapidly. The etching profile must be as vertical as possible, which requires highly selective etch mask materials. Traditionally, silicon oxide (SiOx) has been used as the film to be etched and subsequently removed in HAR capacitors, utilizing the outer surface of the titanium nitride (TiN) electrode to form the capacitor on top of it. This film is called the "mold" oxide, or "core."

[0006] In a pre-clean before depositing the bottom electrode, e.g., TiN, the oxide is isotropically etched. This wet etch can be used to help straighten the tapered etch profile, but the initial critical dimension (CD) must be small to account for post-clean CD growth, which means a higher aspect ratio for HAR reactive ion etching (RIE).

[0007]

[0007] Oxide mold removal must be performed isotropically, and strong hydrofluoric acid (HF) is used to remove the mold oxide with high selectivity to the support layer (SiN-based) in the mold. However, 100 Å to 300 Å of the support layer is removed during this HF etching process, which means that the deposition thickness must be increased by 200 Å to 600 Å, making HAR reactive ion etching (RIE) difficult. Therefore, there is a need in the art for a DRAM capacitor material and method of formation that avoids these problems. Summary of the Invention

[0008]

[0008] One or more embodiments of the present disclosure are directed to a semiconductor device comprising a plurality of pillars extending through a mold stack including a first core carbon layer on an etch stop layer on a substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, and a hard mask layer on the second support layer.

[0009] An additional embodiment of the present disclosure is directed to a method of forming a semiconductor device. In one or more embodiments, the method includes forming a mold stack on an etch stop layer on a substrate, the mold stack including a first core carbon layer on the etch stop layer on the substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, a hard mask layer on the second support layer, and a hard mask release layer on the hard mask layer; etching a plurality of openings in the mold stack, the plurality of openings extending from the top surface of the hard mask release layer to the top surface of the substrate; conformally depositing an electrode layer in the plurality of openings; depositing a core layer on the electrode layer; performing a high aspect ratio etch to remove a portion of the first support layer and a portion of the second support layer; and exposing the mold stack to an isotropic etch to remove the first core carbon layer and the second core carbon layer.

[0010]

[0010] In order that the features of the present disclosure described above may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments. The embodiments described herein are presented by way of example and not by way of limitation to the figures of the accompanying drawings, in which like references indicate similar elements. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a process flow diagram illustrating a method according to one or more embodiments. [Figure 2] 1 is a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 3] 1 is a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 4A-4B] 4A is a top view of the DRAM device of FIG. 3 according to one or more embodiments, and 4B is a top view of the DRAM device of FIG. 3 according to one or more alternative embodiments. [Figure 5] 1 is a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 6] 1 is a cross-sectional view of a DRAM device according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0018] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0019] As used herein and in the appended claims, the term "substrate" refers to a surface, or a portion of a surface, upon which a process acts. Also, unless the context clearly indicates otherwise, those skilled in the art will understand that a reference to a substrate may refer to only a portion of a substrate. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0014]

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0021] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates direct contact between elements, with no intervening elements.

[0016]

[0022] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0017]

[0023] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. A substrate or a portion of a substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to deposit and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or materials on the substrate surface, are simultaneously exposed to two or more reactive compounds, so that no point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used herein and in the appended claims, the term "substantially" as used in this context means that, as will be understood by those skilled in the art, small portions of the substrate may be simultaneously exposed to multiple reactive compounds due to diffusion, and simultaneous exposure is not intended.

[0018]

[0024] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process, with the purge gas flowing only during the time delay between pulses of reactive compounds. The reactive compounds are pulsed alternately until the desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, purge gas is one cycle. The cycle can begin with either compound A or compound B and continue in the respective order of the cycle until a film of the desired thickness is achieved.

[0019]

[0025] In a spatial ALD process embodiment, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously delivered to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. By moving the substrate relative to the gas delivery device, every point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0020]

[0026] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or when there is a significant overlap in the exposure of the precursors.

[0021]

[0027] Plasma-enhanced chemical vapor deposition (PECVD) is widely used for the deposition of thin films due to its cost-effectiveness and versatility in film properties. In a PECVD process, a hydrocarbon source, such as a gaseous or liquid hydrocarbon vapor entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-generated gas, typically helium, is also introduced into the chamber. A plasma is then generated in the chamber, generating excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate positioned in the chamber to form a desired film thereon. The embodiments described herein with respect to PECVD processes can be implemented using any suitable thin film deposition system. Any apparatus descriptions provided herein are exemplary and should not be construed or interpreted as limiting the scope of the embodiments described herein.

[0022]

[0028] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores datum bits by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) on a capacitor. The charge is gated onto the capacitor through an access transistor and sensed by turning on the same transistor and observing the voltage fluctuation caused by dumping the charge packet onto an interconnect line at the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor.

[0023]

[0029] As used herein, the term "capacitor" refers to an electrical component of a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material.

[0024]

[0030] As used herein, the phrase "amorphous hydrogenated carbon," also known as "amorphous carbon" and written as aC:H, refers to a carbon material lacking long-range crystalline order that may contain substantial hydrogen content, e.g., on the order of about 10 atomic % to 45 atomic %. Amorphous carbon has been used as a hard mask material in semiconductor applications due to its chemical inertness, optical transparency, and good mechanical properties.

[0025]

[0031] One or more embodiments provide a DRAM capacitor with carbon as a removable core or as a removable mold material instead of oxide. Other embodiments provide a method for fabricating a DRAM capacitor with carbon as a removable core material. In one or more embodiments, a dense, high-temperature (above 500°C) plasma enhanced chemical vapor deposition (PECVD) carbon material is used as a removable mold material instead of an oxide material.

[0026]

[0032] In one or more embodiments, a carbon deposition process is needed that can be deposited on SiN-based films used for etch stop layers and films used as intermediate support layers. Thus, in one or more embodiments, a SiN-based film that can be deposited on carbon is needed.

[0027]

[0033] In one or more embodiments, titanium nitride (TiN) or other metal nitride films are needed that can be deposited on carbon and still retain the R and electrode properties necessary to form a DRAM capacitor.

[0028]

[0034] In one or more embodiments, a suitable hard mask film is required that has very high selectivity to carbon etch chemistries and etches "through" the intermediate support layer.

[0029]

[0035] In one or more embodiments, small, high aspect ratio openings in the support layer require an isotropic etching process to remove the carbon.

[0030]

[0036] In one or more embodiments, 400 to 600 nm of 500° C. PECVD carbon is deposited on a standard existing silicon boronitride (SiBN) etch stop layer. Approximately 15 nm of carbon-doped silicon nitride (SiCN) film is deposited as the middle support layer. In some embodiments, one or more of silicon oxide (SiOx) or silicon oxynitride (SiON) may be the middle and top support layers. In some embodiments, 3 to 10 nm or approximately 5 nm of silicon oxynitride (SiON and the remainder silicon oxide (SiOx)) may be the middle and top support layers. Approximately 300 to 400 nm of 500° C. PECVD carbon layer is deposited on the carbon-doped silicon nitride (SiCN) to form the top mold carbon. Then, approximately 80 to 100 nm of carbon-doped silicon nitride (SiCN) layer is deposited on the top core carbon to form the top support. In one or more embodiments, the carbon deposition process advantageously forms adhesion to SiN-based films to prevent delamination. In one or more embodiments, the carbon-doped silicon nitride (SiCN) deposition process advantageously forms adhesion to carbon to prevent delamination, although other applications may use silicon nitride (SiN) films.

[0031]

[0037] In one or more embodiments, atomic layer deposition (ALD) titanium tetrachloride (TiCl4) at 400°C to 500°C is used to deposit low resistivity (<500 μΩ·cm) TiN within the HAR carbon pores.

[0032]

[0038] In one or more embodiments, boron nitride (BN) based films are used as hard mask films with very little silicon in the film, thus allowing for very small holes that do not "clog" during the HAR etching process.

[0033]

[0039] In one or more embodiments, the etching chamber used to drill holes in the support layer after the formation of the bottom electrode, e.g., TiN, is used to isotropically remove some or all of the mold carbon using a combination of O and NH radicals.

[0034]

[0040] Embodiments of the present disclosure are described with reference to figures illustrating devices (e.g., DRAMs) and processes for forming DRAMs according to one or more embodiments of the present disclosure. The illustrated processes are merely exemplary of possible applications of the disclosed processes, and one skilled in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0035]

[0041] Exemplary embodiments are described herein with reference to cross-sectional diagrams that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the illustrated shapes are expected, e.g., as a result of manufacturing techniques and / or tolerances. Accordingly, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein and may include deviations in shape due to, for example, manufacturing. For example, an implanted region illustrated as a rectangle may typically have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary transition from implanted to non-implanted region. Similarly, buried regions formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs. Accordingly, the illustrated regions are schematic in nature, and their shapes may not be intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0036]

[0042] Figure 1 is a process flow diagram illustrating a method 10 for forming a semiconductor device according to some embodiments of the present disclosure. Figures 2-6 are cross-sectional views illustrating a semiconductor device according to one or more embodiments. Method 10 is described below with respect to Figures 2-6. Method 10 may be part of a multi-step manufacturing process for semiconductor devices, particularly DRAMs.

[0037]

[0043] In one or more embodiments, method 10 can be performed in any suitable process chamber coupled to a cluster tool, which may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0038]

[0044] Referring to Figure 1, in step 12 of method 10, a mold stack for a capacitor is provided. As used herein and in the appended claims, the term "provided" means that the mold stack is made available for processing (e.g., positioned in a processing chamber). In one or more embodiments, the mold stack is first formed by a series of deposition steps, as described below with respect to Figure 2. In step 14, holes are etched. In step 16, pillars are formed (i.e., bottom electrode deposition). In step 18, HAR holes are patterned and etched into the support layer. In step 20, the carbon layer is isotropically removed. In step 22, the stack can be optionally post-processed.

[0039]

[0045] FIG. 2 is a cross-sectional view illustrating a mold stack of layers used in forming a DRAM capacitor. In one or more embodiments, stack 100 includes an etch stop layer 104 formed on a substrate 102. Etch stop layer 104 may include any suitable material known to those skilled in the art. In one or more embodiments, etch stop layer 104 includes a conformal layer of dielectric material; one or more of SiN, SiCN, SiBN, SiON, and combinations thereof. Etch stop layer 104 may be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, etch stop layer 104 is deposited using a technique selected from CVD, PECVD, and ALD deposition. Etch stop layer 104 may have any suitable thickness known to those skilled in the art. In one or more embodiments, etch stop layer 104 has a thickness in the range of 0.7 nm to 70 nm, including the range of 1.75 nm to 28 nm, including the range of 3.5 nm to 14 nm.

[0040]

[0046] In one or more embodiments, a first core carbon layer 106 a is deposited on top of the etch stop layer 104 .

[0041]

[0047] In one or more embodiments, the first core carbon layer 106a may be deposited at very high temperatures and have a low hydrogen (H) content. In one or more embodiments, the first core carbon layer 106a comprises a dense high-temperature (above 500°C) plasma enhanced chemical vapor deposition (PECVD) carbon material. In some embodiments, the first core carbon layer 106a comprises a predominantly sp 2 may result in a lower density and modulus, which in some circumstances may result in an advantageously higher lateral etch rate or improved etch rate for RIE or isotropic removal etching.

[0042]

[0048] In one or more embodiments, the high sp 3 An amorphous carbon material is advantageously deposited as the first core carbon layer 106a. In one or more embodiments, the deposition is performed at low temperature using a diamond precursor.

[0043]

[0049] In one or more embodiments, the density and, more importantly, Young's modulus of the first core carbon layer 106a are improved to achieve higher etch selectivity. One of the main challenges to achieving higher etch selectivity and improved Young's modulus is the high compressive stress of the film, which results in high wafer warpage, making it unsuitable for certain applications. Therefore, a high density and elastic modulus (e.g., higher sp) with low stress (e.g., less than -500 MPa) and high etch selectivity is desired. 3 There is a need for carbon (diamond-like) films with a higher diamond-like content.

[0044]

[0050] As used herein, the terms "diamond-like" and / or "diamonoid" refer to a class of chemical compounds that have a diamond crystal lattice. Diamondoids can contain one or more carbon cages (e.g., adamantane, diamantane, triamantane, and higher polymantanes). Adamantane-based diamondoids are hydrocarbons composed of fused cyclohexane rings, forming linked cage structures. Diamondoids are substituted and unsubstituted cage-like compounds. These chemical compounds may be naturally occurring or can be synthesized. Diamondoids have high sp 3 They have a high carbon:hydroxide content and a high carbon:hydrogen ratio. In a general sense, diamond-like carbon materials are tough, rigid structures with a dense three-dimensional network of covalent bonds.

[0045]

[0051] In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is greater than 1.8 g / cc, including greater than 1.9 g / cc, and greater than 2.0 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is about 2.1 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b ranges from greater than about 1.8 g / cc to about 2.2 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is greater than about 2.2 g / cc.

[0046]

[0052] 2, in one or more embodiments, the first core carbon layer 106a may have any suitable thickness known to those of ordinary skill in the art. In one or more embodiments, the first core carbon layer 106a has a thickness ranging from 60 nm to 6000 nm, including from 150 nm to 2400 nm, including from 300 nm to 1200 nm, and including from 400 nm to 700 nm.

[0047]

[0053] In one or more embodiments, the first core carbon layer 106a may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the first core carbon layer 106a is deposited by plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, PECVD may be performed at any suitable temperature. In a specific embodiment, PECVD deposition of the first core carbon layer 106a is performed at a temperature in the range of 300°C to 700°C, including the range of 400°C to 600°C, including the range of 450°C to 550°C.

[0048]

[0054] 2, a first support layer 108a is deposited on top of the first core carbon layer 106a. The first support layer 108a may comprise any suitable material known to those skilled in the art. In one or more embodiments, the first support layer 108a comprises a dielectric material.

[0049]

[0055] As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric layer includes one or more of oxide, carbon-doped oxide, silicon oxide (SiOx), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), and silicon carbonitride (SiCN). In one or more embodiments, the dielectric layer includes, but is not limited to, furnace, CVD, PVD, ALD, and spin-on-coat (SoC) deposited films. In one or more embodiments, the dielectric layer may be exposed to in situ or ex situ pre- and post-treatment processes to dope, infuse, implant, heat, freeze, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the surface or bulk of the dielectric. In one or more specific embodiments, the first support layer 108a comprises silicon nitride (SiN). The silicon nitride (SiN) may be doped or undoped. In some embodiments, the silicon nitride is doped with carbon (SiCN).

[0050]

[0056] In one or more embodiments, the first support layer 108a may have any suitable thickness. In some embodiments, the first support layer 108a has a thickness in the range of 2 nm to 100 nm, including the range of 5 nm to 50 nm, including the range of 10 nm to 20 nm. Also, more than one support layer may be present in the carbon mold to balance the need for increased mechanical support with the increased complexity and difficulty of reactive ion etching (RIE) of the film stack.

[0051]

[0057] 2, a second core carbon layer 106b is deposited on top of the first support layer 108a. The second core carbon layer 106b may comprise any suitable material known to those skilled in the art. In some embodiments, the second core carbon layer 106b comprises the same material as the first core carbon layer 106a described above.

[0052]

[0058] In one or more embodiments, the second core carbon layer 106b is deposited at a very high temperature and may have a low hydrogen (H) content. In one or more embodiments, the second core carbon layer 106b comprises a dense high-temperature (above 500°C) plasma enhanced chemical vapor deposition (PECVD) carbon material. In some embodiments, the second core carbon layer 106b comprises a predominantly sp 2 This can result in lower density and modulus, which in some circumstances can lead to lower etch selectivity and pattern integrity. Modulus is a measure of the mechanical strength of the film.

[0053]

[0059] In one or more embodiments, the high sp 3 An amorphous carbon material is advantageously deposited as the second core carbon layer 106b. In one or more embodiments, the deposition is carried out at low temperatures using diamondoid precursors.

[0054]

[0060] In one or more embodiments, the second core carbon layer 106b may have any suitable thickness known to those of ordinary skill in the art. In one or more embodiments, the second core carbon layer 106b has a thickness that is less than the thickness of the first core carbon layer 106a. In one or more embodiments, the second core carbon layer 106b has a thickness in the range of 45 nm to 4500 nm, including the range of 110 nm to 1800 nm, and including the range of 225 nm to 900 nm.

[0055]

[0061] In one or more embodiments, the second core carbon layer 106b may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the second core carbon layer 106b is deposited by plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, PECVD may be performed at any suitable temperature. In a specific embodiment, PECVD deposition of the second core carbon layer 106b is performed at a temperature in the range of 300°C to 700°C, including the range of 400°C to 600°C, including the range of 450°C to 550°C.

[0056]

[0062] 2, a second support layer 108b is deposited on top of the second core carbon layer 106b. The second support layer 108b may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second support layer 108b comprises the same material as the first support layer 108a. In one or more embodiments, the second support layer 108b comprises a dielectric material.

[0057]

[0063] In one or more embodiments, the second support layer 108b includes one or more of oxide, carbon-doped oxide, silicon oxide (SiOx), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), and silicon carbonitride (SiCN). In one or more specific embodiments, the second support layer 108b includes silicon nitride (SiN). The silicon nitride (SiN) may be doped or undoped. In some embodiments, the silicon nitride is doped with carbon (SiCN). The upper support layer may also include all or a portion of the hard mask film remaining after RIE etching.

[0058]

[0064] In one or more embodiments, the second support layer 108b can have any suitable thickness. In one or more embodiments, the second support layer 108b has a thickness that is greater than the thickness of the first support layer 108a. In some embodiments, the top support layer 108b has a thickness in the range of 8 nm to 800 nm, including in the range of 20 nm to 300 nm, including in the range of 30 nm to 150 nm.

[0059]

[0065] Without intending to be bound by theory, it is believed that the deposition of the first core carbon layer 106a and the deposition of the second core carbon layer 106b form an adhesion to the lower etch stop layer 104 and the first support layer 108a, respectively, thereby advantageously preventing the first support layer 108a and the second support layer 108b from separating or peeling off.

[0060]

[0066] 2, a hard mask layer 110 is deposited on top of the second support layer 108b. The hard mask layer 110 may include any suitable material known to those skilled in the art. In one or more embodiments, the hard mask layer 110 includes one or more of silicon oxide (SiOx), silicon carbide (SiC), boron, and boron nitride (BN). In one or more specific embodiments, the hard mask layer 110 includes boron nitride (BN).

[0061]

[0067] Hard mask layer 110 can have any suitable thickness. In one or more embodiments, hard mask layer 110 has a thickness in the range of 20 nm to 1000 nm, including in the range of 30 nm to 500 nm, including in the range of 50 nm to 300 nm.

[0062]

[0068] Referring to FIG. 2 , a hard mask release layer 112 is deposited on top of the hard mask layer 110. The hard mask release layer 112 can include any suitable material. In one or more embodiments, the hard mask release layer 112 includes carbon or silicon oxide (SiOx). In some embodiments, the hard mask release layer 112 includes the same material as the first core carbon layer 106a. In other embodiments, the hard mask release layer 112 includes the same material as the second core carbon layer 106b. The hard mask release layer 112 can have any suitable thickness. In one or more embodiments, the hard mask release layer 112 has a thickness in the range of 20 nm to 1000 nm, including the range of 30 nm to 500 nm, including the range of 50 nm to 300 nm.

[0063]

[0069] 3 is a cross-sectional view 100 illustrating a mold stack of layers used to form a DRAM capacitor having a plurality of openings 114 etched therein. Referring to FIGS. 1 and 3, in step 14, in one or more embodiments, a plurality of openings 114 are formed in the stack by etching from the top surface of the hard mask release layer 112 through the hard mask layer 110, through the second support layer 108b, through the second core carbon layer 106b, through the first support layer 108a, through the first core carbon layer 106a, and through the etch stop layer 104 to expose the top surface of the substrate 102. Thus, in one or more embodiments, each of the plurality of openings 114 extends from the top surface of the hard mask release layer 112 to the top surface of the substrate 102.

[0064]

[0070] In one or more embodiments, sidewall surfaces 115, 117, 119, 121, 123, 125, 127 and bottom 116 are formed in stack opening 114. In one or more embodiments, opening 114 extends from the top surface of hard mask release layer 112 to the bottom surface of substrate 102.

[0065]

[0071] 4A is a top view of the DRAM device of FIG. 3 according to one or more embodiments. Openings 114 are visible in the hard mask release layer 112.

[0066]

[0072] 4B is a top view of the DRAM device of FIG. 3 according to one or more alternative embodiments. Openings 114A and 114B are visible in hard mask release layer 112. In one or more embodiments, the size of second HARC pattern holes or openings 114B is larger than the size of first HARC pattern holes or openings 114A, and there are one-third as many openings 114B as there are openings 114A.

[0067]

[0073] 5 is a cross-sectional view 100 illustrating a mold stack of layers used to form a DRAM capacitor with a plurality of openings 114 filled to form pillars. Referring to FIGS. 1 and 5, in step 16, a pillar bottom electrode layer 116 may be deposited in the plurality of openings 114 by any suitable technique known to those skilled in the art. In some embodiments, the pillar bottom electrode layer 116 may be deposited by atomic layer deposition (ALD).

[0068]

[0074] The pillar bottom electrode layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the pillar bottom electrode layer 116 includes one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten (W). In one or more embodiments, atomic layer deposition (ALD) titanium nitride (TiN) using titanium tetrachloride (TiCl4) at 400° C. to 500° C. is used to deposit low resistivity (<500 μΩ·cm) TiN within the HAR openings 114.

[0069]

[0075] In one or more embodiments, the pillar bottom electrode layer 116 is conformally deposited in each of the plurality of openings 114. As used herein, the term "conformal" means that the layer conforms to the contours of the feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of a feature to the average thickness of the same layer deposited on the processing area or top surface of the substrate. In one or more embodiments, the pillar bottom electrode layer 116 has a thickness in the range of 1 nm to 50 nm, including the range of 3 nm to 20 nm, including the range of 4 nm to 10 nm. The film may partially fill the holes or may completely fill them.

[0070]

[0076] Referring to FIG. 5 , a pillar core layer 118 is deposited in the plurality of openings 114 on the pillar bottom electrode layer 116. The pillar core layer 118 may be deposited by any suitable means known to those skilled in the art, including, but not limited to, ALD, CVD, PVD, etc. In one or more embodiments, the deposition of the pillar core layer 118 is the final gap-fill process. In one or more embodiments, the pillar core layer 118 has a thickness in the range of 1 nm to 50 nm, including in the range of 3 nm to 20 nm, including in the range of 4 nm to 10 nm. The film may partially fill the holes or may completely fill them.

[0071]

[0077] The pillar core layer 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the pillar core layer 118 includes polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin-on dielectric (SOD) glass, organosilicate glass (SiOCH), or silicon carbonitride (SiCN).

[0072]

[0078] 6 is a cross-sectional view 100 illustrating a mold stack of layers used to form a DRAM capacitor with the first core carbon layer 106a and the second core carbon layer 106b removed. Referring to FIGS. 1 and 6, in step 18, high aspect ratio (HAR) holes are patterned and etched into the support layers 108a, 108b. In one or more embodiments, the etching comprises reactive ion etching (RIE). In one or more embodiments, an etch chamber is used to open the holes in the support layers 108a, 108b after the pillar bottom electrode layer 116 is formed.

[0073]

[0079] In step 20, the first core carbon layer 106a and the second core carbon layer 106b are isotropically etched away to form the first core opening 120a and the second core opening 120b. In one or more embodiments, the first core carbon layer 106a and the second core carbon layer 106b are isotropically etched away using a suitable chemistry of nitrogen (N), hydrogen (H), oxygen (O), and / or ammonia (NH). In one or more embodiments, all of the mold carbon is isotropically removed using a combination of O, N, H, and NH radicals.

[0074]

[0080] In one or more embodiments, the first core carbon layer 106a and the second core carbon layer 106b can be isotropically removed in the same chamber as the etching of the support layers 108a, 108b, saving costs and eliminating wet processes that can cause pattern collapse.

[0075]

[0081] 1, the device may be optionally post-processed in step 22. Optional post-processing step 22 may be a process to modify film properties (e.g., annealing or plasma treatment) or a further film deposition process prior to the final deposition of a suitable dielectric material, for example, by ALD and / or CVD processes to form a DRAM capacitor.

[0076]

[0082] The use of the terms "a," "an," and "the" and similar referents in the context of describing the materials and methods described herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if the value were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise stated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better clarify the materials and methods and does not impose a limitation on scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0077]

[0083] As used throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0078]

[0084] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a plurality of pillars extending through a mold stack, the mold stack including: a first core carbon layer on an etch stop layer on a substrate; a first support layer on an upper surface of the first core carbon layer; a second core carbon layer on the first support layer; a second support layer on the second core carbon layer; and a hard mask layer on the second support layer; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein the first core carbon layer and the second core carbon layer independently comprise a diamond-like carbon material.

3. The diamond-like carbon material has more than 40% sp ３ The semiconductor device of claim 2 having a content of

4. The first support layer and the second support layer may be independently made of an oxide, a carbon-doped oxide, silicon dioxide (SiO ２ ), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or silicon carbonitride (SiCN).

5. The semiconductor device of claim 1 , wherein the first support layer and the second support layer comprise silicon carbonitride (SiCN).

6. The semiconductor device of claim 1 , wherein the first support layer comprises silicon nitride (SiN).

7. 10. The semiconductor device of claim 1, wherein the hard mask layer comprises one or more of silicon oxide (SiOx), silicon carbide (SiC), carbon-doped hydrogenated silicon oxide (SiOCH), boron, and boron nitride (BN).

8. 8. The semiconductor device of claim 7, wherein the hard mask layer comprises boron nitride (BN).

9. The semiconductor device of claim 1 , wherein the plurality of pillars include an electrode layer and a core layer.

10. 10. The semiconductor device of claim 9, wherein the electrode layer comprises one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

11. The core layer may be made of polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO ２ 10. The semiconductor device of claim 9, comprising one or more of silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin-on dielectric (SOD) glass, organosilicate glass (SiOCH), and silicon carbonitride (SiCN).

12. 10. The semiconductor device of claim 1, wherein the etch stop layer comprises SiN, SiCN, SiBN, SiON, and combinations thereof.

13. 1. A method of forming a semiconductor device, comprising: forming a mold stack on an etch stop layer on a substrate, the mold stack including: a first core carbon layer on the etch stop layer on the substrate; a first support layer on a top surface of the first core carbon layer; a second core carbon layer on the first support layer; a second support layer on the second core carbon layer; a hard mask layer on the second support layer; and a hard mask release layer on the hard mask layer; Etching a plurality of openings in the mold stack, the plurality of openings extending from a top surface of the hard mask release layer to a top surface of the substrate; conformally depositing an electrode layer in the plurality of openings; depositing a core layer on the electrode layer; performing a high aspect ratio etch to remove a portion of the first support layer and a portion of the second support layer; exposing the mold stack to an isotropic etch to remove the first core carbon layer and the second core carbon layer; A method comprising:

14. The isotropic etching is carried out using oxygen (O ２ ), nitrogen (N ２ ), hydrogen (H ２ ), ammonia (NH ３ 14. The method of claim 13, comprising exposing the compound to radicals of the formula (I) and combinations thereof.

15. The method of claim 13 , wherein the first core carbon layer and the second core carbon layer independently comprise a diamond-like carbon material.

16. The first support layer and the second support layer are independently selected from silicon carbonitride (SiCN), silicon nitride (SiN), and silicon dioxide (SiO ２ 14. The method of claim 13, comprising one or more of:

17. 14. The method of claim 13, wherein the hard mask layer comprises one or more of silicon oxide (SiOx), silicon carbide (SiC), carbon-doped hydrogenated silicon oxide (SiOCH), boron (B), and boron nitride (BN).

18. 18. The method of claim 17, wherein the hard mask layer comprises boron (B) or boron nitride (BN).

19. 14. The method of claim 13, wherein the electrode layer comprises one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

20. The core layer may be made of polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO ２ ), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin-on dielectric (SOD) glass, organosilicate glass (SiOCH), and silicon carbonitride (SiCN).

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