Repeater bubble detection

Abstract

In some examples, an apparatus includes circuitry configured to receive a communication on a first bus (602). The circuitry is also configured to provide the communication on a second bus for a first period of time (604). The circuitry is also configured to monitor a duration of providing the communication on the second bus (606). The circuitry is also configured to cease providing the communication on the second bus for a second period of time in response to the duration exceeding a threshold amount (608).

Description

[Technical Field]

[0001] USB (Universal Serial Bus) is a standard that defines interconnection cables, connectors, and communication protocols between peripheral devices. Embedded USB (eUSB) extends at least some of the USB protocols to interconnect interconnection cables, connectors, and communication protocols between individual subsystems or circuits (e.g., systems on chips (SoCs)). Summary of the Invention

[0002] In some examples, an apparatus includes a circuit including a repeater circuit element, a processing circuit, a first logic circuit, a second logic circuit, a timer circuit, and a third logic circuit. The repeater circuit element has first and second inputs and first and second outputs. The processing circuit has first and second outputs. The first logic circuit has an output and first and second inputs, the first input of the first logic circuit coupled to the second output of the processing circuit and the second input of the first logic circuit coupled to the second output of the repeater circuit element. The second logic circuit has an output and first and second inputs, the first input of the second logic circuit coupled to the output of the first logic circuit. The timer circuit has an output and first and second inputs, the first input of the timer circuit coupled to the output of the first logic circuit, the second input of the timer circuit coupled to the output of the second logic circuit and the output of the timer circuit coupled to the second input of the second logic circuit. The third logic circuit has an output and first and second inputs, the first input of the third logic circuit being coupled to the first output of the processing circuit, the second input of the third logic circuit being coupled to the output of the timer circuit, and the output of the third logic circuit being coupled to the second input of the repeater circuit element.

[0003] In some examples, an apparatus includes circuitry configured to receive a communication on a first bus. The circuitry is also configured to provide the communication on a second bus for a first period of time. The circuitry is also configured to monitor a duration of providing the communication on the second bus. The circuitry is also configured to stop providing the communication on the second bus for a second period of time in response to the duration exceeding a threshold amount.

[0004] In some examples, a method includes receiving data at a repeater via a first bus over consecutive first and second time periods. The method also includes providing data on a second bus of the repeater during the first time period. The method also includes monitoring a duration of the first time period. The method also includes disabling the repeater for a second time period in response to the duration exceeding a threshold amount. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an example system.

[0006] [Figure 2] FIG. 1 is a block diagram of exemplary high-speed (HS) components of a host-side repeater.

[0007] [Figure 3] FIG. 10 is a block diagram of example HS components of a peripheral side repeater.

[0008] [Figure 4] FIG. 2 is a block diagram of an example repeater.

[0009] [Figure 5] 4 is a timing diagram of exemplary signals.

[0010] [Figure 6] 1 is a flowchart of an example method.

[0011] [Figure 7] 1 is a flowchart of an example method.

[0012] [Figure 8] 1 is a flowchart of an example method. DETAILED DESCRIPTION OF THE INVENTION

[0013] As mentioned above, USB is a standard that establishes standards for interconnection cables, connectors, and communication protocols. As referred to herein, USB refers to any version of the USB standard, whether currently existing or later developed, including any amendments or supplements approved by the USB Implementers Forum (USB-IF) or any appropriate organization that replaces and / or supports the USB-IF in its role of overseeing the USB standard. In at least one example, USB as referred to herein encompasses any one or more of the USB 1.0 standard, the USB 2.0 standard, the USB 3.0 standard, the USB 4.0 standard, or any derivatives thereof, such as amended or "x" variants of the above standards. Also, as referred to herein, legacy USB refers to USB 2.x and / or USB 1.x. Embedded USB (eUSB) refers, at least in some examples, to eUSB 2.0 or eUSB 2. Although reference is made herein to eUSB2, in various examples, the teachings of this description may also be applicable to extensions, alternatives, derivatives of eUSB2, or other versions of eUSB2 that share at least some commonality or similarity with eUSB2. Thus, while eUSB2 is referred to herein in an exemplary manner, this description, in some examples, is not limited to implementation in an eUSB 2.0 environment, an eUSB2 environment, or a USB environment.

[0014] Initially, USB was primarily intended for implementation in defining a standard for connection and communication between personal computers and peripheral devices. However, as adoption of the USB standard has grown and implementations of supporting USB standards in computing devices have become widespread, efforts have been made to broaden and extend the applicability of USB. For example, while initially establishing specifications for communication between personal computers and peripheral devices, USB has been expanded to include communication between peripheral devices, communication between personal computers, and other use cases. As a result of such widespread implementation and use of USB, further efforts have been made to utilize USB as a communication protocol between individual subsystems or circuits (e.g., systems-on-chips (SoCs)). Such implementations are sometimes referred to as eUSB 2.0 or, more simply, eUSB 2. New challenges arise when implementing eUSB 2. For example, at the circuit level, computing devices often operate at voltage levels that differ from those of traditional USB, creating obstacles to direct communication between eUSB 2 and traditional USB systems. To mitigate this bottleneck, the eUSB2 repeater acts as a bridge or non-linear read / write bar between eUSB2 and legacy USB systems, or vice versa, translating between legacy USB signaling voltage levels, typically around 3.3 volts (V), and eUSB2 signaling voltage levels, which are circuit levels (e.g., silicon-appropriate voltages), such as around 1.0V, 1.2V, 1.4V, or any other suitable value less than 3.3V.

[0015] In some situations, a device continues signaling beyond the maximum packet duration specified in the communication standard (e.g., USB or eUSB2) with which it is communicating. For example, the maximum packet duration according to some communication standards or protocols may be approximately 20 microseconds (μs). A device that continues signaling beyond this maximum packet duration is said to be babbling. In an example of a communication system including a first device, an eUSB2 repeater, and a second device, where the first device signals data to the repeater, which relays the data to the second device, it may be possible for the second device to detect that the first device is babbling. However, while the repeater is relaying data to the second device, a signal from the second device informing the repeater that the first device is babbling may not be detectable by the repeater because the signaling line between the repeater and the second device is occupied by the data being relayed. To mitigate this, some repeaters may include a separate or dedicated reset pin or port outside of the pins or ports specified according to USB or eUSB2. However, this approach is not standardized and requires extra pins, thus increasing the space and cost of such implementations.

[0016] Examples of the present description provide a repeater that can detect a bubble condition and initiate a connection reset. For example, the repeater may monitor the amount of time the repeater is relaying data from a first device to a second device (or vice versa). In response to the amount of time exceeding a threshold amount, the repeater may be internally disabled to reset the repeater and / or prevent the repeater from relaying data received from the first device and resolve the bubble condition seen at the second device. In some examples, the first device detects the disablement of the repeater and ceases transmission in response to the disablement and disconnection of the repeater.

[0017] 1 is a block diagram of an exemplary system 100. In one example, the system 100 includes a host system 104 having a host device 116 and a repeater (e.g., an eUSB2 repeater) 118, and a peripheral system 108 having a peripheral device 122 and a repeater (e.g., an eUSB2 repeater) 124. The host system 104 is coupled to the peripheral system 108 via a bus 112, such as a USB 2.0 bus. The host device 116 is coupled to the eUSB2 repeater 118 (which may also be referred to as the host-side repeater 118) via an eUSB2 bus 120. The peripheral device 122 is coupled to the eUSB2 repeater 124 (which may also be referred to as the peripheral-side repeater 124) via an eUSB2 bus 126. In various examples, the host device 116 may be an application processor unit (APU), a microcontroller unit (MCU), a general-purpose processor, logic circuits, memory, analog circuitry, and / or a state machine. The peripheral systems 108 may include, for example, an external hard drive, a mouse, a printer, a keyboard, a display, logic circuitry, analog circuitry, and / or a processor.

[0018] In one example, bus 112 is an external connection between host system 104 and peripheral system 108, eUSB2 bus 120 is an interconnection between eUSB2 repeater 118 and host device 116, and eUSB2 bus 126 is an interconnection between eUSB2 repeater 124 and peripheral device 122.

[0019] In some examples, the peripheral system 108 may include the repeater 124, and the host system 104 may not include the repeater 118. In other examples, the host system 104 may include the repeater 118, and the peripheral system 108 may not include the repeater 124.

[0020] In operation, host device 116 transmits downstream packets over eUSB2 bus 120. Repeater 118 converts the downstream packets from eUSB2 signaling voltage levels (e.g., approximately 1.0V to 1.2V) to USB 2.0 signaling voltage levels (e.g., approximately 3.3V) and transmits the downstream packets over bus 112. Repeater 124 receives the downstream packets, converts the downstream packets from USB 2.0 signaling voltage levels (e.g., approximately 3.3V) to eUSB2 signaling levels (e.g., approximately 1.0V to 1.2V), and transmits the downstream packets to peripheral device 122 over eUSB2 bus 126.

[0021] The peripheral device 122 may respond to the host device 116 with upstream packets that are sent to the repeater 124 over the eUSB2 bus 126. The repeater 124 converts the upstream packets from eUSB2 signaling voltage levels to USB 2.0 signaling voltage levels and sends the upstream packets over the bus 112. The repeater 118 receives the upstream packets, converts the upstream packets from USB 2.0 signaling voltage levels to eUSB2 signaling voltage levels, and sends the upstream packets to the host device 116 over the eUSB2 bus 120.

[0022] As mentioned above, in some examples, the eUSB2 bus 126 may be busy (e.g., occupied) via downstream packets, etc. In such examples, the peripheral device 122 cannot send upstream packets to the repeater 124 via the eUSB2 bus 126. Therefore, in examples where the host system 104 is babbling, the peripheral device 122 cannot notify the repeater 124 of the babbling. To mitigate this, in some examples, the repeater 124 includes circuitry (not shown), programming, or a combination thereof, for detecting that the host system 104 is babbling. For example, in response to the repeater 124 receiving a continuous flow of data (e.g., data packets, etc.) from the host system 104 without interruption for longer than a programmed time, the repeater 124 determines that the host system 104 is babbling. In response to determining that the host system 104 is babbling, the repeater 124 disables relaying of received communications to the peripheral device 122. In some examples, the repeater 124 disables repeating of received communications until the bubble condition is resolved (e.g., the host system 104 stops sending data) or the peripheral device 122 resets the repeater 124.

[0023] Although this description considers an example in which the repeater 124 detects that the host system 104 is bubbling, other configurations are possible in various other examples. For example, the repeater 124 can detect that the peripheral device 122 is bubbling, the repeater 118 can detect that the peripheral device 122 is bubbling, the repeater 118 can detect that the host device 110 is bubbling, or any combination thereof.

[0024] 2 is a block diagram of high-speed (HS) components 200 of repeater 118, according to various examples. Repeater 118 includes an eUSB2 port 204 configured to interface with eUSB2 bus 120. As shown in FIG. 1, eUSB2 bus 120 provides a connection to host device 116. eUSB2 port 204 includes an eUSB2 transmitter 208 and an eUSB2 receiver 210. eUSB2 transmitter 208 transmits upstream packets to host device 116 via eUSB2 bus 120. eUSB2 receiver 210 receives downstream packets from host device 116 via eUSB2 bus 120. In one example, eUSB2 transmitter 208 and eUSB2 receiver 210 are implemented using or as buffers.

[0025] The eUSB2 port 204 includes a high speed squelch circuit (eHSSQ) 212 that detects downstream packets on the eUSB2 bus 120. The eHSSQ 212 may detect the start of packet (SOP) of a downstream packet transmitted by the host device 116 over the eUSB2 bus 120 and, in response, assert a squelch signal SQL1 indicating a downstream packet on the eUSB2 bus 120. In one example, to detect the SOP, the eHSSQ 212 detects the presence of a differential voltage on the data lines (e.g., the D+ and D− data lines) of the eUSB2 bus 120 and, in response, asserts a squelch signal SQL1 to indicate that the host device 116 has placed a downstream packet on the eUSB2 bus 120. The eUSB2 port 204 also includes a loss of signal (LOS) circuit 214 that detects the end of packet (EOP) on the eUSB2 bus 120 and, in response, asserts a LOS1 signal.

[0026] The repeater 118 also includes a USB 2.0 port 220 configured to interface with the bus 112. As shown in FIG. 1, the bus 112 provides a connection to the peripheral system 108. The USB 2.0 port 220 includes a USB 2.0 transmitter 224 and a USB 2.0 receiver 226. The USB 2.0 receiver 226 receives upstream packets from the peripheral system 108 via the bus 112. The USB 2.0 transmitter 224 transmits downstream packets to the peripheral system 108 via the bus 112. In one example, the USB 2.0 transmitter 224 and the USB 2.0 receiver 226 are implemented using or as buffers. In some examples, the eUSB2 port 204 operates at a different voltage (e.g., approximately 1 V to 1.2 V) than the USB2 port 220 (e.g., approximately 3 V). In these examples, the repeater 118 may include isolation (eg, galvanic isolation) between the eUSB2 port 204 and the USB2 port 220, allowing these ports to operate at different voltages.

[0027] The USB 2.0 port 220 includes a high-speed squelch circuit (HSSQ) 228 that detects upstream packets on the bus 112. The HSSQ 228 may detect the SOP of an upstream packet transmitted by the peripheral system 108 over the bus 112 and, in response, assert a squelch signal SQL2 to indicate an upstream packet. In one example, to detect the SOP, the HSSQ 228 detects the presence of a differential voltage on the data lines (e.g., the D+ and D− data lines) of the bus 112 and, in response, asserts the squelch signal SQL2 to indicate that the peripheral system 108 has placed an upstream packet on the bus 112. The USB 2.0 port 220 also includes a high-speed disconnect detect circuit (HSDSC) 232 that monitors for removal of peripheral HS termination from the bus 112. The HSDSC 232 asserts a DSC1 signal in response to a peripheral device disconnection from the bus 112.

[0028] 3 is a block diagram of HS components 300 of the repeater 124, according to various examples. The repeater 124 includes an eUSB2 port 304 configured to interface with the eUSB2 bus 126. As shown in FIG. 1, the eUSB2 bus 126 provides a connection to the peripheral device 122. The eUSB2 port 304 includes an eUSB2 receiver 308 and an eUSB2 transmitter 310. The eUSB2 receiver 308 receives upstream packets from the peripheral device 122 via the eUSB2 bus 126. The eUSB2 transmitter 310 transmits downstream packets to the peripheral device 122 via the eUSB2 bus 126. In one example, the eUSB2 receiver 308 and the eUSB2 transmitter 310 are implemented with or as buffers.

[0029] The eUSB2 port 304 includes a high speed squelch circuit (eHSSQ) 312 that detects upstream packets on the eUSB2 bus 126. The eHSSQ 312 may detect the SOP of an upstream packet transmitted by the peripheral device 122 over the eUSB2 bus 126 and, in response, assert a squelch signal SQL3 indicating an upstream packet on the eUSB2 bus 126. In one example, to detect the SOP, the eHSSQ 312 detects the presence of a differential voltage on the data lines of the eUSB2 bus 126 and, in response, provides a squelch signal SQL3 indicating that the peripheral device 122 has placed an upstream packet on the eUSB2 bus 126. The eUSB2 port 304 also includes an LOS circuit 314 that detects an end of packet (EOP) on the eUSB2 bus 126 and, in response, provides a LOS2 signal.

[0030] The repeater 124 also includes a USB 2.0 port 320 coupled to the bus 112. As shown in FIG. 1, the bus 112 provides a connection to the host device 116. The USB 2.0 port 320 includes a USB 2.0 receiver 324 and a USB 2.0 transmitter 326. The USB 2.0 receiver 324 receives downstream packets from the host device 116 via the bus 112. The USB 2.0 transmitter 326 transmits upstream packets to the host device 116 via the bus 112. In one example, the USB 2.0 receiver 324 and the USB 2.0 transmitter 326 are implemented using or as buffers. In some examples, the eUSB2 port 304 operates at a different voltage (e.g., approximately 1-1.2 V) than the USB2 port 320 (e.g., approximately 3 V). In these examples, the repeater 124 includes isolation (eg, galvanic isolation) between the eUSB2 port 304 and the USB2 port 320, isolating them so that they operate at different voltages.

[0031] The USB 2.0 port 320 includes a high-speed squelch circuit HSSQ 328 that detects downstream packets on the bus 112. The HSSQ 328 may detect the SOP of a downstream packet sent by the host device 116 and, in response, assert a squelch signal SQL4 indicating a downstream packet. In one example, to detect the SOP, the HSSQ 328 detects the presence of a differential voltage on the data lines of the bus 112 and, in response, provides SQL4 indicating that the host system 104 has placed a downstream packet on the bus 112.

[0032] In some examples, USB 2.0 port 320 also includes a fast disconnect HSDSC 332, but in other examples, HSDSC 332 is omitted, such as in examples where the peripheral device does not detect the disconnection through the data lines of bus 112. HSDSC 332 asserts the DSC2 signal in response to the disconnection of the host system from bus 112.

[0033] In one example, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 each include an enable input. In response to receiving a signal (enable) having a logic one value at the enable input, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 are enabled and configured to forward received signals. In response to receiving enable having a logic zero value at the enable input, the USB 2.0 receiver 324 and the eUSB2 transmitter 310 are disabled and configured not to forward received signals. For example, as described herein, an enable having a logic zero value may be provided to disable signal forwarding by the USB 2.0 receiver 324 and the eUSB2 transmitter 310 in response to determining a bubble condition. In some examples, the eUSB2 receiver 210 and the USB 2.0 transmitter 224 may also or alternatively have an enable input.

[0034] FIG. 4 is a block diagram of an example repeater 124, according to various examples. In some examples, the repeater 124 includes an HS component 300, a state machine 402, a logic circuit 404, a logic circuit 406, a timer 408, and a logic circuit 410. In the example architecture, the HS component 300 is coupled to the bus 112 and the eUSB2 bus 126, as described above with respect to FIG. 3. The HS component 300 also has an enable input (to which Enable is provided) and a status output (to which SQL4 is provided). In some examples, the enable input is the enable input of the USB 2.0 receiver 324 and the eUSB2 transmitter 310, as described above with respect to FIG. 3, and therefore Enable is provided to the USB 2.0 receiver 324 and the eUSB2 transmitter 310. In some examples, the status output of the HS component 300 is the output of the HSSQ 328, as described above with respect to FIG. 3, and therefore the status signal provided at the status output is SQL4.

[0035] The state machine 402 has a first output and a second output. The logic circuit 404 has a first input coupled to the second output of the state machine 402, a second input coupled to the status output of the high-speed component 300, and an output. In some examples, the second input of the logic circuit 404 is an inverting input. The second input of the logic circuit 404 can be inverted by coupling an inverter (not shown) between the second input of the logic circuit 404 and the status output of the high-speed component 300 or by incorporating inverter circuitry into the circuitry of the logic circuit 404. The logic circuit 406 has a first input coupled to the output of the logic circuit 404, a second input, and an output. The timer 408 has a reset input coupled to the output of the logic circuit 404, an increment input coupled to the output of the logic circuit 406, and an output coupled to the second input of the logic circuit 406. In some examples, the second input of the logic circuit 406 is an inverting input. The second input of the logic circuit 406 may be inverted by coupling an inverter (not shown) between the second input of the logic circuit 406 and the output of the timer 408, or by incorporating inverter circuitry into the circuitry of the logic circuit 406. In some examples, the reset input of the timer 408 is an inverting input. The reset input of the timer 408 may be inverted by coupling an inverter (not shown) between the reset input of the timer 408 and the output of the logic circuit 404, or by incorporating inverter circuitry into the circuitry of the timer 408. The logic circuit 410 has a first input coupled to the first output of the state machine 402, a second input coupled to the output of the timer 408, and an output coupled to the enable input of the high-speed component 300. The second input of the logic circuit 410 may be inverted by coupling an inverter (not shown) between the second input of the logic circuit 410 and the output of the timer 408, or by incorporating inverter circuitry into the circuitry of the logic circuit 410.

[0036] 4, the HS component 300 provides an idle signal that indicates that the repeater 124 is inactive (not repeating), e.g., that the host system 104 is not placing data on the bus 112 for relaying by the repeater 124. In some examples, the idle signal is an active high signal (e.g., has a logic 1 value in response to the absence of data on the bus 112), and in other examples, the idle signal is an active low signal (e.g., has a logic 0 value in response to the absence of data on the bus 112). In one example, the idle signal is SQL4, as described above.

[0037] The state machine 402 provides a state signal at its second output indicating the state of the repeater. The operation of the state machine 402 may proceed according to actions defined by a standard. For example, the state machine 402 may provide a state signal (HS LO) having a value determined based on the USB or eUSB standard, as described above in this specification. In one example, the state machine 402 determines the value of the state signal based on the values of any one or more of the signals provided on bus 112, bus 120, and / or bus 126, as represented by SQL4, SQL3, DSC2, and LOS2, as defined in the standard applicable to the operation of the state machine 402. Although not shown in FIG. 4 , in some examples, the state machine 402 receives any one or more of SQL4, SQL3, DSC2, and / or LOS2 as inputs. The state machine 402 may be collectively referred to as or implemented by a processing circuit. The processing circuitry may be a processor, microprocessor, controller, integrated circuit, field programmable gate array (FPGA), or any other combination of analog, digital, or logic circuits or components coupled to provide functionality, including the implementation of state machine 402. In some examples, logic circuitry 404 performs a logical AND operation such that in response to a state signal having a logic 1 value (e.g., representing repeater 124 in a normal functional mode where high-speed data transmission is available) and an idle signal having a logic 0 value, logic circuitry 404 provides a reset signal at its output having a logic 1 value. In response to an idle signal having a logic 1 value or a state signal having a logic 0 value (e.g., representing repeater 124 in a low-power mode where high-speed data transmission is not available), logic circuitry 404 provides a reset signal having a logic 0 value.

[0038] In some examples, logic circuit 406 performs a logical AND operation such that in response to a reset signal having a logic 1 value and a timer signal provided at the output of timer 408 having a logic 0 value, logic circuit 406 provides an increment signal having a logic 1 value. In response to the timer signal having a logic 1 value or a reset signal having a logic 0 value, logic circuit 406 provides an increment signal having a logic 0 value. Timer 408 includes any suitable circuitry for maintaining and incrementing a count and for providing a timer signal in response to the count exceeding a programmed value. In some examples, the timer signal has a logic 0 value in response to the count maintained by timer 408 being less than the programmed value and has a logic 1 value in response to the count maintained by timer 408 being greater than the programmed value. In some examples, the programmed value represents a maximum packet duration defined by the communications standard in which repeater 124 is operating, as described above. In some examples, timer 408 is clocked by a clock signal (not shown) in response to a reset signal having a logic one value and an increment signal having a logic zero value such that a count maintained by timer 408 is incremented on an edge of the clock signal. In one example, the clock signal is provided by an internal free-running oscillator (not shown) of timer 408 that clocks timer 408. In some examples, the edge is a rising edge of the clock signal, and in other examples, the edge is a falling edge of the clock signal.

[0039] The state machine 402 also provides a repeater enable signal at its first output. The state machine 402 determines the value of the repeater enable signal. In some examples, the logic circuit 410 performs a logical AND operation such that in response to the repeater enable signal having a logic 1 value and the timer signal having a logic 0 value, the logic circuit 410 provides an enable signal having a logic 1 value. In response to the repeater enable signal having a logic 0 value or the timer signal having a logic 1 value, the logic circuit 410 provides an enable signal having a logic 0 value. In response to the enable signal having a logic 1 value, the HS component 300 relays data received on the bus 112 to the eUSB2 bus 126. In response to the enable signal having a logic 0 value, which represents a bubbling state of the device that provided the data on the bus 112, the HS component 300 is disabled and does not relay data received on the bus 112 to the eUSB2 bus 126. For example, Enable having a value of logic 0 disables the USB 2.0 receiver 324 and the eUSB2 transmitter 310, as described above with respect to FIG. 3, and configures them not to forward received signals.

[0040] 5 illustrates various example signal timing diagrams 500. In one example, the signals may be present in and / or represent the operation of a system, such as system 100, peripheral system 108, and / or repeater 124. Diagram 500 includes DP and DM representing the positive and negative components of a differential signal provided on bus 112 (e.g., input to repeater 124), eDP and eDM representing the positive and negative components of a differential signal provided on bus 126 (e.g., output of repeater 124), SQL4, an output signal of timer 408 indicating that a bubble condition has been detected, Enable, the state of state machine 402, the status of timer 408, and a bus reset signal (XeSE1).

[0041] In some examples, at time t1, data (e.g., DP / DM) is detected on bus 112. In response to detecting the data, SQL4 is set to a logic 0 value, and the data is transferred to bus 126 as an eDP / eDM. In response to SQL4 being set to a logic 0 value, timer 408 begins incrementing. At time t2, a count maintained by timer 408 reaches a programmed value indicating a maximum duration for a DP / DM according to the communications standard on which the DP / DM is provided. In response to the count reaching its maximum duration, timer 408 provides an output signal having a logic 1 value to indicate that a bubble condition on bus 112 has been detected. In response to the output signal of timer 408 having a logic 1 value, Enable is provided having a logic 0 value. Enable having a logic 0 value disables relaying of the DP / DM as an eDP / eDM, as described above in this specification. At time t3, data is no longer provided on bus 112, and SQL4 is provided having a logic 1 value. In response to SQL4 having a logic 1 value, timer 408 resets to a count of 0, the output signal of timer 408 is set to logic 0, and Enable is provided having a logic 1 value. Enable having a logic 1 value enables relaying of the DP / DM as an eDP / eDM, as described herein above.

[0042] At time t4, a DP / DM is detected on bus 112. In response to detecting the DP / DM, SQL4 is set to a logic-0 value, and the DP / DM is transferred to bus 126 as an eDP / eDM. In response to SQL4 being set to a logic-0 value, timer 408 begins incrementing. At time t5, peripheral device 122 provides XeSE1 with a logic-1 value. In some examples, XeSE1 is a bus or port reset signal. Repeater 124 may be configured to reset, enter an unconnected state, or perform other actions in response to receiving XeSE1 with a logic-1 value. However, the eDP / eDM relayed on bus 126 by repeater 124 may cause contention on bus 126, preventing repeater 124 from receiving XeSE1 from peripheral device 122. At time t6, the count maintained by timer 408 reaches a programmed value indicating the maximum duration for a DP / DM according to the communication standard based on which DP / DM is provided. In response to the count reaching its maximum duration, the timer 408 provides an output signal having a logic 1 value to indicate that a bubble condition has been detected on the bus 112. In response to the output signal of the timer 408 having a logic 1 value, an Enable having a logic 0 value is provided. The Enable having a logic 0 value disables relaying of DP / DM as eDP / eDM on the bus 126, as described herein above.

[0043] Disabling repeater on bus 126 may resolve the conflict with peripheral device 122 transmitting XeSE1 with a logic 1 value. As a result, at time t7, repeater 124 detects the logic 1 value of XeSE1 and asserts a reset signal to reset, enter an unconnected state, or perform other action.

[0044] 6 is a flowchart of a method 600, according to various examples. In some examples, the method 600 is implemented by a repeater, such as repeater 124, as described herein above. The method 600 is implemented, for example, to detect a bubbling state of a device providing data to the repeater and to cease relaying the data in response to detecting the bubbling state.

[0045] In operation 602, the repeater receives a communication on a first bus. In some examples, the first bus is a USB 2.0 bus, such as USB 2.0 bus 112, and the communication is received from a USB 2.0 device. In other examples, the first bus is an eUSB2 bus, such as eUSB2 bus 126, and the communication is received from an eUSB2 device. In some examples, the communication is organized into packets that are subject to maximum packet length or maximum duration restrictions in order to comply with a particular communication protocol or standard.

[0046] In operation 604, the repeater provides communication on the second bus for a first period of time. Providing communication on the second bus may be referred to as repeating the communication received in operation 602 on the first bus. In some examples, the second bus is an eUSB2 bus and the communication is provided to an eUSB2 device. In other examples, the second bus is a USB 2.0 bus and the communication is provided to a USB 2.0 device.

[0047] In operation 606, the repeater monitors the duration of providing the communication on the second bus. In another example, the repeater monitors the duration of receiving the communication on the first bus. In some examples, the repeater monitors the duration by incrementing a timer count for the monitored time period.

[0048] At operation 608, in response to the duration exceeding a threshold amount, the repeater stops providing the communication on the second bus for a second period of time. For example, in response to the duration exceeding a threshold or programmed amount, the repeater determines that a bubble condition exists. The threshold or programmed amount may be, for example, a maximum packet length or duration for the communication. The maximum packet length or duration may be a duration of time specified in a communication protocol, standard, or specification, as described above herein. In some examples, the repeater stops relaying or providing the communication on the second bus by deasserting the repeater enable signal.

[0049] 7 is a flowchart of a method 700, according to various examples. In some examples, the method 700 is implemented by a repeater, such as repeater 124, as described herein above. The method 700 is implemented, for example, to detect a bubbling state of a device providing data to the repeater and to cease relaying the data in response to detecting the bubbling state.

[0050] In operation 702, the repeater receives data over a first bus for consecutive first and second amounts of time. In some examples, the first bus is a USB 2.0 bus and the data is received from a USB 2.0 device. In other examples, the first bus is an eUSB2 bus and the data is received from an eUSB2 device. In some examples, the data is organized into packets that are subject to maximum packet length or maximum duration restrictions in order to comply with a particular communications protocol or standard.

[0051] In operation 704, the repeater provides data on the second bus for a first time. Providing the data on the second bus may be referred to as repeating the data received in operation 702 on the first bus. In some examples, the second bus is an eUSB2 bus and the data is provided to an eUSB2 device. In other examples, the second bus is a USB 2.0 bus and the data is provided to a USB 2.0 device.

[0052] The repeater monitors the duration of the first amount of time in operation 706. In some examples, the repeater monitors the duration by incrementing a count of a timer for the monitored time period.

[0053] At operation 708, in response to the duration exceeding a threshold amount, the repeater disables repeating for a second amount of time. For example, in response to the duration (e.g., the first amount of time) meeting or exceeding a threshold or programmed amount, the repeater determines that a data bubble condition or a device providing data exists. The threshold or programmed amount may be, for example, a maximum packet length or duration for the data. The maximum packet length or duration may be a duration of time specified in a communications protocol, standard, or specification, as described above in this specification. In some examples, the repeater stops relaying or providing data on the second bus by deasserting the repeater enable signal.

[0054] 8 is a flowchart of a method 800, according to various examples. In some examples, the method 800 is implemented by a repeater, such as the repeater 124 described herein above. The method 800 is implemented, for example, to control the operation of the repeater 124.

[0055] In operation 802, repeater 124 enters high speed operation (e.g., HS LO=1). The repeater 124 entering high speed operation may be determined by state machine 402 based on, for example, the values of any one or more of SQL2, SQL4, signals provided on bus 112, signals provided on bus 120, and / or signals provided on bus 126 as defined in standards applicable to the operation of state machine 402.

[0056] At operation 804, repeater 124 determines whether SQL4 has a value of logical 1. In response to SQL4 having a value of logical 1, method 800 remains at operation 802. In response to SQL4 not having a value of logical 1, method 800 proceeds to operation 806. Although not explicitly shown in FIG. 8 , operation 804 may be responsive to receiving data for relaying by repeater 124, such as a DP / DM on bus 112 for relaying as an eDP / eDM on bus 126, as described above herein.

[0057] In operation 806, the repeater 124 sets Enable to a logic 1 value to repeat the DP / DM as eDP / eDM and proceeds to operation 808.

[0058] At operation 808, the timer 408 determines whether the incremental count (e.g., bubble timer) has exceeded a programmed value (e.g., tmax). In one example, tmax is determined as described above herein based on the communication standard or protocol according to which DP / DM is provided. In response to the bubble timer not exceeding tmax, the method proceeds to operation 810.

[0059] At operation 810, the repeater 124 determines whether SQL4 has a value of logical 1. In response to SQL4 not having a value of logical 1, the method 800 returns to operation 808. In response to SQL4 having a value of logical 1, the method 800 proceeds to operation 812.

[0060] At operation 812, the repeater 124 sets Enable to a logic 0 value to disable repeating of DP / DM as eDP / eDM on the bus 126. The method 800 then returns to operation 804.

[0061] Returning to operation 808, in response to the bubble timer exceeding tmax, the method proceeds to operation 814. At operation 814, the repeater 124 sets Enable to a logic 0 value to disable repeating of DP / DM as eDP / eDM on the bus 126. The method 800 then proceeds to operation 816.

[0062] At operation 816, the repeater 124 determines whether SQL4 has a value of logical 1. In response to SQL4 having a value of logical 1, the method 800 returns to operation 804. In response to SQL4 not having a value of logical 1, the method 800 proceeds to operation 818.

[0063] At operation 818, the repeater 124 determines whether an XeSE1 has been received having a value of logical 1. In response to an XeSE1 having a value of logical 1 not being received, the method 800 returns to operation 816. In response to an XeSE1 having a value of logical 1 being received, the method 800 proceeds to operation 820.

[0064] In operation 820, the repeater 124 resets or enters the unconnected / disconnected state in response to the logic 1 value of XeSE1. In some examples, the state signal is set to a logic 0 value in response to the repeater 124 entering the unconnected / disconnected state.

[0065] Although the operations of methods 600, 700, 800 are described and labeled with reference numbers, in various examples, methods 600, 700, 800 include additional operations not described herein (e.g., intermediate comparisons, logical operations, output selection such as via a multiplexer, etc.), in some examples, any one or more of the operations described herein include one or more sub-operations (e.g., intermediate comparisons, logical operations, output selection such as via a multiplexer, etc.), in some examples, any one or more of the operations described herein are omitted, and / or in some examples, any one or more of the operations described herein are performed in an order other than the order presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.).

[0066] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal that controls device B to perform a certain action, then (A) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0067] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the configuration and / or layout of hardware components, via the device's interconnections, or via a combination thereof.

[0068] A circuit or device described herein as including particular components may instead be combined with those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be combined with at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0069] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to that available prior to the component replacement. A component shown as a resistor, unless otherwise specified, generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

[0070] Use of the phrase "ground voltage potential" in the foregoing description includes chassis ground, ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of the present description. Unless otherwise specified herein, the words "about," "approximately," or "substantially" preceding a parameter are within + / - 10% of that parameter.

[0071] Modifications may be made to the examples described and other embodiments are possible within the scope of the invention.

Claims

1. An electronic circuit, A repeater circuit having first and second inputs and first and second outputs, the repeater circuit including a squelch detector configured to detect downstream packets, A first logic circuit having a first input, a second input coupled to the second output of the repeater circuit, and an output, A second logic circuit having a first input, a second input, and an output, which are coupled to the output of the first logic circuit. A timer circuit having a first input coupled to the output of the first logic circuit, a second input coupled to the output of the second logic circuit, and an output coupled to the second input of the second logic circuit, A third logic circuit having a first input, a second input coupled to the output of the timer circuit, and an output coupled to the second input of the repeater circuit, Electronic circuits, including

2. The electronic circuit according to claim 1, An electronic circuit further comprising a processing circuit having a first output coupled to a first input of the third logic circuit and a second output coupled to a first input of the first logic circuit.

3. The electronic circuit according to claim 2, The processing circuit is an electronic circuit that includes a finite state machine.

4. The electronic circuit according to claim 1, An electronic circuit in which the first, second, and third logic circuits are AND logic circuits.

5. The electronic circuit according to claim 1, An electronic circuit in which the second input of the first logic circuit, the second input of the second logic circuit, and the second input of the third logic circuit are inverting inputs, and the first input of the timer circuit is an inverting input.

6. The electronic circuit according to claim 1, The aforementioned electronic circuit is an embedded universal serial bus (eUSB) repeater.

7. The electronic circuit according to claim 1, An electronic circuit further comprising a universal serial bus device coupled to a first input of the repeater circuit and an eUSB device coupled to a first output of the repeater circuit.

8. The electronic circuit according to claim 1, The aforementioned electronic circuit I received the communication on the first bus. Provide communication on the second bus over the first period of time, The duration of providing the communication on the second bus is monitored, In response to the duration exceeding a threshold amount, the provision of the communication on the second bus is stopped for a second period of time. An electronic circuit configured in such a way.

9. The electronic circuit according to claim 8, An electronic circuit further configured to determine the existence of a bubble state in response to the duration exceeding a threshold amount.

10. The electronic circuit according to claim 9, An electronic circuit in which the threshold amount is the maximum packet length for the communication.

11. The electronic circuit according to claim 10, An electronic circuit in which the aforementioned maximum packet length is the duration according to the Universal Serial Bus (USB) protocol.

12. The electronic circuit according to claim 8, An electronic circuit in which the third logic circuit is configured to provide a repeater enable signal having a deasserted value to the second input of the repeater circuit in order to stop providing the communication on the second bus.

13. The electronic circuit according to claim 8, An electronic circuit in which the timer circuit is configured to monitor the duration of communication on the first bus.

14. The electronic circuit according to claim 1, An electronic circuit in which the third logic circuit is configured to provide a repeater enable signal having a deasserted value to the second input of the repeater circuit in order to stop providing communication on the bus.

15. The electronic circuit according to claim 1, An electronic circuit in which the timer circuit is configured to monitor the duration of communication on a bus.

16. It is a method, Receiving data at the relay device via the first bus over consecutive first and second time periods, To provide data to the second bus of the repeater during the first time period, Monitoring the duration of the first time period, In response to the duration exceeding a certain threshold amount, the repeater is disabled during the second period. Methods that include...

17. The method according to claim 16, A method wherein the threshold amount is the maximum packet length of the data.

18. The method according to claim 17, A method wherein the maximum packet length is the duration of time according to the Universal Serial Bus (USB) protocol.

19. The method according to claim 16, A method for disabling the repeater, thereby preventing the repeater from providing the data to the second bus.

20. The method according to claim 16, A method in which the duration exceeding the threshold amount indicates a bubble state in the data.

21. The method according to claim 16, A method further comprising detecting a bus reset signal on the second bus during the second period.

22. The method according to claim 21, A method further comprising controlling the repeater to enter a disconnected state in response to the bus reset signal.

Images