MRAM integration with self-aligned direct backside contact

Abstract

A backside contact structure is provided that directly connects the MRAM first electrode, present on the backside of the wafer, to the transistor source / drain structure. The backside contact is self-aligned to the MRAM first electrode as well as the transistor source / drain structure. The proximity between the MRAM and the source / drain structure improves device speed. There is no re-sputtering of the backside contact metal onto the MRAM, which does not reduce MRAM yield. (Figure 1A)

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures that include magnetoresistive random access memory (MRAM) on the backside of a wafer and methods for forming the same. [Background technology]

[0002] MRAM is a viable memory option for standalone and embedded applications, such as the Internet of Things (IoT), automotive, or artificial intelligence (AI). MRAM is a nonvolatile random-access memory technology that stores data using magnetic memory elements. These elements typically consist of two ferromagnetic plates, each capable of retaining its magnetization, separated by a thin dielectric layer, or tunnel barrier. One of the plates is a permanent magnet set to a specific polarity, while the magnetization of the other plate can be changed to accommodate an external magnetic field to store memory. MRAM is typically fabricated in the back-end-of-the-line (BEOL) region of a semiconductor structure, resulting in a large distance between the source / drain regions of a field-effect transistor (FET) and the MRAM. Summary of the Invention [Problem to be solved by the invention]

[0003] A backside contact structure is provided that directly connects the MRAM first electrode present on the backside of the wafer to the transistor source / drain structure. The backside contact is self-aligned to the MRAM first electrode as well as the transistor source / drain structure. The proximity between the MRAM and the source / drain structure improves device speed. There is no re-sputtering of the backside contact metal onto the MRAM, which does not reduce MRAM yield. [Means for solving the problem]

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes an MRAM device region and an MRAM disposed on the backside of a wafer. The MRAM includes a first electrode, an MRAM stack, and a second electrode. A first backside source / drain contact structure is present that directly connects the first electrode of the MRAM to a first source / drain structure of a first transistor present on the frontside of the wafer and in the MRAM device region.

[0005] In some embodiments of the present application, the first backside source / drain contact structure has an outermost wall that is substantially vertically aligned with the outermost wall of the first electrode. The term "substantially," when used in conjunction with the phrase "vertically aligned," indicates that the outermost wall of one structure is within ±5.0 percent of the outermost wall of another structure; in some instances, perfect vertical alignment is obtained, and in some embodiments of the present application, the outermost wall of the first backside source / drain contact structure is substantially vertically aligned with the outermost wall of the first source / drain structure of the first transistor. Such "vertical alignment" provides reduced device overlay error.

[0006] In some embodiments of the present application, the first transistor comprises a vertical stack of semiconductor channel material nanosheets and a functional gate structure surrounding each semiconductor channel material nanosheet in the vertical stack of semiconductor channel material nanosheets. Such a transistor can be referred to as a nanosheet field effect transistor. In other embodiments, the first transistor is a planar transistor, a FinFET transistor, or a nanowire transistor.

[0007] In some embodiments of the present application, the structure further comprises a bottom dielectric insulating layer disposed on a surface of the first transistor, the bottom dielectric insulating layer having sidewalls in direct physical contact with outermost walls of the first backside source / drain contact structures.

[0008] In some embodiments of the present application, specifically when a nanosheet field effect transistor is employed as the first transistor, the inner spacer is disposed laterally adjacent to the functional gate structure of the transistor.

[0009] In some embodiments of the present application, the structure further comprises a second source / drain structure disposed on a second side of the functional gate structure of the first transistor opposite the first side of the functional gate structure of the first transistor. In such embodiments, the structure may further comprise a first front-side source / drain contact structure connecting the second source / drain structure of the first transistor to a front-side interconnect processing (BEOL) structure. In embodiments of the present application, the structure includes a carrier wafer disposed on a surface of the front-side BEOL structure.

[0010] In some embodiments of the present application, the structure also includes an MRAM spacer disposed laterally adjacent to and in direct physical contact with the MRAM stack and the second electrode, wherein the MRAM spacer is laterally adjacent to but spaced apart from the first electrode. In such embodiments, the MRAM spacer has a bottom surface disposed between the bottom and top surfaces of the first electrode.

[0011] In some embodiments of the present application, the structure further comprises a backside inter-layer dielectric (ILD) material layer stack laterally surrounding the MRAM and an upper portion of the first backside source / drain contact structure.

[0012] In some embodiments of the present application, the second electrode is in electrical contact with a backside interconnect structure. In such embodiments, the structure further comprises a contact via structure extending vertically through the second electrode, the contact via structure having a first surface in direct contact with the MRAM stack and a second surface opposite the first surface in direct contact with the backside interconnect structure.

[0013] In some embodiments of the present application, the structure further comprises a second transistor disposed on the front side of the wafer and disposed in a logic device region disposed adjacent to the MRAM device region, wherein the second transistor has a first source / drain structure disposed on a first side of a functional gate structure of the second transistor and a second source / drain structure disposed on a second side of the functional gate structure of the second transistor opposite the first side of the functional gate structure of the second transistor.

[0014] In some embodiments of the present application, the semiconductor device further comprises a second backside source / drain contact structure disposed in the logic device region and connecting the first source / drain structure of the second transistor to a backside power rail.

[0015] In some embodiments of the present application, the backside power rail is in electrical contact with a backside interconnect structure, and in embodiments, a via contact structure is disposed between the backside interconnect structure and the backside power rail.

[0016] In some embodiments of the present application, the structure further comprises a front-side source / drain contact structure disposed in the logic device region connecting the second source / drain structure of the second transistor to a front-side BEOL structure, and in some embodiments of the present application, a carrier wafer is disposed on a surface of the front-side BEOL structure.

[0017] In some embodiments of the present application, the second backside source / drain contact structure present in the logic device region has a top surface disposed below a bottom surface of an MRAM spacer surrounding the MRAM device.

[0018] In another embodiment of the present application, a semiconductor structure includes an MRAM device region with an MRAM including a first electrode, an MRAM stack, and a second electrode, located on the backside of a wafer. The MRAM device region also includes a first transistor having a first source / drain structure disposed below the MRAM, and a first backside source / drain contact structure directly connecting the first electrode of the MRAM to the first source / drain structure of the first transistor. In the present application, the first backside source / drain contact structure has an outermost wall substantially vertically aligned with outermost walls of both the first source / drain structure and the first electrode of the first transistor. The structure further includes a logic device region disposed adjacent to the MRAM device region, wherein the logic device region is disposed on the front side of the wafer and has a second transistor having a first source / drain structure disposed on a first side of a functional gate structure of the second transistor, and a second backside source / drain contact structure directly connecting the first source / drain structure of the functional gate structure of the second transistor to a backside power rail.

[0019] In some embodiments, the second backside source / drain contact structure has a top surface disposed below a bottom surface of an MRAM spacer surrounding the MRAM device.

[0020] In some embodiments, the MRAM spacer has a bottom surface disposed between a bottom surface and a top surface of the first electrode.

[0021] In some embodiments, the backside power rail is in electrical contact with a backside interconnect structure disposed on the backside power rail, and the second electrode of the MRAM is in electrical contact with a backside interconnect structure disposed above the MRAM.

[0022] In another aspect of the present application, a method for forming a semiconductor structure is provided. The method of the present application will become more apparent with reference to the drawings and the detailed description that follows. [Brief explanation of the drawings]

[0023] [Figure 1A] 1A and 1B show cross-sectional views of exemplary structures in a logic device region and an MRAM device region, respectively, the exemplary structures comprising at least one nanosheet-containing stack located on a semiconductor substrate including a first semiconductor material layer, an etch stop layer, a second semiconductor material layer, a sacrificial gate structure located on the at least one nanosheet-containing stack, and a hard mask cap located on the sacrificial gate structure, wherein the at least one nanosheet-containing stack comprises alternating recessed sacrificial semiconductor material nanosheets and semiconducting channel material nanosheets. [Figure 1B] 1A and 1B show cross-sectional views of exemplary structures in a logic device region and an MRAM device region, respectively, the exemplary structures comprising at least one nanosheet-containing stack located on a semiconductor substrate including a first semiconductor material layer, an etch stop layer, a second semiconductor material layer, a sacrificial gate structure located on the at least one nanosheet-containing stack, and a hard mask cap located on the sacrificial gate structure, wherein the at least one nanosheet-containing stack comprises alternating recessed sacrificial semiconductor material nanosheets and semiconducting channel material nanosheets.

[0024] [Figure 2A] 1C and 1D show cross-sectional views of the example structures shown in FIGS. 1A and 1B after forming openings in the semiconductor substrate in both the logic device region and the MRAM device region, respectively. [Figure 2B] 1C and 1D show cross-sectional views of the example structures shown in FIGS. 1A and 1B after forming openings in the semiconductor substrate in both the logic device region and the MRAM device region, respectively.

[0025] [Figure 3A] 2C and 2D show cross-sectional views of the example structures shown in FIGS. 2A and 2B, respectively, after forming a block mask in the logic device region but not in the MRAM device region and extending the depth of the opening in the MRAM device region. [Figure 3B] 2C and 2D show cross-sectional views of the example structures shown in FIGS. 2A and 2B, respectively, after forming a block mask in the logic device region but not in the MRAM device region and extending the depth of the opening in the MRAM device region.

[0026] [Figure 4A] 3C and 3D show cross-sectional views of the example structures shown in FIGS. 3A and 3B after removing the block mask and forming sacrificial placeholder material in the openings in the logic device region and the extended depth openings in the MRAM device region, respectively. [Figure 4B] 3C and 3D show cross-sectional views of the example structures shown in FIGS. 3A and 3B after removing the block mask and forming sacrificial placeholder material in the openings in the logic device region and the extended depth openings in the MRAM device region, respectively.

[0027] [Figure 5A] 4C and 4D show cross-sectional views of the example structures shown in FIGS. 4A and 4B, respectively, after recessing the sacrificial placeholder material in both the logic device region and the MRAM device region to provide a sacrificial placeholder material structure in the logic device region and a sacrificial placeholder material structure in the MRAM device region. [Figure 5B] 4C and 4D show cross-sectional views of the example structures shown in FIGS. 4A and 4B, respectively, after recessing the sacrificial placeholder material in both the logic device region and the MRAM device region to provide a sacrificial placeholder material structure in the logic device region and a sacrificial placeholder material structure in the MRAM device region.

[0028] [Figure 6A] 5A and 5B show cross-sectional views of the example structures shown in FIGS. 5A and 5B after forming source / drain structures and a first inter-layer dielectric (ILD) material layer in both the logic device region and the MRAM device region, respectively. [Figure 6B]5A and 5B show cross-sectional views of the example structures shown in FIGS. 5A and 5B after forming source / drain structures and a first inter-layer dielectric (ILD) material layer in both the logic device region and the MRAM device region, respectively.

[0029] [Figure 7A] 6A and 6B show cross-sectional views of the exemplary structures shown in FIGS. 6A and 6B, respectively, after removing the hard mask, the sacrificial gate structure, and each recessed sacrificial semiconductor material nanosheet of the at least one nanosheet-containing material stack in both the logic device region and the MRAM device region, forming a functional gate structure incorporating around each semiconductor channel material nanosheet of the at least one nanosheet-containing stack, forming a second ILD material, forming a front-side source / drain contact structure, forming a front-side BEOL structure, and forming a carrier wafer. [Figure 7B] 6A and 6B show cross-sectional views of the exemplary structures shown in FIGS. 6A and 6B, respectively, after removing the hard mask, the sacrificial gate structure, and each recessed sacrificial semiconductor material nanosheet of the at least one nanosheet-containing material stack in both the logic device region and the MRAM device region, forming a functional gate structure incorporating around each semiconductor channel material nanosheet of the at least one nanosheet-containing stack, forming a second ILD material, forming a front-side source / drain contact structure, forming a front-side BEOL structure, and forming a carrier wafer.

[0030] [Figure 8A] 7A and 7B show cross-sectional views of the example structure after flipping the example structure shown in FIG. 7A and FIG. 7B by 180 degrees and removing the second semiconductor material layer of the semiconductor substrate, where removal stops on the etch stop layer of the semiconductor substrate and, after flipping, the front side of the wafer is now located below the back side of the wafer. [Figure 8B]7A and 7B show cross-sectional views of the example structure after flipping the example structure shown in FIG. 7A and FIG. 7B by 180 degrees and removing the second semiconductor material layer of the semiconductor substrate, where removal stops on the etch stop layer of the semiconductor substrate and, after flipping, the front side of the wafer is now located below the back side of the wafer.

[0031] [Figure 9A] 8A and 8B show cross-sectional views of the example structures shown in FIGS. 8A and 8B, respectively, after removing the etch stop layer of the semiconductor substrate and the first semiconductor material layer to expose a portion of the sacrificial placeholder material structure of the logic device region in the logic device region and a portion of the sacrificial placeholder material structure of the MRAM device region in the MRAM device region. [Figure 9B] 8A and 8B show cross-sectional views of the example structures shown in FIGS. 8A and 8B, respectively, after removing the etch stop layer of the semiconductor substrate and the first semiconductor material layer to expose a portion of the sacrificial placeholder material structure of the logic device region in the logic device region and a portion of the sacrificial placeholder material structure of the MRAM device region in the MRAM device region.

[0032] [Figure 10A] 9C and 9D show cross-sectional views of the example structures shown in FIGS. 9A and 9B, respectively, after forming a first backside ILD material layer. [Figure 10B] 9C and 9D show cross-sectional views of the example structures shown in FIGS. 9A and 9B, respectively, after forming a first backside ILD material layer.

[0033] [Figure 11A] 10A and 10B show cross-sectional views of the exemplary structures shown in FIGS. 10A and 10B, respectively, after removing sacrificial placeholder material structures in the MRAM device region to provide openings that physically expose surfaces of source / drain structures present in the MRAM device region. [Figure 11B]10A and 10B show cross-sectional views of the exemplary structures shown in FIGS. 10A and 10B, respectively, after removing sacrificial placeholder material structures in the MRAM device region to provide openings that physically expose surfaces of source / drain structures present in the MRAM device region.

[0034] [Figure 12A] 11A and 11B show cross-sectional views of the exemplary structures shown in FIGS. 11A and 11B, respectively, after precursor MRAM backside source / drain contact structures have been formed in openings present in the first backside ILD material layer in the MRAM device region. [Figure 12B] 11A and 11B show cross-sectional views of the exemplary structures shown in FIGS. 11A and 11B, respectively, after precursor MRAM backside source / drain contact structures have been formed in openings present in the first backside ILD material layer in the MRAM device region.

[0035] [Figure 13A] 12A and 12B show cross-sectional views of the exemplary structures shown in FIGS. 12A and 12B, respectively, after recessing the precursor MRAM backside source / drain contact structures to provide MRAM backside source / drain contact structures underneath openings present in the first backside ILD material layer in the MRAM device region. [Figure 13B] 12A and 12B show cross-sectional views of the exemplary structures shown in FIGS. 12A and 12B, respectively, after recessing the precursor MRAM backside source / drain contact structures to provide MRAM backside source / drain contact structures underneath openings present in the first backside ILD material layer in the MRAM device region.

[0036] [Figure 14A] 13A and 13B show cross-sectional views of the exemplary structure shown in FIG. 13A and FIG. 13B, respectively, after forming a first electrode on the MRAM backside source / drain contact structure above the opening present in the first backside ILD material layer in the MRAM device region. [Figure 14B]13A and 13B show cross-sectional views of the exemplary structure shown in FIG. 13A and FIG. 13B, respectively, after forming a first electrode on the MRAM backside source / drain contact structure above the opening present in the first backside ILD material layer in the MRAM device region.

[0037] [Figure 15A] 14C and 14D show cross-sectional views of the example structure shown in FIGS. 14A and 14B after forming MRAM stacks in both the logic device region and the MRAM device region, respectively. [Figure 15B] 14C and 14D show cross-sectional views of the example structure shown in FIGS. 14A and 14B after forming MRAM stacks in both the logic device region and the MRAM device region, respectively.

[0038] [Figure 16A] 15A and 15B show cross-sectional views of the exemplary structures shown in FIGS. 15A and 15B, respectively, after patterning the MRAM stack using a second electrode formed on the MRAM stack in the MRAM device region as an etching mask to provide the MRAM stack in the MRAM device region. [Figure 16B] 15A and 15B show cross-sectional views of the exemplary structures shown in FIGS. 15A and 15B, respectively, after patterning the MRAM stack using a second electrode formed on the MRAM stack in the MRAM device region as an etching mask to provide the MRAM stack in the MRAM device region.

[0039] [Figure 17A] 16A and 16B show cross-sectional views of the exemplary structures shown in FIGS. 16A and 16B, respectively, after exposing the sacrificial placeholder material structure in the logic device region and forming MRAM spacers laterally adjacent to both the second electrode and the MRAM stack. [Figure 17B]16A and 16B show cross-sectional views of the exemplary structures shown in FIGS. 16A and 16B, respectively, after exposing the sacrificial placeholder material structure in the logic device region and forming MRAM spacers laterally adjacent to both the second electrode and the MRAM stack.

[0040] [Figure 18A] 17A and 17B show cross-sectional views of the exemplary structures shown in FIGS. 17A and 17B, respectively, after removing sacrificial placeholder material structures in the logic device region to expose source / drain structures present in the logic device region. [Figure 18B] 17A and 17B show cross-sectional views of the exemplary structures shown in FIGS. 17A and 17B, respectively, after removing sacrificial placeholder material structures in the logic device region to expose source / drain structures present in the logic device region.

[0041] [Figure 19A] 18A and 18B show cross-sectional views of the example structures shown in FIGS. 18A and 18B, respectively, after forming logic device backside source / drain contacts on the source / drain structures exposed in the logic device region. [Figure 19B] 18A and 18B show cross-sectional views of the example structures shown in FIGS. 18A and 18B, respectively, after forming logic device backside source / drain contacts on the source / drain structures exposed in the logic device region.

[0042] [Figure 20A] 19A and 19B show cross-sectional views of the example structures shown in FIGS. 19A and 19B, respectively, after forming a backside power rail in the logic device region, a second backside ILD material layer in both the logic device region and the MRAM device region, contact via structures in both the logic device region and the MRAM device region, and backside interconnect structures in both the logic device region and the MRAM device region. [Figure 20B]19A and 19B show cross-sectional views of the example structures shown in FIGS. 19A and 19B, respectively, after forming a backside power rail in the logic device region, a second backside ILD material layer in both the logic device region and the MRAM device region, contact via structures in both the logic device region and the MRAM device region, and backside interconnect structures in both the logic device region and the MRAM device region. DETAILED DESCRIPTION OF THE INVENTION

[0043] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings of the present application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0044] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0045] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0046] Referring initially to FIGS. 1A and 1B, exemplary structures are illustrated in a logic device region 100 and an MRAM device region 102, respectively. The logic device region 100 and the MRAM device region 102 are disposed adjacent to one another and are at the same level in the exemplary structures. The exemplary structures illustrated in FIGS. 1A and 1B include at least one nanosheet-containing stack disposed in a semiconductor substrate. The number of nanosheet-containing stacks present in both the logic device region 100 and the MRAM device region 102 can vary, including but not limited to three nanosheet-containing stacks in each of these device regions. Additionally, the number of nanosheet-containing stacks in the logic device region 100 can be equal to, greater than, or less than the number of nanosheet-containing stacks present in the MRAM device region 102. While the present application describes and illustrates the logic device region 100, it contemplates embodiments in which an analog device region replaces or is used in conjunction with the logic device region 100. Also, although the present application describes the formation of nanosheet field effect transistors (FETs) in both device regions, the present application contemplates embodiments in which the nanosheet FETs are replaced with other types of FETs, including, but not limited to, planar FETs, finFETs, or semiconductor nanowire FETs.

[0047] The semiconductor substrate present in both the logic device region 100 and the MRAM device region 102 includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. Also present is a sacrificial gate structure 22 located on at least one nanosheet-containing stack, with a hard mask cap 24 located on the sacrificial gate structure 22. The at least one nanosheet-containing stack includes alternating recessed sacrificial semiconductor material nanosheets 18 and semiconductor channel material nanosheets 20. The exemplary structure illustrated in FIGS. 1A and 1B further includes a bottom dielectric insulating layer 16 located between the second semiconductor material layer 14 of the semiconductor substrate and the at least one nanosheet-containing stack in both the logic device region 100 and the MRAM device region 102. Also, a dielectric spacer 26 is located above the at least one nanosheet-containing stack, laterally adjacent to the sacrificial gate structure 22 and the hard mask cap 24, and an inner spacer 28 is located laterally adjacent to each recessed sacrificial semiconductor material nanosheet 20. The inner spacer 28 has a first sidewall in direct physical contact with the sidewall of a laterally adjacent recessed sacrificial semiconductor material nanosheet 18 and a second sidewall opposite the first sidewall, and is substantially vertically aligned with the outermost wall of each semiconductor channel material nanosheet 20 and the outermost wall of the dielectric spacer 26.

[0048] The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconducting properties. Examples of first semiconductor materials that may be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The second semiconductor material layer 14 is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 can be compositionally the same as or different from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 can be composed of a dielectric material such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is compositionally different from the semiconductor materials providing both the first semiconductor material layer 10 and the second semiconductor material layer 14.

[0049] In one example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon can be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon can be referred to as a bulk semiconductor substrate.

[0050] As described above, at least one nanosheet-containing stack includes alternating recessed sacrificial semiconductor material nanosheets 18 and semiconducting channel material nanosheets 20. At least one nanosheet-containing stack includes "n" semiconducting channel material nanosheets 20 and "n or n+1" recessed sacrificial semiconductor material nanosheets 18, with "n+1" embodiments not shown. In the illustrated embodiment, at least one nanosheet-containing stack includes "n" recessed sacrificial semiconductor material nanosheets 18 and "n" semiconducting channel material nanosheets 20. In one example, at least one nanosheet-containing stack includes three semiconducting channel material nanosheets 20 and three recessed sacrificial semiconductor material nanosheets 18.

[0051] Each recessed sacrificial semiconductor material nanosheet 18 is composed of a third semiconductor material, while each semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that is compositionally different from the third semiconductor material. In some embodiments, the semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that can provide high channel mobility for a NFET device. In other embodiments, the semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material that can provide high channel mobility for a PFET device.

[0052] The third semiconductor material providing each recessed sacrificial semiconductor material nanosheet 18 and the fourth semiconductor material providing each semiconductor channel material nanosheet 20 may comprise one of the semiconductor materials described above for first semiconductor material layer 10. In one example, the third semiconductor material providing each recessed sacrificial semiconductor material nanosheet 18 is comprised of a silicon germanium alloy, and the fourth semiconductor material providing each semiconductor channel material nanosheet 20 is comprised of silicon.

[0053] Each recessed sacrificial semiconductor material nanosheet 18 has a first width, and each semiconductor channel material nanosheet 20 has a second width greater than the first width. In one example, the first width is 10 nm to 100 nm, and the second width is 20 nm to 130 nm. Each recessed sacrificial semiconductor material nanosheet 18 and each semiconductor channel material nanosheet 20 have the same length. In one example, the length of each recessed sacrificial semiconductor material nanosheet 18 and each semiconductor channel material nanosheet 20 is 10 nm to 130 nm. The vertical height of each recessed sacrificial semiconductor material nanosheet 18 and each semiconductor channel material nanosheet 20 is in the range of 4 nm to 20 nm. The vertical height of each recessed sacrificial semiconductor material nanosheet 18 can be equal to, greater than, or less than the vertical height of each semiconductor channel material nanosheet 20.

[0054] The sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, the sacrificial gate structure 22 can include a sacrificial gate dielectric material. The sacrificial gate dielectric material can be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material can include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, or alloys of such metals.

[0055] The hard mask cap 24 may be composed of a hard mask material such as, for example, silicon dioxide, silicon nitride, silicon oxynitride, or any multilayer combination thereof. The hard mask cap 24 may also be omitted in some embodiments.

[0056] The dielectric spacers 26 are comprised of a gate spacer dielectric material. Examples of gate spacer dielectric materials that can be used to provide the dielectric spacers 26 include, but are not limited to, SiN, SiBCN, SiOCN, or SiOC.

[0057] The bottom dielectric insulating layer 16 is composed of one of the gate spacer dielectric materials described above for the dielectric spacers 26. The bottom dielectric insulating layer 16 and the dielectric spacers 26 are formed simultaneously and are therefore composed of the same compositional gate spacer dielectric material. The bottom dielectric insulating layer 16 may have a thickness of 5 nm to 50 nm, although other thicknesses are contemplated and may be employed for the bottom dielectric insulating layer 16.

[0058] The inner spacers 28 are composed of one of the gate spacer dielectric materials described above for the dielectric spacers 26. The gate spacer dielectric material that provides the inner spacers 28 can be compositionally the same as or compositionally different from the gate dielectric spacer material that provides the dielectric spacers 26.

[0059] 1A and 1B can be formed using conventional nanosheet stack formation processes well known to those skilled in the art. In one example, the exemplary structure shown in FIGS. 1A and 1B can be formed by first forming a sacrificial placeholder material layer (not shown) on the surface of the second semiconductor material layer 14 of a semiconductor substrate, the substrate also including an etch stop layer 12 and a first semiconductor material layer 10. The sacrificial placeholder material layer can include a semiconductor material that is compositionally different from the second semiconductor material that provides the second semiconductor material layer 14, the third semiconductor material that provides each recessed sacrificial semiconductor material nanosheet 18, and the fourth semiconductor material that provides each semiconductor channel material nanosheet 20. Formation of the placeholder material layer can include, for example, an epitaxial growth process or any other deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or evaporation. After forming the placeholder material layer, a material stack of alternating layers of a third semiconductor material and a fourth semiconductor material layer is formed by epitaxial growth or one of the deposition processes described above for forming the placeholder material. Lithography and etching can then be used to pattern the material stack and placeholder material layer into a multilayer material structure that includes remaining portions of the placeholder material layer and remaining portions of the material stack.

[0060] The terms "epitaxial growth" or "epitaxially growing" refer to the growth of a second semiconductor material on the growth surface of a first semiconductor material, where the grown second semiconductor material has the same crystalline properties as the first semiconductor material. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves into the crystalline arrangement of the atoms at the growth surface. Examples of various epitaxial growth process equipment that can be utilized in this application include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures typically range from 550°C to 900°C. Higher temperatures usually result in faster deposition, but faster deposition can lead to crystalline defects and film cracking.

[0061] Next, a sacrificial gate structure 22 and a hard mask cap 24 are formed on this multilayer material by depositing a blanket layer of a sacrificial gate dielectric material (if present), a sacrificial gate material, and a dielectric hard mask material. Deposition of the dielectric hard mask material, the sacrificial gate material, and the blanket layer of the sacrificial gate dielectric material, if present, includes, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of such deposition processes. After forming these blanket layers, a patterning process (including lithography and etching) is used to convert the blanket layer of hard mask material into a hard mask cap 24 and to convert the blanket layer of sacrificial gate dielectric material (if present) and the sacrificial gate dielectric material into a sacrificial gate structure 22. The etching may include dry etching and / or wet chemical etching. The dry etching may include reactive ion etching (RIE), plasma etching, or ion beam etching (IBE). A plurality of such sacrificial gate structures 22 capped with hard mask caps 24 may be formed in each of the logic device region 100 and the MRAM device region 102.

[0062] Next, the placeholder material layer present in the multi-layer material stack is removed using an etching process that selectively removes the placeholder material layer. A space (or gap) is formed between the bottom sacrificial semiconductor material layer of the multi-layer material stack and the second semiconductor material layer 14. This structure is not free-floating but is held in place by the sacrificial gate structure 22. Next, the dielectric spacers 26 and the bottom dielectric insulating layer 16 are simultaneously formed. Specifically, the dielectric spacers 26 and the bottom dielectric insulating layer 16 are formed by depositing a gate dielectric spacer material followed by a spacer etch. The deposition fills the gap and forms the bottom dielectric insulating layer 16. In an embodiment, the dielectric spacers 26 can be I-shaped, with a top surface that is flush with the top surface of the hard mask cap 24.

[0063] After forming the dielectric spacers 22 and bottom dielectric insulating layer 16, the multilayer material stack including alternating layers of the third and fourth semiconductor materials is etched, with the hard mask caps 24 / gate structures 22 and the dielectric spacers 26 acting as an etch mask. The etching stops on the bottom dielectric insulating layer 16. In this application, the unetched (i.e., remaining) portion of each sacrificial semiconductor material layer is referred to as a sacrificial semiconductor material nano-sheet, and the unetched (i.e., remaining) portion of each semiconductor channel material layer is referred to as a semiconductor channel material nano-sheet 20.

[0064] Next, inner spacers 28 are formed. The inner spacers 28 are formed by first recessing each of the sacrificial semiconductor material nanosheets to form inner spacer gaps adjacent the ends of each recessed sacrificial semiconductor material nanosheet 18. After this recessing step, the remaining (i.e., recessed) sacrificial semiconductor material nanosheets 18 have reduced lateral widths compared to the widths of the original sacrificial semiconductor material nanosheets. The recessing step includes a lateral etching process that selectively removes the sacrificial semiconductor material nanosheets relative to the semiconductor channel material nanosheets 20. Next, inner spacers 28 are formed in the inner spacer gaps by conformal deposition of a spacer dielectric material, followed by isotropic etching.

[0065] 2A and 2B, the exemplary structures shown in FIGS. 1A and 1B, respectively, are illustrated after forming openings 32 in the semiconductor substrate in both the logic device region 100 and the MRAM device region 102. The openings 32 in both the logic device region 100 and the MRAM device region 102 may be formed by lithography and etching. The lithography step may include forming a patterned masking layer 30 having openings that physically expose the surface of the bottom dielectric insulating layer 16 in the region located between two adjacent nanosheet stacks, as shown in FIGS. 2A and 2B. The patterned masking layer 30 may include an organic planarization layer (OPL). The etching may include dry etching and / or chemical etching. The etching removes the physically exposed portions of the dielectric insulating layer 16 and stops within the sub-surface of the second dielectric material layer 14. The term "sub-surface" refers to the surface of a structure located between the top and bottom surfaces of the same structure. At this point in the application, the openings 32 formed in each of the logic device region 100 and the MRAM device region 102 extend to a first depth D1 below the top surface of the second dielectric material layer 14. After forming the openings 32 having the first depth D1, the patterned masking layer 30 is removed from the structure using one or more material removal processes.

[0066] 3A and 3B, the exemplary structures shown in FIGS. 2A and 2B, respectively, are illustrated after forming a block mask 31 in the logic device region 100 but not in the MRAM device region 102 and extending the depth of the opening 32 in the MRAM device region 102. By extending the depth of the opening 32 in the MRAM device region 102, an extended depth opening 32E is provided in the MRAM device region 102. The block mask 31 may include an OPL formed by deposition and lithographic patterning. Extending the depth of the opening 32 in the MRAM device region 102 includes an etching process as described above in forming the opening 32. The extended depth opening 32E extends to a second depth D2 below the top surface of the second dielectric material layer 14 in the MRAM device region 102. In the present application, D2 is greater than D1. In one example, D2 is about 90 nm and D1 is about 50 nm; here, the term "about" refers to ±10 percent of the numerical values.

[0067] 4A and 4B, the exemplary structures shown in FIGS. 3A and 3B, respectively, are illustrated after removing block mask 31 and forming sacrificial placeholder material 34 in openings 32 in logic device region 100 and extended depth openings 32E in MRAM device region 102. Block mask 31 is removed from logic device region 100 using one or more material removal processes. Sacrificial placeholder material 34 may be, for example, TiO x or AlO xThe sacrificial placeholder material 34 may include a metal oxide such as TiN or TaN, a metal nitride such as TiN or TaN, or a dielectric material such as SiCO or SiC, or a combination of a SiN liner and a SiO fill. The sacrificial placeholder material 34 may be formed by a deposition process such as CVD, PECVD, ALD, PVD, or spin-on coating. The sacrificial placeholder material 34 fills the opening 32 in the logic device region 100 and the extended depth opening 32E in the MRAM device region 102, and is formed on each of the hard mask-capped sacrificial gate structures present in both the logic device region 100 and the MRAM device region 102.

[0068] 5A and 5B, cross-sectional views of the example structures shown in FIGS. 4A and 4B, respectively, are illustrated after recessing the sacrificial placeholder material 34 in both the logic device region 100 and the MRAM device region 102 to provide a logic device region sacrificial placeholder material structure 34S in the logic device region 100 and a MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102. The recessing of the sacrificial placeholder material 34 in both the logic device region 100 and the MRAM device region 102 includes an etch-back process that selectively removes the sacrificial placeholder material 34. As shown in FIG. 5B, the sacrificial placeholder material structure 35S in the MRAM device region extends deeper into the second semiconductor material layer 14 than the sacrificial placeholder material structure 34S in the logic device region. In particular, the sacrificial placeholder material structure 35S in the MRAM device region extends a second depth D2 below the top surface of the second dielectric material layer 14 in the MRAM device region 102, while the sacrificial placeholder material structure 34S in the logic device region extends a first depth D1 below the top surface of the second dielectric material layer 14 in the logic device region 100.

[0069] 6A and 6B, the exemplary structures shown in FIGS. 5A and 5B, respectively, are illustrated after forming source / drain structures 36 and a first interlayer dielectric (ILD) material layer 38 in both the logic device region 100 and the MRAM device region 102. As used herein, a "source / drain or S / D" structure can be a source region or a drain region, depending on subsequent wiring and application of voltages during field-effect transistor (FET) operation. Each source / drain structure 36 is composed of a semiconductor material and a dopant. The semiconductor material providing the source / drain structures 36 can include one of the semiconductor materials described above for the first semiconductor material layer 10. The semiconductor material providing the source / drain structures 36 can be compositionally the same as or different from each semiconductor channel material nanosheet 20. However, the semiconductor material providing the source / drain structures 36 is compositionally different from each recessed sacrificial semiconductor material nanosheet 18. The dopant present in the source / drain structures 36 can be either a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the source / drain structures 36 are 4×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 In one example, the bottom source / drain structures 36 are composed of phosphorus-doped silicon.

[0070] The source / drain structures 36 can be formed through an epitaxial growth process and are formed on both sides of at least one nanosheet-containing material stack. The source / drain structures 36 grow outward from the physically exposed sidewalls of each semiconductor channel material nanosheet 20. In the logic device region 100, as shown in FIG. 6A, one of the source / drain structures 36 is grown on a sacrificial placeholder material structure 34S in the logic device region, while the other source / drain structure 26 is grown on a bottom dielectric insulating layer 16. In the MRAM device region 102, as shown in FIG. 6B, one of the source / drain structures 36 is grown on a sacrificial placeholder material structure 35S in the MRAM device region, while the other source / drain structure 26 is grown on a bottom dielectric insulating layer 16. The dopants defined above are typically present during the epitaxial growth process or by subsequent implantation. Recess etching can be employed to reduce the height of the source / drain structures 36 so that the same height does not extend above the sacrificial gate structure 22.

[0071] The ILD material layer 38 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants referred to herein are relative to a vacuum unless otherwise stated). Although not shown, the ILD material layer 38 may include a multilayer structure including at least two different dielectric materials stacked one on top of the other, such as silicon nitride and silicon dioxide. The ILD material layer 38 may be formed by a deposition process such as CVD, PECVD, or spin-on coating. Typically, a planarization process (including, for example, chemical mechanical polishing (CMP)) is performed after deposition of the dielectric material providing the ILD material layer 38. This planarization process removes the upper portions of the hard mask caps 24 and dielectric spacers 26, providing a structure in both the logic device region 100 and the MRAM device region 102 in which the ILD material layer 38 has a top surface that is coplanar with the top surface of the sacrificial gate structure 22. As shown in the drawings, the ILD material layer 38 overlies each source / drain structure 36.

[0072] 7A and 7B, the exemplary structures shown in FIGS. 6A and 6B, respectively, are illustrated after removing the sacrificial gate structure 22 and each recessed sacrificial semiconductor material nanosheet 18 of the at least one nanosheet-containing material stack in both the logic device region 100 and the MRAM device region 102, forming a functional gate structure 40 incorporating around each semiconductor channel material nanosheet 20 of the at least one nanosheet-containing stack, forming a second ILD material layer, forming front-side source / drain contact structures 44, forming front-side BEOL structures 46, and forming a carrier wafer 48. In the present application, the combination of the first ILD material layer 38 and the second ILD material layer may be referred to as the front-side ILD material layer 42.

[0073] The sacrificial gate structures 22 and the recessed sacrificial semiconductor material nanosheets 18 are removed using a first etching process that selectively removes the sacrificial gate structures 22 and a second etching process that selectively removes the recessed sacrificial semiconductor material nanosheets 18 relative to the semiconductor channel material nanosheets 20. For example, the second etching can be used to selectively remove SiGe sacrificial semiconductor material nanosheets relative to Si semiconductor channel material nanosheets. Removal of the recessed sacrificial semiconductor material nanosheets 18 provides suspended semiconductor channel material nanosheets 20 in each nanosheet-containing material stack. Removal of the sacrificial gate structures 22 and the recessed sacrificial semiconductor material nanosheets 18 provides gate openings above and below each suspended semiconductor channel material nanosheet 20 in the nanosheet-containing material stack.

[0074] Next, a functional gate structure 40 is formed in each gate opening. Source / drain structures 36 are disposed on each side of the functional gate structure 40. The functional gate structure 40 includes at least a gate dielectric material layer and a gate electrode; the gate dielectric material layer and the gate electrode are not separately illustrated in the drawings of this application. The functional gate structure 40 incorporates the periphery of the semiconductor channel material nanosheet 20, as shown in FIGS. 7A and 7B. As is known, the gate dielectric material layer of the functional gate structure 40 directly contacts the physically exposed portion of each semiconductor channel material nanosheet 20, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the functional gate structure includes a work function metal (WFM) layer (not shown) located between the gate dielectric material layer and the gate electrode. In some embodiments, an optional gate cap (not shown) can be formed on the functional gate structure 40.

[0075] Forming the functional gate structure 40 includes forming continuous layers of gate dielectric material and gate electrode material inside and outside the gate opening. The continuous layer of gate dielectric material may include silicon oxide or a dielectric material having a dielectric constant greater than 4.0 (such a dielectric material may be referred to as a high-k gate dielectric material). Illustrative examples of high-k gate dielectric materials include, for example, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO x High-k gate dielectric materials may include metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead tantalum scandium oxide (Pb(Sc,Ta)O), or lead zinc niobate (Pb(Zn,Nb)O), or combinations thereof. The high-k gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al), or magnesium (Mg), or combinations thereof. The continuous layer of gate dielectric material may be formed using a deposition process such as ALD, CVD, PECVD, or PVD. The continuous layer of gate dielectric material is a conformal layer having a thickness that may range from 1 nm to 10 nm.

[0076] Gate electrode materials include, but are not limited to, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), and the like. XThe gate electrode material may include a conductive metal-containing material including titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide, or nickel silicide. The gate electrode material may be formed using a deposition process such as, for example, ALD, CVD, PECVD, PVD, plating, or sputtering. In some embodiments of the present application, a reflow anneal or silicide anneal may be used after the conductive metal-containing material deposition is performed.

[0077] In some embodiments, a WFM (work function metal) layer can be formed on the continuous layer of gate dielectric material before forming the gate electrode material. In other embodiments, the gate electrode consists solely of WFM. The WFM layer can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to produce an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can produce an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer can be selected to produce a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift" refers to a shift in the effective work function of a metal-containing material toward the valence band of silicon in a silicon-containing material. Examples of materials that can produce a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The WFM layer is a conformal layer that can be formed by a conformal deposition process, such as ALD, CVD, or PECVD. The WFM layer can have a thickness ranging from 1 nm to 20 nm, although other thicknesses greater or less than this range can be used as desired for a particular application.

[0078] After forming the continuous layer of gate dielectric material, the optional layer of WFM, and the gate electrode material, a planarization process such as, for example, chemical mechanical polishing (CMP) is used to remove the continuous layer of gate dielectric material, the optional layer of WFM, and the gate electrode material from outside the gate opening. The remaining continuous layer of gate dielectric material present in the gate opening may be referred to as the gate dielectric material layer, the remaining optional layer of WFM present in the gate opening may be referred to as the WFM layer, and the remaining gate electrode material present in the gate opening provides the gate electrode of functional gate structure 40.

[0079] If present, the gate cap may be comprised of a hard mask material such as silicon dioxide or silicon nitride, with or without an air gap, or the gate cap may consist of only an air gap. The gate cap may be formed by a deposition process followed by a planarization process. In embodiments in which a gate cap is employed, the top of the functional gate structure 40 may be recessed prior to forming the gate cap. In the present application, the top surface of the functional gate structure 40, or the gate cap, if present, is coplanar with the top surface of the first ILD material layer 38.

[0080] A second ILD material layer is then formed over the first ILD material layer 38 and over the top surface of each functional gate structure 40. The second ILD material layer may include any of the dielectric materials described above for the first ILD material layer 38. The dielectric material providing the second ILD material layer may be compositionally the same as or compositionally different from the dielectric material providing the first ILD material layer 38. Again, the combination of the first ILD material layer 38 and the second ILD material layer provides the frontside ILD material layer 42 shown in Figures 7A and 7B. The second ILD material layer may be formed utilizing one of the deposition processes described above for forming the first ILD material layer 38.

[0081] Front-side source / drain contact structures 44 are then formed in each of the logic device region 100 and the MRAM device region 102. As shown in FIG. 7A , the front-side source / drain contact structure 44 in the logic device region 100 extends completely through the front-side ILD material layer 42 and directly contacts one surface of the source / drain structures 36 located above the bottom dielectric insulating layer 16. As shown in FIG. 7B , the front-side source / drain contact structure 44 in the MRAM device region 102 extends completely through the front side of the ILD material layer 42 and directly contacts one surface of the source / drain structures 36 located above the bottom dielectric insulating layer 16. Each front-side source / drain contact structure 44 can comprise compositionally the same or different contact conductor materials. The contact conductor materials can include, for example, a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. In embodiments, each front-side source / drain contact structure 44 may also include a silicide liner, such as TiSi, NiSi, NiPtSi, etc., and a deposited metal liner, such as TiN. The contact conductor material may be formed by any suitable deposition method, such as, for example, ALD, CVD, PVD, or plating. Each front-side source / drain contact structure may be formed by forming trenches in the front-side ILD material layer 42 that physically expose the surfaces of the source / drain structures 36 that overlie the bottom dielectric insulating layer 16. Each trench is then filled with contact conductor material and then planarized to remove the contact conductor material located outside the trenches.

[0082] In some embodiments (not shown), a metal-semiconductor alloy region can be formed in each trench that physically exposes the source / drain structures 36 located above the bottom dielectric insulating layer 16. The metal-semiconductor alloy region can be composed of a silicide or a germicide. In one or more embodiments of the present application, the metal-semiconductor alloy region can be formed by first depositing a metal layer (not shown) in the trench. The metal layer can include metals such as Ni, Co, Pt, W, Ti, Ta, rare-earth metals (e.g., Er, Yt, La), alloys thereof, or any combination thereof. The metal layer can be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer can be 2 nm to 10 nm, although smaller and larger thicknesses can also be employed. A diffusion barrier (not shown), such as TiN or TaN, can then be formed on the metal layer. Subsequently, an annealing process can be performed at high temperature to induce reaction of the semiconductor material of the source / drain structures 26 to provide the metal-semiconductor alloy region. The unreacted portions of the metal layer, and the diffusion barrier, if present, are then removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process may be a wet etch that removes the metal of the metal layer selective to the metal semiconductor alloy in the metal semiconductor alloy region.

[0083] Each front-side source / drain contact structure 44 may include one or more source / drain contact liners (not shown) formed along the sidewalls of the trench prior to forming the front-side source / drain contact structure 44. In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liners may be formed using a conformal deposition process, including CVD or ALD. The formed contact liners may have a thickness ranging from 1 nm to 5 nm, although smaller and larger thicknesses may also be used.

[0084] The front-side BEOL structures 46 include one or more interconnect dielectric material layers that contact one or more wiring regions buried thereon. The front-side BEOL structures 46 can be formed using BEOL processing techniques well known to those skilled in the art. The carrier wafer 48 can include one of the semiconductor materials described above for the first semiconductor material layer 10. In the present application, the carrier wafer 48 is typically bonded to the front-side BEOL structures 46 after the front-side BEOL structures 46 are formed on the front-side ILD material layer 42. As shown in FIGS. 7A and 7B , each front-side source / drain contact structure 44 has a first surface that directly contacts the surface of the front-side BEOL structure 46 and a second surface opposite the first surface that directly contacts the source / drain structures 36 located on the bottom dielectric insulating layer 16.

[0085] 8A and 8B, the exemplary structure shown in FIGS. 7A and 7B, respectively, is flipped 180° to show the exemplary structure after removal of the second semiconductor material layer 14 of the semiconductor substrate, where removal stops on the etch stop layer 12 of the semiconductor substrate. The flipping of the structure can be performed manually or using mechanical means such as, for example, a robotic arm. The removal of the second semiconductor material layer 14 can be performed using any material removal process, such as, for example, etching, that selectively removes the first semiconductor material layer 14.

[0086] 9A and 9B, the example structures shown in FIGS. 8A and 8B, respectively, are illustrated after removing etch stop layer 12 and first semiconductor material layer 10 of the semiconductor substrate to expose portions of sacrificial placeholder material structures 34S in the logic device region of logic device region 100 and portions of sacrificial placeholder material structures 35S in the MRAM device region of MRAM device region 102. Removal of etch stop layer 12 and first semiconductor material layer 10 can be performed using one or more material removal processes that selectively remove etch stop layer 12 and first semiconductor material layer 10 relative to sacrificial placeholder material structures 34S in the logic device region, sacrificial placeholder material structures 35S in the MRAM device region, and bottom dielectric insulating layer 16. In one example, a first etch is used to remove etch stop layer 12, and a second etch different from the first etch is used to remove first semiconductor material layer 10.

[0087] 10A and 10B, the exemplary structures shown in FIGS. 9A and 9B, respectively, are illustrated after forming a first backside ILD material layer 50. The backside ILD material layer 50 includes one of the dielectric materials described above for the first ILD material layer 38. The backside ILD material layer 50 may be formed utilizing one of the deposition processes described above in forming the first ILD material layer 38. A planarization process may follow the deposition process to expose sacrificial placeholder material structures 35S in the MRAM device region 102, as shown in FIG. 10B. As shown in FIG. 10A, a portion of the sacrificial placeholder material structures 34S in the logic device region is not exposed.

[0088] 11A and 11B, the exemplary structures shown in FIGS. 10A and 10B, respectively, are illustrated after removing sacrificial placeholder material structures 35S in the MRAM device region 102 to provide openings 52 that physically expose surfaces of source / drain structures 36 present in the MRAM device region 102. The physically exposed source / drain structures 36 are located on a side of the functional gate structure 40 that faces a side of the functional gate structure 40 that includes the source / drain structures 36 connected to front-side source / drain contact structures 44. In other words, the openings 52 physically expose the source / drain structures 36 on the opposite side of the nanosheet-containing material stack, including the front-side source / drain contact structures 44 that contact the source / drain structures 36 on that side of the nanosheet-containing material stack. Removing the sacrificial placeholder material structures 35S in the MRAM device regions within the MRAM device region 102 includes an etching process, such as, for example, reactive ion etching, that selectively removes the sacrificial placeholder material structures 35S in the MRAM device regions within the MRAM device region 102.

[0089] 12A and 12B, the exemplary structure shown in FIGS. 11A and 11B, respectively, is illustrated after forming precursor MRAM backside source / drain contact structures 54 in openings 52 present in the first backside ILD material layer 50 in the MRAM device region 102. The precursor MRAM backside source / drain contact structures 54 are composed of the materials described above for the frontside source / drain contact structures 44. The precursor MRAM backside source / drain contact structures 54 can be formed utilizing the processes described above in forming the frontside source / drain contact structures 44. The precursor MRAM backside source / drain contact structures 54 have top surfaces that are coplanar with the top surface of the first backside ILD material layer 50.

[0090] 13A and 13B, the exemplary structures shown in FIGS. 12A and 12B, respectively, are illustrated after recessing the precursor MRAM backside source / drain contact structures 54 to provide MRAM backside source / drain contact structures 54S beneath openings 52 present in the first backside ILD material layer 50 in the MRAM device region 102. Recessing the precursor MRAM backside source / drain contact structures 54 includes an optional recess etch process that selectively removes the material or materials that provide the precursor MRAM backside source / drain contact structures 54. The MRAM backside source / drain contact structures 54S have a first surface that extends below the bottom dielectric insulating layer 16 and contacts the surfaces of the source / drain regions 36, and a second surface opposite the first surface and located between the bottom and top surfaces of the first backside ILD material layer 50.

[0091] 14A and 14B, the exemplary structure shown in FIGS. 13A and 13B, respectively, is illustrated after forming a first electrode 56 on an MRAM backside source / drain contact structure 54 above an opening 52 present in a first backside ILD material layer 50 in an MRAM device region 102. The first electrode 56 has a top surface that is coplanar with the top surface of the first backside ILD material layer 50. The first electrode 56 has outermost walls that are substantially aligned with the outermost walls of both the MRAM backside source / drain contact structure 54S and the source / drain structure 36 located directly below the MRAM backside source / drain contact structure 54S. Notably, the first electrode 52, the MRAM backside source / drain contact structure 54S, and the source / drain structure 36 located directly below the MRAM backside source / drain contact structure 54S are self-aligned. The first electrode 56 is composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 56 can be formed by deposition of a conductive material (including, but not limited to, CVD, PECVD, or ALD) followed by a planarization process. The first electrode 56 functions as one of the electrodes of the MRAM formed in the MRAM device region 102.

[0092] 15A and 15B, the exemplary structures shown in FIGS. 14A and 14B, respectively, are illustrated after forming MRAM stacks 58 in both the logic device region 100 and the MRAM device region 102. The MRAM stacks 58 include at least a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments, the MRAM stacks 58 include, from bottom to top, a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. In other embodiments, the MRAM stacks 58 include, from bottom to top, a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. Other well-known MRAM material layers can be formed in the MRAM stacks 58.

[0093] The magnetic reference layer has a fixed magnetization. The magnetic reference layer may be composed of a metal or metal alloy (or stack thereof) including one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer may be a multilayer arrangement having (1) high spin polarization regions formed using metals and / or metal alloys using the metals described above, and (2) regions made of materials or materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, which may be arranged as alternating layers. The strong PMA region can also include alloys that exhibit strong PMA, with exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed. The thickness of the magnetic reference layer depends on the material selected. In one example, the magnetic reference layer may have a thickness of 0.3 nm to 3 nm.

[0094] The tunnel barrier layer is composed of an insulating material and is formed to a thickness that provides an appropriate tunneling resistance. Exemplary materials for the tunnel barrier layer include magnesium oxide, aluminum oxide, titanium oxide, or materials with higher electrical tunneling conductance, such as semiconductors or low bandgap insulators. The thickness of the tunnel barrier layer depends on the material selected. In one example, the tunnel barrier layer can have a thickness of 0.5 nm to 1.5 nm.

[0095] The magnetic free layer can be composed of a magnetic material (or stack of magnetic materials) having a magnetization that can change orientation relative to the magnetization orientation of the magnetic reference layer. Exemplary magnetic materials for the magnetic free layer include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, cobalt-iron-boron alloys, etc. The thickness of the magnetic free layer depends on the material selected. In one example, the magnetic free layer can have a thickness of 0.3 nm to 3 nm.

[0096] The MRAM layer stack 58 may be formed using one or more deposition processes such as, for example, plating, sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or PVD.

[0097] 16A and 16B, the exemplary structure shown in FIGS. 15A and 15B, respectively, is illustrated after patterning the MRAM stack 58 using a second electrode 60 formed on the MRAM stack 58 in the MRAM device region 102 as an etch mask to provide an MRAM stack 58S in the MRAM device region 102. Collectively, the first electrode 56, the MRAM stack 58S, and the top electrode 60 provide the MRAM. In some embodiments, and as illustrated in FIG. 16B, the top electrode 60 and the MRAM stack 58S have a width that is wider than the width of the first electrode 56. As further shown in FIG. 16B, a portion of the MRAM stack 56 extends beyond the width of the bottom electrode 56, and this extended portion of the MRAM stack 56 is located on a mesa region of the first backside ILD material layer 50. The second electrode 60 has an outermost wall that is substantially vertically aligned with the outermost edge of the MRAM stack 58S.

[0098] Patterning the MRAM stack 58 involves forming a blanket layer of one of the conductive materials described above for the bottom electrode 56 on the MRAM stack 58 via a deposition process. After forming the blanket layer of one of the conductive materials described above for the bottom electrode 56, the blanket layer can be patterned into the second electrode 60 using lithography and etching. The second electrode 60 is present only in the MRAM device region 102, and the blanket layer formed in the logic device region 100 is completely removed, as shown in FIG. 16A . The patterned resist used to pattern the second electrode 60 can be removed by ashing, and then the MRAM stack 58 is patterned using a pattern transfer etch (e.g., plasma etching or ion beam etching). During the pattern transfer etch, portions of the MRAM stack 58 not protected by the second electrode 60 are removed. The pattern transfer etch can also remove portions of the first backside ILD material layer 50. 16B , the pattern transfer etch can form mesa regions in the first backside ILD material layer 50. Note that because the first electrode 56 and the MRAM backside source / drain contact structures 54S remain embedded in the first backside ILD material layer 50, no resputtering of metal ions occurs in the MRAM device region 102. Also, because the sacrificial placeholder material structures 34S remain embedded in the first backside ILD material layer 50, no resputtering of metal ions from the sacrificial placeholder material structures 34S occurs in the logic device region 100.

[0099] 17A and 17B, the exemplary structure shown in FIGS. 16A and 16B, respectively, is illustrated after exposing the sacrificial placeholder material structure 34S in the logic device region and forming an MRAM spacer 62 laterally adjacent to both the second electrode 60 and the MRAM stack 62. Exposing the sacrificial placeholder material structure 34S in the logic device region includes an etch, such as a reactive ion etch, that removes the top portion of the first backside ILD material layer 50. This etch occurs in both the logic device region 100 and the MRAM device region 102. In the MRAM device region 102, this etch creates a step in the first backside ILD material layer 50, as shown in FIG. 17B. The MRAM spacer 62 is composed of a dielectric material. In one example, the MRAM spacer 62 is composed of silicon nitride. In another example, the MRAM spacer 62 can be composed of a dielectric material including atoms of silicon, carbon, and hydrogen. In some embodiments, in addition to atoms of carbon and hydrogen, the dielectric material providing the MRAM spacers 62 may include atoms of nitrogen and / or oxygen. In other embodiments, in addition to atoms of silicon, nitrogen, carbon, and hydrogen, the dielectric material providing the MRAM spacers 62 may include atoms of boron. In one example, the MRAM spacers 62 may be comprised of an nBLOK dielectric material, which includes atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the MRAM spacers 62 may be comprised of a SiBCN dielectric material, which includes atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0100] The MRAM spacers 62 can be formed using a deposition process such as PECVD, PVD, or PEALD, followed by a spacer etch. The MRAM spacers 62 can have a thickness of 10 nm to 200 nm. Other thicknesses are possible and can be employed for the MRAM spacers 62. As shown, the MRAM spacers 62 have a bottom surface formed on a stepped region of the first backside ILD material layer 50 and a top surface that is coplanar with the second electrode 60.

[0101] 18A and 18B, the example structures shown in Figures 17A and 17B, respectively, are illustrated after removing sacrificial placeholder material structures 34S in the logic device regions 100 to reveal source / drain structures 36 present in the logic device regions 100 located on the side of the nanosheet-containing material stack that does not include the front-side source / drain contacts 44. Removing the sacrificial placeholder material structures 34S in the logic device regions includes etching that selectively removes the sacrificial placeholder material structures 34S in the logic device regions.

[0102] 19A and 19B, the exemplary structures shown in FIGS. 18A and 18B, respectively, are illustrated after forming logic device backside source / drain contact structures 64 on the exposed source / drain structures 36 in the logic device region 100. The logic device backside source / drain contact structures 64 include the materials described above for the frontside source / drain contact structures 44. The logic device backside source / drain contact structures 64 may be formed by deposition, and an etch-back process may follow the deposition to provide the logic device backside source / drain contact structures 64 shown in FIG. 19A. The logic device backside source / drain contact structures 64 have outermost walls that may be aligned substantially perpendicular to the outermost surfaces of the source / drain regions 36 with which they physically contact. In accordance with the present application, the logic device backside source / drain contact structures 64 have their top surfaces disposed below the bottom surfaces of the MRAM spacers 62.

[0103] 20A and 20B, the exemplary structures shown in FIGS. 19A and 19B, respectively, are illustrated after forming backside power rails 66 in logic device region 100, a second backside ILD material layer in both logic device region 100 and MRAM device region 102, contact via structures 67 in both logic device region 100 and MRAM device region 100, and backside interconnect structures 70 in both logic device region 100 and MRAM device region 102.

[0104] The backside power rail 66 is composed of a power rail conductive material. Exemplary buried power rail conductive materials that may be used to provide the buried power rail include, but are not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), and a thin metal adhesion layer (such as TiN or TaN) is typically formed prior to conductive metal deposition. For clarity, the metal adhesion layer is not separately illustrated in the drawings of this application. The backside power rail 66 may be formed by first forming a block mask (not shown) in the MRAM device region 102. With this block mask in place, the backside power rail 66 is then formed in the logic device region 100 by a deposition process such as, for example, CVD, PECVD, PVD, sputtering, or plating. The block mask is removed during the deposition process. As shown, logic device backside source / drain contact structure 64 has a first surface in physical contact with logic device backside source / drain contact 64 and a second surface opposite the first surface in physical contact with backside power rail 66.

[0105] A second backside ILD material layer is then formed in both the logic device region 100 and the MRAM device region 102. In the logic device region 100, the second backside ILD material layer is spaced apart from the first backside ILD material layer 50 and may therefore be referred to as a separate ILD material layer 68. In the MRAM device region, the second backside ILD material layer is formed over the first backside ILD material layer 50 to form an MRAM backside ILD material layer stack 69. The MRAM backside ILD material layer stack 69 extends over the second electrode 60, as shown in FIG. 20B . The second backside ILD material layer may include one of the dielectric materials described above for the first ILD material layer 38 and may be formed by a deposition process as described above in providing the first ILD material layer 38.

[0106] Contact via structures 67 are then formed in both the logic device region 100 and the MRAM device region 102. Each contact via structure 67 is composed of a conductive metal or a conductive metal alloy. Exemplary conductive materials that can be used in providing the contact via structures 67 include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), or a Cu-Al alloy. Each contact via structure 67 can be formed by first providing a contact via opening in the separate ILD material layer 68 and the MRAM backside ILD material layer stack 69. In the logic device region 100, the contact via opening extends downward through the separate ILD material layer 68 to physically expose the surface of the backside power rail 66. In the MRAM device region 102, the contact via opening extends downward through the MRAM backside ILD material layer stack 69 and the top of the second electrode 60 to physically expose the top surface of the MRAM stack 58S. A conductive material is then formed in each contact via opening using a deposition process. A planarization process can follow the deposition process. In some embodiments, a diffusion barrier material layer (such as Ti or Ta) is deposited along the sidewalls of each of the contact via openings, followed by deposition of a conductive material, followed by a planarization process.

[0107] A backside interconnect structure 70 is then formed in both the logic device region 100 and the MRAM device region 102. The backside interconnect structure 70 comprises materials such as those described above for the frontside BEOL structures 46. The backside interconnect structure 70 may be formed using techniques known in the art. In the logic device region 100, a contact via structure 67 electrically connects the backside power rail 66 to the backside interconnect structure 70, while in the logic device region, the contact via structure 67 electrically connects the MRAM to the backside interconnect structure.

[0108] 20B shows a semiconductor structure including an MRAM (first electrode 56, MRAM stack 58S, and second electrode 60) disposed in an MRAM device region 102 and located on the backside of the wafer. The structure includes a first backside source / drain contact structure (i.e., MRAM backside source / drain contact structure 54S) that directly connects the MRAM first electrode 56 to a first source / drain structure 36 of a functional gate structure 40 that incorporates a first transistor (i.e., semiconductor channel material nano-sheet 20) present in the MRAM device region 102. The logic device region 100 may be laterally adjacent to the MRAM device level and located at the same level as the MRAM device region 102.

[0109] While the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a magnetoresistive random access memory (MRAM) device region and an MRAM disposed on the backside of the wafer, the MRAM including a first electrode, an MRAM stack, and a second electrode; and a first backside source / drain contact structure directly connecting the first electrode of the MRAM to a first source / drain structure of a first transistor present on the front side of the wafer and in the MRAM device region; A semiconductor structure comprising:

2. 2. The semiconductor structure of claim 1, wherein said first backside source / drain contact structure has an outermost wall that is substantially vertically aligned with an outermost wall of said first electrode.

3. 3. The semiconductor structure of claim 2, wherein the outermost wall of the first backside source / drain contact structure is substantially vertically aligned with the outermost wall of the first source / drain structure of the first transistor.

4. 10. The semiconductor structure of claim 1, wherein the first transistor comprises a vertical stack of semiconductor channel material nanosheets and a functional gate structure incorporating around each semiconductor channel material nanosheet of the vertical stack of semiconductor channel material nanosheets.

5. 5. The semiconductor structure of claim 4, further comprising a bottom dielectric insulating layer disposed on a surface of said first transistor, said bottom dielectric insulating layer having sidewalls in direct physical contact with outermost walls of said first backside source / drain contact structures.

6. The semiconductor structure of claim 4 further comprising an inner spacer disposed laterally adjacent said functional gate structure.

7. 10. The semiconductor structure of claim 1, further comprising: a second source / drain structure disposed on a second side of the functional gate structure of the first transistor opposite the first side of the functional gate structure of the first transistor.

8. 8. The semiconductor structure of claim 7, further comprising a first front side source / drain contact structure connecting the second source / drain structure of the first transistor to a back end of line (BEOL) structure.

9. The semiconductor structure of claim 8 , further comprising a carrier wafer disposed on a surface of the front-side BEOL structure.

10. 10. The semiconductor structure of claim 1, further comprising an MRAM spacer disposed laterally adjacent to and in direct physical contact with said MRAM stack and said second electrode, wherein said MRAM spacer is laterally adjacent to but spaced apart from said first electrode.

11. 11. The semiconductor structure of claim 10, wherein the MRAM spacer has a bottom surface disposed between a bottom surface and a top surface of the first electrode.

12. 10. The semiconductor structure of claim 1, further comprising a backside inter-layer dielectric (ILD) material layer stack laterally surrounding said MRAM and an upper portion of said first backside source / drain contact structure.

13. The semiconductor structure of claim 1 , wherein the second electrode is in electrical contact with a backside interconnect structure.

14. 14. The semiconductor structure of claim 13, further comprising a contact via structure extending vertically through the second electrode, the contact via structure having a first surface in direct contact with the MRAM stack and a second surface opposite the first surface in direct contact with the backside interconnect structure.

15. 10. The semiconductor structure of claim 1, further comprising: a second transistor disposed on the front side of the wafer in a logic device region disposed adjacent to the MRAM device region, wherein the second transistor has a first source / drain structure disposed on a first side of a functional gate structure of the second transistor and a second source / drain structure disposed on a second side of the functional gate structure of the second transistor opposite the first side of the functional gate structure of the second transistor.

16. 16. The semiconductor structure of claim 15, further comprising a second backside source / drain contact structure disposed in the logic device region, connecting the first source / drain structure of the second transistor to a backside power rail.

17. 17. The semiconductor structure of claim 16, wherein the backside power rail is in electrical contact with a backside interconnect structure.

18. 20. The semiconductor structure of claim 17, further comprising a via contact structure disposed between the backside interconnect structure and the backside power rail.

19. 16. The semiconductor structure of claim 15, further comprising a front-side source / drain contact structure disposed in the logic device region connecting the second source / drain structure of the second transistor to a front-side BEOL structure.

20. 20. The semiconductor structure of claim 19, further comprising a carrier wafer disposed on a surface of the front-side BEOL structure.

21. 17. The semiconductor structure of claim 16, wherein the second backside source / drain contact structure has a top surface disposed below a bottom surface of an MRAM spacer surrounding the MRAM device.

22. an MRAM device region including a magnetoresistive random access memory (MRAM) stack and a second electrode, the MRAM device region including an MRAM located on the backside of the wafer, a first transistor having a first source / drain structure disposed below the MRAM, and a first backside source / drain contact structure directly connecting the first electrode of the MRAM to the first source / drain structure of the first transistor, wherein the first backside source / drain contact structure has an outermost wall substantially vertically aligned with outermost walls of both the first source / drain structure and the first electrode of the first transistor; and a logic device region disposed adjacent to the MRAM device region, the logic device region being disposed on the front side of the wafer and having a second transistor having a first source / drain structure disposed on a first side of a functional gate structure of the second transistor, and a second backside source / drain contact structure directly connecting the first source / drain structure of the functional gate structure of the second transistor to a backside power rail; A semiconductor structure comprising:

23. 23. The semiconductor structure of claim 22, wherein the second backside source / drain contact structure has a top surface disposed below a bottom surface of an MRAM spacer surrounding the MRAM device.

24. 24. The semiconductor structure of claim 23, wherein the MRAM spacer has a bottom surface disposed between a bottom surface and a top surface of the first electrode.

25. 23. The semiconductor structure of claim 22, wherein the backside power rail is in electrical contact with a backside interconnect structure disposed on the backside power rail, and the second electrode of the MRAM is in electrical contact with the backside interconnect structure disposed on the MRAM.

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