Group III oxide devices with selected semi-insulating areas.

Abstract

III-oxide semiconductor devices with effective device isolation and edge termination regions.

Description

[Technical Field]

[0001] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with U.S. Government support from the Air Force Office of Funded Research under Contract No. E70-8618 / 8619. The U.S. Government has certain rights in this invention.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 395,809, filed August 6, 2022, which is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0003] These teachings generally relate to group III-oxide semiconductor devices having selected semi-insulating areas.

[0004] Among the future materials for high-power electronics, beta-phase gallium oxide (β-Ga2O3) has become a promising candidate due to its high critical magnetic field, relatively low hardness, and low-cost melt-growth processing. These properties enable gallium oxide to compete as a cost-effective replacement and upgrade for current Si-, SiC-, and GaN-based power electronics while remaining compatible with existing Si-centric CMP processes. However, fundamental building blocks such as selective semi-insulating definition have not been effectively demonstrated. Due to its intrinsic material properties, Ga2O3 cannot utilize ambipolar homojunctions for edge termination and device isolation, which are utilized in many power devices.

[0005] Ga2O3 isolation schemes via magnesium (Mg) doping, nitrogen (N) doping, thermal oxidation, hetero pn-junctions, and mesa etching have been reported. However, these results do not demonstrate the thermal and frequency dependence of each scheme. Mesa etching also fails to change the conductivity of gallium oxide; it only removes material to create an air barrier.

[0006] Therefore, alternative schemes need to be developed for effective device isolation and edge termination in Ga2O3.

[0007] A need exists for Group II oxide semiconductor devices with effective device isolation and edge termination regions. Summary of the Invention

[0008] III-oxide semiconductor devices with effective device isolation and edge termination regions are presented below.

[0009] In one or more embodiments, a III-oxide semiconductor device includes a III-oxide layer extending from a bottom distal surface to a top distal surface and from a first side extending from the bottom distal surface to the top distal surface to a second side extending from the bottom distal surface to the top distal surface, and at least one deep acceptor-doped region on a region of the III-oxide layer, the at least one deep acceptor-doped region including one or more regions extending from the first side to a III-oxide semiconductor structure, a region extending from the second side to a III-oxide semiconductor structure or another III-oxide semiconductor structure, a region extending between two III-oxide semiconductor structures, or a region extending between two III-oxide semiconductor subdevices. In one example, the deep acceptor does not include magnesium (Mg) or nitrogen (N). In another example, the at least one deep acceptor can include iron (Fe), copper (Cu), zinc (Zn), and cobalt (Co).

[0010] For a better understanding of the present teachings, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description, the scope of which is set forth in the appended claims. [Brief explanation of the drawings]

[0011] [Figure 1A] 1 is a diagrammatic representation of an illustrative device of these teachings.

[0012] [Figure 1B] 1 is a diagrammatic representation of another embodiment of a device of these teachings.

[0013] [Figure 1C] 10 is a diagrammatic representation of yet another embodiment of a device of these teachings.

[0014] [Figure 1D] 10 is a diagrammatic representation of yet another embodiment of a device of these teachings.

[0015] [Figure 1E] 10 is a diagrammatic representation of yet another embodiment of a device of these teachings.

[0016] [Figure 1F] 1 is a diagrammatic representation of a nitrogen implantation device used in these teachings.

[0017] [Figure 1G] Diagrammatic representation of the iron injection device used in these instructions.

[0018]

[0019] [Figure 2A] 1 is a diagrammatic representation of a variation of one embodiment of a device of these teachings.

[0020] [Figure 2B] 10 is a diagrammatic representation of a variation of another embodiment of the device of these teachings.

[0021] [Figure 2C] 10 is a diagrammatic representation of a further variation in this alternative embodiment of a device of these teachings.

[0022] [Figure 2D] 10 is a diagrammatic representation of a further variation of one embodiment of a device of these teachings.

[0023] [Figure 2E] 10 is a diagrammatic representation of a variation of yet another embodiment of the device of these teachings. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following detailed description sets forth a presently contemplated mode for carrying out these teachings. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of these teachings, since the scope of these teachings is best defined by the appended claims.

[0025] As used herein, "doping" refers to the introduction of foreign elements (not found in pure semiconductor crystals) into semiconductor crystals. The introduction of foreign elements can be achieved by diffusion or ion implantation. Techniques such as ion implantation, diffusion, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and pulsed laser deposition (PLD) ion implantation and diffusion are typically used to create selective area doping, although these teachings are not limited to only those techniques. (See, for example, Wafer Fabrication: Doping Techniques, available at www.halbleiter.org / en / waferfabrication / doping / .)

[0026] As used herein, an "acceptor" is a dopant atom that can form a p-type region when substituted into a semiconductor lattice.

[0027] As used herein, a "deep acceptor" is an acceptor whose acceptor energy level is too far from the valence band to create a free hole.

[0028] Studies have shown that conventional acceptor doping may not result in p-type conductivity because all acceptors are too deep to create free holes. However, incorporating acceptor impurities can still be useful to create semi-insulating materials (controlling conductivity), which can be used in devices with effective device isolation and edge termination. Edge termination requires complementary / compensating dopants, precise spatial control of doping, and known behavior of the edge material. Device isolation requires minimal leakage current that is robust to frequency and temperature. Complementary doping can deplete the drift region and create a resistive region to block current.

[0029] Deep acceptor doping by nitrogen implantation has been demonstrated (see, for example, Wong, M. H. et al. (2018), Applied Physics Letters, 113(10), 102103), but blocking was evaluated only under DC conditions. Nitrogen was found to exhibit a much lower thermal diffusivity than magnesium (Mg), which allows for the use of higher annealing temperatures to maximize N activation efficiency without significantly altering the impurity profile. Significant long-term charge trapping in the N-implanted layer has been shown (see, for example, Fregolent, M. et al. (2021), Journal of Applied Physics, 130(24), 2457040), but the approximately 0% trapped charge observed at 0.1 seconds suggests a frequency above which blocking does not occur.

[0030] The devices shown in Figures 1F and 1G were fabricated (including annealing) to determine the frequency-dependent behavior of nitrogen-implanted and ion-implanted III-oxide devices. Measurements showed that the nitrogen-implanted devices exhibited similar DC and pulsed IV characteristics, and that under DC conditions, the nitrogen-implanted layer blocked current. However, under pulsed conditions, the nitrogen-implanted layer only reduced forward current for long periods of time, and for very short periods of time, the nitrogen-implanted layer acted transparent to current conduction. Measurements also showed that the implanted iron blocked current under DC conditions. Under pulsed conditions, the iron-implanted layer blocked current volts in both the forward and reverse directions, and the current blockage was maintained in high-frequency measurements.

[0031] As used herein, "III" refers to one of the semiconductor elements and aluminum, or a combination of a semiconductor element and aluminum or aluminum from Group III. Of the Group III elements, those skilled in the art will know that boron trioxide is not a semiconductor. (Boron trioxide is most often found in a glassy (amorphous) form; however, it can crystallize after prolonged annealing (i.e., prolonged heating). See www.chemeurope.com / en / encyclopedia / Boron_trioxide.html.) Those skilled in the art will also know that thallium trioxide can be a degenerate (very highly doped) semiconductor (see Richard J. Phillips et al., Electrochemical and photoelectrochemical deposition of thallium(III) oxide thin films, Journal of Materials Research 4, 923-929 (1989), and H.P. Geserich, Phys. Status Solidi 25, 741 (1968)), making it unlikely to be used in transistors. Those skilled in the art will know that nihonium (the element formerly known as ununtrium) has no oxides because its most stable isotope (nihonium-286) has a half-life of about 8 seconds and decays into roentgenium, which is also unstable and part of the copper group (see periodic-table.com / nihonium / ).

[0032] In one or more embodiments, a III-oxide semiconductor device includes a III-oxide layer extending from a bottom distal surface to a top distal surface and from a first side extending from the bottom distal surface to the top distal surface to a second side extending from the bottom distal surface to the top distal surface; and at least one deep acceptor-doped region doped on a region of the III-oxide layer, the at least one deep acceptor-doped region including one or more of a region extending from the first side to a III-oxide semiconductor structure, a region extending from the second side to a III-oxide semiconductor structure or another III-oxide semiconductor structure, a region extending between two III-oxide semiconductor structures, or a region extending between two III-oxide semiconductor sub-devices.

[0033] In one example, the at least one deep acceptor is not magnesium (Mg) or nitrogen (N). In another example, the at least one deep acceptor can include at least one of iron (Fe), copper (Cu), zinc (Zn), or cobalt (Co).

[0034] In one example, the doping depth of the at least one deep acceptor-doped region is about 5 nm to several μm.

[0035] The activation temperature can vary. Typically, the activation temperature is 950°C, but can vary from about 400°C to about 1500°C.

[0036] Doping with deep acceptors can be carried out in multiple steps, with each doping step having a different concentration of deep acceptor.

[0037] In another example, the width of the at least one deep acceptor-doped region varies with distance from the top distal surface, and the variation in width can be the result of doping the deep acceptor at an angle relative to the substrate (typically when the doping is by implantation).

[0038] In yet another example, the concentration of the at least one deep acceptor-doped region varies with distance from the top distal surface. The concentration of the at least one deep acceptor-doped region varies with distance from the top distal surface. 16 cm -3 ~Approx. 5×10 20 cm -3 Typically, the concentration of the at least one deep acceptor-doped region is between 5±3×10 18 cm -3 is.

[0039] In yet another embodiment, the concentration of the at least one deep acceptor doped region is greater than the concentration of carriers in the group III oxide layer.

[0040] To further elucidate these teachings, an illustrative specific example is presented herein below in which the group III oxide semiconductor material is Ga2O3 and the deep acceptor is Fe. It should be noted that these teachings are not limited to this specific example.

[0041] In one example, in a III-oxide semiconductor device of these teachings, the at least one deep acceptor-doped region includes a first deep acceptor-doped region extending from a first side surface to the first side surface of the III-oxide semiconductor structure, the III-oxide semiconductor structure being an upright channel and a second deep acceptor-doped region. In the first deep acceptor-doped region, the upright channel extends to the distal top surface and extends from the distal top surface to a third distal surface, the third distal surface being disposed between the distal top surface and the bottom distal surface. The second deep acceptor-doped region extends from the second side surface to the second side surface of the III-oxide semiconductor structure and from the distal top surface to the third distal surface. Figure 1A shows the above example in which the deep acceptor is iron (Fe).

[0042] Referring to FIG. 1A, in the illustrated example, one Fe-doped region 20 extends from a first side to the upright channel (III-oxide semiconductor structure), and another Fe-doped region 15 extends from a second side to the other side of the III-oxide semiconductor structure. The Fe-doped region extends from the distal top surface to a third distal surface, which is disposed between the distal top surface and the bottom distal surface. A conductive layer 27 is disposed on the distal top surface section of the upright channel. Another conductive layer 25 is disposed on the bottom distal surface section of the III-oxide layer. (As used herein, a conductive layer includes a layer of material selected so that the potential difference between the conductive layer and the III-oxide semiconductor is sufficiently low for electrical conduction.) Examples of conductive layers include titanium (Ti) and indium-tin-oxide (ITO), although these teachings are not limited to these examples. Group III oxide layer 10 extends from the bottom distal surface to the top distal surface and from a first side of the group III oxide layer that extends from the bottom distal surface to the top distal surface to a second side of the group III oxide layer that extends from the bottom distal surface to the top distal surface.

[0043] The device shown in FIG. 1A is a Schottky diode, but other junctions, including PN diodes and metal-insulator-semiconductors, are also within the scope of these teachings. In the specific example of a PN diode, the III-oxide semiconductor structure is a vertical channel with a p-type heterojunction. Examples of p-type heterojunctions include GaN / Ga2O3 or NiO x / Ga2O3, but these teachings are not limited to these examples.

[0044] In some examples, as shown in FIG. 2A, at least one of the first side of the III-oxide semiconductor structure and the second side of the III-oxide semiconductor structure is inclined with respect to a plane perpendicular to the distal top surface.

[0045] In another specific example of a III-oxide semiconductor device of these teachings, the III-oxide semiconductor structure includes several channels extending from a central distal surface located between a bottom distal surface and a first intermediate distal surface. In another specific example of a III-oxide semiconductor device of these teachings, the III-oxide semiconductor structure includes several channels extending from a central distal surface located between the bottom distal surface and the first intermediate distal surface. In one example, the at least one deep acceptor-doped region includes a first deep acceptor-doped region, several deep acceptor-doped regions, and a final deep acceptor-doped region. The first deep acceptor-doped region extends from the central distal surface to the top distal surface and from a first side extending from the central distal surface to the top distal surface to a first side of a first channel from the several channels extending from the central distal surface to the top distal surface. Each one of the deep acceptor-doped regions extends from the central distal surface to the second intermediate distal surface and from a second side of a leading one of the channels extending from the central distal surface to the second intermediate distal surface to a first side of a trailing one of the channels extending from the central distal surface to the second intermediate distal surface. In some examples, the first intermediate distal surface is located above the top distal surface. In other examples, the second intermediate distal surface is located on the top distal surface, and the third intermediate distal surface is located on the top distal surface.

[0046] In yet another example, as shown in FIG. 2C, in at least one of several deep acceptor-doped regions, the doping concentration varies along the distance from the central distal surface to the second intermediate distal surface.

[0047] In yet another example, as shown in FIG. 2C, at least a portion of at least one side of at least one channel from the number of channels is inclined relative to a plane perpendicular to the central distal surface.

[0048] Specific examples are also possible in which the first deep acceptor-doped region extends from a first side extending from the second intermediate distal surface to the third intermediate distal surface and from the second intermediate distal surface to the third intermediate distal surface to a first side of a first channel from several channels extending from the second intermediate distal surface to the third intermediate distal surface, and each of the several deep acceptor-doped regions extends from a second side of a leading channel from the several channels extending from the central distal surface to the top distal surface and from the central distal surface to the top distal surface to a first side of a subsequent channel from the several channels extending from the central distal surface to the top distal surface. Variations on the above examples are also possible for these specific examples. Figure 1B shows the above specific example in which the group III oxide semiconductor structure includes several channels. In Figure 1B, the deep acceptor is iron (Fe).

[0049] 1B, in the illustrated embodiment, one Fe-doped region 30 extends from a first side to a first III-oxide semiconductor structure 40, which is a number of upright channels 40, 45, 50, and another Fe-doped region 35 extends from a second side to a final second side of the III-oxide semiconductor structure 50. The Fe-doped region extends from a third distal surface to a position within the III-oxide layer, which is located between the distal top and bottom surfaces. Each one of several other Fe-doped regions 47, 52 extends from one side of one of the upright channels 40, 45 to the opposite side of the next upright channel 45, 50. A dielectric layer is disposed on the side of the upright channel, on the third distal surface of each of the several Fe-doped regions 47, 52, on a portion of one Fe-doped region 30 extending from a position between the first side and a side opposite the first side of the first upright channel 40 of the upright channels, and on a portion of another Fe-doped region 35 extending from a side of the last upright channel of the upright channels, the side of the last upright channel of the upright channels being opposite the second side, and the section extends from a position between the second side and the side of the last upright channel of the upright channels to the side of the last upright channel of the upright channels. A conductive layer is disposed on the portion of the upright channel extending from the third distal surface to the distal top surface and on the dielectric layer. Another conductive layer 25 is disposed on the bottom distal surface section of the group III oxide layer. The thickness and material of the dielectric layer can vary depending on the device structure. The thickness of the dielectric layer can vary between about 1 nm and about 1000 nm. Typically, the thickness of the dielectric layer varies between about 5 nm and about 30 nm. Examples of dielectric materials include aluminum oxide (Al2O3), silicon dioxide (SiO2), and hafnium oxide (HfO2), although these teachings are not limited to only these examples.

[0050] In some embodiments, the bottom distal surface of the group III oxide layer is disposed on a deep acceptor-doped group III oxide substrate.

[0051] In one of some specific examples, a III-oxide semiconductor device includes first and second III-oxide semiconductor structures, each one of the first and second III-oxide semiconductor structures formed in a separate region of a III-oxide layer, and the at least one deep acceptor-doped region extends from the first III-oxide semiconductor structure to the second III-oxide semiconductor structure. In one example, the first III-oxide semiconductor structure extends from the first side surface to the first intermediate side surface, and the second III-oxide semiconductor structure extends from the second intermediate side surface to the second side surface, and the at least one deep acceptor-doped region includes a deep acceptor-doped region extending from the first intermediate side surface to the second intermediate side surface. The first group III oxide semiconductor structure extends from the first side surface to the first intermediate side surface, the second group III oxide semiconductor structure extends from the second intermediate side surface to the second side surface, and the at least one deep acceptor-doped region includes a deep acceptor-doped region extending from the first intermediate side surface to the second intermediate side surface.

[0052] 1C , in the illustrated embodiment, the Fe-doped region 55 extends from one side of one III-oxide semiconductor subdevice 57 to the side of another III-oxide semiconductor subdevice 62, which is opposite the one side of the one III-oxide semiconductor subdevice, and extends from the distal top surface to the bottom distal surface. An Fe-doped β-Ga2O3 substrate layer 60 is disposed on the bottom distal surfaces of the two III-oxide semiconductor subdevices within the Fe-doped region. In the illustrated embodiment, the two III-oxide semiconductor subdevices are FETs. A source conductive layer is disposed on a portion of the distal top surface of each of the III-oxide semiconductor subdevices, and a drain conductive layer is disposed on another portion of the distal top surface of each of the III-oxide semiconductor subdevices, the other portion being separated from and opposite the first portion. A dielectric layer is disposed on the distal top surface of each of the III-oxide semiconductor subdevices and between the source and drain conductive layers. In each of the two III-oxide semiconductor sub-devices, a gate conductive layer is disposed on the dielectric layer and is separated from the source and drain conductive layers.

[0053] In some embodiments, the III-oxide semiconductor structure includes a roughened region extending from the first intermediate side to the fourth intermediate side and from the second intermediate side to the third intermediate side, the roughened region extending from the central distal surface to the bottom distal surface. The III-oxide semiconductor structure includes a first pillar extending from the first intermediate side to the second intermediate side and a second pillar extending from the third intermediate side to the fourth intermediate side. The at least one deep acceptor-doped region includes a first deep acceptor-doped region extending from the first side to the first intermediate side and a second deep acceptor-doped region extending from the fourth intermediate side to the second side. The at least one deep acceptor-doped region also includes a third deep acceptor-doped region disposed between the first deep acceptor-doped region and the second deep acceptor-doped region and extending from the second intermediate side to a third intermediate side and from the central distal surface to the top distal surface, the central distal surface being located between the bottom distal surface and the top distal surface.

[0054] 1D , in the illustrated example, the first Fe-doped region 20 extends from a first side surface to a side surface of the first III-oxide semiconductor structure, the first III-oxide semiconductor structure 67 connects to the anode conductive layer, the second Fe-doped region 15 extends from a second side surface to a side surface of the second III-oxide semiconductor structure, the second III-oxide semiconductor structure 72 connects to the cathode conductive layer, and the third Fe-doped region 65 extends from another side surface of the first III-oxide semiconductor structure 67 to another side surface of the second III-oxide semiconductor structure 72, the other side surface of the second III-oxide semiconductor structure 72 being opposite to the other side surface of the first III-oxide semiconductor structure 67. The first and second Fe-doped regions 20, 15 extend from the distal top surface to the bottom distal surface. The third Fe-doped region 65 extends from the distal top surface to a position between the distal top surface and the bottom distal surface. An anode conductive layer is disposed on the first III-oxide semiconductor structure 67 at its distal top surface. A cathode conductive layer is disposed on the second III-oxide semiconductor structure 72 as its distal top surface. An Fe-doped β-Ga2O3 substrate layer 60 is disposed on the bottom distal surface of the III-oxide layer 10 and on the first and second Fe-doped regions 20, 15.

[0055] In still other embodiments, the III-oxide semiconductor structure includes a III-oxide semiconductor pillar extending from a first intermediate side to a second intermediate side and disposed on the upper distal surface of the III-oxide layer, the first side of the III-oxide semiconductor pillar being disposed a distance away from the first intermediate side and the second side of the III-oxide semiconductor pillar being disposed a distance away from the second intermediate side. The at least one deep acceptor-doped region includes a first deep acceptor-doped region extending from the first side to the first intermediate side and a second deep acceptor-doped region extending from the second intermediate side to the second side.

[0056] 1E, in the illustrated embodiment, one Fe-doped region 20 extends from a first side to a side of the group-III oxide layer 10, and another Fe-doped region 15 extends from a second side to another side of the group-III oxide layer 10. The one Fe-doped region 20 and the other Fe-doped region 15 extend from the top distal surface to the bottom distal surface. An upstanding group-III oxide channel 70 extends from the distal top surface to the third distal surface. A first (cathode) conductive layer is disposed on the top distal surface extending from the first side of the group-III oxide layer 10 to a position away from the upstanding group-III oxide channel 75. A second (cathode) conductive layer is disposed on the top distal surface extending from the second side of the group-III oxide layer 10 to a position away from the upstanding group-III oxide channel 75. A third (anode) conductive layer is disposed on the upstanding group-III oxide channel 75 at the third distal surface. 1E, the first and second conductive layers are conductive layers for the cathode, and the third conductive layer is a conductive layer for the anode. An Fe-doped β-Ga2O3 substrate layer 60 is disposed on the bottom distal surface of group III oxide layer 10 and on Fe-doped regions 15, 20.

[0057] Several variations of the embodiment shown in FIGS. 1A-1E are shown in FIGS. 2A-2E. Referring to FIG. 2A, the embodiment shown therein is a variation of the embodiment shown in FIG. 1A. In the variation shown in FIG. 2A, the single Fe-doped region 85 has varying widths, which vary with distance from the top distal surface. The variation in width can result from Fe doping at a predetermined angle relative to a line on the bottom distal surface, defined in a plane perpendicular to the bottom distal surface, for example, if deposition is by ion implantation. The predetermined angle is between 0 and 180 degrees, preferably between 45 and 135 degrees. (Alternatively, the predetermined angle is defined relative to a line perpendicular to the bottom distal surface and a line in a plane perpendicular to the bottom distal surface. Such angles are complementary to the aforementioned angle definitions, and the same ranges apply.) The width of the upright channel 82 also varies with distance from the top distal surface, and the variation in width of the upright channel is complementary (or opposite) to the variation in width of the single Fe-doped region 85. A field plate layer is disposed on the distal top surface over another Fe-doped region 80 and is in electrical contact with a conductive layer disposed over the upright channel. The field plate is electrically conductive.

[0058] 2B, the embodiment shown therein is a variation of the embodiment shown in FIG. 1B. In the variation shown in FIG. 2B, a dielectric layer is disposed on the side of the upright channel 90 and on the third distal surface of each of several Fe-doped regions 95. A conductive layer is disposed on the dielectric layer and on the distal top surface of the upright channel 90. A passivation layer is disposed on a portion of the conductive layer on the distal top surface of the upright channel, the portion extending from approximately the center of the conductive layer on the distal top surface of the upright channel to the side of the last upright channel and onto the dielectric layer on another Fe-doped region 95. In another embodiment, a passivation layer is disposed on a portion of the conductive layer on the distal top surface of the upright channel, the portion extending from approximately the center of the conductive layer on the distal top surface of the upright channel to the side of the first upright channel and onto the dielectric layer on one Fe-doped region. Examples of passivation layer materials include alumina (Al2O3), silicon dioxide (SiO2), Flourinert, and SU-8, but these teachings are not limited to just these examples.

[0059] Referring to FIG. 2C, the embodiment shown therein is another variation of the embodiment shown in FIG. 1B. In the variation shown in FIG. 2C, one Fe-doped region 125 extends from the fourth distal surface to the bottom distal surface, with the fourth distal surface being between the third distal surface and the bottom distal surface. The width of the first upright channel 107 varies from a larger width at the fourth distal surface to a smaller width at the top distal surface. Some or all of the other Fe-doped regions 110, 105, 120 may have different widths, and the width varies from the fourth distal surface to the third distal surface. Some or all of the other Fe-doped regions 110, 105, 120 may not be perfectly vertical. The dielectric layer is disposed on one Fe-doped region at the fourth distal surface, on the side of the upright channels 107, 117 from the distal top surface to the surface of one Fe-doped channel 125 at the fourth distal surface and from the distal top surface to the surfaces of several other Fe-doped regions 105, 110, and on a portion of another Fe-doped region 120 at the third distal surface, the portion extending from the side of the final upright channel 117 to a position between the side of the final upright channel 117 and the second side of the group III oxide layer 10.

[0060] In further embodiments, the at least one deep acceptor-doped region includes several deep acceptor-doped subregions. In one example, the deep acceptor-doped subregions from the second subregion to the next to last subregion are each disposed on top of the preceding subregion. In another example, each subregion has its own doping concentration. In yet another example, each subregion has its own doping concentration. In a further example, each subregion has a first side surface that is substantially parallel to the first side surface for the first subregion and to the last subregion for the second subregion, and a second side surface that is substantially parallel to the first side surface for the first subregion. In some embodiments, each subregion has its own doping concentration. In one example, each subregion extends from the central distal surface to the top distal surface. In a further example, a III-oxide semiconductor pillar is disposed between each two subsequent subregions.

[0061] Referring to FIG. 2D , the illustrated embodiment is another variation of the embodiment shown in FIG. 1A . In the variation shown in FIG. 2D , one Fe-doped region 130 includes several subregions of different widths 135, 140, and 145. In the illustrated embodiment, the first subregion with the narrower width 135 is located on the third distal surface. The widths of the subsequent subregions 140 and 145 increase from above the first subregion 135 to the distal top surface. Another Fe-doped region 150 includes several other subregions 152, 155, and 157 extending from the distal top surface to a fourth distal surface, which is located between the distal top surface and the third distal surface. A first of the other subregions extends from the second side of the group III oxide layer 10 to a distance between the second side of the group III oxide semiconductor structure and the second side of the group III oxide layer 10. Subsequent ones of the other subregions are disposed adjacent to one another up to a second side of the group III oxide layer. Each one of the other subregions can have a different Fe concentration. A group III oxide semiconductor pillar 160 is disposed between each two subsequent subregions.

[0062] 2E, the embodiment shown therein is another variation of the embodiment shown in FIG. 1C. In the variation shown in FIG. 2E, the first III-oxide semiconductor structure 165 extends from the first side to the first intermediate side, the second III-oxide semiconductor structure 170 extends from the second intermediate side to the second side, at least one deep acceptor region 175 has a deep acceptor region extending from the first intermediate side to the second intermediate side, the first III-oxide semiconductor structure has a textured region extending from the third intermediate side to the fourth intermediate side, the textured region extending from the central distal surface to the bottom distal surface, and the textured region creating two pillars, one pillar extending from the first side to the third intermediate side and the second pillar extending from the fourth intermediate side to the first intermediate side.

[0063] In Figures 1B, 2B, and 2C, the height of any one of the upright channels (sometimes referred to as a "fin") is about 50 nm to about 10 μm, preferably about 400 nm to about 2 μm. The distance between any two of the upright channels (sometimes referred to as the width of the "trench") is about 10 nm to about 50 μm, preferably about 100 nm to about 5 μm. The "trench depth" in Figure 2B refers to the distance between the original upper distal surface and the new surface created through selective material removal. The "trench doping depth" in Figure 2C refers to the depth to which Fe is doped.

[0064] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Unless otherwise indicated, all numbers expressing quantities of ingredients, reaction conditions, and the like used in the specification and claims are to be understood as modified in all instances by the term "about."

[0065] It should be noted that for purposes of better describing and defining the present teachings, terms of degree (e.g., "substantially," "about," etc.) may be used within the specification and / or claims. Such terms of degree are utilized herein to express the inherent degree of uncertainty that may result from any quantitative comparison, value, measurement, and / or other expression. Terms of degree may also be utilized herein to express the extent to which a quantitative expression may vary (e.g., ±10%) from the stated reference without resulting in a change in the basic functionality of the subject matter at issue.

[0066] While these teachings have been described in terms of various embodiments, it should be understood that these teachings are also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims.

Claims

1. 1. A group III oxide semiconductor device, comprising: a group III oxide layer extending from a bottom distal surface to a top distal surface and from a first side to a second side, the first side extending from the bottom distal surface to the top distal surface and the second side extending from the bottom distal surface to the top distal surface; at least one deep acceptor region doped on a region of the Group III oxide layer, the at least one deep acceptor region including one or more of a region extending from the first side to a Group III oxide semiconductor structure, a region extending from the second side to another Group III oxide semiconductor structure, or a region extending between two Group III oxide semiconductor structures, wherein the deep acceptor is not magnesium (Mg) or nitrogen (N); A group III oxide semiconductor device comprising:

2. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region has a depth of about 5 nm to about 10 μm.

3. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region has a depth of about 50 nm to about 5 μm.

4. the at least one deep acceptor region is about 1×10 １６ cm －３ ~Approx. 5×10 ２０ cm －３ 10. The Group III oxide semiconductor device of claim 1, having a deep acceptor concentration of

5. 10. The Group III oxide semiconductor device of claim 1, wherein said at least one deep acceptor region has a deep acceptor concentration greater than a concentration of carriers in said Group III oxide layer.

6. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region comprises two or more layers having different deep acceptor concentrations between the layers or different lengths, widths, depths, and / or areas between two adjacent layers.

7. The Group III oxide semiconductor device of claim 1 further comprising one or more conductive layers.

8. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region is in contact with at least one of a deep acceptor gallium oxide structure or a non-deep acceptor doped gallium oxide structure.

9. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region is in contact with at least one of a deep acceptor doped gallium oxide structure or a non-deep acceptor doped gallium oxide structure.

10. 10. The Group III oxide semiconductor device of claim 1, wherein the deep acceptor comprises at least one of iron (Fe), copper (Cu), zinc (Zn), or cobalt (Co).

11. 10. The Group III oxide semiconductor device of claim 1, wherein the deep acceptor comprises at least one of iron (Fe), copper (Cu), or cobalt (Co).

12. 10. The Group III oxide semiconductor device of claim 1, wherein the deep acceptor is iron (Fe).

13. the at least one deep acceptor region comprises: a first deep acceptor region extending from the first side to a first side of the III-oxide semiconductor structure, the III-oxide semiconductor structure being a vertical channel, the vertical channel extending to the distal top surface and from the distal top surface to a third distal surface, the third distal surface being disposed between the distal top surface and the bottom distal surface; a second deep acceptor region extending from the second side surface to a second side surface of the III-oxide semiconductor structure and from the distal top surface to the third distal surface; 10. The Group III oxide semiconductor device of claim 1, comprising:

14. 14. The Group III oxide semiconductor device of claim 13, wherein the deep acceptor is iron (Fe).

15. 14. The Group III oxide semiconductor device of claim 13, wherein at least one of the first side of the Group III oxide semiconductor structure and the second side of the Group III oxide semiconductor structure is sloped with respect to a plane perpendicular to the distal top surface.

16. 16. The Group III oxide semiconductor device of claim 15, wherein the deep acceptor is iron (Fe).

17. 10. The Group III oxide semiconductor device of claim 1, wherein the Group III oxide semiconductor structure includes a number of channels, the number of channels extending from a central distal surface located between the bottom distal surface and a first intermediate distal surface.

18. the at least one deep acceptor region comprises: a first deep acceptor-doped region extending from the central distal surface to the top distal surface and from the first side extending from the central distal surface to the top distal surface to a first side of a first channel from the number of channels extending from the central distal surface to the top distal surface; a number of deep acceptor regions, each one of the number of deep acceptor-doped regions extending from the central distal surface to a second intermediate distal surface and from a second side of a preceding channel of the number of channels extending from the central distal surface to the second intermediate distal surface to a first side of a succeeding channel of the number of channels extending from the central distal surface to the second intermediate distal surface; a final deep acceptor-doped region extending from the central distal surface to a third intermediate distal surface and from the second side extending from the central distal surface to the third intermediate distal surface to a second side of a final channel from the several channels extending from the central distal surface to the third intermediate distal surface; 20. The Group III oxide semiconductor device of claim 17, comprising:

19. 20. The group III oxide semiconductor device of claim 18, wherein the first intermediate distal surface is located above the top distal surface.

20. 20. The group III oxide semiconductor device of claim 19, wherein the second intermediate distal surface is located on the top distal surface and the third intermediate distal surface is located on the top distal surface.

21. 20. The group III oxide semiconductor device of claim 18, wherein at least a portion of at least one side surface of at least one channel from the number of channels is inclined with respect to a plane perpendicular to the central distal surface.

22. 20. The Group III oxide semiconductor device of claim 18, wherein at least one of the several deep acceptor regions has a doping concentration that varies along a distance from the central distal surface to the second intermediate distal surface.

23. the at least one deep acceptor region comprises: a first deep acceptor-doped region extending from a second intermediate distal surface to a third intermediate distal surface and from the first side extending from the second intermediate distal surface to the third intermediate distal surface to a first side of a first channel from the number of channels extending from the second intermediate distal surface to the third intermediate distal surface; a number of deep acceptor regions, each one of the number of deep acceptor-doped regions extending from the central distal surface to the top distal surface and from a second side of a preceding channel of the number of channels extending from the central distal surface to the top distal surface to a first side of a subsequent channel of the number of channels extending from the central distal surface to the top distal surface; a final deep acceptor-doped region extending from the second side surface extending from the central distal surface to the top distal surface and from the central distal surface to a fourth intermediate distal surface to a second side surface of a final channel from the several channels extending from the central distal surface to the top distal surface; 20. The Group III oxide semiconductor device of claim 17, comprising:

24. 24. The group III oxide semiconductor device of claim 23, wherein the first intermediate distal surface is located above the top distal surface.

25. 25. The Group III oxide semiconductor device of claim 24, wherein the second intermediate distal surface is located below the top distal surface and the third intermediate distal surface is located below the top distal surface.

26. 24. The group III oxide semiconductor device of claim 23, wherein at least a portion of at least one side of at least one channel from said number of channels is inclined with respect to a plane perpendicular to said central distal surface.

27. 24. The Group III oxide semiconductor device of claim 23, wherein at least one of the several deep acceptor regions has a doping concentration that varies along a distance from the central distal surface to the top distal surface.

28. 10. The Group III oxide semiconductor device of claim 1, wherein the bottom distal surface of the Group III oxide layer is disposed on a deep acceptor III oxide substrate.

29. 30. The Group III oxide semiconductor device of claim 28, comprising first and second Group III oxide semiconductor structures, each one of the first and second Group III oxide semiconductor structures formed in separate regions of the Group III oxide layer, and the at least one deep acceptor region extending for the first Group III oxide semiconductor structure to the second Group III oxide semiconductor structure.

30. 30. The Group III oxide semiconductor device of claim 29, wherein the first Group III oxide semiconductor structure extends from the first side surface to a first intermediate side surface, the second Group III oxide semiconductor structure extends from a second intermediate side surface to the second side surface, and the at least one deep acceptor region comprises a deep acceptor region extending from the first intermediate side surface to the second intermediate side surface.

31. 31. The Group III oxide semiconductor device of claim 30, wherein the deep acceptor region extends from the bottom distal surface to the top distal surface.

32. 29. The Group III oxide semiconductor device of claim 28, wherein the Group III oxide semiconductor structure has a textured region extending from a first medial side to a fourth medial side and extending from a second medial side to a third medial side, the textured region extending from a central distal surface to the bottom distal surface, and the Group III oxide semiconductor structure includes a first pillar extending from the first medial side to the second medial side and a second pillar extending from a third medial side to the fourth medial side.

33. 33. The Group III oxide semiconductor device of claim 32, wherein the at least one deep acceptor region includes a first deep acceptor region extending from the first side surface to a first intermediate side surface and a second deep acceptor region extending from a fourth intermediate side surface to the second side surface, and the at least one deep acceptor region also includes a third deep acceptor region disposed between the first and second deep acceptor regions and extending from the second intermediate side surface to the third intermediate side surface and from the central distal surface to the top distal surface, the central distal surface being located between the bottom distal surface and the top distal surface.

34. 29. The Group III oxide semiconductor device of claim 28, wherein the Group III oxide semiconductor structure comprises a Group III oxide semiconductor pillar extending from a first intermediate side to a second intermediate side and disposed on the top distal surface of the Group III oxide layer, a first side of the Group III oxide semiconductor pillar disposed a distance away from the first intermediate side and a second side of the Group III oxide semiconductor pillar disposed a distance away from the second intermediate side, and the at least one deep acceptor region comprises a first deep acceptor region extending from the first side to the first intermediate side and a second deep acceptor region extending from the second intermediate side to the second side.

35. 31. The Group III oxide semiconductor device of claim 30, wherein the first Group III oxide semiconductor structure has a textured region extending from a third intermediate side to a fourth intermediate side, the textured region extending from a central distal surface to the bottom distal surface, the textured region creating two pillars, one pillar extending from the first side to the third intermediate side and a second pillar extending from the fourth intermediate side to the first intermediate side.

36. 30. The Group III oxide semiconductor device of claim 28, wherein the deep acceptor used to dope the Group III oxide substrate comprises iron (Fe).

37. 10. The Group III oxide semiconductor device of claim 1, wherein the at least one deep acceptor region comprises several deep acceptor doped sub-regions.

38. 38. The Group III oxide semiconductor device of claim 37, wherein the deep acceptor doped subregions from the second subregion to the next to last subregion are each disposed on the preceding subregion.

39. 39. The Group III oxide semiconductor device of claim 38, wherein each subregion has a doping concentration for said each subregion.

40. 38. The Group III oxide semiconductor device of claim 37, wherein each subregion has a first side surface of the subregion that is substantially parallel to the first side surface for the first subregion and a second side surface of the subregion that is substantially parallel to the first side surface for the first subregion to a final subregion for the second subregion.

41. 41. The Group III oxide semiconductor device of claim 40, wherein each subregion has a doping concentration for said each subregion.

42. 41. The Group III oxide semiconductor device of claim 40, wherein each subregion extends from a central distal surface to the top distal surface.

43. 43. The Group III oxide semiconductor device of claim 42, wherein a Group III oxide semiconductor pillar is disposed between every two subsequent sub-regions.

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