Semiconductor package substrate and semiconductor package including the same

Abstract

The semiconductor package substrate of the embodiment includes an insulating layer having an upper surface and a lower surface, and a through electrode penetrating the upper surface and the lower surface of the insulating layer, and the side surface of the through electrode includes concave and convex portions alternately arranged along the vertical direction. Furthermore, a semiconductor package substrate according to another embodiment includes an insulating layer having an upper surface and a lower surface, and a through hole penetrating the upper surface and the lower surface of the insulating layer, and a sidewall of the through hole includes concave and convex portions alternately arranged along a vertical direction.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor package substrate and a semiconductor package including the same. [Background technology]

[0002] 2. Description of the Related Art As the performance of electric / electronic products continues to improve, technologies for attaching more packages to a substrate with a limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has been increasing due to the high specifications of products to which semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). In order to ensure reliability as the size of semiconductor packages increases, various configurations, such as those including interposers to connect multiple chips, are being researched.

[0004] In addition, semiconductor packages used in products providing the Internet of Things (IoT), autonomous vehicles, high-performance servers, etc., are required to have high performance and high reliability as they are becoming increasingly integrated. Here, high performance includes the ability to transmit signals at high speeds, the integration of the semiconductor package, and a high allowable current for transmittable signals.

[0005] In order to achieve miniaturization and integration of semiconductor packages, pad sizes are being reduced. The pads may be mounting pads connected to a chip or bump pads connected to various substrates. Here, the various substrates may include additional packages such as memory substrates, interposers connecting the chip and the semiconductor package substrate, and main boards of electronic devices to which the semiconductor package is applied.

[0006] Such a semiconductor package substrate is provided as a multilayer semiconductor package substrate. The multilayer semiconductor package substrate includes through electrodes disposed in through holes formed in a core substrate such as a copper clad laminate (CCL). In this case, the number of layers in a semiconductor package substrate is increasing as the wiring becomes more complex, and the thickness of the core substrate is increasing to improve strength and warpage characteristics due to the increased area. For example, while the thickness of a conventional core substrate was approximately 200 μm, the thickness has recently tended to increase by several times or more.

[0007] In this case, if the thickness of the core substrate increases, it becomes difficult to form through holes in the core substrate using a laser, and therefore, conventionally, through holes are formed in the core substrate using a drill machine.

[0008] However, when a through hole is formed using a drilling machine, the time required for the manufacturing process of the semiconductor package substrate increases, which reduces productivity and yield. Furthermore, the drilling machine is more expensive than laser equipment, which increases the manufacturing cost of the semiconductor package substrate.

[0009] Therefore, a new method is required to efficiently form through holes in semiconductor package substrates including core substrates of 200 μm or more. [Patent Document 1] KR10-2011-0016266A Summary of the Invention [Problem to be solved by the invention]

[0010] The embodiments provide a semiconductor package substrate with a new structure and a semiconductor package including the same.

[0011] Also, the embodiment provides a semiconductor package substrate capable of forming a through hole in a core substrate of 200 μm or more using a laser process, and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a semiconductor package substrate in which the difference between the maximum width and the minimum width of the through-hole in the vertical direction is minimized, and a semiconductor package including the same.

[0013] Further, the embodiments provide a semiconductor package substrate that prevents the size of the through-hole from expanding and allows the inclination of the inner wall of the through-hole to be nearly perpendicular, and a semiconductor package including the same.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the embodiments pertain from the following description. [Means for solving the problem]

[0015] The semiconductor package substrate of the embodiment includes an insulating layer having an upper surface and a lower surface, and a through electrode penetrating the upper surface and the lower surface of the insulating layer, and the side surface of the through electrode includes concave and convex portions alternately arranged along the vertical direction.

[0016] Furthermore, a semiconductor package substrate according to another embodiment includes an insulating layer having an upper surface and a lower surface, and a through hole penetrating the upper surface and the lower surface of the insulating layer, and a sidewall of the through hole includes concave and convex portions alternately arranged along a vertical direction.

[0017] The semiconductor package substrate further includes a through electrode disposed in the through hole, and a side surface of the through electrode has a convex portion corresponding to the convex portion on the side wall of the through hole and a concave portion corresponding to the concave portion on the side wall of the through hole.

[0018] The semiconductor package substrate further includes an insulating member penetrating the insulating layer, and the through electrode is provided to cover an outer surface of the insulating member.

[0019] The through electrodes each have a plurality of recesses and protrusions arranged alternately along the vertical direction.

[0020] The insulating member includes a first portion having a first width in a horizontal direction and a second portion having a second width in the horizontal direction that is different from the first width.

[0021] Moreover, the first width is larger than the second width, the first portion overlaps the concave portion of the through electrode in the horizontal direction, and the second portion overlaps the convex portion of the through electrode in the horizontal direction.

[0022] The insulating layer also includes a resin and reinforcing fibers arranged within the resin, and the reinforcing fibers include first fibers arranged in a first horizontal direction and second fibers arranged in a second horizontal direction perpendicular to the first horizontal direction.

[0023] The reinforcing fibers also include a plurality of groups spaced apart from one another along the vertical direction and each group includes one of the first and second fibers.

[0024] Moreover, the recess of the through electrode overlaps with the reinforcing fiber in the horizontal direction.

[0025] The thickness of the insulating layer in the vertical direction satisfies the range of 250 μm to 1200 μm.

[0026] The through-hole of the insulating layer has an inner wall including a plurality of first inner walls having protrusions and a second inner wall having no protrusions.

[0027] Also, the second inner wall refers to a portion of the inner wall of the through-hole that has a recess.

[0028] The through electrode includes a first portion in contact with the first inner wall and a second portion in contact with the second inner wall, and the first and second through patterns have a step.

[0029] Moreover, the first portion of the through electrode has a recess corresponding to the recess of the through hole, and the second portion of the through electrode has a protrusion corresponding to the protrusion of the through hole.

[0030] Furthermore, the thickness of each of the first and second portions of the through electrode in the horizontal direction satisfies the range of 10 μm to 25 μm.

[0031] Furthermore, the thickness of the first portion of the through electrode in the horizontal direction is the same as the thickness of the second portion in the horizontal direction.

[0032] The first through electrode includes a first metal layer disposed on an inner wall of the first through hole of the insulating layer, and a second metal layer disposed on the first metal layer.

[0033] In addition, the minimum width of the region having the smallest width in the entire vertical area of the first through hole satisfies the range of 55% to 95% of the maximum width of the region having the largest width in the entire vertical area of the first through hole. [Effects of the Invention]

[0034] In the semiconductor package substrate of the embodiment, a through hole with a minimized difference between the maximum width and the minimum width is formed in a first insulating layer having a thickness of 250 μm or more using a laser process equipment, thereby improving the physical and electrical characteristics of the first through electrode provided in the semiconductor package substrate.

[0035] Specifically, the first insulating layer is a core layer containing reinforcing fibers.

[0036] In this case, when the through hole is formed in the first insulating layer using a laser device, the through hole includes regions with different widths in the vertical direction, and the minimum width is less than 50% of the maximum width. As a result, in the comparative example, there is a problem in that the through electrode is unevenly disposed due to differences in plating speed in different regions during the plating process to dispose the through electrode in the through hole.

[0037] In the comparative example, the laser intensity was increased in the laser process conditions to minimize the difference between the minimum and maximum widths, but this resulted in a size expansion problem in which the through-hole size was formed larger than the target size.

[0038] In another comparative example, through holes are formed using a machine drilling device to minimize the difference between the minimum and maximum widths. However, when using the machine drilling device, only one through hole can be formed at a time, which results in a problem of reduced production yield.

[0039] In contrast, in an embodiment, a through hole is formed in a first insulating layer using at least two coordinate codes (T-codes). According to the embodiment, by using two coordinate codes according to energy intensity, laser process conditions can be changed during the through hole formation process. According to the embodiment, a first mask having an opening of a first size is irradiated with a laser of a first laser energy intensity using the first coordinate code to form a portion of the through hole. Furthermore, a second mask having an opening of a second size different from the first size is irradiated with a laser of a second laser energy intensity different from the first laser energy intensity using the second coordinate code to form the remaining portion of the through hole. As a result, the embodiment can prevent expansion of the through hole size and can form a through hole in the first insulating layer using laser equipment with a minimized difference between the maximum width and the minimum width. As a result, the embodiment can address uneven thickness of the first through electrode during a plating process to dispose the first through electrode in the first through hole. Furthermore, it can address physical issues such as peeling of the first through electrode from the first insulating layer or cracks occurring in the first through electrode. As a result, the embodiment can improve the physical properties of a semiconductor package substrate. As described above, in the embodiment, the first through-holes can be arranged to have a uniform thickness in the first insulating layer due to improved plating characteristics. This minimizes signal loss transmitted through the first through-holes, prevents voltage drops, and is advantageous for impedance matching, thereby increasing the flexibility of wiring design. Furthermore, the first through-holes according to the embodiment can improve the electrical characteristics of the semiconductor package substrate and the semiconductor package including the same.

[0040] In addition, the embodiment may form through holes using a laser device in a first insulating layer having a vertical thickness of 250 μm to 1200 μm and containing reinforcing fibers therein. As a result, the embodiment may reduce the time required to form through holes compared to forming through holes using a machine drilling device. As a result, the embodiment may improve the production yield of semiconductor package substrates. Furthermore, the embodiment may form through holes in all insulating layers of a multilayer substrate, including a core layer, using only a laser device. As a result, the embodiment may improve the efficiency of a manufacturing process of a semiconductor package substrate. Furthermore, the embodiment may reduce the manufacturing cost of a semiconductor package substrate because it does not require the use of a relatively expensive machine drilling device. [Brief explanation of the drawings]

[0041] [Figure 1a] FIG. 1a is a cross-sectional view illustrating a semiconductor package substrate according to a first comparative example. [Figure 1b] FIG. 1b is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example. [Figure 2a] FIG. 2a is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 2b] FIG. 2b is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 2c] FIG. 2c is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 2d] FIG. 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 2e] FIG. 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 2f] FIG. 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 2g] FIG. 2g is a cross-sectional view showing a semiconductor package according to the seventh embodiment. [Figure 3a]FIG. 3a is a diagram showing a semiconductor package substrate according to a first embodiment. [Figure 3b] FIG. 3b is a diagram showing a semiconductor package substrate according to a second embodiment. [Figure 4] FIG. 4 is a cross-sectional view illustrating the first insulating layer of the embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a first through hole provided in the first insulating layer of FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a first through electrode and an insulating member disposed in the through hole of FIG. [Figure 7] FIG. 7 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer of the first embodiment. [Figure 8] FIG. 8 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer of the second embodiment. [Figure 9] FIG. 9 is an optical microscope photograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment. [Figure 10-14] 10 to 14 are diagrams showing a part of a method for manufacturing a semiconductor package substrate according to an embodiment in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0042] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] However, the technical concept of the present invention is not limited to the described embodiments, but can be embodied in various different forms, and one or more of the components of the embodiments can be selectively combined or substituted within the scope of the technical concept of the present invention.

[0044] Furthermore, unless otherwise clearly and specifically stated, terms (including technical and scientific terms) used in the embodiments of the present invention are to be interpreted as meanings that are commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms such as dictionary-defined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to explain the embodiments and are not intended to limit the present invention.

[0045] In this specification, the singular can include the plural unless otherwise specified in the phrase, and when it is stated that "A and at least one (or one or more) of B and C" it can include one or more of all possible combinations of A, B and C. Furthermore, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b) etc. can be used.

[0046] Such terms are used to distinguish a component from other components, and do not limit the nature or order of the components, etc. When a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" to the other component by another component.

[0047] Furthermore, when it is stated that something is formed or disposed "above or below" a component, "above or below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components. Furthermore, when it is expressed as "above or below," it can mean not only the upper direction but also the lower direction based on one component.

[0048] FIG. 1a is a cross-sectional view illustrating a semiconductor package substrate according to a first comparative example, and FIG. 1b is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.

[0049] Before describing the comparative example, it is noted that semiconductor package substrates are required to have a high density in accordance with the trend toward higher performance electronic devices and higher integration of semiconductor devices, and therefore have a multi-layer structure.

[0050] Products that use such multi-layer semiconductor package substrates include FCBGA (Flip Chip Ball Grid Array) and FCCSP (Flip Chip Chip Scale Package). Some semiconductor package substrates used in FCBGA and FCCSP include a core layer.

[0051] The core layer has a certain thickness as an insulating layer having rigidity to realize a multi-layer buildup. The thickness of the core layer varies depending on the number of layers in the multi-layer buildup. For example, the core layer may have a thickness of 250 μm to 1200 μm to reduce voltage drop and / or signal loss due to complex wiring on the semiconductor package substrate.

[0052] Furthermore, through electrodes are formed in the core layer for electrical connection with the circuit patterns of each layer. The through electrodes may be formed by filling through holes that penetrate the upper and lower surfaces of the core layer with a conductive material. However, the above-mentioned core layer has a thickness of 250 μm to 1200 μm, and therefore, the process of forming the through holes and / or the process of forming the through electrodes in the comparative example have the following problems.

[0053] The through holes are formed using either a laser device or a drilling machine device. Figure 1a shows a first comparative example in which the through holes are formed using a laser device, and Figure 1b shows a second comparative example in which the through holes are formed using a drilling machine device.

[0054] 1a(a), in the first comparative example, an insulating layer 10 to be used as a core layer is prepared. At this time, the thickness t of the insulating layer 10 may be 250 μm to 1200 μm.

[0055] In the first comparative example, a through hole is formed in the insulating layer 10 using a laser device.

[0056] At this time, since the insulating layer 10 has a thickness t of 250 μm to 1200 μm, it is difficult to form through-holes by performing laser processing on only one side of the insulating layer 10. Therefore, in the first comparative example, through-holes are formed by performing laser processing on both the upper and lower surfaces of the insulating layer 10.

[0057] Specifically, in the first comparative example, a first part of the through hole is formed on the upper surface of the insulating layer 10 to correspond to the target size that the through hole should have, and a second part connected to the first part of the through hole is formed on the lower surface of the insulating layer 10.

[0058] However, when the laser energy intensity is set to correspond to the target size as shown in (b) of Figure 1a, the laser energy intensity is small compared to the thickness of the insulating layer 10, so when forming the first part 11 and the second part 12 as described above, a non-penetration problem may occur in which the first part 11 and the second part 12 are not connected to each other.

[0059] Therefore, in the first comparative example, the energy intensity of the laser is set to be large in order to solve the above-mentioned problem of incomplete penetration of the insulating layer 10. As a result, as shown in (c) of FIG. 1a, a first part 11 and a second part 12 having sizes larger than the target size that the through-hole should have are formed.

[0060] However, in this case, the through-hole has a width w1 that is larger than the target size, which makes it difficult to adjust the sizes of the through-hole and the through-electrode formed by filling it in the first comparative example to the desired target size.

[0061] Furthermore, in the first comparative example, as the size of the through hole becomes larger, problems such as voids (a phenomenon in which part of the through hole is not filled) and dimples may occur due to differences in plating speed during the process of filling the inside of the through hole with a conductive material.

[0062] In addition, in the first comparative example, a specific through hole is irradiated with a laser beam multiple times using one coordinate code (e.g., T-code). In this case, since the first comparative example uses one coordinate code, it is impossible to change the laser process conditions while multiple steps are in progress. Here, the laser process conditions may refer to the mask size, pulse width, energy intensity, collimation, number of steps, etc.

[0063] Therefore, in Comparative Example 1, when the initially set laser process conditions correspond to the target size, a non-penetration problem occurs. Furthermore, in Comparative Example 1, even if a through hole is formed penetrating the insulating layer 10, the minimum width of the entire area of the through hole in the vertical direction is less than 50% of the maximum width. As the difference between the minimum and maximum widths increases, there is a problem that the plating characteristics in the plating process for forming the through electrode deteriorate.

[0064] Referring to yet another prior art, as shown in (a) and (b) of FIG. 1b, in the second comparative example, the through-hole 20 is formed using a drilling machine equipment such as a CNC (computer numerical control) drill, rather than a laser.

[0065] When using a drilling machine, the slope of the inner wall of the through hole formed in the insulating layer 10 is substantially close to vertical.

[0066] However, since such through-holes 20 do not include a plating bridge, unlike the hourglass-shaped through-holes of FIG. 1a, it is difficult to uniformly fill the through-holes 20 with a conductive material.

[0067] Furthermore, drilling equipment is more expensive than laser equipment, so forming through holes using drilling equipment can result in significant infrastructure costs and increased manufacturing costs for semiconductor package substrates.

[0068] Furthermore, when the through hole 20 is formed using a drilling machine, there is a problem that productivity of the semiconductor package substrate is reduced. Specifically, when the drilling machine is used, for example, only one through hole can be formed at a time. As a result, the time required for the manufacturing process of the semiconductor package substrate is increased by several times or more compared to when a laser device is used, which results in a problem of reduced productivity and yield.

[0069] However, when forming through holes using the laser equipment according to the present embodiment, multiple through holes can be formed at once using openings included in a mask, and uniform through electrodes can be formed in each of the multiple through holes. Furthermore, compared to using a drill machine, the time required for manufacturing a semiconductor package substrate can be significantly reduced, thereby significantly improving productivity and yield.

[0070] In the embodiment, a through electrode with improved electrical and physical reliability can be formed inside a through hole formed in a core layer having a thickness of 250 μm to 1200 μm. For example, in the embodiment, a semiconductor package substrate including a through electrode with a new structure and a package substrate including the same are provided.

[0071] <Electronic Devices> Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described.

[0072] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0073] The electronic device includes a main board (not shown). The main board is physically and / or electrically connected to various components. The main board is also connected to a semiconductor package substrate according to the embodiment. Various semiconductor elements are mounted on the semiconductor package substrate.

[0074] The semiconductor device may include active and / or passive elements. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of active devices, such as transistors, are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) semiconductor chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0075] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and other memory chips.

[0076] On the other hand, the product group of semiconductor package substrates to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited to these.

[0077] Hereinafter, a semiconductor package including a semiconductor package substrate according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including the semiconductor package substrate, which will be described later. The semiconductor package substrate in one embodiment may be referred to as a first semiconductor package substrate, which will be described later, and the semiconductor package substrate in another embodiment may be referred to as a second semiconductor package substrate, which will be described later.

[0078] Figure 2a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0079] Referring to FIG. 2 a , the semiconductor package of the first embodiment may include a first semiconductor package substrate 100 , a second semiconductor package substrate 200 , and a semiconductor device 300 .

[0080] The first semiconductor package substrate 100 refers to a package substrate.

[0081] For example, the first semiconductor package substrate 100 may provide a space to which at least one external substrate is coupled. The external substrate may refer to the second semiconductor package substrate 200 coupled on the first semiconductor package substrate 100. Alternatively, the external substrate may refer to a main board included in an electronic device coupled below the first semiconductor package substrate 100.

[0082] Although not shown in the drawings, first semiconductor package substrate 100 may provide a space in which at least one semiconductor device is mounted in addition to the space in which second semiconductor package substrate 200 is mounted.

[0083] First semiconductor package substrate 100 includes at least one insulating layer, electrodes disposed on the at least one insulating layer, and a through portion penetrating through the at least one insulating layer.

[0084] A second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100 .

[0085] Exemplarily, the second semiconductor package substrate 200 may be an interposer. The second semiconductor package substrate 200 may provide a space in which at least one semiconductor device is mounted. The second semiconductor package substrate 200 is connected to at least one semiconductor device 300. For example, the second semiconductor package substrate 200 may provide a space in which a first semiconductor device 310 and / or a second semiconductor device 320 is mounted. The second semiconductor package substrate 200 may electrically connect the first semiconductor device 310 and the second semiconductor device 320, and may also electrically connect the first and second semiconductor devices 310 and 320 to the first semiconductor package substrate 100. That is, the second semiconductor package substrate 200 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor devices and the package substrate. Furthermore, to alleviate stress and warpage issues that arise due to the increased number of insulating layers stacked in a multi-layer build-up, the semiconductor package substrate may be divided into the first semiconductor package substrate 100 and the second semiconductor package substrate 200.

[0086] 2a illustrates two semiconductor devices 310 and 320 disposed on second semiconductor package substrate 200, but is not limited thereto. For example, one semiconductor device may be disposed on second semiconductor package substrate 200, or alternatively, three or more semiconductor devices may be disposed on second semiconductor package substrate 200.

[0087] In one embodiment, second semiconductor package substrate 200 may be an active interposer that functions as a semiconductor device. When second semiconductor package substrate 200 functions as an active circuit, the package of this embodiment has multiple logic chips mounted on first semiconductor package substrate 100 so that they are stacked vertically. A first logic chip among the logic chips that corresponds to the active interposer not only functions as the logic chip, but also transmits signals between first semiconductor package substrate 100 and a second logic chip disposed thereon.

[0088] According to another embodiment, the second semiconductor package substrate 200 may be a passive interposer. For example, the second semiconductor package substrate 200 may perform a signal relay function between the semiconductor device 300 and the first semiconductor package substrate 100. For example, the number of terminals on the semiconductor device 300 is gradually increasing due to factors such as 5G, Internet of Things (IOT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first semiconductor package substrate 100 is connected to the main board of an electronic device. Therefore, in order to provide the width and spacing required for the electrodes provided on the first semiconductor package substrate 100 to be connected to the semiconductor device 300 and the main board, respectively, the thickness of the first semiconductor package substrate 100 increases or the layer structure of the first semiconductor package substrate 100 becomes complex. Therefore, in the first embodiment, the second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100 and the semiconductor device 300. The second semiconductor package substrate 200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 300 .

[0089] On the other hand, the semiconductor package of the first embodiment may include a connecting portion.

[0090] For example, the semiconductor package includes a first connection portion 410 disposed between a first semiconductor package substrate 100 and a second semiconductor package substrate 200. The first connection portion 410 couples the second semiconductor package substrate 200 to the first semiconductor package substrate 100 and electrically connects them.

[0091] For example, the semiconductor package may further include a second connection part 420 disposed between the second semiconductor package substrate 200 and the semiconductor device 300. The second connection part 420 may couple the semiconductor device 300 onto the second semiconductor package substrate 200 and electrically connect them.

[0092] The semiconductor package includes a third connection portion 430 disposed on the bottom surface of the first semiconductor package substrate 100. The third connection portion 430 couples the first semiconductor package substrate 100 to the main board and electrically connects them together.

[0093] In this case, the first connecting part 410, the second connecting part 420, and the third connecting part 430 may represent at least one bonding method among wire bonding, solder bonding, and direct bonding between metals. That is, since the first connecting part 410, the second connecting part 420, and the third connecting part 430 have a function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0094] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The direct metal bonding method may refer to directly bonding multiple components by applying heat and pressure between the multiple components to recrystallize them without using materials such as solder, wire, or conductive adhesive. The direct metal bonding method may refer to a bonding method using the second connecting part 420. In this case, the second connecting part 420 may refer to a metal layer formed between the multiple components by recrystallization.

[0095] The first connecting portion 410, the second connecting portion 420, and the third connecting portion 430 may bond the plurality of components to each other using a TC (Thermal Compression) bonding method. TC bonding may refer to a method of bonding the plurality of components by applying heat and pressure to the first connecting portion 410, the second connecting portion 420, and the third connecting portion 430.

[0096] In this case, protrusions are arranged on electrodes on which the first connection portion 410, the second connection portion 420, and the third connection portion 430 are arranged in at least one of the first semiconductor package substrate 100 and the second semiconductor package substrate 200. The protrusions may protrude outward from the first semiconductor package substrate 100 or the second semiconductor package substrate 200.

[0097] The protrusion may be referred to as a bump, a post, or a pillar. Preferably, the protrusion may refer to an electrode of the second semiconductor package substrate 200 on which a second connection portion 420 for coupling with the semiconductor device 300 is disposed. That is, as the pitch of the terminals of the semiconductor device 300 becomes finer, short circuits may occur between the second connection portions 420 connected to the terminals of the semiconductor device 300. Therefore, in this embodiment, in order to reduce the volume of the second connection portion 420, the electrode of the second semiconductor package substrate 200 on which the second connection portion 420 is disposed may include a protrusion. The protrusion may improve the alignment between the electrode of the second semiconductor package substrate 200 and the terminal of the semiconductor device 300 and prevent the second connection portion 420 from spreading.

[0098] 2b, the semiconductor package of the second embodiment differs from the semiconductor package of the first embodiment in that it includes connecting members 210 that horizontally connect a plurality of semiconductor elements arranged on a second semiconductor package substrate 200. The connecting members 210 can be referred to as a bridge substrate.

[0099] In one embodiment, the connecting member 210 may be a silicon bridge, i.e., the connecting member 210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0100] In another embodiment, the connecting member 210 may be an organic bridge. For example, the connecting member 210 may include an organic material. For example, the connecting member 210 may include an organic substrate including an organic material instead of a silicon substrate, and a redistribution layer disposed on the organic substrate.

[0101] The connecting member 210 may be, but is not limited to, embedded in the second semiconductor package substrate 200. For example, the connecting member 210 may be disposed in a protruding structure above the second semiconductor package substrate 200.

[0102] In addition, the second semiconductor package substrate 200 may include a cavity, and the connecting member 210 may be disposed within the cavity of the second semiconductor package substrate 200 .

[0103] 2c, the semiconductor package of the third embodiment includes a second semiconductor package substrate 200 and a semiconductor device 300. The semiconductor package of the third embodiment has a structure in which the first semiconductor package substrate 100 is removed from the semiconductor package of the second embodiment.

[0104] That is, the second semiconductor package substrate 200 of the third embodiment can function as an interposer and also as a package substrate.

[0105] The first connection portion 410 disposed on the bottom surface of the second semiconductor package substrate 200 can couple the second semiconductor package substrate 200 to a main board of an electronic device.

[0106] Referring to FIG. 2 d , the semiconductor package of the fourth embodiment includes a first semiconductor package substrate 100 and a semiconductor device 300 .

[0107] In this case, the semiconductor package of the fourth embodiment has a structure in which the second semiconductor package substrate 200 is removed, compared to the semiconductor package of the second embodiment.

[0108] That is, the first semiconductor package substrate 100 of the fourth embodiment can function as a package substrate and also as an interposer that connects the semiconductor devices 300 and the main board. To this end, the first semiconductor package substrate 100 can include a connecting member 110 for connecting the plurality of semiconductor devices. The connecting member 110 can be a silicon bridge or an organic bridge that connects the plurality of semiconductor devices.

[0109] Referring to FIG. 2e, the semiconductor package of the fifth embodiment further includes a third semiconductor element 330 compared to the semiconductor package of the fourth embodiment.

[0110] To this end, a fourth connection part 440 is disposed on the bottom surface of the first semiconductor package substrate 100 .

[0111] The third semiconductor element 330 is disposed on the fourth connection portion 400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0112] In this case, the third semiconductor device 330 may have a structure in which it is disposed on the lower surface of the second semiconductor package substrate 200 in the semiconductor package of FIG. 2c.

[0113] Referring to FIG. 2 f , the semiconductor package of the sixth embodiment includes a first semiconductor package substrate 100 .

[0114] A first semiconductor device 310 is disposed on the first semiconductor package substrate 100. To this end, a first connection part 410 is disposed between the first semiconductor package substrate 100 and the first semiconductor device 310.

[0115] The first semiconductor package substrate 100 also includes a conductive coupling part 450. The conductive coupling part 450 may further protrude from the first semiconductor package substrate 100 toward the second semiconductor device 320. The conductive coupling part 450 may be referred to as a bump or alternatively as a post. The conductive coupling part 450 may be disposed in a protruding structure on an electrode disposed on the top side of the first semiconductor package substrate 100.

[0116] The second semiconductor device 320 is disposed on the conductive coupling part 450 of the first semiconductor package substrate 100. At this time, the second semiconductor device 320 is connected to the first semiconductor package substrate 100 via the conductive coupling part 450. In addition, a second connection part 420 is disposed on the first semiconductor device 310 and the second semiconductor device 320.

[0117] As a result, the second semiconductor element 320 is electrically connected to the first semiconductor element 310 via the second connection portion 420 .

[0118] That is, the second semiconductor chip 320 is connected to the first semiconductor package substrate 100 through the conductive coupling portion 450 and also connected to the first semiconductor chip 310 through the second connection portion 420 .

[0119] At this time, the second semiconductor device 320 receives a power signal through the conductive coupling part 450. In addition, the second semiconductor device 320 can exchange communication signals with the first semiconductor device 310 through the second connection part 420.

[0120] The semiconductor package of the sixth embodiment provides a power signal to the second semiconductor device 320 via the conductive coupling part 450, thereby providing sufficient power to drive the second semiconductor device 320. As a result, the embodiment can improve the driving characteristics of the second semiconductor device 320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 320. Furthermore, the embodiment allows the power signal and the communication signal of the second semiconductor device 320 to be provided via different paths via the conductive coupling part 450 and the second connection part 420. As a result, the embodiment can solve the problem of loss of the communication signal due to the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal. Meanwhile, the second semiconductor device 320 in the sixth embodiment may be disposed on the first semiconductor package substrate 100 using a package-on-package (POP) structure. For example, the second semiconductor device 320 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 450. In this case, the memory package may not be connected to the first semiconductor device 310. For example, in the case of a POP structure, the second connection portion 420 may be omitted.

[0121] Meanwhile, the semiconductor package according to the sixth embodiment may include a molding member 1460. The molding member 1460 is disposed between the first substrate 1100 and the second semiconductor element 1320. For example, the molding member 1460 may mold the first connecting portion 1410, the second connecting portion 1420, the first semiconductor element 1310, and the conductive coupling portion 1450.

[0122] Referring to FIG. 2g, the semiconductor package of the seventh embodiment includes a first semiconductor package substrate 100, a first connecting portion 410, a semiconductor device 300, and a third connecting portion 430.

[0123] The semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 110 is removed and the first semiconductor package substrate 100 includes a plurality of substrate layers.

[0124] The first semiconductor package substrate 100 includes multiple substrate layers. For example, the first semiconductor package substrate 100 may include a first substrate layer 100A corresponding to a package substrate and a second substrate layer 100B corresponding to a redistribution layer of a connecting member.

[0125] That is, first semiconductor package substrate 100 has second substrate layer 100B, which corresponds to the rewiring layer, disposed on first substrate layer 100A.

[0126] In other words, the semiconductor package of the seventh embodiment includes a semiconductor package substrate including an integrally formed first substrate layer 100A and a second substrate layer 100B. The material of the insulating layer of the second substrate layer 100B may be different from the material of the insulating layer of the first substrate layer 100A. For example, the material of the insulating layer of the second substrate layer 100B may include a photo-curable material. For example, the second substrate layer 100B may be a PID (Photo Imageable Dielectric). The second substrate layer 100B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second substrate layer 100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first substrate layer 100A and forming miniaturized electrodes on the insulating layers of the photo-curable material. As a result, the second substrate 100B may be a redistribution layer including miniaturized electrodes.

[0127] The semiconductor package substrate according to the embodiment will be described below.

[0128] Before describing the semiconductor package substrate of the embodiment, the semiconductor package substrate described below may refer to any one of a plurality of semiconductor package substrates included in a previous semiconductor package.

[0129] For example, in one embodiment, the semiconductor package substrate described below may refer to the first semiconductor package substrate 100 and / or the second semiconductor package substrate 200 illustrated in any one of FIGS. 2a to 2g.

[0130] FIG. 3a is a view showing a semiconductor package substrate according to a first embodiment, and FIG. 3b is a view showing a semiconductor package substrate according to a second embodiment.

[0131] Hereinafter, a semiconductor package substrate according to an embodiment will be briefly described with reference to FIG. 3a, and a partial configuration different from that of FIG. 3a will be described with reference to FIG. 3b.

[0132] The semiconductor package substrate 500 of the embodiment includes an insulating layer 510. In this case, the insulating layer 510 of the embodiment may have a multi-layer structure. For example, the insulating layer 510 of the semiconductor package substrate of the embodiment may include a first insulating layer 511, a second insulating layer 512, and a third insulating layer 513. In FIG. 3, the second insulating layer 512 and the third insulating layer 513 are illustrated as a single layer, but the present invention is not limited thereto, and a configuration in which multiple insulating layers are stacked may also be used.

[0133] The first insulating layer 511 may include a different insulating material than the second insulating layer 512 and the third insulating layer 513 .

[0134] For example, the first insulating layer 511 may include an insulating material containing reinforcing fibers and may be a core layer.

[0135] For example, the first insulating layer 511 may include a prepreg. The first insulating layer 511 may increase the physical strength of the semiconductor package substrate and improve warpage characteristics.

[0136] The first insulating layer 511 of the embodiment may have a structure in which a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, is impregnated with epoxy resin or the like.

[0137] In addition, the prepreg constituting the first insulating layer 511 of the embodiment may include a fiber layer in the form of a woven fabric sheet woven with carbon fiber threads.

[0138] Specifically, the first insulating layer 511 may include a resin and reinforcing fibers disposed within the resin. The resin may be, but is not limited to, an epoxy resin. The resin is not particularly limited to epoxy resin, and may, for example, include one or more epoxy groups within the molecule, or alternatively, may include two or more epoxy groups, or alternatively, may include four or more epoxy groups. Furthermore, the resin constituting the first insulating layer 511 may include a naphthalene group, and may be, for example, an aromatic amine type, but is not limited thereto. Examples of the resin include bisphenol A-type epoxy resins, bisphenol F-type epoxy resins, bisphenol S-type epoxy resins, phenol novolac-type epoxy resins, alkylphenol novolac-type epoxy resins, biphenyl-type epoxy resins, aralkyl-type epoxy resins, dicyclopentadiene-type epoxy resins, naphthalene-type epoxy resins, naphthol-type epoxy resins, epoxy resins that are condensates of phenols with aromatic aldehydes having a phenolic hydroxyl group, biphenylaralkyl-type epoxy resins, fluorene-type epoxy resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, and phosphorous-based epoxy resins, and include naphthalene-based epoxy resins, bisphenol A-type epoxy resins, phenol novolac epoxy resins, cresol novolac epoxy resins, rubber-modified epoxy resins, and phosphorous-based epoxy resins. The reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (e.g., aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. The reinforcing fibers may be arranged in a cross-sectional shape in the resin.

[0139] On the other hand, glass fiber, carbon fiber, aramid fiber (for example, aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material can be used.

[0140] In this case, at least two layers of reinforcing fibers may be provided in the first insulating layer 511. This can further improve the rigidity of the substrate 500 in this embodiment.

[0141] The vertical thickness of the first insulating layer 511 may be greater than the vertical thickness of at least one of the second insulating layer 512 and the third insulating layer 513. For example, the vertical thickness of the first insulating layer 511 may be three or more times, four or more times, five or more times, seven or more times, or ten or more times the vertical thickness of the second insulating layer 512 and the third insulating layer 513.

[0142] Recently, as semiconductor packages have become more sophisticated, the number of insulating layers in semiconductor package substrates has also increased. For example, the number of insulating layers in a semiconductor package substrate may be 10 or more, 12 or more, 16 or more, or 20 or more. Specifically, if the second insulating layer 512 and the third insulating layer 513 are each stacked in multiple layers, as shown in the figure, stress from each insulating layer may cause warping of the semiconductor package substrate. Warping of the semiconductor package substrate may make it difficult to accurately position the through-hole electrodes included in the semiconductor package substrate. Furthermore, warping of the semiconductor package substrate may cause problems such as misalignment of the semiconductor device during the process of mounting the semiconductor device on the semiconductor package substrate. Therefore, to prevent warping of the semiconductor package substrate, the vertical thickness of the first insulating layer 511 may be 250 μm or more. This increases the physical rigidity of the semiconductor package substrate and improves the warpage characteristics of the semiconductor package substrate during the packaging process. Furthermore, if the thickness of the first insulating layer 511 is excessively large, the process of forming through-holes in the first insulating layer 511 becomes difficult, which may result in a deterioration in the electrical characteristics of signals and / or power applied to the semiconductor element. Furthermore, it becomes difficult to slim down the semiconductor package, which makes it difficult to reduce the volume of the electronic device. Therefore, it is appropriate that the vertical thickness of the first insulating layer 511 be 1200 μm or less.

[0143] The second insulating layer 512 and the third insulating layer 513 may include an insulating material different from that of the first insulating layer 511. For example, the second insulating layer 512 and the third insulating layer 513 may not include reinforcing fibers, but this is not limiting.

[0144] For example, the second insulating layer 512 and the third insulating layer 513 may include any one of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric resin (PID), BT, and the like.

[0145] In addition, the second insulating layer 512 and the third insulating layer 513 may contain reinforcing fibers, which may be glass fibers or may contain a GCP (Glass Core Primer) material, but are not limited thereto.

[0146] Furthermore, the second insulating layer 512 and the third insulating layer 513 may be, but are not limited to, a CCL (Copper Clad Laminate) type insulating layer.

[0147] The second insulating layer 512 and the third insulating layer 513 may have a vertical thickness ranging from 10 μm to 50 μm. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 μm, the warpage characteristics of the semiconductor package substrate 500 may be reduced. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 μm, the circuit pattern layer included in the semiconductor package substrate 500 may not be reliably protected or its insulating characteristics may be reduced, resulting in reduced electrical reliability. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 μm, the overall thickness of the semiconductor package substrate 500 increases, thereby increasing the thickness of the semiconductor package. If the thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 μm, it becomes difficult to miniaturize the circuit pattern layer of the semiconductor package substrate 500.

[0148] The vertical thickness may refer to the length from the top to the bottom or from the bottom to the top of the semiconductor package substrate 500. Here, the top may refer to the highest position in the vertical direction of each component, and the bottom may refer to the lowest position in the vertical direction of each component. These positions may be referred to interchangeably.

[0149] Meanwhile, although the second insulating layer 512 and the third insulating layer 513 are illustrated as being composed of one layer each in the drawings, the present invention is not limited to this. For example, the semiconductor package substrate 500 of the embodiment may have a structure of 11 insulating layers. In this case, the second insulating layer 512 and the third insulating layer 513 may each be composed of five layers. For example, the semiconductor package substrate 500 of the embodiment may have a structure of 17 insulating layers. In this case, the second insulating layer 512 and the third insulating layer 513 may each be composed of eight layers.

[0150] The semiconductor package substrate 500 may include a circuit pattern layer disposed on an insulating layer 510 .

[0151] The semiconductor package substrate 500 may include a first circuit pattern layer 521 disposed on an upper surface of the first insulating layer 511. The semiconductor package substrate 500 may include a second circuit pattern layer 522 disposed on a lower surface of the first insulating layer 511. The semiconductor package substrate 500 may include a third circuit pattern layer 523 disposed on an upper surface of the second insulating layer 512. The semiconductor package substrate 500 may include a fourth circuit pattern layer 524 disposed on a lower surface of the third insulating layer 513.

[0152] The third circuit pattern layer 523, which is disposed on the uppermost side of the circuit pattern layers, may include an electrode pattern on which a semiconductor device is disposed. In this case, as shown in FIG. 3b, the semiconductor package substrate may include a protrusion 590 disposed on the electrode pattern of the third circuit pattern layer 523 and protruding toward the semiconductor device. The protrusion 590 may be referred to as a bump. The protrusion 590 may also be referred to as a post. The protrusion 590 may also be referred to as a pillar. That is, as the pitch of the terminals of semiconductor devices becomes finer, thermal compression (TC) bonding, which applies heat and pressure to a conductive adhesive disposed between the electrode pattern and the terminals of the semiconductor device to bond them, may be used. When using TC (thermal compression) bonding, the protrusion 590 may improve the alignment between the electrode pattern and the terminals of the semiconductor device and prevent the diffusion of the conductive adhesive. In addition, the volume of the conductive adhesive disposed for each terminal may be reduced, thereby preventing electrical shorts due to the fine pitch of the terminals. Here, the conductive adhesive is illustratively solder, but is not limited to this.

[0153] The circuit pattern layers 521, 522, 523, and 524 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern layers 521, 522, 523, and 524 may include a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the circuit pattern layers 521, 522, 523, and 524 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0154] The circuit pattern layers 521, 522, 523, and 524 may have a thickness in the range of 10 μm to 25 μm. The thickness of the circuit pattern layers 521, 522, 523, and 524 may refer to the thickness in the vertical direction.

[0155] If the thickness of the circuit pattern layers 521, 522, 523, and 524 is less than 10 μm, the resistance of the circuit pattern layers 521, 522, 523, and 524 increases, which may reduce the allowable current of transmittable signals. Furthermore, if the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 μm, it becomes difficult to miniaturize the circuit pattern layers 521, 522, 523, and 524. If the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 μm, the thickness of the insulating layer 510 must be increased accordingly, and as described above, each insulating layer must be thick to fulfill its insulating and / or protective functions. This increases the thickness of the semiconductor package substrate and the semiconductor package, making it difficult to mitigate warpage of the semiconductor package substrate.

[0156] The circuit pattern layers 521, 522, 523, and 524 may include pads connected to through-electrodes of the semiconductor package substrate 500 and at least one electrode pattern connected to an external substrate or a semiconductor device. In addition, the circuit pattern layers 521, 522, 523, and 524 may include traces of signal transmission lines connected to the pads and electrode patterns.

[0157] The circuit pattern layers 521, 522, 523, and 524 can be formed using conventional semiconductor package substrate manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0158] The semiconductor package substrate 500 may include a first through-electrode 530 penetrating the first insulating layer 511. For example, the first insulating layer 511 may include a first through-hole penetrating both the top and bottom surfaces. The first through-electrode 530 may be provided by filling at least a portion of the first through-hole of the first insulating layer 511. In addition, the semiconductor package substrate 500 may include an insulating member 540 filling the remaining portion of the first through-hole of the first insulating layer 511 to improve the flatness of the first circuit pattern layer 521 if the first through-electrode 530 cannot completely fill the first through-hole. The first through-electrode 530 may be disposed between the insulating member 540 and the first insulating layer 511. The insulating member 540 may be referred to as a hole plugging layer. The insulating member 540 may include an insulating material. For example, the insulating member 540 may be a paste made of an insulating ink material. For example, the insulating member 540 may be a plugging ink. However, the embodiment is not limited thereto. For example, the insulating member 540 may include a conductive material, such as a conductive paste containing conductive metal powder.

[0159] The semiconductor package substrate 500 may include a second through-electrode 550 penetrating the second insulating layer 512. For example, the second insulating layer 512 may include a second through-hole penetrating the top surface and the bottom surface. The second through-electrode 550 may be provided to entirely fill the second through-hole of the second insulating layer 512.

[0160] The semiconductor package substrate 500 may include a third through-electrode 560 penetrating the third insulating layer 513. For example, the third insulating layer 513 may include a third through-hole penetrating the top and bottom surfaces. The third through-electrode 560 may be provided to entirely fill the third through-hole of the third insulating layer 513.

[0161] The first through-hole electrode 530, the second through-hole electrode 550, and the third through-hole electrode 560 may have different shapes.

[0162] The first through hole, the second through hole, and the third through hole may have different shapes. Accordingly, the slope of the first through electrode 530, the slope of the second through electrode 550, and the slope of the third through electrode 560 surrounding the insulating member 540 disposed in the first through hole are different from each other. Exemplarily, the slope of the side surface of the first through electrode 530, the slope of the side surface of the second through electrode 550, and the slope of the side surface of the third through electrode 560 are different from each other. Exemplarily, the vertical cross-sectional shape of the first through electrode 530, the vertical cross-sectional shape of the side surface of the second through electrode 550, and the vertical cross-sectional shape of the third through electrode 560 are different from each other.

[0163] 5, the inner wall of the first through hole may include a plurality of recesses and protrusions, and the recesses and protrusions may be provided in a structure in which they are alternately stacked along the vertical direction. Here, a protrusion refers to a region that protrudes and / or bulges toward the horizontal center of the first through hole, and a recess refers to a region that is recessed in the opposite direction.

[0164] Alternatively, the second through holes may have a shape in which the width decreases from the top to the bottom, and may be arranged without including a plurality of recesses and protrusions, unlike the first through holes.

[0165] The third through hole may have a shape whose width increases from the top to the bottom. The third through hole may be arranged so as not to include a plurality of recesses or protrusions. The third through hole may have a shape symmetrical to the second through hole with respect to the first insulating layer 511, but is not limited thereto.

[0166] In this case, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may correspond to the thickness of the first insulating layer 511. As a result, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may be 250 μm to 1200 μm.

[0167] In this embodiment, the first through holes are formed in the first insulating layer 511 using a laser device, and the difference between the maximum and minimum widths of the first through holes in the vertical direction is minimized. Here, the vertical direction refers to the thickness direction from the top surface to the bottom surface of the first insulating layer 511.

[0168] According to the conventional technology, a drilling machine must be used as in the comparative example in order to minimize the difference between the maximum and minimum widths of the first through-hole 530. However, as described above, when forming a through-hole using a drilling machine, the slope of the inner wall of the through-hole is nearly vertical, so although it is possible to minimize the difference between the maximum and minimum widths of the first through-hole, problems such as reduced productivity, reduced yield, and increased process costs arise.

[0169] Therefore, in this embodiment, a through hole with a minimized difference between the maximum width and the minimum width of the first insulating layer 511 is formed using a laser device instead of a drilling machine device.

[0170] To this end, the Example uses multiple coordinate codes (e.g., T-codes) to form the first through holes in the first insulating layer 511. That is, when using laser equipment, the Comparative Example uses only one coordinate code to form the through holes in the core layer corresponding to the first insulating layer 511. This makes it difficult to change the laser process conditions during the process of forming the through holes. Therefore, when the through holes are formed using laser equipment using only one coordinate code, the through holes have an hourglass shape in which the width gradually decreases from the top and / or bottom to the center, and therefore the minimum width is less than 50% of the maximum width.

[0171] Alternatively, in this embodiment, the first through-holes are formed in the first insulating layer 511 using at least two coordinate codes.

[0172] In the embodiment, a first coordinate code is used to form a portion of the first through hole in the first insulating layer 511. Thereafter, the embodiment uses a second coordinate code to form a remaining portion of the first through hole connected to the portion of the first through hole in the first insulating layer 511. In this way, the embodiment can finally form a first through hole that penetrates the first insulating layer 511.

[0173] In this case, since the embodiment uses two coordinate codes, it is possible to change the laser process conditions during the process of forming the first through hole, unlike the comparative example.

[0174] Therefore, in the embodiment, it is possible to form the first through hole with a minimized difference between the maximum width and the minimum width in the first insulating layer 511 corresponding to the core layer using a laser device.

[0175] That is, the embodiment performs a first process of forming a portion of a first through hole in the first insulating layer 511 using a first coordinate code, and a second process of forming a remaining portion of the first insulating layer 511 connected to the portion of the first through hole using a second coordinate code. At this time, a first mask having an opening of a first size is used to form the portion of the first through hole in the first process using the first coordinate code. The first size may correspond to a target size that the first through hole should have. Thus, the embodiment forms portions of the first through hole corresponding to the target size on each of the upper and lower surfaces of the first insulating layer 511 using the first mask.

[0176] In the embodiment, after a portion of the first through hole is formed, a second process using a second coordinate code is performed. In this process using the second coordinate code, a second mask having an opening of a second size different from the first size is used to form the remaining portion of the first through hole. The second size is smaller than the first size. In the embodiment, the energy intensity of the laser is increased in the second process using the second mask to form the remaining portion of the first through hole. Specifically, in the first process using the first mask to form the remaining portion of the first through hole, the embodiment irradiates the first insulating layer 511 with a laser having a first energy intensity. Furthermore, in the second process using the second mask to form the remaining portion of the first through hole, the embodiment irradiates the first insulating layer 511 with a laser having a second energy intensity greater than the first energy intensity. The size of the opening in the second mask is smaller than the target size of the first through hole. That is, in this embodiment, a laser having a relatively low energy intensity is irradiated onto an opening of a first mask having a first size, and a laser having a relatively high energy intensity is irradiated onto an opening of a second mask having a second size smaller than the first size. Therefore, this embodiment can minimize the difference between the maximum and minimum widths of the entire vertical area of the first through hole. Furthermore, the size of the opening of the second mask used when irradiating the laser having a relatively high energy intensity is smaller than the target size, so this embodiment can prevent the size of the first through hole from expanding.

[0177] In conclusion, the embodiment can form a first through hole having an inner wall with a substantially vertical slope and a size corresponding to a target size using a laser device according to the above-described method.

[0178] This will be explained in more detail below.

[0179] 3a, the semiconductor package substrate 500 of the embodiment includes a protective layer. The protective layer may also be referred to as an insulating layer or a resist layer. The protective layer refers to the outermost insulating layer of the semiconductor package substrate. The protective layer functions to protect the outermost surface of the semiconductor package substrate 500 and to prevent short circuits between adjacent conductive adhesives. Therefore, the protective layer may also be functionally referred to as a "protective layer." For example, when the conductive adhesive is used as a solder, the protective layer may be referred to as a solder resist.

[0180] Specifically, the protective layer includes a first protective layer 570 disposed on the upper surface of the second insulating layer 512. The first protective layer 570 includes at least one first opening 571 that vertically overlaps a portion of the third circuit pattern layer 523. The first opening 571 may be provided to correspond to an area where a conductive adhesive, such as a connecting portion, is to be disposed.

[0181] The protective layer also includes a second protective layer 580 disposed on the lower surface of the third insulating layer 53. The second protective layer 580 includes at least one second opening 581 that vertically overlaps the fourth circuit pattern layer 524. The second opening 581 may be provided to correspond to an area where a conductive adhesive, such as a connecting portion, is to be disposed.

[0182] The first protective layer 570 and the second protective layer 580 may include an organic polymer material. For example, the first protective layer 570 and the second protective layer 580 may be solder protective layers. As an example, the first protective layer 570 and the second protective layer 580 may include an epoxy acrylate resin. More specifically, the first protective layer 570 and the second protective layer 580 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto. For example, the first protective layer 570 and the second protective layer 580 may include any one of a photo solder protective layer, a coverlay, and a polymer material.

[0183] The first protective layer 570 and the second protective layer 580 may have a thickness of 1 μm to 20 μm. If the thickness of the first protective layer 570 and the second protective layer 580 exceeds 20 μm, the overall thickness of the semiconductor package substrate and the overall thickness of the semiconductor package increase, and stress increases, resulting in increased warpage of the semiconductor package substrate.

[0184] Furthermore, if the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 μm, the circuit pattern layer will not be stably protected, and if the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 μm, the electrical reliability of the semiconductor package substrate and the electrical reliability of the semiconductor package may be reduced.

[0185] Hereinafter, the first through-holes, the first through-electrodes, and the insulating members formed in the first insulating layer 511 according to the embodiment will be described in more detail.

[0186] Figure 4 is a cross-sectional view for explaining the first insulating layer of the embodiment, Figure 5 is a cross-sectional view showing a first through hole provided in the first insulating layer of Figure 4, Figure 6 is a cross-sectional view showing a first through electrode and an insulating member arranged in the through hole of Figure 5, Figure 7 is a drawing showing the layer structure of the first through electrode and first circuit pattern layer of the first embodiment, Figure 8 is a drawing showing the layer structure of the first through electrode and first circuit pattern layer of the second embodiment, and Figure 9 is an optical microscope photograph of an actual product including the first through hole, first through electrode and insulating member according to the embodiment.

[0187] Hereinafter, the first through electrode 530, the first circuit pattern layer 521, the second circuit pattern layer 522, the first through electrode 530, and the insulating member 540 according to the embodiment will be described in detail with reference to FIGS.

[0188] The thickness T1 in the vertical direction of the first insulating layer 511 of the embodiment can satisfy the range of 250 μm to 1200 μm as described above.

[0189] At this time, referring to FIG. 4, the first insulating layer 511 may include a resin 511a and reinforcing fibers 511b disposed within the resin 511a.

[0190] The reinforcing fibers 511b may include a plurality of fibers arranged in different directions within the resin 511a. For example, the reinforcing fibers 511b may include first fibers arranged in a first horizontal direction and second fibers arranged in a second horizontal direction perpendicular to the first horizontal direction. For example, the wavy fibers of the reinforcing fibers 511b in FIG. 4 may be the first fibers, and the dotted fibers may be the second fibers.

[0191] The first fiber of the reinforcing fibers 511b can be referred to as a warp yarn, and the second fiber of the reinforcing fibers 511b can be referred to as a fill yarn.

[0192] That is, the reinforcing fibers 511b may be made of a bundle of filaments that are long glass fibers, and the first and second fibers of the reinforcing fibers 511b may be arranged in first and second horizontal directions that intersect with each other within the resin 511a, but are not limited thereto.

[0193] The reinforcing fibers 511b may be divided into a plurality of groups. For example, the reinforcing fibers 511b may be divided into a plurality of groups that are spaced apart from each other in the vertical direction within the resin 511a of the first insulating layer 511.

[0194] For example, the reinforcing fibers 511b may include first to third groups that are separated from one another along the vertical direction between the upper surface 511U and the lower surface 511L of the first insulating layer 511. The reinforcing fibers of the first to third groups are arranged in the horizontal direction within the first insulating layer 511. The reinforcing fibers of the first to third groups are spaced apart from one another in the vertical direction within the first insulating layer 511.

[0195] In this case, although the drawings show that the reinforcing fibers 511b are arranged in three groups in the first insulating layer 511, the present invention is not limited thereto. For example, the number of groups of the reinforcing fibers 511b may be determined based on the vertical thickness of the first insulating layer 511. For example, if the vertical thickness of the first insulating layer 511 is 250 μm, the reinforcing fibers 511b may be divided into three groups and arranged in the first insulating layer 511. For example, as shown in FIG. 9, if the vertical thickness of the first insulating layer 511 is 300 μm, the reinforcing fibers 511b may be divided into four groups and arranged in the first insulating layer 511.

[0196] As a result, the first insulating layer 511 is divided into a plurality of regions in the vertical direction. For example, the first insulating layer 511 may include a first region 511R1 that does not include reinforcing fibers 511b in the vertical direction and a second region 511R2 that includes reinforcing fibers 511b.

[0197] The second region 511R2 of the first insulating layer 511 may be provided in plural, spaced apart from each other in the vertical direction with the first region 511R1 of the first insulating layer 511 sandwiched therebetween.

[0198] Referring to Figures 4 to 6, when the reinforcing fibers 511b are divided into three groups, the second region 511R2 of the first insulating layer 511 may include at least three sub-regions spaced apart from each other with the first region 511R1 sandwiched therebetween.

[0199] For example, the first region 511R1 of the first insulating layer 511 may include 1-1 to 1-4 sub-regions 511R11, 511R12, 511R13, and 511R14, starting from a position adjacent to the upper surface 511U of the first insulating layer 511. The second region 511R2 of the first insulating layer 511 may include 2-1 to 2-3 sub-regions 511R21, 511R22, and 511R23, which are disposed between the 1-1 to 1-4 sub-regions 511R11, 511R12, 511R13, and 511R14, respectively. The second region 511R2 may be located farther away from the upper surface 511U and the lower surface 511L of the first insulating layer 511 than the first region 511R1. This is because if the reinforcing fibers 511b are exposed on the upper surface 511U or the lower surface 511L of the first insulating layer 511, the physical reliability and electrical reliability of the circuit pattern layer may be reduced.

[0200] 5 and 6, the first through hole TH1 is formed using at least two coordinate codes using laser equipment, so that concave and convex portions are alternately arranged along the vertical direction on the inner wall of the first through hole TH1. In addition, the difference between the minimum and maximum widths of the first through hole TH1 having concave and convex portions in the embodiment is smaller than the difference between the minimum and maximum widths of the first through hole TH1 formed using one coordinate code using conventional laser equipment.

[0201] Alternatively, recesses may be provided in the 1-1 to 1-4 sub-regions 511R11, 511R12, 511R13, and 511R14, and protrusions may be provided in the 2-1 to 2-3 sub-regions 511R21, 511R22, and 511R23. This is because the etching rate of the resin layer made of only resin 511a in the first insulating layer 511 is greater than the etching rate of the layer provided with reinforcing fibers 511b, and therefore the recesses and protrusions may be provided at the above-mentioned positions, but this is not limitative.

[0202] 5, the inner wall of the first through hole TH1 includes a first inner wall IW1 and a second inner wall IW2. The second inner wall IW2 of the first through hole TH1 may be provided as a convex portion that bulges toward the inside of the first through hole TH1 compared to the first inner wall IW1.

[0203] That is, the inner wall of the first insulating layer 511 constituting the first through hole TH1 in the embodiment includes a second inner wall IW2 that bulges toward the first through hole TH1 from the first inner wall IW1. Also, referring to FIG. 5, the first inner wall IW1 has a vertical slope for example, but is not limited thereto, and may be formed as a recess that is recessed toward the outer surface of the first insulating layer 511.

[0204] In this embodiment, the second inner wall IW2 may include a plurality of convex portions spaced apart from one another in the vertical direction. The convex portions may also be regions whose widths vary. For example, the convex portions may be curved surfaces having a constant curvature along the vertical direction, but are not limited thereto.

[0205] As a result, in this embodiment, the inner walls IW1 and IW2 of the first through hole TH1 have protrusions and recesses, allowing the first through electrodes to be uniformly arranged in the first through hole TH1, thereby enabling stable impedance matching and reducing voltage drop, current and / or signal loss. Furthermore, reliability against thermal stress can be improved. That is, the horizontal width of the first through electrode is arranged to be thicker than the thickness of the conventional vertical first through electrode 530 shown in FIG. 3a, thereby reducing voltage drop, current and / or signal loss, and providing a structure more advantageous for heat dissipation.

[0206] The first inner wall IW1 may be formed in a first region 511R1 of the first insulating layer 511 in the first through-hole TH1, and the second inner wall IW2 may be formed in a second region 511R2 of the first insulating layer 511 in the first through-hole TH1.

[0207] That is, in this embodiment, a first through hole TH1 is formed in a first insulating layer 511 having a thickness T1 of 250 μm or more using a laser. In this case, if a laser is used, the reinforcing fibers 511b provided in the first insulating layer 511 cannot be easily removed. Therefore, the first insulating layer 511 of the embodiment may include a second inner wall IW2 that corresponds to the inner wall of the second region 511R2 of the first insulating layer 511 where the reinforcing fibers 511b are arranged and bulges toward the first through hole TH1. Each of the first inner wall IW1 and the second inner wall IW2 may include a plurality of sub-parts.

[0208] For example, the first inner wall IW1 may include 1-1 to 1-4 subparts IW1-1, IW1-2, IW1-3, and IW1-4 based on those adjacent to the upper surface 511U of the first insulating layer 511. The second inner wall IW2 may include 2-1 to 2-3 subparts IW2-1, IW2-2, and IW2-3 disposed between the 1-1 to 1-4 subparts IW1-1, IW1-2, IW1-3, and IW1-4, respectively.

[0209] The number of subparts of the second inner wall IW2 may correspond to the number of groups of reinforcing fibers 511b provided in the first insulating layer 511. Thus, the number of subparts of the second inner wall IW2 may be more than two, three or more, four or more, or five or more.

[0210] The first through hole TH1 has a first width W1 in the horizontal direction in a region corresponding to the 1-1 subpart IW1-1 of the first inner wall IW1, and then a second width W2 (smaller than the first width W1) in a region corresponding to the 2-1 subpart IW2-1 of the second inner wall IW2. The first through hole TH1 also has the first width W1 in a region corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1, and then a second width W2 (smaller than the first width W1) in a region corresponding to the 2-2 subpart IW2-2 of the second inner wall IW2. The first through hole TH1 also has the first width W1 in a region corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1, and then a second width W2 (smaller than the first width W1) in a region corresponding to the 2-3 subpart IW2-3 of the second inner wall IW2. The first insulating layer 511 again has the first width W1 in a region corresponding to the 1-4 subpart IW1-4 of the first inner wall IW1. However, referring to Fig. 9, the first through hole TH1 does not have to have the same first width W1 in all of the regions corresponding to the 1-1 to 1-4 subparts IW1-1, IW1-2, IW1-3, and IW1-4 of the first inner wall IW1, and does not have to have the same second width W2 in all of the regions corresponding to the 2-1 to 2-3 subparts IW2-1, IW2-2, and IW2-3 of the second inner wall IW2.

[0211] In the embodiment, the first insulating layer 511 includes reinforcing fibers 511b vertically spaced apart in groups of more than two, three or more, four or more, or five or more. The inner wall of the first insulating layer 511 in which the first through hole TH1 is formed includes a plurality of convex portions that bulge toward the center of the first through hole TH1 in the area where the reinforcing fibers 511b are arranged. The convex portions may be vertically spaced apart from one another on the first insulating layer 511. Each convex portion extends along the circumferential direction of the inner wall of the first through hole TH1. The first width W1 of the first through hole TH1 may refer to the horizontal width of the area having the widest width in the entire vertical direction. The second width W2 of the first through hole TH1 may refer to the horizontal width of the area having the smallest width in the entire vertical direction.

[0212] In the case of through holes formed in insulating layers of 250 μm or more using the laser equipment of the comparative example, the second width was less than 50% of the first width.

[0213] Alternatively, the second width W2 of the embodiment may be in the range of 55% to 95% of the first width W1.

[0214] If the second width W2 is less than 55% of the first width W1, the difference in width of the through hole becomes too large, which can degrade the plating characteristics during the plating process to fill the through hole. For example, if the difference in width is too large, the difference in plating growth rate during the plating process also becomes large, which can result in the presence of void regions, or empty spaces not filled with metal material, within the through hole. Also, if the second width W2 exceeds 95% of the first width W1, the absence of a plating bridge can degrade the plating characteristics during the plating process.

[0215] Meanwhile, the first through electrode 530 and the insulating member 540 of the embodiment may be disposed in the first through hole TH1.

[0216] The first through-electrode 530 may be in contact with inner walls IW1 and IW2 of the first insulating layer 511 including the first through-hole TH1. The insulating member 540 may be disposed inside the first through-electrode 530 within the first through-hole TH1. Exemplarily, the first through-electrode 530 may be provided to cover the outside of the insulating member 540 within the first through-hole TH1.

[0217] The first through-hole electrode 530 may have a constant thickness and may be disposed on an inner wall of the first insulating layer 511 including the first through-hole TH1. The thickness of the first through-hole electrode 530 may refer to the horizontal distance of the first through-hole electrode 530. Specifically, the thickness of the first through-hole electrode 530 may refer to the horizontal width of the first through-hole electrode 530.

[0218] In this case, the first through electrode 530 may be divided into a plurality of portions. For example, the first through electrode 530 may include a recessed portion disposed on the first inner wall IW1 corresponding to the first region 511R1 of the first insulating layer 511. The first through electrode 530 may also include a protruding portion disposed on the second inner wall IW2 corresponding to the second region 511R2 of the first insulating layer 511. The side surface of the first through electrode 530 including the recessed and protruding portions may have a step in the vertical direction. Specifically, the recessed portion of the first through electrode 530 does not overlap with the reinforcing fibers 511b in the horizontal direction. The protruding portion of the first through electrode 530 overlaps with the reinforcing fibers 511b in the horizontal direction. Preferably, the protruding portion of the first through electrode 530 corresponds to the protruding portion provided on the second inner wall IW2 of the first insulating layer 511. The recessed portion of the first through electrode 530 corresponds to the recessed portion provided on the first inner wall IW1 of the first insulating layer 511. 9, the first through-hole electrode 530 may have a shape in which recesses and protrusions are alternately arranged in the vertical direction. In this case, the recesses of the first through-hole electrode 530 correspond to the recesses formed on the first inner wall IW1 of the first through-hole TH1, and the protrusions of the first through-hole electrode 530 correspond to the protrusions formed on the second inner wall IW2 of the first through-hole TH1, but this is not intended to be limiting.

[0219] The first through-hole electrode 530 may have a third thickness W3 in the horizontal direction in the region where the recessed portion is provided. The first through-hole electrode 530 may have a fourth thickness W4 in the horizontal direction in the region where the protrusion is provided. In this case, the third thickness W3 may correspond to the fourth thickness W4. For example, the third thickness W3 and the fourth thickness W4 may be the same. That is, the first through-hole electrode 530 may have the same thickness in the horizontal direction in the region where the recessed portion is provided and the region where the protrusion is provided. Here, having the same thickness may mean that the difference in thickness in the horizontal direction in the region where the recessed portion is provided and the region where the protrusion is provided is 3 μm or less.

[0220] The thicknesses W3 and W4 of the first through-electrode 530 in the horizontal direction may be in the range of 10 μm to 25 μm.

[0221] If the horizontal thickness of the first through-hole electrode 530 is less than 10 μm, the resistance of the first through-hole electrode 530 increases, and the allowable current of transmittable signals may decrease. Furthermore, if the horizontal thickness of the first through-hole electrode 530 is less than 10 μm, the electrical characteristics may be degraded. For example, if the horizontal thickness of the first through-hole electrode 530 is less than 10 μm, the reinforcing fibers 511b exposed through the first through-hole TH1 may not be reliably covered by the first through-hole electrode 530. Furthermore, if the reinforcing fibers 511b are not covered by the first through-hole electrode 530, the reinforcing fibers 511b may cause a problem of degraded electrical characteristics. If the horizontal thickness of the first through-hole electrode 530 exceeds 25 μm, the thickness difference between the regions where the recessed portions of the first through-hole electrode 530 are formed and the regions where the protruding portions of the first through-hole electrode 530 are formed increases due to differences in plating growth rates during the process of forming the first through-hole electrode 530.

[0222] The insulating member 540 may include a region whose width changes from the upper surface to the lower surface. For example, the insulating member 540 may have a plurality of recesses recessed inward and a plurality of protrusions bulging toward the first through-electrode 530. The insulating member 540 may have a plurality of recesses spaced apart in the vertical direction. Furthermore, the protrusions of the insulating member 540 may be provided between each of the plurality of recesses of the insulating member 540.

[0223] 6, the insulating member 540 may include a first portion 541 having a fifth width W5 and a second portion 542 having a sixth width W6 smaller than the fifth width W5. A protrusion that bulges toward the first through-electrode 530 may be provided on a side surface of the first portion 541 of the insulating member 540. A recess that is recessed inward may be provided on a side surface of the second portion 542 of the insulating member 540.

[0224] That is, the inner wall of the first through hole TH1 of the first insulating layer 511 includes a convex portion that bulges to correspond to the reinforcing fiber 511b. Thus, the insulating member 540 may also include a concave portion that corresponds to the convex portion of the first through hole TH1. Exemplarily, the insulating member 540 may include a concave portion that overlaps horizontally with the convex portion of the first through hole TH1. Also, the insulating member 540 may include a convex portion that overlaps horizontally with the concave portion of the first through hole TH1. Here, although FIG. 6 illustrates the side surface of the first portion 541 of the insulating member 540 as being vertical, this is not limiting. For example, the side surface of the first portion 541 may be formed as a curved convex portion that bulges toward the first through electrode 530.

[0225] The insulating member 540 may have a plurality of first portions 541 spaced apart from one another in the vertical direction.

[0226] For example, as shown in FIG. 6, the first portion 541 of the insulating member 540 may include a 1-1 portion 541-1, a 1-2 portion 541-2, a 1-3 portion 541-3, and a 1-4 portion 541-4.

[0227] The second portion 542 of the insulating member 540 may include a 2-1 portion 542-1, a 2-2 portion 542-2, and a 2-3 portion 542-3. The 2-1 portion 542-1, the 2-2 portion 542-2, and the 2-3 portion 542-3 may be portions that overlap the reinforcing fibers 511b in the horizontal direction.

[0228] The 1-1 portion 541-1, the 1-2 portion 541-2, the 1-3 portion 541-3, and the 1-4 portion 541-4 may be portions that do not overlap the reinforcing fibers 511b in the horizontal direction.

[0229] The 2-1 portion 542-1, the 2-2 portion 542-2, and the 2-3 portion 542-3 may have a width smaller than the 1-1 portion 541-1, the 1-2 portion 541-2, the 1-3 portion 541-3, and the 1-4 portion 541-4 due to the reinforcing fibers 511b.

[0230] Meanwhile, the first through electrode 530 may be composed of a plurality of layers. For example, the first through electrode 530 may be formed together with the first circuit pattern layer 521 and the second circuit pattern layer 522 when the first circuit pattern layer 521 and the second circuit pattern layer 522 are formed. This allows the first through electrode 530 to have a layer structure corresponding to the layers constituting the first circuit pattern layer 521 and the second circuit pattern layer 522.

[0231] The first circuit pattern layer 521 can include multiple metal layers.

[0232] For example, the first circuit pattern layer 521 may include a first metal layer 521-1 disposed on the first insulating layer 511, a second metal layer 521-2 disposed on the first metal layer 521-1, and a third metal layer 521-3 disposed on the second metal layer 521-2.

[0233] The first metal layer 521-1 of the first circuit pattern layer 521 may refer to a copper foil layer attached to the surface of the first insulating layer 511.

[0234] The second metal layer 521-2 of the first circuit pattern layer 521 may be a plating layer formed on the first metal layer 521-1 by electroless plating. For example, the second metal layer 521-2 of the first circuit pattern layer 521 may be a chemical copper plating layer.

[0235] The third metal layer 521-3 of the first circuit pattern layer 521 may be a plated layer formed by electrolytic plating using the second metal layer 521-2 as a seed layer. For example, the third metal layer 521-3 of the first circuit pattern layer 521 may be an electrolytic plated layer.

[0236] 7, the third metal layer 521-3 of the first circuit pattern layer 521 in the first embodiment is disposed on the upper surface of the insulating member 540. In this case, the third metal layer 521-3 of the first circuit pattern layer 521 is formed by performing electrolytic plating multiple times.

[0237] 8, the third metal layer 521-3 of the first circuit pattern layer 521 in the second embodiment does not have to cover the upper surface of the insulating member 540. In this case, the third metal layer 521-3 of the first circuit pattern layer 521 is formed by performing electrolytic plating once. In this case, the third metal layer 521-3 of the first circuit pattern layer 521 does not have to overlap the upper surface of the insulating member 540 in the vertical direction.

[0238] Meanwhile, the first through electrode 530 may include a fourth metal layer 530-1 corresponding to the second metal layer 521-2 of the first circuit pattern layer 521, and a fifth metal layer 530-2 disposed on the fourth metal layer 530-1 and corresponding to the third metal layer 521-3 of the first circuit pattern layer 521.

[0239] The fourth metal layer 530-1 of the first through-electrode 530 may be provided on an inner wall of the first insulating layer 511 including the first through-hole TH1. The fifth metal layer 530-2 of the first through-electrode 530 is disposed between the fourth metal layer 530-1 of the first through-electrode 530 and the insulating member 540.

[0240] Meanwhile, the thicknesses W4 and W5 of the first through-electrode 530 in the horizontal direction may refer to the sum of the thicknesses of the fourth metal layer 530-1 and the fifth metal layer 530-2 of the first through-electrode 530 in the horizontal direction.

[0241] 9, according to the embodiment, the first insulating layer 511 may have a thickness of 400 μm or more in the vertical direction, and the reinforcing fibers 511b are arranged in four groups in the vertical direction. Therefore, the inner wall of the first through hole TH1 of the first insulating layer 511 may have protruding portions corresponding to the four groups of reinforcing fibers 511b.

[0242] 9, the first through-hole electrode 530 disposed on the sidewall of the first through-hole TH1 includes one surface facing the insulating member 540 and the other surface facing the first insulating layer 511, and the one surface includes a convex portion protruding toward the insulating member 540 and a concave portion recessed toward the first through-hole TH1. The first through-hole electrode 530 illustrated in FIG. 9 illustrates one cross section, and one surface of the first through-hole electrode 530 is disposed to cover the insulating member 540.

[0243] The recessed portions of the first through-hole electrodes 530 may face each other and overlap in the horizontal direction, and the protruding portions of the first through-hole electrodes 530 may face each other and overlap in the horizontal direction. Alternatively, the protruding portions and the recessed portions may be alternately arranged in the vertical direction. This allows the first through-hole electrodes 530 to be disposed with a relatively uniform thickness in the horizontal direction, and can be disposed thicker than in a process using a drill machine.

[0244] The other surface of the first through-hole electrode 530 may have a different shape from the one surface. That is, the other surface of the first through-hole electrode 530 that overlaps horizontally with the one surface where the concave portion is disposed may not have a concave surface or may have a different curvature. Referring to FIG. 9 , the curvature of the one surface of the first through-hole electrode 530 is shown to be different from the curvature of the other surface that overlaps horizontally with the concave surface. This not only improves the bonding strength between the insulating member 540 and the first through-hole electrode 530 and improves heat dissipation characteristics, but also improves the mechanical reliability of the semiconductor package substrate by controlling stress. Similarly, the convex portion of the one surface of the first through-hole electrode 530 may have a different curvature from the convex portion of the other surface that overlaps horizontally with it. The convex portion of the other surface is arranged in a structure that covers the glass fiber differently from the convex portion of the one surface, and therefore has a different curvature from the convex portion of the one surface. Specifically, when the first through-hole electrode 530 covers the glass fiber, the horizontal thickness of the first through-hole electrode 530 must be 10 μm or more to prevent the problem of reduced electrical characteristics. Therefore, in order to prevent the convex portions on the other surface from covering the glass fibers and deteriorating the electrical properties, the convex portions on one surface and the convex portions on the other surface can be arranged to have different curvatures.

[0245] 10 to 14 are views showing a part of a method for manufacturing a semiconductor package substrate according to an embodiment in the order of steps. The process of forming the first through-holes TH1 in the first insulating layer 511 will be described below.

[0246] 10 , in this embodiment, a first insulating layer 511 is provided. The first insulating layer 511 may be made of CCL. Therefore, copper foil layers are disposed on both sides of the first insulating layer 511. The copper foil layers may include a first metal layer 521-1 of a first circuit pattern layer 521 and a first metal layer 522-1 of a second circuit pattern layer 522.

[0247] Thereafter, in the embodiment, a process of forming the first through hole TH1 in the first insulating layer 511 may be performed.

[0248] The first through hole TH1 is formed by a plurality of laser processes using a plurality of coordinate codes.

[0249] In this case, the first insulating layer 511 has a vertical thickness of 250 μm or more. Therefore, it is difficult to form the first through hole TH1 penetrating the first insulating layer 511 on only one side of the first insulating layer 511. Therefore, in this embodiment, a process of forming a portion of the first through hole TH1 may be performed primarily on the upper side of the first insulating layer 511.

[0250] To this end, referring to FIG. 11 , an embodiment may perform a process of forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511 using a first coordinate code (T-code A). The first coordinate code (T-code A) may include position information (TCI) corresponding to the position where the first through hole TH1 is to be formed. The embodiment may also form a portion of the first through hole TH1 by irradiating a laser on the upper side of the first insulating layer 511 using the first coordinate code (T-code A). Here, a first mask having an opening of a first size may be used in the process of forming a portion of the first through hole TH1 using the first coordinate code (T-code A). The embodiment may also perform a process of forming a first portion HP1, which is a portion of the first through hole TH1, on the upper side of the first insulating layer 511 by irradiating a laser of a first laser energy intensity through the opening of the first mask.

[0251] 12, in this embodiment, a process may be performed to form a second portion HP2 connected to the first portion BP1 on the upper side of the first insulating layer 511 using a second coordinate code (T-code B). In this case, the second coordinate code (T-code B) may include location information (TCI) corresponding to the first coordinate code (T-code A).

[0252] In addition, in the embodiment, when the second coordinate code (T-code B) is used, different laser process conditions are applied from those used when the first coordinate code (T-code A) is used to form the second part HP2 of the first through hole TH1 connected to the first part BP1 of the first through hole TH1.

[0253] In this case, in the process of forming the first portion BP1 of the first through hole TH1 using the second coordinate code (T-code B), a second mask having an opening of a second size smaller than the first size may be used. Also, in the embodiment, the second portion HP2 of the first through hole TH1 may be formed on the first insulating layer 511 by irradiating a laser having a second energy intensity greater than the first energy intensity through the opening of the second mask.

[0254] Therefore, in this embodiment, the horizontal widths of the first portion HP1 and the second portion HP2 of the first through hole TH1 may be substantially the same. However, the first insulating layer 511 includes reinforcing fibers 511b. Therefore, protrusions are provided in the first portion HP1 and the second portion HP2 of the first through hole TH1 in areas that overlap the reinforcing fibers 511b in the horizontal direction.

[0255] 13, the embodiment may use a first coordinate code (T-code A) to perform a process of forming the remaining portion of the first through hole TH1 below the first insulating layer 511. Specifically, the embodiment may apply first laser process conditions according to the first coordinate code (T-code A) to form a third portion HP3 of the first through hole TH1 vertically aligned with the first portion HP1 and the second portion HP2 of the first through hole TH1.

[0256] 14, in this embodiment, a process for forming a fourth portion HP4 connected to the third portion HP3 of the first through hole TH1 using a second coordinate code (T-code B) can be performed. The fourth portion HP4 is connected to the second portion HP2, thereby forming the final first through hole TH1.

[0257] Meanwhile, when a semiconductor package substrate having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stabilize functions such as signal transmission or power supply. For example, when a semiconductor package substrate having the features of the present invention performs a semiconductor packaging function, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it performs a signal transmission function, it can solve noise problems. As a result, the semiconductor package substrate having the above-described inventive features can maintain stable functions in IT devices and home appliances, and the entire product and the semiconductor package substrate to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0258] When a semiconductor package substrate having the above-described inventive features is used in a transportation device such as a vehicle, it can solve problems of distortion in signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from external influences, and solve problems of leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the semiconductor package substrate to which the present invention is applied can be functionally integrated or technically interlocked with each other. Furthermore, when a semiconductor package substrate having the above-described inventive features is used in a transportation device such as a vehicle, it can transmit high-current signals required by the vehicle at high speed, thereby improving the safety of the transportation device. Furthermore, it enables normal operation of the semiconductor package substrate and the semiconductor package including the same even in unexpected situations that occur in various driving environments of the transportation device, thereby protecting the driver safely.

[0259] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

[0260] The above description has focused on the embodiments, but these are merely illustrative and do not limit the present invention. A person skilled in the art to which the present invention pertains may make various modifications and applications not exemplified above within the scope of the essential characteristics of the present embodiments. For example, each component specifically presented in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the present invention as defined by the appended claims.

Claims

1. An insulating layer comprising an upper surface and a lower surface, and including a reinforcing member, The insulating layer includes through electrodes that penetrate the upper and lower surfaces, The insulating layer is provided with alternating first regions having the reinforcing member and second regions not having the reinforcing member along the vertical direction. The circuit board has a side surface of the through electrode that includes a recess that overlaps with the first region along the horizontal direction and a protrusion that overlaps with the second region along the horizontal direction.

2. The reinforcing member is arranged to extend along the horizontal direction within the first region of the insulating layer, The insulating layer includes through holes penetrating the upper and lower surfaces, The circuit board according to claim 1, wherein the side wall of the through-hole includes a protrusion that overlaps with the first region and the recess of the through-electrode along the horizontal direction, and a recess that overlaps with the second region and the protrusion of the through-electrode along the horizontal direction.

3. The circuit board according to claim 2, wherein the recesses and protrusions of the through electrodes and through holes are arranged alternately along the vertical direction.

4. Further comprising an insulating member that penetrates the upper and lower surfaces of the insulating layer, The circuit board according to claim 1, wherein the through electrode is provided while covering the outside of the insulating member.

5. The circuit board according to claim 1, wherein the recess and protrusion of the through electrode have different inclinations or curvatures.

6. The circuit board according to claim 4, wherein the insulating member includes a first part having a first width in the horizontal direction and a second part having a second width greater than the first width in the horizontal direction.

7. The first portion of the insulating member overlaps the recess of the through electrode and the first region of the insulating layer along the horizontal direction, The circuit board according to claim 6, wherein the second portion of the insulating member overlaps with the protrusion of the through electrode and the second region of the insulating layer along the horizontal direction.

8. The horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, The circuit board according to claim 1, wherein the reinforcing member disposed in the first region of the insulating layer includes a first reinforcing fiber disposed in the first horizontal direction and a second reinforcing fiber disposed in the second horizontal direction.

9. The circuit board according to claim 1, wherein the first region of the insulating layer is located further from the upper surface of the insulating layer than the second region of the insulating layer.

10. The circuit board according to claim 1, wherein the first region of the insulating layer is located further from the lower surface of the insulating layer than the second region of the insulating layer.

11. The circuit board according to claim 1, wherein the first length of the convex portion in the vertical direction is different from the second length of the concave portion in the vertical direction.

12. The circuit board according to claim 11, wherein the first length is smaller than the second length.

13. The circuit board according to claim 11, wherein each of the first length and the second length is in the range of 10 μm to 25 μm.

14. The through electrode includes a first part including the recess and a second part including the protrusion, The circuit board according to claim 1, wherein the horizontal thickness of the first part is the same as the horizontal thickness of the second part.

15. The circuit board according to claim 1, wherein the through electrode includes a first metal layer disposed on the inner wall of a through hole penetrating the insulating layer, and a second metal layer disposed on the first metal layer.

16. The through electrode includes a first surface that contacts the inner wall of the through hole penetrating the insulating layer and a second surface that contacts the insulating member, The protrusion and recess of the through electrode are provided on the first side surface of the through electrode, The circuit board according to claim 4, wherein the second side surface of the through electrode includes a recess that overlaps with a protrusion provided on the first side surface along the horizontal direction, and a protrusion that overlaps with the recess provided on the first side surface along the horizontal direction.

17. The insulating layer is a core insulating layer, An upper build-up structure disposed on the upper surface of the core insulating layer, The circuit board according to claim 1, further comprising a lower build-up structure disposed on the lower surface of the core insulating layer.

18. The circuit board according to claim 17, further comprising a connecting member embedded in the upper build-up structure.

19. The circuit board according to claim 18, further comprising semiconductor elements disposed on the upper build-up structure.

20. The semiconductor element includes a first semiconductor element and a second semiconductor element spaced apart along the horizontal direction, The circuit board according to claim 19, wherein each of the first semiconductor element and the second semiconductor element includes a region that overlaps with the connecting member along the vertical direction.

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