Package with chiplet located between integrated device and metallization portion - Patent Application 20070122997

Abstract

A package comprising: a first metallization portion; a first integrated device coupled to the first metallization portion via a first plurality of pillar interconnects; and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device via the first plurality of inter-pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of non-provisional application No. 17 / 894,043, filed with the United States Patent Office on August 23, 2022, the entire contents of which are incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Various features relate to packages that include integrated devices. [Background technology]

[0003]

[0003] A package may include a substrate, an integrated device, and a passive device. These components are coupled together to provide a package that can perform various electrical functions. How the integrated device, substrate, and passive components are coupled together affects how the package functions as a whole. There is a continuing need to provide packages with better performance. Summary of the Invention

[0004] Various features relate to packages that include integrated devices.

[0005]

[0005] One example provides a package comprising: a first metallization portion; a first integrated device coupled to the first metallization portion via a first plurality of pillar interconnects; and a first chiplet located between the first integrated device and the first metallization portion, the first chiplet being coupled to the first integrated device via a first plurality of inter-pillar interconnects.

[0006] Another example provides a device that includes a package comprising: a first metallization portion, a first integrated device coupled to the first metallization portion via a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion, the first chiplet coupled to the first integrated device via the first plurality of inter-pillar interconnects.

[0007] Another example provides a method of fabricating a package. The method provides a first integrated device and a first plurality of inter-pillar interconnects. The method forms an encapsulation layer that encapsulates the first integrated device and the first plurality of inter-pillar interconnects. The method forms the first plurality of pillar interconnects configured to be coupled to the first integrated device. The method couples a first chiplet to the first integrated device via the first plurality of inter-pillar interconnects. The method forms a first metallization portion such that the first metallization portion is coupled to the first chiplet and the first encapsulation layer.

[0008]

[0008] Another example provides a package comprising: a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion via a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, the first chiplet configured to be electrically coupled to the first integrated device via the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, the second chiplet configured to be electrically coupled to the second integrated device via the first metallization portion.

[0009] Another example provides a device that includes a package comprising: a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion via a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, the first chiplet configured to be electrically coupled to the first integrated device via the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, the second chiplet configured to be electrically coupled to the second integrated device via the first metallization portion.

[0010] Another example provides a method of fabricating a package. The method provides a first integrated device and a second integrated device. The method forms an encapsulation layer that encapsulates the first integrated device and the second integrated device. The method forms a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device. The method forms a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the first metallization portion. The method bonds a first chiplet and a second chiplet to the first metallization portion. The method forms another encapsulation layer that encapsulates the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method forms a second metallization portion such that the second metallization portion is coupled to the first chiplet and the second chiplet.

[0011] Another example provides a method of fabricating a package. The method forms a second metallization portion. The method forms a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the second metallization portion. The method bonds a first chiplet and a second chiplet to the second metallization portion. The method forms an encapsulation layer that encapsulates the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method forms the first metallization portion such that the first metallization portion is coupled to the first chiplet and the second chiplet. The method bonds a first integrated device and a second integrated device to the first metallization portion. [Brief explanation of the drawings]

[0012]

[0012] Various features, properties, and advantages may become apparent by reading the "Form for Implementing the Invention" set forth below in conjunction with the drawings in which like reference characters identify corresponding parts throughout. [Figure 1]

[0013] 1 shows a plan view of a package with an integrated device, a metallization portion, and a deep trench capacitor between the integrated device and the metallization portion. [Figure 2]

[0014] 1 shows a plan view of a package with an integrated device, a metallization portion, and a deep trench capacitor between the integrated device and the metallization portion. [Figure 3]

[0015] 1 shows a plan view of a package comprising an integrated device, a metallization portion, and a chiplet between the integrated device and the metallization portion. [Figure 4]

[0016] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, and multiple deep trench capacitors. [Figure 5]

[0017] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 6]

[0018] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, bridges, and multiple chiplets. [Figure 7]

[0019] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, and multiple deep trench capacitors. [Figure 8]

[0020] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 9]

[0021] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, bridges, and multiple chiplets. [Figure 10]

[0022] 1 shows a plan view of a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 11]

[0023] 1 shows a cross-sectional side view of a deep trench capacitor. [Figure 12A]

[0024] 1 illustrates an exemplary sequence for fabricating a deep trench capacitor. [Figure 12B] 1 illustrates an exemplary sequence for fabricating a deep trench capacitor. [Figure 12C] 1 illustrates an exemplary sequence for fabricating a deep trench capacitor. [Figure 12D] 1 illustrates an exemplary sequence for fabricating a deep trench capacitor. [Figure 13]

[0025] 1 illustrates an exemplary flow diagram of a method for fabricating a deep trench capacitor. [Figure 14A]

[0026] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 14B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 14C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 14D] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 15A]

[0027] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 15B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 15C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 16A]

[0028] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 16B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 16C]1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices, metallization portions, bridges, and multiple deep trench capacitors. [Figure 17A]

[0029] 1 illustrates an exemplary sequence for fabricating a substrate. [Figure 17B] 1 illustrates an exemplary sequence for fabricating a substrate. [Figure 18]

[0030] 1 shows an exemplary flow diagram of a method for fabricating a substrate. [Figure 19]

[0031] Illustrated are various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0032] In the following description, specific details are set forth to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will understand that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0014]

[0033] The present disclosure describes a package including a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion via a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, the first chiplet configured to be electrically coupled to the first integrated device via the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, the second chiplet configured to be electrically coupled to the second integrated device via the first metallization portion. The first chiplet may include a first active chiplet or a first passive chiplet. The second chiplet may include a second active chiplet or a second passive chiplet. Placing the first chiplet closer to the first integrated device and the second chiplet closer to the second integrated device helps improve package performance. Reducing the electrical path between the first integrated device and the first chiplet and / or the electrical path between the second integrated device and the second chiplet helps reduce signal and / or current latency, which may help improve package performance. As described further below, instead of one integrated device performing all package functions, various package functions are performed by different integrated devices and / or different chiplets. By redistributing package functions across different integrated devices and / or different chiplets, cost reductions can be achieved in fabricating the package while still providing a package with high performance capabilities.

[0015] Exemplary Package with Integrated Device and Chiplet

[0034] FIG. 1 shows a cross-sectional side view of a package 100 including an integrated device and a chiplet. The package 100 includes a metallization portion 102, an integrated device 104, a chiplet 106, a plurality of pillar interconnects 107, and an encapsulation layer 108. The plurality of pillar interconnects 107 includes a plurality of pillar interconnects 107a and a plurality of pillar interconnects 107b. The package 100 is coupled to a substrate 109 via a plurality of solder interconnects 196. In some implementations, the substrate 109 may be considered part of the package 100. A plurality of solder interconnects 198 are coupled to a bottom portion of the substrate 109. The substrate 109 may be configured to be coupled to a board (not shown), such as a printed circuit board (PCB), via the plurality of solder interconnects 198. The substrate 109 includes at least one dielectric layer 190 (e.g., at least one substrate dielectric layer) and a plurality of interconnects 192 (e.g., a plurality of substrate interconnects).

[0016]

[0035] The integrated device 104 is coupled to the metallization portion 102 via a plurality of pillar interconnects 107a. The integrated device 104 is coupled to the chiplet 106 via a plurality of pillar interconnects 107b and a plurality of solder interconnects 140. The plurality of pillar interconnects 107b may be located between the integrated device 104 and the chiplet 106. The plurality of pillar interconnects 107b may include a plurality of inter-pillar interconnects. The inter-pillar interconnects may be similar to the plurality of pillar interconnects 107a. However, the inter-pillar interconnects may be shorter than the plurality of pillar interconnects 107a. The inter-pillar interconnects may be located between the integrated device 104 and the chiplet 106. The chiplet 106 is coupled to the metallization portion 102. The chiplet 106 may be configured as a passive chiplet. The chiplet 106 may be configured as a trench capacitor device (e.g., a deep trench capacitor (DTC) device). The chiplet 106 is located between the metallization portion 102 and the integrated device 104. The chiplet 106 includes a front surface and a back surface. The front surface of the chiplet 106 faces the integrated device 104. For example, the front surface of a deep trench capacitor faces the integrated device 104.

[0017]

[0036] Chiplet 106 includes a die substrate 160, a plurality of through-substrate vias 162, a plurality of trench interconnects 164, a plurality of trench interconnects 166, and a plurality of trench capacitors 167. The plurality of trench interconnects 164 are located on a front surface (e.g., a top surface) of chiplet 106. The plurality of trench interconnects 166 are located on a rear surface (e.g., a bottom surface) of chiplet 106. One or more of the through-substrate vias from the plurality of through-substrate vias 162 may be coupled to one or more trench capacitors from the plurality of trench capacitors 167. The plurality of through-substrate vias 162 may be coupled to the plurality of trench interconnects 164 and the plurality of trench interconnects 166. The plurality of trench interconnects 164 are coupled to the plurality of pillar interconnects 107b via a plurality of solder interconnects 140. Thus, for example, the plurality of solder interconnects 140 are coupled to the plurality of trench interconnects 164 and the plurality of pillar interconnects 107b. The plurality of trench interconnects 166 may be coupled (e.g., directly coupled) to the metallization portion 102. For example, the plurality of trench interconnects 166 may be configured to be directly coupled to the metallization interconnects 121 from the metallization portion 102 such that the plurality of trench interconnects 166 contact the plurality of metallization interconnects 121 from the metallization portion 102. The plurality of trench interconnects 166 may be optional. In some implementations, the plurality of through-substrate vias 162 may be configured to be coupled (e.g., directly coupled) to the metallization portion 102. For example, the plurality of through-substrate vias 162 may be configured to be directly coupled to the metallization interconnects 121 from the metallization portion 102 such that the plurality of through-substrate vias 162 contact the plurality of metallization interconnects 121 from the metallization portion 102. A more detailed example of a trench capacitor is shown and described below in at least Figure 11 of this disclosure. The front surface of the chiplet faces the integrated device 104.

[0018]

[0037] The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization portion 102 may include a redistribution portion. The plurality of metallization interconnects 121 may include a plurality of redistribution interconnects. The metallization portion 102 may be a means for metallization interconnects. The plurality of metallization interconnects 121 may be bonded to a rear surface of the chiplet 106. For example, the plurality of metallization interconnects 121 may be bonded to a plurality of trench interconnects 166 or a plurality of through-substrate vias 162. The plurality of metallization interconnects 121 may be bonded to a plurality of pillar interconnects 107a.

[0019]

[0038] As described above, the metallization portions (e.g., 102, 702) may include redistribution portions that include redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The redistribution interconnects may include portions having a U-shape or a V-shape. The terms “U-shape” and “V-shape” are interchangeable. The terms “U-shape” and “V-shape” may refer to the side profile shapes of the interconnects and / or redistribution interconnects. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have top and bottom portions. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0020]

[0039] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one pillar interconnect from the plurality of pillar interconnects 107a.

[0021]

[0040] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 166, at least one through-substrate via from the plurality of through-substrate vias 162, at least one trench interconnect from the plurality of trench interconnects 164, at least one solder interconnect from the plurality of solder interconnects 140, and / or at least one pillar interconnect from the plurality of pillar interconnects 107b.

[0022]

[0041] Integrated device 104 may be configured to be electrically coupled to chiplet 106 via a plurality of pillar interconnects 107b and a plurality of solder interconnects 140. Accordingly, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between integrated device 104 and chiplet 106 may include at least one pillar interconnect from the plurality of pillar interconnects 107b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0023]

[0042] The encapsulation layer 108 may be bonded to the metallization portion 102, the integrated device 104, and the chiplet 106. The encapsulation layer 108 may be bonded to the plurality of pillar interconnects 107. The encapsulation layer 108 may be bonded to a first surface (e.g., a top surface) of the metallization portion 102. The encapsulation layer 108 may encapsulate (e.g., partially or completely) the integrated device 104 and the chiplet 106. FIG. 1 shows that the rear surface of the integrated device 104 is exposed and not covered by an encapsulation layer. However, in some implementations, the rear surface of the integrated device 104 may be bonded to the encapsulation layer 108. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0024]

[0043] Metallization portion 102 is coupled to substrate 109 via a plurality of solder interconnects 196. For example, a metallization interconnect from plurality of metallization interconnects 121 may be coupled to an interconnect from plurality of interconnects 192 via a plurality of solder interconnects 196. Underfill 105 is coupled to substrate 109, metallization portion 102, and encapsulation layer 108. Underfill 105 may be considered part of package 100.

[0025]

[0044] The location and / or placement of the chiplets 106 near the integrated device 104 helps to reduce signal and / or current latency between the integrated device 104 and the chiplets 106, thereby helping to improve the performance of the integrated device 104 and / or package 100. The chiplets 106 are described as being configured as deep trench capacitors. However, as described further below, different implementations may use chiplets configured to perform other operations and / or functionality.

[0026]

[0045] The use of integrated devices, chiplets, and metallization portions in the package of Figure 1, and at least those described in Figures 2-10, provides several advantages. First, it can result in cost reductions for the package by redistributing various functions of the package across at least one integrated device and at least one chiplet. The integrated devices and chiplets can be fabricated using different technology nodes, which may have different costs.

[0027]

[0046] A technology node may refer to a particular fabrication process and / or technology used to fabricate integrated devices and / or chiplets. A technology node may specify the smallest possible size (e.g., minimum size) that can be fabricated (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces components (e.g., traces, transistors) with fine details may be more expensive and have higher yield losses than a technology node that produces components (e.g., traces, transistors) with less fine details. Thus, a more advanced technology node may be more expensive and have higher yield losses than a less advanced technology node. If all of the functionality of a package is realized within a single integrated device, the same technology node is used to fabricate the entire integrated device, even if some of the functionality of the integrated device need not be fabricated using that particular technology node. Thus, an integrated device is locked to one technology node. To optimize package costs, some of the functions may be realized in different integrated devices and / or chiplets, and the different integrated devices and / or chiplets may be fabricated using different technology nodes to reduce overall cost. For example, functions requiring the use of a leading-edge technology node may be realized in an integrated device, while functions that can be implemented using a less advanced technology node may be realized in another integrated device and / or one or more chiplets. One example is an integrated device fabricated using a first technology node (e.g., a leading-edge technology node) configured to provide a computing application and at least one chiplet fabricated using a second technology node configured to provide other functionality, where the second technology node is less expensive than the first technology node and where the second technology node fabricates components having a minimum size that is larger than the minimum size of components fabricated using the first technology node.Example computational applications may include high-performance computing and / or processing, which may be achieved by fabricating and packing as many transistors as possible in an integrated device; integrated devices configured for computational applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes because these chiplets may not require as many transistors as fabricated in the chiplet. Thus, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets may reduce the overall cost of the package compared to using a single integrated device to perform all of the functions of the package.

[0028]

[0047] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign every single integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve the package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or differently configured first integrated device. This saves costs by not having to redesign the first chiplet when a package with an improved integrated device is created.

[0029]

[0048] Furthermore, chiplets can be coupled to the integrated device via copper-to-copper hybrid bonds or via solder interconnects so that the chiplets are very close to the integrated device. For example, the chiplets and integrated device can be implemented using metallization (e.g., rewiring) to position the chiplets as close as possible to the integrated device, thereby reducing the electrical path between the chiplets and the integrated device. This helps improve the performance of the integrated device and the power delivered to the integrated device. In some implementations, the minimum pitch of interconnects coupled to the chiplets can be as small as about 20 micrometers.

[0030]

[0049] Additionally, chiplets including trench capacitors offer several technical advantages. Trench capacitors and / or trench capacitor devices provide capacitors with high capacitance and / or high capacitance density. Capacitors with higher capacitance density allow for more compact form factors for packaging, as these capacitors may occupy less space but provide the same and / or comparable capacitance as larger-sized capacitors. The compact form factor of trench capacitors allows them to be located very close to integrated devices, which can help improve power delivery performance to integrated devices. Furthermore, because these trench capacitors have a small form factor, they can be implemented using metallization instead of being implemented within the package substrate. Thus, high-capacitance capacitors can be implemented during package fabrication instead of when the package is bonded to the substrate.

[0031]

[0050] High capacitance capacitors are particularly important in certain types of processing operations, such as computing applications (e.g., high performance processing). The use of chiplets, integrated devices, and metallization portions as described in this disclosure helps to improve inter-die communication, which helps to improve the overall performance of the integrated device(s) and package.

[0032]

[0051] 2 shows a cross-sectional side view of package 200 including an integrated device and a chiplet. Package 200 includes metallization portion 102, integrated device 104, chiplet 106, a plurality of pillar interconnects 107, encapsulation layer 108, encapsulation layer 208, and dielectric layer 281. Package 200 is similar to package 100 of FIG. 1 and, therefore, includes the same or similar components arranged and / or configured in the same and / or similar manner as package 100. For example, chiplet 106 may be configured to operate as a deep trench capacitor, such as at least that described in FIG. 11.

[0033]

[0052] The package 200 includes two encapsulation layers separated by a dielectric layer. The encapsulation layer 108 may be a first encapsulation layer, and the encapsulation layer 208 may be a second encapsulation layer. The dielectric layer 281 is located between the encapsulation layer 108 and the encapsulation layer 208. The dielectric layer 281 is bonded to the inner surface of the encapsulation layer 108 and the inner surface of the encapsulation layer 208. The dielectric layer 281 may include polyimide (PI). In some implementations, the encapsulation layer 208 may be the same as the encapsulation layer 108. In some implementations, the encapsulation layer 208 may have one or more properties different from the encapsulation layer 108. For example, the encapsulation layer 108 may include a higher concentration of filler than the encapsulation layer 208. As further described below with respect to at least FIG. 14A , the multiple pillar interconnects 107 may include a seed layer (e.g., a metal seed layer, a copper seed layer) that is planar with respect to the dielectric layer 281. The encapsulation layer 108 is bonded to the integrated device 104, at least a portion of the plurality of pillar interconnects 107 a, and at least a portion of the plurality of pillar interconnects 107 b. The encapsulation layer 208 is bonded to the metallization portion 102, the chiplet 106, the plurality of solder interconnects 140, and at least a portion of the plurality of pillar interconnects 107 a.

[0034]

[0053] 3 shows a cross-sectional side view of a package 300 including an integrated device and a chiplet. Package 300 includes metallization portion 102, integrated device 104, chiplet 306, a plurality of pillar interconnects 107, encapsulation layer 108, encapsulation layer 208, and dielectric layer 281. Package 300 is similar to package 100 of FIG. 1 and / or package 200 of FIG. 2 and, therefore, includes the same or similar components arranged and / or configured in the same and / or similar manner as package 100 and / or package 200.

[0035]

[0054] Chiplet 306 may be configured to provide different functionality than chiplet 106. Chiplet 306 may be configured as an active chiplet or a passive chiplet. Chiplet 306 may be configured to operate as a memory (e.g., a first memory, a second memory), a power management integrated circuit (PMIC) (e.g., a first power management integrated circuit, a second power management integrated circuit), and / or a voltage regulator (e.g., a first voltage regulator, a second voltage regulator). Chiplet 306 may include an integrated device having a smaller size than integrated device 104. Chiplet 306 may include a die substrate, multiple die transistors, and multiple die interconnects (all not shown). In some implementations, chiplet 306 may include multiple through-substrate vias (not shown).

[0036]

[0055] The chiplet 306 is coupled to the integrated device 104 via a plurality of solder interconnects 140 and a plurality of pillar interconnects 107b. The front surface of the chiplet 306 faces the integrated device 104. FIG. 3 shows that the rear surface of the chiplet 306 does not contact the metallization portion 102. However, in some implementations, the chiplet 306 may contact the metallization portion 102. In some implementations, the rear surface of the chiplet 306 may contact the metallization portion 102. For example, the rear surface of the chiplet 306 may contact and / or be coupled to the metallization interconnect 121 of the metallization portion 102, similar to that described for the chiplet 106 in FIGS. 1 and 2 . The front surface of the chiplet 306 may face the integrated device 104.

[0037]

[0056] 4 shows a package 400 including at least two integrated devices and at least two chiplets. The package 400 includes an integrated device 104, a chiplet 106, an integrated device 404, a chiplet 406, a metallization portion 102, and an encapsulation layer 108. The chiplet 106 is located between the integrated device 104 and the metallization portion 102. The chiplet 406 is located between the integrated device 404 and the metallization portion 102. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404, the chiplet 106, and the chiplet 406. The encapsulation layer 108 may be bonded to the metallization portion 102.

[0038]

[0057] The package 400 is coupled to the substrate 109 via a plurality of solder interconnects 196. A plurality of solder interconnects 198 may be coupled to the substrate 109. The underfill 105 is coupled to the substrate 109, the metallization portion 102, and the encapsulation layer 108.

[0039]

[0058] The integrated device 104 is coupled to the metallization portion 102 via a plurality of pillar interconnects 107a. The integrated device 104 is coupled to the chiplet 106 via a plurality of pillar interconnects 107b and a plurality of solder interconnects 140. The plurality of pillar interconnects 107b may be located between the integrated device 104 and the chiplet 106. The chiplet 106 is coupled to the metallization portion 102. The chiplet 106 may be configured as a passive chiplet. The chiplet 106 may be configured as a deep trench capacitor (DTC). The chiplet 106 is located between the metallization portion 102 and the integrated device 104. The chiplet 106 includes a front surface and a back surface. The front surface of the chiplet 106 faces the integrated device 104. For example, the front surface of a deep trench capacitor faces the integrated device 104.

[0040]

[0059] The integrated device 404 is coupled to the metallization portion 102 via a plurality of pillar interconnects 407a. The integrated device 404 is coupled to the chiplet 406 via a plurality of pillar interconnects 407b and a plurality of solder interconnects 440. The plurality of pillar interconnects 407b may be located between the integrated device 404 and the chiplet 406. The plurality of pillar interconnects 407b may include a plurality of inter-pillar interconnects. The inter-pillar interconnects may be similar to the plurality of pillar interconnects 407a. However, the inter-pillar interconnects may be shorter than the plurality of pillar interconnects 407a. The inter-pillar interconnects may be located between the integrated device 404 and the chiplet 406. The chiplet 406 is coupled to the metallization portion 102. The chiplet 406 may be configured as a passive chiplet. The chiplet 406 may be configured as a deep trench capacitor (DTC). The chiplet 406 is located between the metallization portion 102 and the integrated device 404. The chiplet 406 includes a front surface and a back surface. The front surface of the chiplet 406 faces the integrated device 404. For example, the front surface of a deep trench capacitor faces the integrated device 404.

[0041]

[0060] Integrated device 104 may be configured to be electrically coupled to integrated device 404 via metallization portion 102. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 via an electrical path that includes (i) at least one pillar interconnect from the plurality of pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, and (iii) at least one pillar interconnect from the plurality of pillar interconnects 407a.

[0042]

[0061] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one pillar interconnect from the plurality of pillar interconnects 107a.

[0043]

[0062] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 166, at least one through-substrate via from the plurality of through-substrate vias 162, at least one trench interconnect from the plurality of trench interconnects 164, at least one solder interconnect from the plurality of solder interconnects 140, and / or at least one pillar interconnect from the plurality of pillar interconnects 107b.

[0044]

[0063] Integrated device 104 may be configured to be electrically coupled to chiplet 106 via a plurality of pillar interconnects 107b and a plurality of solder interconnects 140. Accordingly, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between integrated device 104 and chiplet 106 may include at least one pillar interconnect from the plurality of pillar interconnects 107b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0045]

[0064] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 404 may include at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one pillar interconnect from the plurality of pillar interconnects 407a.

[0046]

[0065] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 404 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 466, at least one through-substrate via from the plurality of through-substrate vias 462, at least one trench interconnect from the plurality of trench interconnects 464, at least one solder interconnect from the plurality of solder interconnects 440, and / or at least one pillar interconnect from the plurality of pillar interconnects 407b.

[0047]

[0066] The integrated device 404 may be configured to be electrically coupled to the chiplet 406 via the plurality of pillar interconnects 407b and the plurality of solder interconnects 440. Accordingly, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 404 and the chiplet 406 may include at least one pillar interconnect from the plurality of pillar interconnects 407b and / or at least one solder interconnect from the plurality of solder interconnects 440.

[0048]

[0067] 5 shows a package 500 including a bridge, at least two integrated devices, and at least two chiplets. Package 500 includes integrated device 104, chiplet 106, integrated device 404, chiplet 406, metallization portion 102, bridge 505, and encapsulation layer 108. Package 500 is similar to package 400 and may be configured similarly to that described for package 400. Chiplet 106 is located between integrated device 104 and metallization portion 102. Chiplet 406 is located between integrated device 404 and metallization portion 102. Encapsulation layer 108 encapsulates integrated device 104, integrated device 404, chiplet 106, chiplet 406, and bridge 505. Encapsulation layer 108 may be bonded to metallization portion 102.

[0049]

[0068] The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The bridge 505 is bonded to the metallization portion 102. A front surface of the bridge 505 may be bonded to the metallization portion 102.

[0050]

[0069] Integrated device 104 may be configured to be electrically coupled to integrated device 404 via metallization portion 102 and bridge 505. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 via an electrical path that includes (i) at least one pillar interconnect from the plurality of pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, (iii) at least one die interconnect from bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one pillar interconnect from the plurality of pillar interconnects 407a.

[0051]

[0070] In some implementations, package 400 and / or package 500 may include a dielectric layer 281 located within encapsulation layer 108, similar to that described for package 200 and / or package 300.

[0052]

[0071] 6 shows a package 600 including a bridge, at least two integrated devices, and at least two chiplets. Package 600 includes integrated device 104, chiplet 306, integrated device 404, chiplet 606, metallization portion 102, bridge 505, and encapsulation layer 108. Package 600 is similar to packages 400 and 500 and may be configured similarly as described for packages 400 and 500. Chiplet 306 is located between integrated device 104 and metallization portion 102. Chiplet 606 is located between integrated device 404 and metallization portion 102. Encapsulation layer 108 encapsulates integrated device 104, integrated device 404, chiplet 306, chiplet 606, and bridge 505. Encapsulation layer 108 may be bonded to metallization portion 102.

[0053]

[0072] The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The bridge 505 is bonded to the metallization portion 102. A front surface of the bridge 505 may be bonded to the metallization portion 102.

[0054]

[0073] Integrated device 104 may be configured to be electrically coupled to integrated device 404 via metallization portion 102 and bridge 505. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 via an electrical path that includes (i) at least one pillar interconnect from the plurality of pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, (iii) at least one die interconnect from bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one pillar interconnect from the plurality of pillar interconnects 407a.

[0055]

[0074] The integrated device 104 may be configured to be electrically coupled to the chiplet 306 via the plurality of pillar interconnects 107b and the plurality of solder interconnects 140. Accordingly, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 104 and the chiplet 306 may include at least one pillar interconnect from the plurality of pillar interconnects 107b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0056]

[0075] The integrated device 404 may be configured to be electrically coupled to the chiplet 606 via the plurality of pillar interconnects 207b and the plurality of solder interconnects 240. Accordingly, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 404 and the chiplet 606 may include at least one pillar interconnect from the plurality of pillar interconnects 207b and / or at least one solder interconnect from the plurality of solder interconnects 240.

[0057]

[0076] 7 shows a package 700 including at least two integrated devices and at least two chiplets. The package 700 includes an integrated device 104, a chiplet 106, an integrated device 404, a chiplet 406, a metallization portion 102, a metallization portion 702, an encapsulation layer 108, and an encapsulation layer 708. The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization portion 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 721. The encapsulation layer 108 encapsulates the integrated device 104 and the integrated device 404. The encapsulation layer 108 can be bonded to the metallization portion 102.

[0058]

[0077] Chiplet 106 is located between metallization portion 102 and metallization portion 702. Chiplet 106 may be coupled to metallization portion 102 via a plurality of solder interconnects 710. The plurality of solder interconnects 710 may be coupled to at least one interconnect from chiplet 106 and at least one metallization interconnect from the plurality of metallization interconnects 121 of metallization portion 102. Chiplet 106 may contact metallization portion 702. For example, an interconnect from chiplet 106 may contact at least one metallization interconnect from the plurality of metallization interconnects 721 of metallization portion 702. Chiplet 406 is located between metallization portion 102 and metallization portion 702. Chiplet 406 may be coupled to metallization portion 102 via a plurality of solder interconnects 740. Chiplet 406 may contact metallization portion 702. For example, an interconnect from chiplet 406 may contact at least one metallization interconnect from multiple metallization interconnects 721 of metallization portion 702.

[0059]

[0078] The encapsulation layer 708 may encapsulate the chiplet 106 and the chiplet 406. The encapsulation layer 708 may be coupled to the metallization portion 102 and the metallization portion 702. A plurality of through-mold vias 780 may be located within the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization portion 102 and the metallization portion 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization portion 102 and the metallization portion 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization portion 102 and (ii) the plurality of metallization interconnects 721 of the metallization portion 702.

[0060]

[0079] Integrated device 104 is configured to be electrically coupled to integrated device 404 via metallization portion 102. For example, the electrical path between integrated device 104 and integrated device 404 may include at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102. The electrical path between integrated device 104 and integrated device 404 may be configured for signals (e.g., input / output signals) between integrated device 104 and integrated device 404.

[0061]

[0080] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 106, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0062]

[0081] In some implementations, the electrical path between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0063]

[0082] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 406, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0064]

[0083] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0065]

[0084] Integrated device 104 is configured to be electrically coupled to chiplet 106. For example, integrated device 104 may be configured to be electrically coupled to chiplet 106 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 710.

[0066]

[0085] Integrated device 404 is configured to be electrically coupled to chiplet 406. For example, integrated device 404 may be configured to be electrically coupled to chiplet 406 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 740.

[0067]

[0086] 8 shows a package 800 including at least two integrated devices and at least two chiplets. Package 800 is similar to package 700, and therefore package 800 may be configured similarly to that described for package 700. Package 800 includes integrated device 104, chiplet 106, integrated device 404, chiplet 406, metallization portion 102, metallization portion 702, bridge 505, encapsulation layer 108, and encapsulation layer 708. Metallization portion 102 includes at least one dielectric layer 120 and multiple metallization interconnects 121. Metallization portion 702 includes at least one dielectric layer 720 and multiple metallization interconnects 721. Encapsulation layer 108 encapsulates integrated device 104 and integrated device 404. Encapsulation layer 108 may be bonded to metallization portion 102.

[0068]

[0087] Chiplet 106 is located between metallization portion 102 and metallization portion 702. Chiplet 106 may be coupled to metallization portion 102 via a plurality of solder interconnects 710. The plurality of solder interconnects 710 may be coupled to at least one interconnect from chiplet 106 and at least one metallization interconnect from the plurality of metallization interconnects 121 of metallization portion 102. Chiplet 106 may contact metallization portion 702. For example, an interconnect from chiplet 106 may contact at least one metallization interconnect from the plurality of metallization interconnects 721 of metallization portion 702. Chiplet 406 is located between metallization portion 102 and metallization portion 702. Chiplet 406 may be coupled to metallization portion 102 via a plurality of solder interconnects 740. Chiplet 406 may contact metallization portion 702. For example, an interconnect from chiplet 406 may contact at least one metallization interconnect from multiple metallization interconnects 721 of metallization portion 702.

[0069]

[0088] The bridge 505 is located between the metallization portion 102 and the metallization portion 702. The bridge 505 is coupled to the metallization portion 102 via a plurality of solder interconnects 850. The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. A front surface of the bridge 505 may be coupled to the metallization portion 102.

[0070]

[0089] The encapsulation layer 708 may encapsulate the chiplet 106, the chiplet 406, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization portion 102 and the metallization portion 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization portion 102 and the metallization portion 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization portion 102 and the metallization portion 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization portion 102 and (ii) the plurality of metallization interconnects 721 of the metallization portion 702.

[0071]

[0090] Integrated device 104 is configured to be electrically coupled to integrated device 404 via metallization portion 102 and bridge 505. For example, the electrical pathway between integrated device 104 and integrated device 404 may include (i) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102, (ii) at least one solder interconnect from the plurality of solder interconnects 850, (iii) bridge 505, (iv) at least one solder interconnect from the plurality of solder interconnects 850, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102. The electrical pathway between integrated device 104 and integrated device 404 may be configured for signals (e.g., input / output signals) between integrated device 104 and integrated device 404.

[0072]

[0091] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 106, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0073]

[0092] In some implementations, the electrical path between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0074]

[0093] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 406, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0075]

[0094] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0076]

[0095] Integrated device 104 is configured to be electrically coupled to chiplet 106. For example, integrated device 104 may be configured to be electrically coupled to chiplet 106 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 710.

[0077]

[0096] Integrated device 404 is configured to be electrically coupled to chiplet 406. For example, integrated device 404 may be configured to be electrically coupled to chiplet 406 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 740.

[0078]

[0097] 9 shows a package 900 including at least two integrated devices and at least two chiplets. Package 900 is similar to package 800, and therefore package 900 may be configured similarly to that described for package 800. Package 900 includes integrated device 104, chiplet 306, integrated device 404, chiplet 606, metallization portion 102, metallization portion 702, bridge 505, encapsulation layer 108, and encapsulation layer 708. Metallization portion 102 includes at least one dielectric layer 120 and multiple metallization interconnects 121. Metallization portion 702 includes at least one dielectric layer 720 and multiple metallization interconnects 721. Encapsulation layer 108 encapsulates integrated device 104 and integrated device 404. Encapsulation layer 108 may be bonded to metallization portion 102.

[0079]

[0098] Chiplet 306 is located between metallization portion 102 and metallization portion 702. Chiplet 306 may be coupled to metallization portion 102 via a plurality of solder interconnects 710. The plurality of solder interconnects 710 may be coupled to at least one interconnect from chiplet 306 and at least one metallization interconnect from the plurality of metallization interconnects 121 of metallization portion 102. Chiplet 306 may contact metallization portion 702. For example, an interconnect from chiplet 306 may contact at least one metallization interconnect from the plurality of metallization interconnects 721 of metallization portion 702. Chiplet 606 is located between metallization portion 102 and metallization portion 702. Chiplet 606 may be coupled to metallization portion 102 via a plurality of solder interconnects 740. Chiplet 606 may contact metallization portion 702. For example, an interconnect from chiplet 606 may contact at least one metallization interconnect from multiple metallization interconnects 721 of metallization portion 702.

[0080]

[0099] The bridge 505 is located between the metallization portion 102 and the metallization portion 702. The bridge 505 is coupled to the metallization portion 102 via a plurality of solder interconnects 850. The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. A front surface of the bridge 505 may be coupled to the metallization portion 102.

[0081]

[0100] The encapsulation layer 708 may encapsulate the chiplet 306, the chiplet 606, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization portion 102 and the metallization portion 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization portion 102 and the metallization portion 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization portion 102 and the metallization portion 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization portion 102 and (ii) the plurality of metallization interconnects 721 of the metallization portion 702.

[0082]

[0101] The front surface of bridge 505 faces metallization portion 102. The front surface of chiplet 306 faces metallization portion 102. The front surface of chiplet 606 faces metallization portion 102.

[0083]

[0102] Integrated device 104 is configured to be electrically coupled to integrated device 404 via metallization portion 102 and bridge 505. For example, the electrical pathway between integrated device 104 and integrated device 404 may include (i) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102, (ii) at least one solder interconnect from the plurality of solder interconnects 850, (iii) bridge 505, (iv) at least one solder interconnect from the plurality of solder interconnects 850, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102. The electrical pathway between integrated device 104 and integrated device 404 may be configured for signals (e.g., input / output signals) between integrated device 104 and integrated device 404.

[0084]

[0103] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 306, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0085]

[0104] In some implementations, the electrical path between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0086]

[0105] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the chiplet 606, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0087]

[0106] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0088]

[0107] Integrated device 104 is configured to be electrically coupled to chiplet 306. For example, integrated device 104 may be configured to be electrically coupled to chiplet 306 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 710.

[0089]

[0108] Integrated device 404 is configured to be electrically coupled to chiplet 606. For example, integrated device 404 may be configured to be electrically coupled to chiplet 606 via an electrical path that includes at least one metallization interconnect from the plurality of metallization interconnects 121 and at least one solder interconnect from the plurality of solder interconnects 740.

[0090]

[0109] FIG. 10 shows a package 1000 including at least two integrated devices and at least two chiplets. Package 1000 is similar to package 900, and therefore package 1000 may be configured similarly to that described for package 1000. Package 1000 includes integrated device 104, chiplet 106, integrated device 404, chiplet 406, metallization portion 102, metallization portion 702, bridge 505, encapsulation layer 108, and encapsulation layer 708. Metallization portion 102 includes at least one dielectric layer 120 and multiple metallization interconnects 121. Metallization portion 702 includes at least one dielectric layer 720 and multiple metallization interconnects 721. Encapsulation layer 108 encapsulates integrated device 104 and integrated device 404. Encapsulation layer 108 may be bonded to metallization portion 102.

[0091]

[0110] Chiplet 106 is located between metallization portion 102 and metallization portion 702. Chiplet 106 may be coupled to metallization portion 702 via a plurality of solder interconnects 710. The plurality of solder interconnects 710 may be coupled to at least one interconnect from chiplet 106 and at least one metallization interconnect from the plurality of metallization interconnects 721 of metallization portion 702. Chiplet 106 may contact metallization portion 102. For example, an interconnect from chiplet 106 may contact at least one metallization interconnect from the plurality of metallization interconnects 121 of metallization portion 102. Chiplet 406 is located between metallization portion 102 and metallization portion 702. Chiplet 406 may be coupled to metallization portion 702 via a plurality of solder interconnects 740. The chiplets 406 may contact the metallization portion 102. For example, an interconnect from the chiplet 406 may contact at least one metallization interconnect from the plurality of metallization interconnects 121 of the metallization portion 102.

[0092]

[0111] The bridge 505 is located between the metallization portion 102 and the metallization portion 702. The bridge 505 is bonded to the metallization portion 102. The bridge 505 may include a die substrate and a plurality of die interconnects. The bridge 505 may include a dielectric layer. A front surface of the bridge 505 may be bonded to the metallization portion 102. A rear surface of the bridge 505 may be bonded to the metallization portion 702 via an adhesive 1005. For example, a rear surface of the die substrate of the bridge 505 may be bonded to the metallization portion 702 via an adhesive 1005. A front surface of the bridge 505 faces the metallization portion 102. A front surface of the chiplet 406 faces the metallization portion 102. A front surface of the chiplet 406 faces the metallization portion 102.

[0093]

[0112] The encapsulation layer 708 may encapsulate the chiplet 106, the chiplet 406, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization portion 102 and the metallization portion 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization portion 102 and the metallization portion 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization portion 102 and the metallization portion 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization portion 102 and (ii) the plurality of metallization interconnects 721 of the metallization portion 702.

[0094]

[0113] Integrated device 104 is coupled to metallization portion 102 via a plurality of solder interconnects 1010. Integrated device 404 is coupled to metallization portion 102 via a plurality of solder interconnects 1030. Integrated device 104 is configured to be electrically coupled to integrated device 404 via metallization portion 102 and bridge 505. For example, an electrical path between integrated device 104 and integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 1010, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102, (iii) bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121 from metallization portion 102, and (v) at least one solder interconnect from the plurality of solder interconnects 830. An electrical path between the integrated device 104 and the integrated device 404 may be configured for signals (eg, input / output signals) between the integrated device 104 and the integrated device 404 .

[0095]

[0114] In some implementations, an electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (ii) at least one solder interconnect from the plurality of solder interconnects 1060, (iv) the chiplet 106, (v) at least one metallization interconnect from the plurality of metallization interconnects 121, and (vi) at least one solder interconnect from the plurality of solder interconnects 1010.

[0096]

[0115] In some implementations, the electrical path between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder interconnect from the plurality of solder interconnects 1010.

[0097]

[0116] In some implementations, the electrical path (e.g., configured to supply power) between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (ii) at least one solder interconnect from the plurality of solder interconnects 1040, (iv) the chiplet 406, (v) at least one metallization interconnect from the plurality of metallization interconnects 121, and (vi) at least one solder interconnect from the plurality of solder interconnects 1030.

[0098]

[0117] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder interconnect from the plurality of solder interconnects 1030.

[0099]

[0118] Integrated device 104 is configured to be electrically coupled to chiplet 106. For example, integrated device 104 may be configured to be electrically coupled to chiplet 106 via an electrical path that includes at least one solder interconnect from the plurality of solder interconnects 1010 and at least one metallization interconnect from the plurality of metallization interconnects 121.

[0100]

[0119] Integrated device 404 is configured to be electrically coupled to chiplet 406. For example, integrated device 404 may be configured to be electrically coupled to chiplet 406 via an electrical path that includes at least one solder interconnect from the plurality of solder interconnects 1030 and at least one metallization interconnect from the plurality of metallization interconnects 121.

[0101]

[0120] The package 1000 is coupled to a substrate 709 via a plurality of solder interconnects 196. The substrate 709 may be a board (e.g., a printed circuit board).

[0102]

[0121] 1-10 illustrate various packages that include at least one chiplet located near an integrated device. The use of chiplets and integrated devices with metallization portion(s) provides several advantages. First, the chiplets can be fabricated using a different fabrication process (e.g., technology node) than the integrated device. This helps reduce costs because the chiplets may not need to be fabricated using the most expensive fabrication process. Furthermore, the use of chiplets with metallization portion(s) helps improve electrical performance between the integrated device and / or chiplets because the chiplets and / or integrated device can be located near each other.

[0103]

[0122] As described above, the package may include several metallization portions. Any of the metallization portions may be a first metallization portion and / or any of the metallization portions may be a second metallization portion. For example, in some implementations, metallization portion 102 may be considered a first metallization portion and metallization portion 702 may be considered a second metallization portion. In some implementations, metallization portion 702 may be considered a first metallization portion and metallization portion 102 may be considered a second metallization portion.

[0104]

[0123] As described above, chiplets may include trench capacitors and / or be configured to operate as trench capacitor devices. Trench capacitors and / or trench capacitor devices provide capacitors with high capacitance and / or high capacitance density. Capacitors with higher capacitance density allow for more compact form factors for packaging because they may occupy less space but provide the same and / or comparable capacitance as larger sized capacitors. The compact form factor of trench capacitors allows them to be located very close to integrated devices, which may help improve power delivery performance to the integrated devices. Furthermore, because these trench capacitors have a small form factor, they may be implemented using metallization instead of being implemented within a package substrate.

[0105] Exemplary Chiplet with Trench Capacitor

[0124] 11 shows a cross-sectional side view of a chiplet 1100 configured as a trench capacitor device. The chiplet 1100 may be an integrated passive device including multiple trench capacitors (e.g., deep trench capacitors). The chiplet 1100 may be a means for trench capacitance. The chiplet 1100 may represent the chiplet 106 and / or the chiplet 406. The chiplet 1100 includes a front surface and a back surface. The front surface of the chiplet 1100 may include multiple trench capacitors.

[0106]

[0125] Chiplet 1100 includes a chiplet substrate 1102 and a plurality of trench capacitors 1105. A plurality of solder interconnects (not shown) may be coupled to chiplet 1100. Chiplet substrate 1102 may include silicon (Si). Chiplet substrate 1102 may include a plurality of trenches and / or cavities upon which capacitors may be formed. Examples of trenches and / or cavities are further described below in at least Figures 12A-12C.

[0107]

[0126] The plurality of trench capacitors 1105 includes trench capacitor 1105a and trench capacitor 1105b. Trench capacitor 1105a and trench capacitor 1105b may be configured to be part of the same capacitor (e.g., a first capacitor, a first trench capacitor). Trench capacitor 1105a and trench capacitor 1105b may be coupled to and / or configured to be part of a first power distribution network (PDN). Trench capacitor 1105a and trench capacitor 1105b may be configured to be part of a first electrical path for a first power for the package. Trench capacitor 1105a and trench capacitor 1105b may be configured to be coupled to integrated device(s).

[0108]

[0127] 11, chiplet 1100 includes a chiplet substrate 1102, an oxide layer 1104, a first conductive layer 1106, a dielectric layer 1108, and a second conductive layer 1110. First conductive layer 1106 and / or second conductive layer 1110 may include polysilicon. Oxide layer 1104 and / or dielectric layer 1108 may include SiO (e.g., low-pressure chemical vapor deposition (LPCVD) SiO) or SiN (e.g., LPCVD SiN). Portions of oxide layer 1104, first conductive layer 1106, dielectric layer 1108, and second conductive layer 1110 may be located within trenches and / or cavities in chiplet substrate 1102. It should be noted that chiplet substrate 1102 may be considered to have trenches or cavities even if the trenches or cavities are filled with one or more materials.

[0109]

[0128] Trench capacitor 1105a (e.g., first trench capacitor, first capacitor, means for first trench capacitance) may be defined by (i) a first portion of oxide layer 1104, (ii) a first portion of first conductive layer 1106, (iii) a first portion of dielectric layer 1108, and (iv) a first portion of second conductive layer 1110 located within a trench (e.g., a first trench) in chiplet substrate 1102.

[0110]

[0129] Trench capacitor 1105b (e.g., second trench capacitor, second capacitor, means for second trench capacitance) may be defined by (i) a second portion of oxide layer 1104, (ii) a second portion of first conductive layer 1106, (iii) a second portion of dielectric layer 1108, and (iv) a second portion of second conductive layer 1110, located within a trench (e.g., a second trench) in chiplet substrate 1102. Note that trench capacitor 1105b may be part of the same capacitor as trench capacitor 1105a. That is, trench capacitor 1105a and trench capacitor 1105b may be configured to be electrically coupled together to form a capacitor (e.g., a first capacitor) having a larger capacitance.

[0111]

[0130] Chiplet 1100 also includes interconnect 1109, interconnect 1192, and interconnect 1194. Interconnect 1109 is coupled to interconnect 1192 and interconnect 1194. Interconnect 1109 may be a through-substrate via extending through chiplet substrate 1102. Interconnect 1192 may be a pad interconnect. Interconnect 1194 may be a pad interconnect. Interconnect 1192 may be located on the front side of chiplet 1100. Interconnect 1192 may be located on the rear side of chiplet 1100. Interconnect 1109 may be a chiplet through-substrate interconnect. A chiplet may include at least one chiplet through-substrate interconnect.

[0112]

[0131] The integrated device (e.g., 104, 404) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 104, 404) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a chiplet. Chiplets may be fabricated using processes that offer better yields compared to other processes used to fabricate other types of integrated devices, thereby lowering the overall cost of fabricating the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As described above, using several chiplets to perform several functions may reduce the overall cost of the package relative to using a single chip to perform all of the package's functions.In some implementations, one or more of the chiplets (e.g., 106, 306, 406, 606, 1100) and / or one or more of the integrated devices (e.g., 104, 404) described herein may be fabricated using the same technology node or two or more different technology nodes. For example, the integrated device (e.g., 104) may be fabricated using a first technology node, and the chiplet (e.g., 106) may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, the integrated device (e.g., 104) may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet (e.g., 106) may include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, the integrated device 104 and the integrated device 404 of the package may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet (eg, 106) and another chiplet (eg, 406) in a package may be fabricated using the same technology node or different technology nodes.

[0113]

[0132] As an example, in some implementations, a first integrated device (e.g., 104) may include a first plurality of die interconnects including a first minimum spacing, and a second integrated device (e.g., 404) may include a second plurality of die interconnects including a second minimum spacing. A chiplet (e.g., 106, 306, 406) may include a plurality of interconnects including a third minimum spacing. In some implementations, the third minimum spacing may be different from the first minimum spacing and / or the second minimum spacing. As another example, in some implementations, an integrated device (e.g., 104, 404) may include a plurality of die interconnects including a first minimum spacing, and a chiplet (e.g., 106, 306, 406) may include a plurality of interconnects including a second minimum spacing. In yet another example, in some implementations, an integrated device (e.g., 104, 404) may include a first plurality of transistors including a first minimum spacing, and a chiplet (e.g., 106, 306, 606) may include a second plurality of transistors including a second minimum spacing. In some implementations, the first minimum spacing is smaller than the second minimum spacing. In some implementations, the first minimum spacing may be the same as the second minimum spacing.

[0114] Exemplary Sequence for Fabricating Chiplets with Trench Capacitors

[0133] In some implementations, fabricating a chiplet with a trench capacitor involves several processes. Figures 12A-12D show an example sequence for providing or fabricating a chiplet with a trench capacitor. In some implementations, the sequence of Figures 12A-12D may be used to provide or fabricate the chiplet 1100 of Figure 11. However, the process of Figures 12A-12D may be used to fabricate any of the chiplets described in this disclosure (e.g., 106, 406).

[0115]

[0134] It should be noted that the sequences of FIGS. 12A to 12D may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a chiplet having a trench capacitor. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0116]

[0135] Step 1 shows the state after substrate 1102 is provided, as shown in FIG. 12A. Substrate 1102 can be a chiplet substrate. Substrate 1102 can include silicon (Si).

[0117]

[0136] Step 2 shows the state after a plurality of trenches 1200 are formed in substrate 1102. The plurality of trenches 1200 can include a plurality of cavities. The plurality of trenches 1200 can include a first trench, a second trench, a third trench, and a fourth trench. The trenches can have different shapes and / or different depths. An etching process can be used to form the plurality of trenches. The plurality of trenches 1200 can be spaced equidistantly or have different spacings.

[0118]

[0137] Step 3 shows the state after an oxide layer 1104 is formed on the surface of substrate 1102, as shown in FIG. 12B. A deposition process can be used to form the oxide layer 1104 on the surface of substrate 1102 including above and within the plurality of trenches 1200. For example, a chemical vapor deposition (CVD) process can be used to form the oxide layer 1104. A low-pressure chemical vapor deposition (LPCVD) process can be used to form the oxide layer 1104. The oxide layer 1104 can take the shape and / or contour of the plurality of trenches 1200.

[0119]

[0138] Stage 4 illustrates the state after the first conductive layer 1106 is formed on the oxide layer 1104. The first conductive layer 1106 may include polysilicon. A deposition process may be used to form the first conductive layer 1106 on the oxide layer 1104, including over and within the plurality of trenches 1200. For example, a chemical vapor deposition (CVD) process may be used to form the first conductive layer 1106. A low-pressure chemical vapor deposition (LPCVD) process may be used to form the first conductive layer 1106. The first conductive layer 1106 may take the shape and / or contour of the oxide layer 1104 and / or the plurality of trenches 1200. The first conductive layer 1106 may include polysilicon. The first conductive layer 1106 may be doped. An example of a dopant includes boron. Thus, for example, the first conductive layer 1106 may include LPCVD polysilicon doped with boron.

[0120]

[0139] Stage 5, as shown in Figure 12C, illustrates the state after a dielectric layer 1108 has been formed over the first conductive layer 1106. A deposition and / or lamination process may be used to form the dielectric layer 1108 over the first conductive layer 1106, including over and within the plurality of trenches 1200.

[0121]

[0140] Stage 6 illustrates the state after a second conductive layer 1110 is formed on the dielectric layer 1108. The second conductive layer 1110 may include polysilicon. A deposition process may be used to form the second conductive layer 1110 on the dielectric layer 1108, including over and within the plurality of trenches 1200. For example, a chemical vapor deposition (CVD) process may be used to form the second conductive layer 1110. A low-pressure chemical vapor deposition (LPCVD) process may be used to form the second conductive layer 1110. An etching process may be used to form various portions of the second conductive layer 1110. The second conductive layer 1110 may fill the plurality of trenches 1200. The second conductive layer 1110 may be doped. An example of a dopant includes boron. Thus, for example, the second conductive layer 1110 may include LPCVD polysilicon doped with boron. Stage 6 may also indicate when additional portion(s) of the first conductive layer 1106 may be formed. The additional portion(s) of the first conductive layer 1106 may be formed through opening(s) in the dielectric layer 1108. The additional portion(s) of the first conductive layer 1106 that are not covered by the dielectric layer 1108 may be used as pads to be coupled to solder interconnects. The additional portion(s) of the first conductive layer 1106 may be formed using a deposition process. The first conductive layer 1106 and / or the second conductive layer 1110 may include polysilicon.

[0122]

[0141] Stage 7, as shown in Figure 12D, illustrates the state after at least one cavity 1210 has been formed in the substrate 1102. Etching and / or laser processes (e.g., laser ablation) may be used to form the at least one cavity 1210 extending through the entire thickness of the substrate 1102.

[0123]

[0142] Stage 8 shows the state after interconnects 1109, 1192, and 1194 have been formed. A plating process may be used to form interconnects 1109, 1192, and 1194. Stage 8 shows an example chiplet 1100 that includes multiple trench capacitors 1105.

[0124] 1 is an exemplary flow diagram of a method for fabricating a chiplet with a trench capacitor;

[0143] In some implementations, fabricating a chiplet with trench capacitors involves several processes. FIG. 13 shows an example flow diagram of a method 1300 for providing or fabricating a chiplet with trench capacitors. In some implementations, the method 1300 of FIG. 13 can be used to provide or fabricate the chiplet 1100 of FIG. 11 . However, the method 1300 can be used to fabricate any chiplet with trench capacitors. The method 1300 of FIG. 13 will be used to describe fabricating the chiplet 1100.

[0125]

[0144] 13 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a chiplet with trench capacitors. In some implementations, the order of the processes may be changed or modified.

[0126]

[0145] The method includes (at 1305) providing a substrate (e.g., 1102). The substrate 1102 may be a chiplet substrate. The substrate 1102 may include silicon (Si). Step 1 of Figure 12A illustrates and describes one example of providing a chiplet substrate.

[0127]

[0146] The method forms (at 1310) a plurality of trenches (e.g., 1200) in a substrate (e.g., 1102). The plurality of trenches 1200 may include a plurality of cavities. The plurality of trenches 1200 may include a first trench, a second trench, a third trench, and a fourth trench. The trenches may have different shapes and / or different depths. An etching process may be used to form the plurality of trenches 1200. The plurality of trenches 1200 may be equally spaced apart or may have different spacings. Step 2 of FIG. 12A illustrates and describes one example of forming trenches.

[0128]

[0147] The method forms (at 1315) an oxide layer (e.g., 1104) over the plurality of trenches. The oxide layer 1104 may be formed over the surface of the substrate 1102. A deposition process may be used to form the oxide layer 1104 over the surface of the substrate 1102, including over and within the plurality of trenches 1200. A low-pressure chemical vapor deposition (LPCVD) process may be used to form the oxide layer 1104. The oxide layer 1104 may take the shape and / or contour of the plurality of trenches 1200. Step 3 of FIG. 12B illustrates and describes one example of forming an oxide layer.

[0129]

[0148] The method includes (at 1320) forming a first conductive layer (e.g., 1106) on the oxide layer (e.g., 1104). The first conductive layer 1106 may be formed on the oxide layer 1104. The first conductive layer 1106 may include polysilicon. A deposition process may be used to form the first conductive layer 1106 on the oxide layer 1104, including on and within the plurality of trenches 1200. For example, a low-pressure chemical vapor deposition (LPCVD) process may be used to form the first conductive layer 1106. The first conductive layer 1106 may take the shape and / or contour of the oxide layer 1104 and / or the plurality of trenches 1200. Forming the first conductive layer 1106 may include doping the first conductive layer 1106 with a dopant. Step 4 of FIG. 12B illustrates and describes one example of forming a first conductive layer.

[0130]

[0149] The method forms (at 1325) a dielectric layer (e.g., 1108) over the first conductive layer (e.g., 1106). A deposition process may be used to form the dielectric layer 1108 over the first conductive layer 1106, including over and within the plurality of trenches 1200. Step 5 of Figure 12C illustrates and describes one example of forming the dielectric layer.

[0131]

[0150] The method forms (at 1330) a second conductive layer (e.g., 1110) on the dielectric layer (e.g., 1108). The second conductive layer 1110 may include polysilicon. A deposition process may be used to form the second conductive layer 1110 on the dielectric layer 1108, including over and within the plurality of trenches 1200. A low-pressure chemical vapor deposition (LPCVD) process may be used to form the second conductive layer 1110. The second conductive layer 1110 may fill the plurality of trenches 1200. In some implementations, additional portion(s) of the first conductive layer 1106 may also be formed (at 1330). The additional portion(s) of the first conductive layer 1106 may be formed through opening(s) in the dielectric layer 1108. The additional portion(s) of the first conductive layer 1106 may be used as pad(s) configured to be coupled to solder interconnects. Step 6 of Figure 12D illustrates an example of forming a second conductive layer.

[0132]

[0151] The method forms (at 1335) at least one cavity (e.g., 1210) in the substrate 1102. An etching process and / or a laser process (e.g., laser ablation) may be used to form the at least one cavity 1210 extending through the entire thickness of the substrate 1102. Step 7 of Figure 12D illustrates and describes one example of forming at least one cavity in a substrate.

[0133]

[0152] The method forms at least one interconnect (e.g., 1109) within a cavity (e.g., 1210) of a substrate (e.g., 1102) (at 1340). In some implementations, a first interconnect (e.g., 1192) can be formed on a first surface of the substrate, and a second interconnect (e.g., 1194) can be formed on a second surface of the substrate. The first interconnect and the second interconnect can be coupled to an interconnect located within the cavity of the substrate. A plating process can be used to form the interconnects (e.g., 1109, 1192, 1194). Step 8 of FIG. 12D illustrates and describes an example of forming at least one interconnect within a cavity of a substrate.

[0134] Exemplary sequence for fabricating a package comprising an integrated device and a chiplet

[0153] FIGS. 14A - 14D show an exemplary sequence for providing or fabricating a package that includes an integrated device and a chiplet. In some implementations, the sequence of FIGS. 14A - 14D can be used to provide or fabricate package 500 of FIG. 5, or any of the packages described in this disclosure.

[0135]

[0154] Note that the sequence of FIGS. 14A - 14D can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure. The sequence of FIGS. 14A - 14D can be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0136]

[0155] Stage 1 illustrates the state after integrated device 104 and integrated device 404 are provided on carrier 1400, as shown in FIG. 14A . A pick-and-place process may be used to place the rear surfaces of integrated device 104 and integrated device 404 on carrier 1400. Carrier 1400 may include tape. Integrated device 104 may include multiple pillar interconnects 1407. Multiple pillar interconnects 1407 may include multiple inter-pillar interconnects. Integrated device 404 may include multiple pillar interconnects 1447. Multiple pillar interconnects 1447 may include multiple inter-pillar interconnects. Some of multiple pillar interconnects 1407 may represent multiple pillar interconnects 107b. Some of multiple pillar interconnects 1447 may represent multiple pillar interconnects 407b.

[0137]

[0156] Stage 2 shows the state after the encapsulation layer 108 is formed on the carrier 1400, the integrated device 104, and the integrated device 404. The encapsulation layer 108 is bonded to the carrier 1400, the integrated device 104, and the integrated device 404. The encapsulation layer 108 may encapsulate the plurality of pillar interconnects 1407 and the plurality of pillar interconnects 1447. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 108 and / or portions of the pillar interconnects 1407 of the integrated device 104 and / or portions of the pillar interconnects 1447 of the integrated device 404, thereby creating a flat surface.

[0138]

[0157] Stage 3 illustrates the state after a dielectric layer 281 is optionally formed on the surface of the encapsulation layer 108. Openings exposing the pillar interconnects of the integrated device 104 and the pillar interconnects of the integrated device 404 may be present in the dielectric layer 281. The dielectric layer 281 may include polyimide (PI). The dielectric layer 281 may help create a more planar surface. In some implementations, a seed layer 1401 may optionally be formed on the pillar interconnects. The seed layer 1401 may be located in the openings of the dielectric layer 281. The seed layer 1401 may help interconnects to be formed on the pillar interconnects.

[0139]

[0158] Stage 4 illustrates the state after (i) multiple pillar interconnects 1404 are formed and coupled to the pillar interconnects of integrated device 104, and (ii) multiple pillar interconnects 1414 are formed and coupled to the pillar interconnects of integrated device 404. A plating process may be used to form multiple pillar interconnects 1404 and / or 1414. Multiple pillar interconnects 1404 may represent multiple pillar interconnects 107a. Multiple pillar interconnects 1414 may represent multiple pillar interconnects 407a. In some implementations, multiple pillar interconnects 1404 may include seed layer 1401 and / or multiple pillar interconnects 1407. In some implementations, multiple pillar interconnects 1414 may include seed layer 1401 and / or multiple pillar interconnects 1447. 14A-14D do not depict dielectric layer 281 and seed layer 1401. However, it should be noted that dielectric layer 281 and seed layer 1401 may be positioned within the package in a manner consistent with that described in this disclosure.

[0140]

[0159] Stage 5 shows the state after chiplet 106 has been bonded to pillar interconnects 1407 of integrated device 104 via solder interconnects 140. Stage 5 also shows the state after chiplet 406 has been bonded to pillar interconnects 1447 of integrated device 404 via solder interconnects 440. A solder reflow process may be used to bond chiplets 106 and 406 to their respective pillar interconnects. Stage 5 also shows the state after bridge 505 has been disposed on encapsulation layer 108. A rear surface of bridge 505 may be disposed on and / or bonded to encapsulation layer 108. If dielectric layer 281 is present, then the rear surface of bridge 505 may be disposed on and / or bonded to dielectric layer 281.

[0141]

[0160] Stage 6 illustrates the state after encapsulation layer 1408 is formed over encapsulation layer 108, dielectric layer 281, chiplets 106, chiplets 406, multiple pillar interconnects 1404, and / or multiple pillar interconnects 1414. The encapsulation layer 1408 is bonded to encapsulation layer 108, dielectric layer 281, chiplets 106, chiplets 406, multiple pillar interconnects 1404, and / or multiple pillar interconnects 1414. The encapsulation layer 1408 may include a mold, a resin, and / or an epoxy. The encapsulation layer 1408 may be a means for encapsulation. The encapsulation layer 1408 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, an encapsulation layer 1408 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 1408 and / or portions of the pillar interconnects 1404 and / or portions of the pillar interconnects 1414, thereby creating a flat surface.

[0142]

[0161] Stage 7, as shown in FIG. 14B, depicts the state after dielectric layer 1420 is formed on encapsulation layer 108. Note that encapsulation layer 108 can refer to encapsulation layer 108 and encapsulation layer 1408. In some implementations, encapsulation layer 108 shown in Stage 7 can include dielectric layer 281 as described above in FIG. 14A. A lamination process can be used to form dielectric layer 1420.

[0143]

[0162] Stage 8 shows the state after a plurality of cavities 1421 have been formed in the dielectric layer 1420. The plurality of cavities 1421 may be openings in the dielectric layer 1420 that expose the interconnects. An exposure and development process may be used to form the plurality of cavities 1421.

[0144]

[0163] Stage 9 shows the state after a plurality of metallization interconnects 1422 have been formed in and on the dielectric layer 1420. A plating process may be used to form the plurality of metallization interconnects 1422.

[0145]

[0164] Stage 10 shows the state after dielectric layer 1430 has been formed on dielectric layer 1420. To form dielectric layer 1430, a lamination process may be used.

[0146]

[0165] Stage 11, as shown in Figure 14C, shows the state after cavities 1431 have been formed in dielectric layer 1430. The cavities 1431 may be openings in dielectric layer 1430 that expose the interconnects. An exposure and development process may be used to form the cavities 1431.

[0147]

[0166] Stage 12 shows the state after a plurality of metallization interconnects 1432 have been formed in and on the dielectric layer 1430. The plurality of metallization interconnects 1432 may be bonded to the plurality of metallization interconnects 1422. A plating process may be used to form the plurality of metallization interconnects 1432. The dielectric layer 1420, the dielectric layer 1430, the plurality of metallization interconnects 1422, and the plurality of metallization interconnects 1432 may form the metallization portion 102. The plurality of metallization interconnects 1422 and the plurality of metallization interconnects 1432 may be represented by the plurality of metallization interconnects 122. The dielectric layer 1420 and the dielectric layer 1430 may be represented by at least one dielectric layer 120.

[0148]

[0167] Stage 13 shows the state after the plurality of solder interconnects 196 have been bonded to the metallization portion 102. The plurality of solder interconnects 196 may be bonded to the plurality of metallization interconnects 122 of the metallization portion 102. A solder reflow process may be used to bond the plurality of solder interconnects 196 to the metallization portion 102.

[0149]

[0168] Stage 14 shows the state after the carrier 1400 has been debonded from the encapsulation layer 108, leaving the package 500 including the integrated device 104, the integrated device 404, the chiplet 106, the chiplet 406, the bridge 505, the metallization portion 102, and the encapsulation layer 108.

[0150]

[0169] Stage 15, as shown in Figure 14D, depicts the state after package 500 has been coupled to substrate 109 via a plurality of solder interconnects 196. A solder reflow process may be used to couple package 500 to substrate 109.

[0151]

[0170] Stage 16 shows the state after underfill 105 has been formed between package 500 and substrate 109. Underfill 105 may be bonded to substrate 109 and to the sides of package 500.

[0152]

[0171] 14A-14D illustrate an example method of fabricating a package. The method may provide a first integrated device and a first plurality of inter-pillar interconnects. The method may form an encapsulation layer that encapsulates the first integrated device and the first plurality of inter-pillar interconnects. The method may form a first plurality of pillar interconnects configured to be coupled to the first integrated device. The method may couple a first chiplet to the first integrated device via the first plurality of inter-pillar interconnects. The method may form a first metallization portion such that the first metallization portion is coupled to the first chiplet and the first encapsulation layer. In some implementations, the method may form a second encapsulation layer that encapsulates the first chiplet. The second encapsulation layer and the encapsulation layer may be part of the same encapsulation layer. The method may provide a second integrated device and a second plurality of inter-pillar interconnects, and forming the encapsulation layer includes forming an encapsulation layer that further encapsulates the second integrated device and the second plurality of inter-pillar interconnects. The method may couple the second chiplet to the second integrated device via a second plurality of inter-pillar interconnects. The method may provide a bridge configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0153] Exemplary Sequence for Fabricating a Package with Integrated Devices and Chiplets

[0172] 15A-15C illustrate an example sequence for providing or fabricating a package including an integrated device and a chiplet. In some implementations, the sequence of FIG. 15A-15C can be used to provide or fabricate package 800 of FIG. 8 or any of the packages described herein.

[0154]

[0173] Note that the sequences of FIGS. 15A to 15C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure. The sequences of FIGS. 15A to 15C can be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0155]

[0174] Step 1 shows the state after the integrated device 104 and the integrated device 404 are provided on the carrier 1500, as shown in FIG. 15A. A pick-and-place process can be used to place the back surfaces of the integrated device 104 and the integrated device 404 on the carrier 1500. The carrier 1500 can include a tape.

[0156]

[0175] Step 2 shows the state after the encapsulation layer 108 is formed on the carrier 1500, the integrated device 104, and the integrated device 404. The encapsulation layer 108 is bonded to the carrier 1500, the integrated device 104, and the integrated device 404. The encapsulation layer 108 can include a mold, a resin, and / or an epoxy. The encapsulation layer 108 can be a means for encapsulation. The encapsulation layer 108 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove a portion of the encapsulation layer 108, thereby creating a flat surface.

[0157]

[0176] Stage 3 shows the state after metallization portion 102 has been formed. Metallization portion 102 may be formed over integrated device 104, integrated device 404, and encapsulation layer 108. Metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. Metallization portion 102 may be formed in a manner similar to that described for metallization portion 102 shown in Figures 14A-14D.

[0158]

[0177] Stage 4, as shown in Figure 15B, depicts the state after multiple pillar interconnects 1580 have been formed. A plating process may be used to form the multiple pillar interconnects 1580. The multiple pillar interconnects may be coupled to the multiple metallization interconnects 122.

[0159]

[0178] Stage 5 shows the state after chiplet 106 has been bonded to the plurality of metallization interconnects 122 via the plurality of solder interconnects 740. Stage 5 also shows the state after chiplet 406 has been bonded to the plurality of metallization interconnects 122 via the plurality of solder interconnects 740. A solder reflow process may be used to bond chiplet 106 and chiplet 406 to the plurality of metallization interconnects 122. Stage 5 also shows the state after bridge 505 has been bonded to the plurality of metallization interconnects 122 via the plurality of solder interconnects 850. The front surface of bridge 505 may face metallization portion 102.

[0160]

[0179] Stage 6 illustrates the state after an encapsulation layer 708 is formed over the encapsulation layer 108, the chiplets 106, the chiplets 406, the bridge 505, and the plurality of pillar interconnects 1580. The encapsulation layer 708 is bonded to the encapsulation layer 108, the chiplets 106, the chiplets 406, the bridge 505, and the plurality of pillar interconnects 1580. The plurality of pillar interconnects 1580 may be represented as a plurality of through-mold vias 780 in the encapsulation layer 708. The encapsulation layer 708 may include a mold, a resin, and / or an epoxy. The encapsulation layer 708 may be a means for encapsulation. The encapsulation layer 708 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 708 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 708 and / or portions of the through-mold vias 780, thereby creating a flat surface.

[0161]

[0180] Stage 7, as shown in Figure 15C, illustrates the state after metallization portion 702 has been formed. Metallization portion 702 may be formed over encapsulation layer 708, chiplet 106, and chiplet 406. Metallization portion 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 722. Metallization portion 702 may be formed in a manner similar to that described for metallization portion 102 shown in Figures 14A-14D.

[0162]

[0181] Stage 8 illustrates the state after the plurality of solder interconnects 196 have been bonded to the metallization portion 702. The plurality of solder interconnects 196 may be bonded to the plurality of metallization interconnects 722 of the metallization portion 702. A solder reflow process may be used to bond the plurality of solder interconnects 196 to the metallization portion 702. Stage 8 also illustrates the state after the carrier 1500 has been debonded from the encapsulation layer 108, leaving a package 800 that includes the integrated device 104, the integrated device 404, the chiplet 106, the chiplet 406, the bridge 505, the metallization portion 102, the metallization portion 702, the encapsulation layer 108, and the encapsulation layer 708.

[0163]

[0182] 15A-15C illustrate an example method of fabricating a package. The method may provide a first integrated device and a second integrated device. The method may form an encapsulation layer encapsulating the first integrated device and the second integrated device. The method may form a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device. The method may form a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the first metallization portion. The method may bond a first chiplet and a second chiplet to the first metallization portion. The method may form another encapsulation layer encapsulating the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method may form a second metallization portion such that the second metallization portion is coupled to the first chiplet and the second chiplet. In some implementations, coupling the first chiplet and the second chiplet to the first metallization portion includes coupling the first chiplet to the first metallization portion such that a front surface of the first chiplet faces the first metallization portion, and coupling the second chiplet to the first metallization portion such that a front surface of the second chiplet faces the first metallization portion. The first chiplet may be coupled to the first metallization portion via a first plurality of solder interconnects. The second chiplet may be coupled to the first metallization portion via a second plurality of solder interconnects. The method may couple a bridge to the first metallization portion such that a front surface of the bridge faces the first metallization portion. The bridge may be coupled to the first metallization portion via a plurality of solder interconnects.

[0164]

[0183] Any of the metallization portions can be the first metallization portion and / or any of the metallization portions can be the second metallization portion. For example, in some implementations, the metallization portion 102 can be regarded as the first metallization portion and the metallization portion 702 can be regarded as the second metallization portion. In some implementations, the metallization portion 702 can be regarded as the first metallization portion and the metallization portion 102 can be regarded as the second metallization portion.

[0165] Exemplary sequence for fabricating a package comprising an integrated device and a chiplet

[0184] FIGS. 16A-16C illustrate an exemplary sequence for providing or fabricating a package that includes an integrated device and a chiplet. In some implementations, the sequence of FIGS. 16A-16C can be used to provide or fabricate the package 1000 of FIG. 10 or any of the packages described in this disclosure.

[0166]

[0185] Note that the sequence of FIGS. 16A-16C can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure. The sequence of FIGS. 16A-16C can be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0167]

[0186] Stage 1, as shown in Figure 16A, illustrates the state after metallization portion 702 has been formed on carrier 1600. Metallization portion 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 722. Metallization portion 702 may be formed in a manner similar to that described for metallization portion 102 shown in Figures 14A-14D.

[0168]

[0187] Stage 2 shows the state after multiple pillar interconnects 1680 have been formed. A plating process may be used to form the multiple pillar interconnects 1680. The multiple pillar interconnects may be coupled to multiple metallization interconnects 722.

[0169]

[0188] Stage 3 shows the state after chiplet 106 has been bonded to the plurality of metallization interconnects 722 via a plurality of solder interconnects 1060. Stage 3 also shows the state after chiplet 406 has been bonded to the plurality of metallization interconnects 722 via a plurality of solder interconnects 1040. A solder reflow process may be used to bond chiplet 106 and chiplet 406 to the plurality of metallization interconnects 722.

[0170]

[0189] 16B, after bridge 505 has been bonded to multiple metallization interconnects 722 via adhesive 1005. The rear surface of bridge 505 may be bonded to metallization portion 702 via adhesive 1005. For example, the rear surface of the die substrate of bridge 505 may be bonded to metallization portion 702 via adhesive 1005.

[0171]

[0190] Stage 5 illustrates the state after an encapsulation layer 708 is formed over the metallization portion 702, the chiplets 106, the chiplets 406, the bridge 505, and the pillar interconnects 1680. The encapsulation layer 708 is bonded to the metallization portion 702, the chiplets 106, the chiplets 406, the bridge 505, and the pillar interconnects 1680. The pillar interconnects 1680 may be represented as through-mold vias 780 in the encapsulation layer 708. The encapsulation layer 708 may include a mold, a resin, and / or an epoxy. The encapsulation layer 708 may be a means for encapsulation. The encapsulation layer 708 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 708 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 708 and / or portions of the through-mold vias 780, thereby creating a flat surface.

[0172]

[0191] Stage 6 shows the state after metallization portion 102 has been formed. Metallization portion 102 may be formed over encapsulation layer 708, bridge 505, chiplet 106, and chiplet 406. Metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. Metallization portion 102 may be formed in a manner similar to that described for metallization portion 102 shown in Figures 14A-14D.

[0173]

[0192] 16C , after the integrated device 104 is bonded to the metallization portion 102 via a plurality of solder interconnects 1010. The integrated device 104 is bonded to a plurality of metallization interconnects 122 via a plurality of solder interconnects 1010. Stage 7 also shows the state after the integrated device 404 is bonded to the metallization portion 102 via a plurality of solder interconnects 1030. The integrated device 404 is bonded to a plurality of metallization interconnects 122 via a plurality of solder interconnects 1030. A solder reflow process may be used to bond the integrated device 104 and the integrated device 404 to the metallization portion 102.

[0174]

[0193] Stage 8 illustrates the state after the encapsulation layer 108 is formed over the integrated device 104, the integrated device 404, and the metallization portion 102. The encapsulation layer 108 is bonded to the metallization portion 102, the integrated device 104, and the integrated device 404. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove a portion of the encapsulation layer 108.

[0175]

[0194] Stage 9 shows the state after carrier 1600 has been debonded from metallization portion 702, leaving package 1000 including integrated device 104, integrated device 404, chiplet 106, chiplet 406, bridge 505, metallization portion 702, metallization portion 102, encapsulation layer 108, and encapsulation layer 708.

[0176]

[0195] Stage 9 also illustrates the state after the plurality of solder interconnects 196 have been bonded to the metallization portion 702. The plurality of solder interconnects 196 may be bonded to the plurality of metallization interconnects 722 of the metallization portion 702. A solder reflow process may be used to bond the plurality of solder interconnects 196 to the metallization portion 702.

[0177]

[0196] 16A-16C illustrate an example method of fabricating a package. The method may form a second metallization portion. The method may form a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the second metallization portion. The method may bond a first chiplet and a second chiplet to the second metallization portion. The method may form an encapsulation layer that encapsulates the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method may form the first metallization portion such that the first metallization portion is coupled to the first chiplet and the second chiplet. The method may bond a first integrated device and a second integrated device to the first metallization portion. In some implementations, coupling the first chiplet and the second chiplet to the second metallization portion includes coupling the first chiplet to the second metallization portion such that a rear surface of the first chiplet faces the second metallization portion, and coupling the second chiplet to the second metallization portion such that a rear surface of the second chiplet faces the second metallization portion. The first chiplet may be coupled to the second metallization portion via a first plurality of solder interconnects. The second chiplet is coupled to the second metallization portion via a second plurality of solder interconnects. The method may couple the bridge to the second metallization portion such that a rear surface of the bridge faces the second metallization portion. The method may form an encapsulation layer that encapsulates the first integrated device and the second integrated device.

[0178]

[0197] Any of the metallization portions can be the first metallization portion and / or any of the metallization portions can be the second metallization portion. For example, in some implementations, the metallization portion 102 can be regarded as the first metallization portion, and the metallization portion 702 can be regarded as the second metallization portion. In some implementations, the metallization portion 702 can be regarded as the first metallization portion, and the metallization portion 102 can be regarded as the second metallization portion.

[0179] Exemplary sequence for fabricating a substrate

[0198] In some implementations, fabricating a substrate includes several processes. FIGS. 17A - 17B show an exemplary sequence for providing or fabricating a substrate. In some implementations, the sequence of FIGS. 17A - 17B can be used to provide or fabricate the substrate 109. However, the processes of FIGS. 17A - 17B can be used to fabricate any of the substrates described in the present disclosure.

[0180]

[0199] Note that the sequence of FIGS. 17A - 17B can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0181]

[0200] Stage 1, as shown in FIG. 17A , depicts the state after carrier 1700 is provided. Seed layer 1701 and interconnects 1702 may be located on carrier 1700. Interconnects 1702 may be located on seed layer 1701. Plating and etching processes may be used to form interconnects 1702. In some implementations, carrier 1700 may be provided with seed layer 1701 and a metal layer that is patterned to form interconnects 1702. Interconnects 1702 may represent at least some of the interconnects from multiple interconnects 192.

[0182]

[0201] Stage 2 shows the state after dielectric layer 1720 is formed over carrier 1700, seed layer 1701, and interconnects 1702. A deposition process and / or lamination process may be used to form dielectric layer 1720. Dielectric layer 1720 may include prepreg and / or polyimide. Dielectric layer 1720 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0183]

[0202] Stage 3 shows the state after multiple cavities 1710 have been formed in the dielectric layer 1720. The multiple cavities 1710 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0184]

[0203] Stage 4 shows the state after interconnects 1712 have been formed in and on dielectric layer 1720, including in and on the plurality of cavities 1710. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0185]

[0204] Stage 5 shows the state after dielectric layer 1722 is formed over dielectric layer 1720 and interconnects 1712. A deposition process and / or lamination process may be used to form dielectric layer 1722. Dielectric layer 1722 may include prepreg and / or polyimide. Dielectric layer 1722 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0186]

[0205] Stage 6, as shown in Figure 17B, illustrates the state after multiple cavities 1730 have been formed in dielectric layer 1722. Multiple cavities 1730 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0187]

[0206] Stage 7 shows the state after interconnects 1714 have been formed in and on dielectric layer 1722, including in and on a plurality of cavities 1730. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0188]

[0207] Stage 8 shows the state after carrier 1700 has been debonded (e.g., detached, removed, ground) from at least one dielectric layer 190 and seed layer 1701, and portions of seed layer 1701 have been removed (e.g., etched away) to leave at least one dielectric layer 190 and metallization portion 102 including multiple interconnects 192. At least one dielectric layer 190 may represent dielectric layer 1720 and / or dielectric layer 1722. Multiple interconnects 192 may represent interconnects 1702, 1712, and / or 1714.

[0189]

[0208] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0190] 1 is an exemplary flow diagram of a method for fabricating a substrate;

[0209] In some implementations, fabricating a substrate includes several processes. Figure 18 shows an example flow diagram of a method 1800 for providing or fabricating a substrate. In some implementations, the method 1800 of Figure 18 can be used to provide or fabricate a substrate(s) of the present disclosure. For example, the method 1800 of Figure 18 can be used to fabricate the metallization portion 102.

[0191]

[0210] 18 may combine one or more processes to simplify and / or clarify the method of providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0192]

[0211] The method provides (at 1805) a carrier (e.g., 1700). Different implementations may use different materials for the carrier 1700. The carrier 1700 may include a seed layer (e.g., 1701). The seed layer 1701 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or carrier tape. Step 1 of FIG. 17A illustrates and describes one example of a carrier with a provided seed layer.

[0193]

[0212] The method forms and patterns (at 1810) interconnects on the carrier 1700 and seed layer 1701. A metal layer can be patterned to form the interconnects. A plating process can be used to form the metal layer and interconnects. In some implementations, the carrier and seed layer can include a metal layer. A metal layer overlies the seed layer, and the metal layer can be patterned to form the interconnects (e.g., 192). Step 1 of FIG. 17A illustrates and describes one example of forming and patterning interconnects on a seed layer and carrier.

[0194]

[0213] The method forms / provides (at 1815) a dielectric layer 1720 over the seed layer 1701, the carrier 1700, and the interconnects 1702. A deposition process and / or a lamination process may be used to form the dielectric layer 1720. The dielectric layer 1720 may include prepreg and / or polyimide. The dielectric layer 1720 may include a photoimageable dielectric. Forming the dielectric layer 1720 may also include forming a plurality of cavities (e.g., 1710) in the dielectric layer 1720. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 17A illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0195]

[0214] The method forms (at 1820) interconnects in and on the dielectric layer. For example, interconnects 1712 may be formed in and on dielectric layer 1720. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 17A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0196]

[0215] The method forms / provides (at 1825) a dielectric layer 1722 over the dielectric layer 1720 and the interconnects 1712. A deposition process and / or a lamination process may be used to form the dielectric layer 1722. The dielectric layer 1722 may include a prepreg and / or a polyimide. The dielectric layer 1722 may include a photoimageable dielectric. Forming the dielectric layer 1722 may also include forming a plurality of cavities (e.g., 1730) in the dielectric layer 1722. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 5-6 of Figures 17A-17B illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0197]

[0216] The method forms (at 1830) interconnects in and on the dielectric layer. For example, interconnect 1714 can be formed in and on dielectric layer 1722. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Step 7 of FIG. 17B illustrates and describes one example of forming interconnects in and on the dielectric layer. The method can form additional dielectric layer(s) and additional interconnects, as described at 1825 and 1830.

[0198]

[0217] In some implementations, once all of the dielectric layer(s) and additional interconnects have been formed, the method may debond (at 1835) the carrier (e.g., 1700) from the seed layer (e.g., 1701). The carrier 1700 may be removed and / or ground away. The method may also remove (at 1835) portions of the seed layer (e.g., 1701). An etching process may be used to remove portions of the seed layer 1701. Step 8 of FIG. 17B illustrates and describes one example of carrier debonding and seed layer removal.

[0199]

[0218] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0200] Exemplary Electronic Devices

[0219] FIG. 19 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1902, a laptop computer device 1904, a fixed location terminal device 1906, a wearable device 1908, or an autonomous vehicle 1910 may include a device 1900 as described herein. The device 1900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1902, 1904, 1906, and 1908 and the vehicle 1910 shown in FIG. 19 are merely exemplary. Other electronic devices may also be equipped with device 1900, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0201]

[0220] One or more of the components, processes, features, and / or functions shown in Figures 1-11, 12A-12D, 13, 14A-14D, 15A-15C, 16A-16C, 17A-17B, and / or 18-19 may be rearranged and / or combined into a single component, process, feature, or function, or may be incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. Also, it should be noted that Figures 1-11, 12A-12D, 13, 14A-14D, 15A-15C, 16A-16C, 17A-17B, and / or 18-19 and their corresponding descriptions in this disclosure are not limited to die and / or ICs. 1-11, 12A-12D, 13, 14A-14D, 15A-15C, 16A-16C, 17A-17B, and / or 18-19, and their corresponding descriptions, may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0202]

[0221] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the location, position, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0203]

[0222] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspect” does not require all aspects of the present disclosure to include the described feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other even though they are not in direct physical contact with each other. An object coupled to another object may also be coupled to at least a portion of the other object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate current between them. Use of the terms “first,” “second,” “third,” and “fourth” (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The term “encapsulating” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A top component may be located above a bottom component. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component "over" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being located above another component, the term "over" as used herein can be used to refer to a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but not in direct contact with the second component, (2) that the first component is present on (e.g., on the surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component located "in" a second component can be partially located within the second component or completely located within the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within 10 percent of "value X." For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0204]

[0223] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0205]

[0224] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0206]

[0225] In the following, further examples are described to facilitate understanding of the present invention.

[0207]

[0226] Aspect 1: A package comprising: a first metallization portion; a first integrated device coupled to the first metallization portion via a first plurality of pillar interconnects; and a first chiplet located between the first integrated device and the first metallization portion, the first chiplet being coupled to the first integrated device via a first plurality of inter-pillar interconnects.

[0208]

[0227] Aspect 2: The package of aspect 1, wherein the first chiplet includes a trench capacitor.

[0209]

[0228] Aspect 3: The package of Aspect 2, wherein the first chiplet includes a chiplet substrate, a plurality of trench capacitors, and at least one chiplet substrate through-interconnect.

[0210]

[0229] Aspect 4: The package of aspect 1, wherein the first chiplet includes a memory, a power management integrated circuit, or a voltage regulator.

[0211]

[0230] Embodiment 5: The package of embodiments 1-4, further comprising an encapsulation layer coupled to the first metallization portion and the first integrated device.

[0212]

[0231] Aspect 6: The package of aspect 5, wherein the encapsulation layer comprises a first encapsulation layer bonded to the first integrated device and a second encapsulation layer bonded to the first metallization portion.

[0213]

[0232] Aspect 7: The package of Aspect 6, further comprising a dielectric layer located between the first sealing layer and the second sealing layer, the dielectric layer being bonded to the first sealing layer and the second sealing layer.

[0214]

[0233] Aspect 8: The package of aspects 1 to 7, further comprising: a second integrated device coupled to the first metallization portion via a second plurality of pillar interconnects; and a second chiplet located between the second integrated device and the first metallization portion, the second chiplet being coupled to the second integrated device via a second plurality of inter-pillar interconnects.

[0215]

[0234] Aspect 9: The package of aspect 8, further comprising a bridge coupled to the first metallization portion, the bridge configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0216]

[0235] Aspect 10: A package as described in aspect 8 or 9, wherein the first chiplet is laterally surrounded by a first plurality of pillar interconnects and the second chiplet is laterally surrounded by a second plurality of pillar interconnects.

[0217]

[0236] Embodiment 11: A package described in embodiments 8 to 10, wherein the first integrated device includes a first plurality of die interconnects including a first minimum spacing, and the second integrated device includes a second plurality of die interconnects including a second minimum spacing.

[0218]

[0237] Example 12: The package of example 11, wherein the first chiplet includes a plurality of interconnects that include a third minimum spacing.

[0219]

[0238] Aspect 13: A package described in aspects 1 to 10, wherein the first integrated device includes a plurality of die interconnects including a first minimum spacing, and the first chiplet includes a plurality of interconnects including a second minimum spacing.

[0220]

[0239] Embodiment 14: The package of embodiment 13, wherein the first minimum spacing is smaller than the second minimum spacing.

[0221]

[0240] Aspect 15: The package of aspects 1 to 10, wherein the first integrated device includes a first plurality of transistors including a first minimum spacing, and the first chiplet includes a second plurality of transistors including a second minimum spacing.

[0222]

[0241] Aspect 16: A device comprising a package, the package comprising: a first metallization portion, a first integrated device coupled to the first metallization portion via a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion, the first chiplet coupled to the first integrated device via the first plurality of inter-pillar interconnects.

[0223]

[0242] Embodiment 17: The device of embodiment 16, wherein the first chiplet includes a trench capacitor.

[0224]

[0243] Example 18: The device of example 17, wherein the first chiplet includes a chiplet substrate, a plurality of trench capacitors, and at least one chiplet substrate through-interconnect.

[0225]

[0244] Aspect 19: The device of aspect 16, wherein the first chiplet includes a memory, a power management integrated circuit, or a voltage regulator.

[0226]

[0245] Aspect 20: The device described in aspects 16 to 19, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0227]

[0246] Aspect 21: A method of making a package. The method provides a first integrated device and a first plurality of inter-pillar interconnects. The method forms an encapsulation layer that encapsulates the first integrated device and the first plurality of inter-pillar interconnects. The method forms the first plurality of pillar interconnects configured to be coupled to the first integrated device. The method couples a first chiplet to the first integrated device via the first plurality of inter-pillar interconnects. The method forms a first metallization portion such that the first metallization portion is coupled to the first chiplet and the first encapsulation layer.

[0228]

[0247] Example 22: The method of example 21, wherein the first chiplet includes a trench capacitor.

[0229]

[0248] Example 23: The method of example 22, wherein the first chiplet includes a chiplet substrate, a plurality of trench capacitors, and at least one chiplet substrate through-interconnect.

[0230]

[0249] Aspect 24: The method of aspect 21, wherein the first chiplet includes a memory, a power management integrated circuit, or a voltage regulator.

[0231]

[0250] Embodiment 25: The method of any one of embodiments 21 to 24, further forming a second encapsulation layer that encapsulates the first chiplet.

[0232]

[0251] Embodiment 26: The method of embodiment 25, wherein the second sealing layer and the sealing layer are part of the same sealing layer.

[0233]

[0252] Embodiment 27: The method of any of embodiments 21 to 26, further including providing a second integrated device and a second plurality of inter-pillar interconnects, wherein forming an encapsulation layer includes forming an encapsulation layer that further encapsulates the second integrated device and the second plurality of inter-pillar interconnects, and coupling the second chiplet to the second integrated device via the second plurality of inter-pillar interconnects.

[0234]

[0253] Example 28: The method of example 27, further comprising providing a bridge configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0235]

[0254] Embodiment 29: The method of embodiments 21 to 28, wherein the first integrated device includes a plurality of die interconnects including a first minimum spacing, and the first chiplet includes a plurality of interconnects including a second minimum spacing.

[0236]

[0255] Embodiment 30: The method of embodiments 21 to 29, wherein the first integrated device includes a first plurality of transistors including a first minimum spacing, and the first chiplet includes a second plurality of transistors including a second minimum spacing.

[0237]

[0256] Aspect 31: A package comprising: a first metallization portion; a first integrated device coupled to the first metallization portion; a second integrated device coupled to the first metallization portion; a second metallization portion coupled to the first metallization portion via a first plurality of pillar interconnects; a first chiplet located between the first metallization portion and the second metallization portion, the first chiplet configured to be electrically coupled to the first integrated device via the first metallization portion; and a second chiplet located between the first metallization portion and the second metallization portion, the second chiplet configured to be electrically coupled to the second integrated device via the first metallization portion.

[0238]

[0257] Aspect 32: The package of Aspect 31, further comprising a bridge located between the first metallization portion and the second metallization portion.

[0239]

[0258] Embodiment 33: The package of embodiment 31 or 32, further comprising a first encapsulation layer coupled to the first metallization portion, the first integrated device, and the second integrated device.

[0240]

[0259] Aspect 34: The package described in aspect 33, further comprising a second encapsulation layer coupled to the first metallization portion, the second metallization portion, the first chiplet, and the second chiplet, wherein the second encapsulation layer is positioned between the first metallization portion and the second metallization portion.

[0241]

[0260] Aspect 35: A package described in aspects 31 to 34, wherein the first chiplet includes a first trench capacitor, a first memory, a first power management integrated circuit, or a first voltage regulator, and the second chiplet includes a second trench capacitor, a second memory, a second power management integrated circuit, or a second voltage regulator.

[0242]

[0261] Aspect 36: A package described in aspects 31 to 35, wherein a first integrated device is coupled to a first metallization portion via a first plurality of solder interconnects, and a second integrated device is coupled to the first metallization portion via a second plurality of solder interconnects.

[0243]

[0262] Aspect 37: A package described in aspects 31 to 36, wherein a first chiplet is coupled to a first metallization portion via a first plurality of solder interconnects, and a second chiplet is coupled to the first metallization portion via a second plurality of solder interconnects.

[0244]

[0263] Aspect 38: The package described in aspect 37, further comprising a bridge located between the first metallization portion and the second metallization portion, the bridge being coupled to the first metallization portion via a third plurality of solder interconnects.

[0245]

[0264] Aspect 39: A package as described in aspect 38, wherein a front surface of the bridge faces the first metallization portion, a front surface of the first chiplet faces the first metallization portion, and a front surface of the second chiplet faces the first metallization portion.

[0246]

[0265] Aspect 40: A package as described in aspects 31 to 36, wherein the first chiplet is coupled to the second metallization portion via a first plurality of solder interconnects, and the second chiplet is coupled to the second metallization portion via a second plurality of solder interconnects.

[0247]

[0266] Aspect 41: The package described in aspect 40, further comprising a bridge located between the first metallization portion and the second metallization portion, the bridge being coupled to the first metallization portion via a third plurality of solder interconnects.

[0248]

[0267] Aspect 42: A package as described in aspect 41, wherein a front surface of the bridge faces the first metallization portion, a front surface of the first chiplet faces the first metallization portion, and a front surface of the second chiplet faces the first metallization portion.

[0249]

[0268] Embodiment 43: A package described in embodiments 31 to 42, wherein the first integrated device includes a first plurality of die interconnects including a first minimum spacing, and the second integrated device includes a second plurality of die interconnects including a second minimum spacing.

[0250]

[0269] Embodiment 44: The package of any one of embodiments 31 to 43, wherein the first chiplet includes a plurality of interconnects that include a third minimum spacing.

[0251]

[0270] Aspect 45: A package described in aspects 31 to 42, wherein the first integrated device includes a plurality of die interconnects including a first minimum spacing, and the first chiplet includes a plurality of interconnects including a second minimum spacing.

[0252]

[0271] Aspect 46: A package described in aspects 31 to 45, wherein the first integrated device includes a first plurality of transistors including a first minimum spacing, and the first chiplet includes a second plurality of transistors including a second minimum spacing.

[0253]

[0272] Aspect 47: A device comprising a package, the package comprising: a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion via a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, the first chiplet configured to be electrically coupled to the first integrated device via the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, the second chiplet configured to be electrically coupled to the second integrated device via the first metallization portion.

[0254]

[0273] Aspect 48: The device of aspect 47, wherein the first chiplet includes a first trench capacitor, a first memory, a first power management integrated circuit, or a first voltage regulator, and the second chiplet includes a second trench capacitor, a second memory, a second power management integrated circuit, or a second voltage regulator.

[0255]

[0274] Aspect 49: A device described in aspect 47 or 48, wherein the first integrated device includes a plurality of die interconnects including a first minimum spacing, and the first chiplet includes a plurality of interconnects including a second minimum spacing.

[0256]

[0275] Aspect 50: The device described in aspects 47 to 49, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0257]

[0276] Aspect 51: A method of making a package. The method provides a first integrated device and a second integrated device. The method forms an encapsulation layer that encapsulates the first integrated device and the second integrated device. The method forms a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device. The method forms a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the first metallization portion. The method bonds a first chiplet and a second chiplet to the first metallization portion. The method forms another encapsulation layer that encapsulates the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method forms a second metallization portion such that the second metallization portion is coupled to the first chiplet and the second chiplet.

[0258]

[0277] Aspect 52: The method of aspect 51, wherein bonding the first chiplet and the second chiplet to the first metallization portion includes bonding the first chiplet to the first metallization portion so that a front surface of the first chiplet faces the first metallization portion, and bonding the second chiplet to the first metallization portion so that a front surface of the second chiplet faces the first metallization portion.

[0259]

[0278] Aspect 53: The method of aspect 52, wherein a first chiplet is coupled to a first metallization portion via a first plurality of solder interconnects, and a second chiplet is coupled to the first metallization portion via a second plurality of solder interconnects.

[0260]

[0279] Embodiment 54: The method of any one of embodiments 51-53, further comprising bonding the bridge to the first metallization portion such that a front surface of the bridge faces the first metallization portion.

[0261]

[0280] Embodiment 55: The method of embodiment 54, wherein the bridge is coupled to the first metallization portion via a plurality of solder interconnects.

[0262]

[0281] Aspect 56: A method of making a package. The method forms a second metallization portion. The method forms a first plurality of pillar interconnects and a second plurality of pillar interconnects such that the first plurality of pillar interconnects and the second plurality of pillar interconnects are coupled to the second metallization portion. The method bonds a first chiplet and a second chiplet to the second metallization portion. The method forms an encapsulation layer that encapsulates the first plurality of pillar interconnects, the second plurality of pillar interconnects, the first chiplet, and the second chiplet. The method forms the first metallization portion such that the first metallization portion is coupled to the first chiplet and the second chiplet. The method bonds a first integrated device and a second integrated device to the first metallization portion.

[0263]

[0282] Aspect 57: The method of aspect 56, wherein bonding the first chiplet and the second chiplet to the second metallization portion includes bonding the first chiplet to the second metallization portion so that a rear surface of the first chiplet faces the second metallization portion, and bonding the second chiplet to the second metallization portion so that a rear surface of the second chiplet faces the second metallization portion.

[0264]

[0283] Aspect 58: The method of aspect 57, wherein the first chiplet is coupled to the second metallization portion via a first plurality of solder interconnects, and the second chiplet is coupled to the second metallization portion via a second plurality of solder interconnects.

[0265]

[0284] Aspect 59: The method of aspect 56 or 57, further comprising bonding the bridge to the second metallization portion such that a rear surface of the bridge faces the second metallization portion.

[0266]

[0285] Embodiment 60: The method of any one of embodiments 56 to 59, further comprising forming another encapsulating layer that encapsulates the first integrated device and the second integrated device.

[0267]

[0286] Various features of the present disclosure described herein can be implemented in a variety of systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. It is a package, The first metallization part, A first integrated device directly coupled to the first metallization portion via a first plurality of pillar interconnections, A package comprising a first chiplet located between the first integrated device and the first metallization portion, the first chiplet being directly coupled to the first integrated device via a first plurality of pillar interconnects.

2. The package according to claim 1, wherein the first chiplet includes a trench capacitor.

3. The first chiplet mentioned above, Chiplet board and Multiple trench capacitors, The package according to claim 2, comprising at least one chiplet substrate through-connector.

4. The package according to claim 1, wherein the first chiplet includes a memory, a power management integrated circuit, or a voltage regulator.

5. The package according to claim 1, further comprising the first metallization portion and a sealing layer coupled to the first integrated device.

6. The sealing layer, A first sealing layer coupled to the first integrated device, The package according to claim 5, comprising a second sealing layer bonded to the first metallization portion.

7. The package according to claim 6, further comprising a dielectric layer located between the first sealing layer and the second sealing layer, wherein the dielectric layer is bonded to the first sealing layer and the second sealing layer.

8. A second integrated device coupled to the first metallization portion via a second plurality of pillar interconnections, The package according to claim 1, further comprising a second chiplet located between the second integrated device and the first metallization portion, the second chiplet being coupled to the second integrated device via a second plurality of inter-pillar interconnectors.

9. The package according to claim 8, further comprising a bridge coupled to the first metallization portion, wherein the bridge is configured to provide at least one electrical path between the first integrated device and the second integrated device.

10. The first chiplet is surrounded laterally by the first plurality of pillar interconnections, The package according to claim 8, wherein the second chiplet is laterally surrounded by the second plurality of pillar interconnections.

11. The first integrated device includes a first plurality of die interconnection sections, including a first minimum spacing. The second integrated device includes a second plurality of die interconnections, including a second minimum spacing. The package according to claim 8, wherein the first chiplet includes a plurality of interconnection portions including a third minimum spacing.

12. The first integrated device includes a plurality of die interconnection sections including a first minimum spacing, The first chiplet includes a plurality of interconnection parts including a second minimum spacing, The package according to claim 1, wherein the first minimum interval is smaller than the second minimum interval.

13. The first integrated device includes a first plurality of transistors, including a first minimum spacing, The package according to claim 1, wherein the first chiplet includes a second plurality of transistors with a second minimum spacing.

14. It is a device, A package comprising the one described in any one of claims 1 to 13, The device is selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in an automated vehicle.

15. A method for creating a package, To provide a first integrated device and a first interconnection section between multiple pillars, To form a sealing layer that seals the first integrated device and the interconnection portion between the first plurality of pillars, To form a first plurality of pillar interconnects configured to be directly coupled to the first integrated device, The first chiplet is directly coupled to the first integrated device via the first plurality of pillar interconnection parts, A method comprising forming the first metallization portion such that the first metallization portion is bonded to the first chiplet and the sealing layer.

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