Gate structure, semiconductor device, and method for manufacturing the same

Abstract

The present invention discloses a gate structure, a semiconductor device, and a method for manufacturing a semiconductor device. The gate structure includes a gate portion and a field plate portion. The field plate portion includes at least two field plate sub-portions. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two portions by a first plane. Within two adjacent field plate sub-portions, in the plane where the bottom surface of the gate portion away from the lower field plate sub-portion is located, the projection of the terminal point of the lower surface of the lower field plate sub-portion is located on one side closest to the first plane of the projection of the terminal point of the lower surface of the upper field plate sub-portion, and the terminal point of the lower surface of the upper field plate sub-portion overlaps with the terminal point where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. In the gate structure of the present invention, two adjacent field plate sub-portions are connected non-vertically, optimizing the electric field distribution and improving the reliability and stability of the semiconductor device.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a gate structure, a semiconductor device, and a method for manufacturing the semiconductor device. [Background technology]

[0002] The 5G communications field requires high bandwidth and high frequency semiconductor devices, but the gate structure design and process flow strongly affect the frequency characteristics of the semiconductor device and directly affect the operating frequency of the semiconductor device. Furthermore, the gate structure design has a significant impact on the device's electric field, which is extremely important for maintaining the reliability and stability of the semiconductor device. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a gate structure, a semiconductor device and a method for manufacturing the semiconductor device, thereby further improving the bandwidth and high frequency performance of the semiconductor device, and also improving the reliability and stability of the semiconductor device. [Means for solving the problem]

[0004] According to a first aspect of the present invention, a gate structure includes a gate portion and a field plate portion. The field plate portion includes at least two field plate sub-portions. Within two adjacent field plate sub-portions, the field plate sub-portion farther from the gate portion is an upper field plate sub-portion, and the field plate sub-portion closest to the gate portion is a lower field plate sub-portion. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two portions by a first plane. In one portion, on a plane where the bottom surface of the gate portion farther from the lower field plate sub-portion is located, a projection of an end point of the lower surface of the lower field plate sub-portion is located on one side closer to the first plane than a projection of an end point of the lower surface of the upper field plate sub-portion, and the end point of the lower surface of the upper field plate sub-portion overlaps with an end point where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. The upper surface of one field plate sub-portion is the surface away from the gate portion, the lower surface of one field plate sub-portion is the surface close to the gate portion, and on the same side of the same field plate sub-portion, one tip point is an end point close to the first plane of the surface of the field plate sub-portion, and one end point is an end point away from the first plane of the surface of the field plate sub-portion.

[0005] According to a second aspect of the present invention, the gate structure includes a gate portion and a field plate portion. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, the gate portion includes a bottom surface away from the field plate portion and a first side surface adjacent to the bottom surface. In the plane where the bottom surface of the gate portion is located, the projection of the end point where the gate portion is connected to the field plate portion is located on the side away from the first plane of the projection of the end point where the bottom surface is connected to the first side surface. In the two parts, the distance relationship between the end point where the gate portion is connected to the field plate portion and the end point where the bottom surface is connected to the first side surface is M0 < L0 and MO' < L0. In the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the end point where the gate portion located on one side of the first plane is connected to the field plate portion and the projection of the end point where the bottom surface is connected to the first side surface, M0' is the distance between the projection of the end point where the gate portion located on the other side of the first plane is connected to the field plate portion and the projection of the end point where the bottom surface is connected to the first side surface, and L0 is the distance between the projection of the end point where the bottom surface located on one side of the first plane is connected to the first side surface and the projection of the end point where the bottom surface located on the other side of the first plane is connected to the first side surface.

[0006] According to a third aspect of the present invention, a semiconductor device includes a substrate, a semiconductor layer formed on one side of the substrate, a passivation layer formed on one side of the semiconductor layer away from the substrate, and the gate structure according to the first aspect or the second aspect. The gate structure is formed on one side of the passivation layer away from the substrate. The field plate portion is formed on one side of the gate portion away from the semiconductor layer.

[0007] According to a fourth aspect of the present invention, a method for manufacturing a semiconductor device is for manufacturing the semiconductor device according to the third aspect. The manufacturing method includes forming a semiconductor layer on one side of the substrate; forming a passivation layer on one side of the semiconductor layer away from the substrate; a first photoresist is applied to the passivation layer using a first photoresist, and the passivation layer is etched to form a first layer opening in the passivation layer, the opening size of the first photoresist before etching is L1+L1'+L0+M0+M0' in a direction perpendicular to a direction from the substrate to the passivation layer, the opening size of the first photoresist after etching is L1+L1'+L0+M0+M0'+M1+M1', and the size of the first layer opening in a direction from the substrate to the passivation layer is D1; using a second photoresist to apply a second photoresist to the passivation layer based on the first layer aperture, and etching the passivation layer to form a second layer aperture located below the first layer aperture in the passivation layer, the aperture size of the second photoresist before etching being L0 in a direction perpendicular to a direction from the substrate to the passivation layer, and the aperture size of the second photoresist after etching being L0+M0+M0', the size of the second layer aperture being D0 in a direction from the substrate to the passivation layer, and exposing the semiconductor layer through the second layer aperture; depositing a gate structure to form a gate portion and a field plate portion, the gate portion completely filling the second-layer aperture, and the field plate portion covering the gate portion and completely filling the first-layer aperture.

[0008] According to a fifth aspect of the present invention, a method for manufacturing a semiconductor device is for manufacturing the semiconductor device of the third aspect, the method comprising the steps of: forming a semiconductor layer on one side of a substrate; forming a passivation layer on a side of the semiconductor layer away from the substrate; a first photoresist is applied to the passivation layer using photoresist, and the passivation layer is etched to form a first layer opening in the passivation layer, the opening size of the photoresist before etching is L0 in a direction perpendicular to a direction from the substrate to the passivation layer, the opening size of the photoresist after etching is L0+M0+M0', and the size of the first layer opening in a direction from the substrate to the passivation layer is D0; The photoresist is widened by selective etching, and an opening size of the widened photoresist is L1+L1′+L0+M0+M0′ in a direction perpendicular to a direction from the substrate to the passivation layer; Using the spread photoresist, a second photoresist is applied to the passivation layer based on the first layer aperture, and the passivation layer is etched to move the first layer aperture entirely downward toward the substrate, forming a second layer aperture in the passivation layer located above the first layer aperture, such that the opening size of the spread photoresist after etching is L1+L1'+L0+M0+M0'+M1+M1' in a direction perpendicular to the direction from the substrate to the passivation layer, and the size of the second layer aperture is D1 in a direction from the substrate to the passivation layer, exposing the semiconductor layer through the first layer aperture; depositing a gate structure to form a gate portion and a field plate portion, the gate portion completely filling the first-layer aperture, and the field plate portion covering the gate portion and completely filling the second-layer aperture.

[0009] A gate structure according to an embodiment of the present invention includes a gate portion and a field plate portion. The field plate portion includes at least two field plate sub-portions. In a direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two portions by a first plane. Within two adjacent field plate sub-portions, in a plane where the bottom surface of the gate portion away from the lower field plate sub-portion is located, the projection of the end point of the lower surface of the lower field plate sub-portion is located on one side of the first plane adjacent to the projection of the end point of the lower surface of the upper field plate sub-portion, and the end point of the lower surface of the upper field plate sub-portion overlaps with the end point where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. Adjacent field plate sub-portions are connected non-vertically, optimizing the electric field distribution and improving the reliability and stability of the semiconductor device.

[0010] It should be noted that the contents of this part are not intended to determine the main or important features of the embodiments of the present invention, and do not limit the scope of the present invention. Other features of the present invention will be easily understood through the following description. [Brief explanation of the drawings]

[0011] In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings necessary for use in the description of the embodiments will be briefly described below. However, the drawings described below are only some embodiments of the present invention, and it is obvious that a person skilled in the art can obtain other drawings based on these drawings without making any creative efforts. [Figure 1] 1 is a diagram showing a configuration of a gate structure according to a first embodiment of the present invention. [Figure 2] 1 is a diagram showing a configuration of a gate structure according to a first embodiment of the present invention. [Figure 3] 1 is a diagram showing a configuration of a gate structure according to a first embodiment of the present invention. [Figure 4] 1 is a diagram showing a configuration of a gate structure according to a first embodiment of the present invention. [Figure 5]FIG. 10 is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 9] 10 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. [Figures 10A-10F] 10A and 10B are diagrams showing the configuration of an intermediate structure formed in the manufacturing process of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] 10 is a flowchart of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. [Figures 12A-12F] 10A and 10B are diagrams showing the configuration of an intermediate structure formed in the manufacturing process of a semiconductor device according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to help those skilled in the art to better understand the content of the present invention, the following will more clearly and in detail explain the technical solutions in the embodiments of the present invention with the accompanying drawings of the embodiments of the present invention. The following embodiments are not all of the embodiments, but only some of the embodiments of the present invention. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present invention without creative work should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "comprise" and "have" and any variations thereof in the present specification, claims, and drawings are intended to be non-exclusive inclusive. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, and may further include steps or units not listed, or may further include other steps or units inherent to such process, method, product, or apparatus.

[0014] During the design and manufacturing process of semiconductor devices, the design of the gate and gate field plate is particularly important and plays a key role in the reliability and stability of the semiconductor device's operating performance. Conventional gate field plate designs limit the electric field relaxation function, so reducing the electric field at the gate requires either increasing the length of the field plate or shortening the distance between the field plate and the two-dimensional electron gas channel. However, these two methods increase the electric field at the gate field plate, creating a risk of dielectric breakdown at the field plate, and also increase the gate capacitance, affecting bandwidth and high-frequency performance.

[0015] Therefore, how to further improve the bandwidth and high frequency performance of semiconductor devices, as well as improve the reliability and stability of semiconductor devices, and realize large-scale commercial production and manufacturing has become a problem that needs to be solved.

[0016] A gate structure, a semiconductor device, and a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 12F.

[0017] First Example FIG. 1 is a diagram showing the configuration of a gate structure according to a first embodiment of the present invention. As shown in FIG. 1, gate structure 10 includes gate portion 11 and field plate portion 12. Field plate portion 12 includes at least two field plate sub-portions. Of two adjacent field plate sub-portions, the field plate sub-portion away from gate portion 11 is the upper field plate sub-portion, and the field plate sub-portion closest to gate portion 11 is the lower field plate sub-portion. In the direction from gate portion 11 to field plate portion 12, gate portion 11 and field plate portion 12 are divided by a first plane (the plane on which the dashed line in FIG. 1 is located) into two portions: a portion to the left of the dashed line and a portion to the right of the dashed line. In one portion (the portion to the left of the dashed line or the portion to the right of the dashed line), in the plane where the bottom surface of the gate portion 11 away from the lower field plate sub-portion is located, the projection of the terminal point of the lower surface of the lower field plate sub-portion is located on one side close to the gate portion 11 (or the first plane) of the projection of the tip point of the lower surface of the upper field plate sub-portion, and the tip point of the lower surface of the upper field plate sub-portion overlaps with the end point where the top surface of the lower field plate sub-portion is connected to the bottom surface of the upper field plate sub-portion.

[0018] The first plane may be a plane that divides the gate portion into two equal parts and is perpendicular to the plane on which the bottom surface of the gate portion is located, or may be only a plane that is perpendicular to the plane on which the bottom surface of the gate portion is located, but the present invention is not limited to these.

[0019] The upper side is the direction away from the gate portion 11, and the lower side is the direction approaching the gate portion 11. The upper surface of one field plate sub-portion is the surface away from the gate portion 11, and the lower surface of one field plate sub-portion is the surface approaching the gate portion 11. On the same side surface of the same field plate sub-portion, one tip point is the end point of that side surface of the field plate sub-portion in the direction approaching the gate portion 11, i.e., the end point approaching the first plane of the side surface, and one terminal point is the end point of that side surface of the field plate sub-portion in the direction away from the gate portion 11, i.e., the end point away from the first plane of the side surface. In other words, the tip point of one surface is paired with the terminal point.

[0020] In this embodiment, field plate portion 12 includes first field plate sub-portion 121 (i.e., lower field plate sub-portion) and second field plate sub-portion 122 (i.e., upper field plate sub-portion) that are aligned in a direction away from gate portion 11. As shown in FIG. 1 , in the portion to the left of the dashed line, terminal point 1212′ of the lower surface of first field plate sub-portion 121 is located on one side of terminal point 1221′ of the lower surface of second field plate sub-portion 122 that is close to gate portion 11 (or the first plane), and terminal point 1221′ of the lower surface of second field plate sub-portion 122 overlaps with terminal point 1213′ where the upper surface of first field plate sub-portion 121 is connected to the lower surface of second field plate sub-portion 122. Similarly, in the portion to the right of the dashed line, the above-described positional relationship also exists at each terminal point, and therefore, details thereof will be omitted here.

[0021] FIG. 2 is a diagram showing the configuration of a gate structure according to a first embodiment of the present invention. Referring to FIG. 2, FIG. 2 exemplarily shows that the field plate portion 12 includes a first field plate sub-portion 121, a second field plate sub-portion 122... a Nth field plate sub-portion 12N along the direction in which the field plate portion 12 is separated from the gate portion 11. As shown in FIG. 2, in two adjacent field plate sub-portions, the field plate sub-portion separated from the gate portion 11 is the Xth field plate sub-portion 12X, and the field plate sub-portion close to the gate portion 11 is the (X - 1)th field plate sub-portion 12(X - 1). Here, 1 < X ≦ N. The end point of the lower surface of the (X - 1)th field plate sub-portion 12(X - 1) (that is, the lower field plate sub-portion) is located on the side close to the gate portion 11 of the tip point of the lower surface of the Xth field plate sub-portion 12X (that is, the upper field plate sub-portion). The tip point of the lower surface of the Xth field plate sub-portion 12X (that is, the upper field plate sub-portion) overlaps with the end point where the upper surface of the (X - 1)th field plate sub-portion 12(X - 1) is connected to the lower surface of the Xth field plate sub-portion 12X.

[0022] Two adjacent field plate sub-portions are connected non-vertically, that is, the side surface of the lower field plate sub-portion is connected non-vertically to the lower surface of the upper field plate sub-portion, thereby optimizing the distribution of the electric field and improving the reliability and stability of the semiconductor device.

[0023] In an alternative embodiment, the side surface of the uppermost Nth field plate sub-portion 12N (that is, the field plate sub-portion farthest from the gate portion 11) may be a side surface perpendicular to the upper surface of the adjacent lower field plate sub-portion (that is, the (N - 1)th field plate sub-portion 12(N - 1)), or may be a side surface not perpendicular to the upper surface of the adjacent lower field plate sub-portion (that is, the (N - 1)th field plate sub-portion 12(N - 1)).

[0024] In other embodiments, the field plate portion may include a plurality of field plate sub - portions, and preferably includes N field plate sub - portions. Here, N ∈ [2, 4] and N is an integer.

[0025] FIG. 1 and FIG. 2 exemplarily show a connection form of two adjacent field plate sub - portions. In one embodiment, as shown in FIG. 3, two adjacent field plate sub - portions are connected by a curve. That is, the side surfaces of the lower field plate sub - portion and the upper field plate sub - portion are both curved surfaces. In an alternative embodiment, as shown in FIG. 4, two adjacent field plate sub - portions are connected by a polygonal surface. That is, the side surfaces of the lower field plate sub - portion and the upper field plate sub - portion are both polygonal surfaces.

[0026] In an alternative embodiment, when the field plate portion 12 shown in FIG. 2 includes three field plate sub - portions, that is, when N = 3, the side surface of the uppermost third field plate sub - portion 123 may be a side surface perpendicular to the upper surface of the adjacent lower field plate sub - portion 122, or may be a curved surface.

[0027] On the right - hand side of the dashed line, for two adjacent field plate sub - portions, the positional relationship is M(X - 1)<L(X - 1) and M(X - 1)<D(X - 1). Here, X is an integer greater than or equal to 2. Similarly, on the left - hand side of the dashed line, for two adjacent field plate sub - portions, since the above - mentioned positional relationship exists, the details are omitted here.

[0028] Optionally, taking FIG. 1 as an example, on the right - hand side of the dashed line, for two adjacent field plate sub - portions, the positional relationship is M1<L1 and M1<D1.

[0029] In the plane where the bottom surface of the gate portion 11 is located, M1 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1212 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion). L1 is the distance between the projection of the tip point 1211 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion) and the projection of the end point 1212 of the lower surface. In the plane perpendicular to the plane where the bottom surface of the gate portion 11 is located, D1 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1212 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion).

[0030] According to such an installation, non - vertical continuation of two adjacent field plate sub - portions can be realized. Thereby, the parasitic capacitance of the source or drain can be reduced, and the bandwidth and high - frequency performance of the semiconductor device can be improved.

[0031] On the right - hand side of the dashed line, for two adjacent field plate sub - portions, the positional relationship is L(X - 1)<LX. X is an integer greater than or equal to 2. Similarly, on the left - hand side of the dashed line, for two adjacent field plate sub - portions, since the above - mentioned positional relationship exists, the details are omitted here.

[0032] Optionally, taking FIG. 1 as an example, on the right - hand side of the dashed line, for two adjacent field plate sub - portions, the positional relationship is L1<L2.

[0033] In the plane where the bottom surface of the gate portion 11 is located, L1 is the distance between the projection of the tip point 1211 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion) and the projection of the end point 1212 of the lower surface. L2 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1222 of the lower surface.

[0034] Such an arrangement allows for an optimized electric field distribution under the field plate portion, reducing the risk of dielectric breakdown of the field plate portion.

[0035] Although the above example shows the positional relationship between two adjacent field plate sub-portions when a field plate portion includes two field plate sub-portions, when a field plate portion includes multiple field plate sub-portions, the positional relationship between any two adjacent field plate sub-portions in the multiple field plate sub-portions also satisfies the above relationship, and therefore details thereof will be omitted in the present invention. The connection points (also referred to as end points) referred to in the present invention are only used for cross-sectional views, but connection surfaces are specifically used for perspective structures, and therefore do not limit the scope of protection of the present invention.

[0036] 2, the positional relationship between the first field plate sub-portion 121 adjacent to the gate portion 11 and the gate portion 11 (also referred to as the size relationship between the first field plate sub-portion 121 adjacent to the gate portion 11 and located on the opposite side of the gate portion 11) is L1 = L1'. The positional relationship between the Nth field plate sub-portion 12N farthest from the gate portion 11 and the N-1th field plate sub-portion 12(N-1) (also referred to as the size relationship between the Nth field plate sub-portion 12N farthest from the gate portion 11 and located on the opposite side of the N-1th field plate sub-portion 12(N-1) adjacent to the Nth field plate sub-portion 12N farthest from the gate portion 11) is LN = LN'. This arrangement optimizes the electric field at one end of the gate portion close to the source, thereby improving the reliability and stability of the semiconductor device. In this embodiment, the structure of the gate portion 11 satisfies M0 = M0'. In this embodiment, the gate portion 11 and the field plate portion 12 both have a symmetrical structure.

[0037] In another embodiment, the positional relationship between the first field plate sub-portion 121 adjacent to the gate portion 11 and the gate portion 11 is L1>L1′, and the positional relationship between the Nth field plate sub-portion 12N, the farthest from the gate portion 11, and the N-1th field plate sub-portion 12(N-1) is LN>LN′. Because the gate-drain voltage is much greater than the gate-source voltage during semiconductor device operation, designing L1>L1′ and LN>LN′ can avoid the introduction of parasitic capacitance in L1′ and LN′, further improving the bandwidth and high-frequency performance of the semiconductor device. In this embodiment, the structure of the gate portion 11 satisfies M0>M0′. Both the gate portion 11 and the field plate portion 12 in this embodiment have asymmetric structures.

[0038] In another embodiment, the structure of gate portion 11 satisfies M0=M0′, the positional relationship between gate portion 11 and a first field plate sub-portion 121 adjacent to gate portion 11 is L1>L1′, and the positional relationship between any pair of adjacent two field plate sub-portions among the multiple field plate sub-portions (e.g., Xth field plate sub-portion 12X and X-1th field plate sub-portion 12(X-1)) is LX>LX′, where X is greater than or equal to 2 and less than or equal to N. This arrangement optimizes the electric field at one end of the gate portion adjacent to the source, thereby improving the reliability and stability of the semiconductor device. In this embodiment, gate portion 11 has a symmetrical structure, and field plate portion 12 has an asymmetrical structure.

[0039] In another embodiment, the structure of the gate portion 11 satisfies M0 = M0', the positional relationship between the gate portion 11 and a first field plate sub-portion 121 adjacent to the gate portion 11 is L1 = L1', and the positional relationship between any pair of adjacent two field plate sub-portions in the plurality of field plate sub-portions (e.g., the Xth field plate sub-portion 12X and the X-1th field plate sub-portion 12(X-1)) is LX > LX', where X is greater than or equal to 2 and less than or equal to N. This arrangement optimizes the electric field at one end of the gate portion adjacent to the source, thereby improving the reliability and stability of the semiconductor device. In this embodiment, the gate portion 11 and the first field plate sub-portion 121 both have a symmetrical structure, and the field plate sub-portions other than the first field plate sub-portion 121 among the plurality of field plate sub-portions have an asymmetrical structure.

[0040] On the plane on which the bottom surface of gate portion 11 is located, L1 is the distance between the projection of the leading point and the projection of the terminal point on the underside of first field plate sub-portion 121 located on one side of the first plane (to the right of the dashed line) and adjacent to gate portion 11; L1' is the distance between the projection of the leading point and the projection of the terminal point on the underside of first field plate sub-portion 121 located on the other side of the first plane (to the left of the dashed line) and adjacent to gate portion 11; LN is the distance between the projection of the leading point and the projection of the terminal point on the underside of Nth field plate sub-portion 12N located on one side of the first plane (to the right of the dashed line) and farthest from gate portion 11; and LN' is the distance between the projection of the leading point and the projection of the terminal point on the underside of Nth field plate sub-portion 12N located on the other side of the first plane (to the left of the dashed line) and farthest from gate portion 11.

[0041] The gate structure according to the embodiment of the present invention is widely applicable to fields such as high frequency microwaves and power electronics, etc. In particular, it exhibits significant advantages in gallium nitride electronic devices, which have a large band gap, a high electron drift velocity, a high dielectric breakdown field strength, and excellent thermal conductivity, and the formed metal electrodes have excellent quality and stability, significantly improving the electrical performance of the electrodes and better meeting the high performance requirements in rapidly developing fields such as electronic communications.

[0042] Second Example 5 is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. Referring to FIG. 5, in the portion to the right of the dashed line, gate portion 11 includes a bottom surface 110 that is away from field plate portion 12 and a first side surface 111 that is adjacent to bottom surface 110. Similarly, in the portion to the left of the dashed line, gate portion 11 also includes a first side surface (not shown).

[0043] In the portion to the right of the dashed line, on the plane on which bottom surface 110 of gate portion 11 is located, a projection of endpoint 1112 where gate portion 11 is connected to first field plate sub-portion 121 of field plate portion 12 is located on one side away from gate portion 11 (or the first plane indicated by the dashed line) of a projection of endpoint 1111 where bottom surface 110 is connected to first side surface 111. In the portion to the left of the dashed line, a projection of endpoint 1112' where gate portion 11 is connected to first field plate sub-portion 121 of field plate portion 12 is located on one side away from gate portion 11 (or the first plane indicated by the dashed line) of a projection of endpoint 1111' where bottom surface 110 is connected to first side surface 111.

[0044] The first side surface is located on one side of the end point 1111 of the bottom surface of the gate portion 11, away from the plane where the bottom surface is located and close to the plane where the field plate portion 12 is located.

[0045] In this embodiment, the endpoints 1111 and 1111', and the endpoints 1112 and 1112' are not actually distinguishable, but are distinguished by whether the endpoints are located on the same side of the first plane. The endpoints 1111 and 1112 are on the same side, and the endpoints 1111' and 1112' are on the other side.

[0046] In two parts, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 (which is also referred to as the distance relationship between the end point where the gate part 11 is connected to the field plate part 12 and the end point where the bottom surface 110 is connected to the first side surface) is M0 < L0 and MO' < L0. Preferably, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 is M0 < L0 / 4 and MO' < L0 / 4.

[0047] The structure of the gate part 11 satisfies M0 = MO', so that this gate structure can be more appropriately applied in the field of high-frequency communication.

[0048] In other embodiments, in two parts, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 (which is also referred to as the distance relationship between the end point where the gate part 11 is connected to the field plate part 12 and the bottom surface 110 of the gate part 11) is M0 ≤ D0 and MO' ≤ D0.

[0049] In the plane where the bottom surface of the gate part 11 is located, M0 is the distance between the projection of the end point 1112 where the gate part 11 located on one side of the first plane (that is, the right side of the dashed line) is connected to the first field plate sub-part 121 in the field plate part 12 and the projection of the end point 1111 where the bottom surface 110 is connected to the first side surface 111. MO' is the distance between the projection of the end point 1112' where the gate part 11 located on the other side of the first plane (that is, the left side of the dashed line) is connected to the first field plate sub-part 121 in the field plate part 12 and the projection of the end point 1111' where the bottom surface 110 is connected to the first side surface 111. L0 is the distance between the projection of the end point 1111 where the bottom surface 110 located on one side of the first plane is connected to the first side surface 111 and the projection of the end point 1111' where the bottom surface 110 located on the other side of the first plane is connected to the first side surface 111. D0 is the vertical distance between the upper surface and the bottom surface of the gate part 11.

[0050] In an alternative embodiment, the top surface of gate portion 11 and bottom surface 110 of gate portion 11 may be connected by a polygonal surface, i.e., if MO'≦D0 is satisfied, the connecting side between end point 1112 where gate portion 11, located on one side of the first plane, is connected to first field plate sub-portion 121 of field plate portion 12, and end point 1111 where bottom surface 110 is connected to first side surface 111 may be a polygonal surface. Similarly, if MO'≦D0 is satisfied, the connecting side between end point 1112' where gate portion 11, located on the other side of the first plane, is connected to first field plate sub-portion 121 of field plate portion 12, and end point 1111' where bottom surface 110 is connected to first side surface 111 may be a polygonal surface.

[0051] In other words, the connection relationship between the bottom surface 110 and the first side surface 111, or the connection relationship between the first side surface 111 and the underside of the field plate portion 12, is a non-vertical connection, and there is a trade-off between the distance between the end point 1111 where the bottom surface 110 is connected to the first side surface 111 and the end point 1112 where the gate portion 11 is connected to the field plate portion 12, thereby improving the frequency characteristics.

[0052] Such placement can reduce parasitic capacitance and improve the bandwidth and high frequency performance of the semiconductor device.

[0053] 6 is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. As shown in FIG. 6, gate portion 11 further includes second side surface 112. End point 1113 at which one end of second side surface 112 is connected to first side surface 111 is located on the same side of the first plane as the end point at which second side surface 112 is connected to field plate portion 12.

[0054] In one embodiment, on the plane on which bottom surface 110 is located, the projection of endpoint 1112 where second side surface 112 is connected to field plate portion 12 is located on one side of the projection of endpoint 1113 where one end of second side surface 112 is connected to first side surface 111, away from endpoint 1111 (or the first plane) where bottom surface 110 is connected to first side surface 111. In another embodiment, on the plane on which bottom surface 110 is located, the projection of endpoint 1113 where one end of second side surface 112 is connected to first side surface 111 overlaps with the projection of endpoint 1112 where second side surface 112 is connected to field plate portion 12.

[0055] The connecting side between end point 1111 where bottom surface 110 is connected to first side surface 111 and end point 1112 where gate portion 11 is connected to first field plate sub-portion 121 in field plate portion 12 may be flat or curved. In an alternative embodiment, end point 1111 where bottom surface 110 is connected to first side surface 111 and end point 1112 where gate portion 11 is connected to first field plate sub-portion 121 in field plate portion 12 are connected by a polygonal surface.

[0056] Third Example FIG. 7 is a diagram showing the configuration of a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 7, the semiconductor device includes a substrate 60, a semiconductor layer 50, a source 20, a drain 30, a passivation layer 40, and a gate structure 10. The semiconductor layer 50 is formed on one side of the substrate 60. The source 20 and the drain 30 are formed on one side of the semiconductor layer 50 away from the substrate 60. The passivation layer 40 is formed on one side of the semiconductor layer 50 away from the substrate 60. The gate structure 10 is formed on one side of the passivation layer 40 away from the substrate 60. It can be seen from FIG. 1 that the field plate portion 12 of the gate structure 10 is located on one side of the gate portion 11 of the gate structure 10 away from the semiconductor layer 50.

[0057] Preferably, in one embodiment of the present invention, the material of the passivation layer includes silicon nitride and / or silicon oxynitride. The substrate may be made of one of silicon, sapphire, silicon carbide, or gallium arsenide. The semiconductor layer may be made of at least one of gallium nitride, aluminum gallium nitride, or indium gallium nitride.

[0058] Based on the above embodiment, as shown in FIG. 8 , the semiconductor layer 50 further includes a nucleation layer 51, a buffer layer 52, a channel layer 53, a barrier layer 54, and a cap layer (not shown), which are sequentially arranged in a direction away from the substrate 60. In this embodiment, the barrier layer 54 contacts the source 20 and the drain 30, respectively, to form ohmic contacts. The channel layer 53 and the barrier layer 54 form a heterojunction. A two-dimensional electron gas layer 55 is formed at the heterojunction. The bottom surface of the gate portion 11 may contact the upper surface of the barrier layer 54 away from the substrate 60, or may be located within the barrier layer 54.

[0059] In the portion to the right of the dashed line, the positional relationship between two adjacent field plate sub-portions and two-dimensional electron gas layer 55 is L(X-1)<5.5*H(X-1) and LX<5.5*HX, where X is an integer greater than or equal to 2. Similarly, in the portion to the left of the dashed line, the above-mentioned positional relationship also exists between two adjacent field plate sub-portions and two-dimensional electron gas layer 55, so details thereof will be omitted here.

[0060] 8, when X=2, the positional relationship between two adjacent field plate sub-sections and two-dimensional electron gas layer 55 is L1<5.5*H1 and L2<5.5*H2. Depending on the positional relationship between the bottom surface of gate section 11 and barrier layer 54, the relationship between D0, L1, D1, and L2 may be appropriately adjusted to satisfy the distance requirement between field plate section 12 and two-dimensional electron gas layer 55.

[0061] In the portion to the right of the dashed line, in the plane where the bottom surface of gate portion 11 is located, L(X-1) is the distance between the projection of the leading point and the projection of the terminal point of the lower surface of X-1th field plate subportion 12(X-1) (i.e., the lower field plate subportion), and LX is the distance between the projection of the leading point and the projection of the terminal point of the lower surface of X-th field plate subportion 12X (i.e., the upper field plate subportion). H(X-1) is the vertical distance between the lower surface of X-1st field plate subportion 12(X-1) and the two-dimensional electron gas layer 55. HX is the vertical distance between the lower surface of X-th field plate subportion 12X and the two-dimensional electron gas layer 55.

[0062] After L(X-1) > 5.5 * H(X-1) (and LX > 5.5 * HX), the length of field plate portion 12 is further increased. This provides a further relaxation effect on the electric field and increases parasitic capacitance. Because the distance between field plate portion 12 and two-dimensional electron gas layer 55 has a significant impact on device performance, adjusting the depth to which the bottom surface of gate portion 11 extends into semiconductor layer 50 can adjust the thickness of field plate portion 12, controlling the ranges of D2 and D3, and adjusting the configuration for a power device.

[0063] The gallium nitride high frequency device formed by the semiconductor device structure of the present invention improves the power and frequency of the gallium nitride high frequency device while maintaining stable performance of the semiconductor device, making it more suitable for use in the high frequency 5G communication area.

[0064] In the above specific embodiment, the end point is only used for the cross-sectional view, but the connecting surface is specifically used for the perspective view structure, which does not limit the protection scope of the present invention.

[0065] Fourth Example 9 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. This method is for manufacturing the above-described semiconductor device. FIGS. 10A to 10F are diagrams showing the configuration of an intermediate structure formed in the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. Referring to FIGS. 10A to 10F, this manufacturing method includes the following steps.

[0066] S110: A semiconductor layer 50 is formed on one side of the substrate 60.

[0067] S120: Form a passivation layer 40 on one side of the semiconductor layer 50 away from the substrate 60.

[0068] S130: A first photoresist is applied to the passivation layer 40 using the first photoresist 70, and the passivation layer 40 is etched to form a first-layer opening in the passivation layer 40. Note that in the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size (also referred to as width) of the first photoresist before etching is L1+L1′+L0+M0+M0′, and the opening size of the first photoresist after etching is L1+L1′+L0+M0+M0′+M1+M1′, and the size (also referred to as depth) of the first-layer opening in the direction from the substrate 60 to the passivation layer 40 is D1.

[0069] Specifically, referring to FIGS. 10C and 10D, a first photoresist 70 is formed on one side of the passivation layer 40 away from the semiconductor layer 50, and an opening having a size of L1+L1′+L0+M0+M0′ is formed. A first photoresist is then applied to the passivation layer 40 at the opening location. The opening size of the first photoresist after etching (i.e., the opening size of the first-layer aperture) is L1+L1′+L0+M0+M0′+M1+M1′. In this embodiment, during the process of etching the passivation layer 40 to form the first-layer aperture, the passivation layer 40 is etched and the first photoresist 70 at the edge of the first-layer aperture is simultaneously etched. Therefore, the opening size of the first photoresist after etching is larger than the opening size of the first photoresist before etching, and the side of the first-layer aperture has a certain slope. In this embodiment, the first photoresist 70 has a substantially wedge shape before being etched, and the tips of the wedge shape of the first photoresist 70 on both sides of the opening point toward the opening. Preferably, the inclination angle of the tips of the first photoresist 70 is different from the inclination angle of the passivation layer 40 after etching.

[0070] S140: Using second photoresist 80, a second photoresist is applied to passivation layer 40 based on the first layer aperture, and passivation layer 40 is etched to form a second layer aperture in passivation layer 40 located below the first layer aperture. Note that in the direction perpendicular to the direction from substrate 60 to passivation layer 40, the aperture size of second photoresist 80 before etching is L0, and the aperture size of second photoresist 80 after etching is L0+M0+M0'. In the direction from substrate 60 to passivation layer 40, the size of the second layer aperture is D0, and the semiconductor layer 50 is exposed through the second layer aperture.

[0071] Referring to Figures 10E and 10F, a second photoresist 80 is formed on the bottom of the first-layer aperture, leaving an opening of size L0. A second photoresist is then applied to the passivation layer 40 at the aperture location. The opening size of the second photoresist 80 after etching is L0 + M0 + M0'. In this embodiment, the second photoresist 80 at the bottom of the first-layer aperture is used as the starting point. During the etching of the passivation layer 40 to form the second-layer aperture, the passivation layer 40 is etched and the second photoresist 80 at the edge of the second-layer aperture is simultaneously etched. Therefore, the opening size of the second photoresist 80 after etching is larger than the opening size of the second photoresist 80 before etching, and the side surfaces of the second-layer aperture also have a certain slope. In this embodiment, the second photoresist 80 is approximately wedge-shaped before etching, with the tips of the wedge shapes of the second photoresist 80 on both sides of the aperture pointing toward the aperture. Preferably, the slope angle of the top of the second photoresist 80 is different from the slope angle of the passivation layer 40 after etching.

[0072] S150: Gate structure 10 is deposited to form gate portion 11 and field plate portion 12. Note that gate portion 11 completely fills the second-layer opening, and field plate portion 12 covers gate portion 11 and completely fills the first-layer opening.

[0073] In an alternative embodiment, after forming the semiconductor layer 50, the source 20 and the drain 30 are formed, and the method further includes forming a passivation layer 40 covering the source 20 and the drain 30 on one side of the semiconductor layer 50 facing away from the substrate 60. In another alternative embodiment, after forming the passivation layer 40 on one side of the semiconductor layer 50 facing away from the substrate, holes are correspondingly opened in the passivation layer 40 to expose the semiconductor layer 50, and the source 20 and the drain 30 are formed in the opened holes. In this embodiment, the source 20 and the drain 30 are located on both sides of the gate structure 10.

[0074] Fifth Example Fig. 11 is a flowchart of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. This method is used to manufacture the semiconductor device of the above-mentioned embodiment. Figs. 12A to 12F are diagrams showing the manufacturing process of a semiconductor device according to the fifth embodiment of the present invention. Referring to Figs. 12A to 12F, this manufacturing method includes the following steps.

[0075] S210: A semiconductor layer 50 is formed on one side of the substrate 60.

[0076] S220: Form a passivation layer 40 on one side of the semiconductor layer 50 away from the substrate 60.

[0077] S230: A first photoresist is applied to the passivation layer 40 using photoresist 70, and the passivation layer 40 is etched to form a first-layer opening in the passivation layer 40. In a direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size of the photoresist 70 before etching is L0, and the opening size of the photoresist 70 after etching is L0+M0+M0'. In the direction from the substrate 60 to the passivation layer 40, the size of the first-layer opening is D0.

[0078] Specifically, referring to FIGS. 12C and 12D, photoresist 70 is formed on one side of passivation layer 40 away from semiconductor layer 50, and an opening of size L0 is formed. A first photoresist is applied to passivation layer 40 at the opening position. The opening size of photoresist 70 after etching (i.e., the opening size of the first-layer opening) is L0 + M0 + M0'. In this embodiment, when etching passivation layer 40 with photoresist 70 to form the first-layer opening, the passivation layer 40 is etched and the photoresist 70 at the edge of the first-layer opening is simultaneously etched. Therefore, the opening size of photoresist 70 after etching is larger than the opening size of photoresist 70 before etching, and the side of the first-layer opening has a certain slope. In this embodiment, before etching, the photoresist 70 has an approximately wedge-shaped shape near the opening, with the tips of the wedge-shaped photoresist 70 on both sides of the opening pointing toward the opening. Preferably, the slope angle of the top of the photoresist 70 is different from the slope angle of the passivation layer 40 after etching.

[0079] S240: The etched photoresist 70 is widened by selective etching. Note that the opening size of the widened photoresist 70 in the direction perpendicular to the direction from the substrate 60 to the passivation layer 40 is L1+L1′+L0+M0+M0′.

[0080] S250: Using the spread photoresist 70, a second photoresist is applied to the passivation layer 40 based on the first layer aperture, and the passivation layer 40 is etched to move the first layer aperture entirely downward toward the substrate 60, forming a second layer aperture in the passivation layer 40 located above the first layer aperture. In the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size of the spread photoresist 70 after etching is L1+L1'+L0+M0+M0'+M1+M1'. In the direction from the substrate 60 to the passivation layer 40, the size of the second layer aperture is D1, and the first layer aperture exposes the semiconductor layer 50.

[0081] In this embodiment, the passivation layer 40 is etched using the spread photoresist 70 to form the second-layer aperture. In addition to etching the passivation layer 40, the photoresist 70 at the edge of the second-layer aperture is also etched. Therefore, the aperture size of the photoresist 70 after etching is larger than the aperture size of the photoresist 70 before etching, and the side of the second-layer aperture may also have a certain slope. In this embodiment, before etching, the photoresist 70 has a roughly wedge-shaped shape near the aperture, with the tips of the wedge-shaped photoresist 70 on both sides of the aperture pointing toward the aperture. Preferably, the slope angle of the tip of the photoresist 70 is different from the slope angle of the passivation layer 40 after etching.

[0082] S260: Gate structure 10 is deposited to form gate portion 11 and field plate portion 12. Note that gate portion 11 completely fills the first-layer opening, and field plate portion 12 covers gate portion 11 and completely fills the second-layer opening.

[0083] In an alternative embodiment, after forming the semiconductor layer 50, the source 20 and the drain 30 are formed, and the method further includes forming a passivation layer 40 covering the source 20 and the drain 30 on one side of the semiconductor layer 50 away from the substrate 60. In another alternative embodiment, after forming the passivation layer 40 on one side of the semiconductor layer 50 away from the substrate 60, corresponding holes are opened in the passivation layer 40 to expose the semiconductor layer 50, and the source 20 and the drain 30 are formed in the openings. In this embodiment, the source 20 and the drain 30 are located on either side of the gate structure 10.

[0084] In an alternative embodiment, the photoresist of the above embodiment may be used to fabricate openings of the same thickness but without sloped surfaces.

[0085] It should be understood that steps can be rearranged, added, or deleted using the various forms of flow shown above. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and this is not a limitation hereof.

[0086] The above specific embodiments do not limit the scope of protection of the present invention. It should be understood by those skilled in the art that various modifications, combinations, subcombinations, and substitutions may be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of the present invention should be included in the scope of protection of the present invention.

Claims

1. A gate structure comprising: a gate portion and a field plate portion; the field plate portion includes at least two field plate sub-portions; Within two adjacent field plate sub-portions, the field plate sub-portion away from the gate portion is an upper field plate sub-portion, and the field plate sub-portion closest to the gate portion is a lower field plate sub-portion; the gate portion and the field plate portion are divided into two portions by a first plane in a direction from the gate portion to the field plate portion; in one portion, a projection of an end point of the lower surface of the lower field plate sub-portion on a plane on which a bottom surface of the gate portion away from the lower field plate sub-portion is located is located on one side of a projection of an end point of the lower surface of the upper field plate sub-portion that is close to the first plane, and an end point of the lower surface of the upper field plate sub-portion overlaps with an end point where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion; a top surface of one field plate sub-portion being a surface away from the gate portion, a bottom surface of one field plate sub-portion being a surface close to the gate portion, and on the same side of the same field plate sub-portion, one tip point is an end point of the surface of the field plate sub-portion close to the first plane, and one end point is an end point of the surface of the field plate sub-portion away from the first plane.

2. In one portion, the positional relationship between the two adjacent field plate sub-portions is M(X-1)<L(X-1) and M(X-1)<D(X-1); X is an integer of 2 or more, In a plane on which the bottom surface of the gate portion is located, M(X-1) is the distance between a projection of a leading point on the lower surface of the upper field plate sub-portion and a projection of an end point on the lower surface of the lower field plate sub-portion, and L(X-1) is the distance between a projection of a leading point on the lower surface of the lower field plate sub-portion and a projection of an end point on the lower surface of the lower field plate sub-portion, 2. The gate structure of claim 1, wherein, in a plane perpendicular to the plane on which the bottom surface of the gate portion is located, D(X-1) is the distance between a projection of an end point where the top surface of the lower field plate sub-portion is connected to the bottom surface of the upper field plate sub-portion and a projection of an end point of the bottom surface of the lower field plate sub-portion.

3. In one portion, the positional relationship between the two adjacent field plate sub-portions is L(X-1)<LX; X is an integer of 2 or more, 3. The gate structure according to claim 1, wherein, in a plane on which the bottom surface of the gate portion is located, L(X-1) is the distance between a projection of a leading point on the lower surface of the lower field plate sub-portion and a projection of an end point on the lower surface of the lower field plate sub-portion, and LX is the distance between a projection of a leading point on the lower surface of the upper field plate sub-portion and a projection of an end point on the lower surface of the upper field plate sub-portion.

4. In one portion, the gate portion includes a bottom surface remote from the field plate portion and a first side surface adjacent to the bottom surface; a projection of an end point where the gate portion is connected to the field plate portion on a plane where a bottom surface of the gate portion is located is located on one side away from the first plane of a projection of an end point where the bottom surface is connected to the first side surface; in the two portions, a distance relationship between an end point where the gate portion is connected to the field plate portion and an end point where the bottom surface is connected to the first side surface is M<L and M'<L, 4. The gate structure of claim 1, wherein, in a plane where a bottom surface of the gate portion is located, M0 is a distance between a projection of an end point where the gate portion, located on one side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; M0' is a distance between a projection of an end point where the gate portion, located on the other side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; and L0 is a distance between a projection of an end point where the bottom surface, located on one side of the first plane, is connected to the first side surface and a projection of an end point where the bottom surface, located on the other side of the first plane, is connected to the first side surface.

5. 5. The gate structure according to claim 1, wherein M0<L0 / 4 and MO'<L0 / 4.

6. In one portion, the gate portion includes a bottom surface remote from the field plate portion and a first side surface adjacent to the bottom surface; a projection of an end point where the gate portion is connected to the field plate portion on a plane where a bottom surface of the gate portion is located is located on one side away from the first plane of a projection of an end point where the bottom surface is connected to the first side surface; In the two portions, a distance relationship between an end point where the gate portion is connected to the field plate portion and a bottom surface of the gate portion satisfies MO≦DO and MO′≦DO; 6. The gate structure of claim 1, wherein, in a plane where a bottom surface of the gate portion is located, M0 is a distance between a projection of an end point where the gate portion, located on one side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; M0' is a distance between a projection of an end point where the gate portion, located on the other side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; and D0 is a vertical distance between an upper surface of the gate portion adjacent to the field plate portion and a bottom surface of the gate portion.

7. 7. The gate structure according to claim 5, wherein M0=MO'.

8. In one part, the gate portion further includes a second side; one end of the second side surface is connected to the first side surface and the other end is connected to the field plate portion, The positional relationship between an end point at which the second side surface is connected to the field plate portion and an end point at which the first side surface is connected to the second side surface is as follows: a projection of an end point where the second side surface is connected to the field plate portion on a plane where a bottom surface of the gate portion is located is located on one side away from the first plane of a projection of an end point where the first side surface is connected to the second side surface; or 8. The gate structure according to claim 5, wherein, in a plane on which a bottom surface of the gate portion is located, a projection of an end point where the second side surface is connected to the field plate portion overlaps with a projection of an end point where the first side surface is connected to the second side surface.

9. A gate structure comprising: a gate portion and a field plate portion; the gate portion and the field plate portion are divided into two portions by a first plane in a direction from the gate portion to the field plate portion; In one portion, the gate portion includes a bottom surface remote from the field plate portion and a first side surface adjacent to the bottom surface; a projection of an end point where the gate portion is connected to the field plate portion on a plane where a bottom surface of the gate portion is located is located on one side away from the first plane of a projection of an end point where the bottom surface is connected to the first side surface; in the two portions, a distance relationship between an end point where the gate portion is connected to the field plate portion and an end point where the bottom surface is connected to the first side surface is M<L and M'<L, and a gate structure, wherein, on a plane where a bottom surface of the gate portion is located, M0 is a distance between a projection of an end point where the gate portion, located on one side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; M0' is a distance between a projection of an end point where the gate portion, located on the other side of the first plane, is connected to the field plate portion and a projection of an end point where the bottom surface is connected to the first side surface; and L0 is a distance between a projection of an end point where the bottom surface, located on one side of the first plane, is connected to the first side surface and a projection of an end point where the bottom surface, located on the other side of the first plane, is connected to the first side surface.

10. In one portion, a distance relationship between an end point where the gate portion is connected to the field plate portion and a bottom surface of the gate portion satisfies M0≦D0; 10. The gate structure according to claim 9, wherein D0 is the vertical distance between the top surface of the gate portion adjacent to the field plate portion and the bottom surface of the gate portion.

11. In one part, the gate portion further includes a second side; one end of the second side surface is connected to the first side surface and the other end is connected to the field plate portion, The positional relationship between an end point at which the second side surface is connected to the field plate portion and an end point at which the first side surface is connected to the second side surface is as follows: a projection of an end point where the second side surface is connected to the field plate portion on a plane where a bottom surface of the gate portion is located is located on one side away from the first plane of a projection of an end point where the first side surface is connected to the second side surface; or 11. The gate structure of claim 9, wherein a projection of an end point where the second side surface is connected to the field plate portion overlaps a projection of an end point where the first side surface is connected to the second side surface on a plane where a bottom surface of the gate portion is located.

12. 12. The gate structure according to claim 9, wherein M0=MO'.

13. A semiconductor device, A substrate; a semiconductor layer formed on one side of the substrate; a passivation layer formed on one side of the semiconductor layer away from the substrate; The gate structure according to any one of claims 1 to 12, the gate structure is formed on one side of the passivation layer away from the substrate; The semiconductor device, wherein the field plate portion is located on one side of the gate portion away from the semiconductor layer.

14. further comprising a nucleation layer, a buffer layer, a channel layer, and a barrier layer, arranged in sequence in a layer direction away from the substrate; the channel layer and the barrier layer form a heterojunction; a two-dimensional electron gas layer is formed at the heterojunction; the field plate portion includes at least two field plate sub-portions; the positional relationship between two adjacent field plate sub-portions and the two-dimensional electron gas layer is such that L(X-1)<5.5*H(X-1) and LX<5.5*HX; X is an integer of 2 or more, the gate portion and the field plate portion are divided into two portions by a first plane in a direction from the gate portion to the field plate portion; In one part, in a plane where the bottom surface of the gate portion is located, L(X-1) is the distance between a projection of a leading point on the lower surface of a lower field plate sub-portion and a projection of an end point on the lower surface of the lower field plate sub-portion, LX is the distance between a projection of a leading point on the lower surface of an upper field plate sub-portion and a projection of an end point on the lower surface of the upper field plate sub-portion, H(X-1) is the vertical distance between the lower surface of the lower field plate sub-portion and the two-dimensional electron gas layer, and HX is the vertical distance between the lower surface of the upper field plate sub-portion and the two-dimensional electron gas layer; between two adjacent field plate sub-portions, the field plate sub-portion away from the gate portion is the upper field plate sub-portion, and the field plate sub-portion close to the gate portion is the lower field plate sub-portion; In each portion, an upper surface of one field plate sub-portion is a surface away from the gate portion, and a lower surface of one field plate sub-portion is a surface adjacent to the gate portion; 14. The semiconductor device of claim 13, wherein on the same side of the same field plate sub-portion, one leading point is an end point that is close to the first plane of the surface of the field plate sub-portion, and the other trailing point is an end point that is away from the first plane of the surface of the field plate sub-portion.

15. A method for manufacturing the semiconductor device according to claim 13 or 14, comprising the steps of: forming a semiconductor layer on one side of a substrate; forming a passivation layer on a side of the semiconductor layer away from the substrate; a first photoresist is applied to the passivation layer using a first photoresist, and the passivation layer is etched to form a first layer opening in the passivation layer, the opening size of the first photoresist before etching is L1+L1'+L0+M0+M0' in a direction perpendicular to a direction from the substrate to the passivation layer, the opening size of the first photoresist after etching is L1+L1'+L0+M0+M0'+M1+M1', and the size of the first layer opening in a direction from the substrate to the passivation layer is D1; using a second photoresist to perform a second photoresist on the passivation layer based on the first layer opening, and etching the passivation layer to form a second layer opening in the passivation layer located below the first layer opening, wherein the opening size of the second photoresist before etching is L0 in a direction perpendicular to a direction from the substrate to the passivation layer, and the opening size of the second photoresist after etching is L0+M0+M0', and the size of the second layer opening in a direction from the substrate to the passivation layer is D0, and the semiconductor layer is exposed through the second layer opening; depositing a gate structure to form a gate portion and a field plate portion, the gate portion completely filling the second-layer aperture, and the field plate portion covering the gate portion and completely filling the first-layer aperture; in a direction from the gate portion to the field plate portion, the field plate portion includes at least two field plate sub-portions, the gate portion and the field plate portion being divided into two portions by a first plane; In the two portions, on a plane where a bottom surface of the gate portion is located, M0 is the distance between a projection of an end point where the gate portion located on one side of the first plane is connected to a field plate sub-portion adjacent to the gate portion and a projection of an end point where the bottom surface of the gate portion is connected to a first side surface of the gate portion; M0' is the distance between a projection of an end point where the gate portion located on the other side of the first plane is connected to a field plate sub-portion adjacent to the gate portion and a projection of an end point where the bottom surface is connected to the first side surface; and M1 is the distance between a projection of an end point of a bottom surface of a field plate sub-portion adjacent to the gate portion located on one side of the first plane and a projection of a tip point of a bottom surface of a field plate sub-portion connected to the field plate sub-portion adjacent to the gate portion. , M1′ is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on the other side of the first plane and adjacent to the gate portion and a projection of an end point of a lower surface of a field plate sub-portion connected to the field plate sub-portion adjacent to the gate portion; L1 is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on one side of the first plane and adjacent to the gate portion and a projection of the end point; L1′ is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on the other side of the first plane and adjacent to the gate portion and a projection of the end point; L0 is the distance between a projection of an end point where the bottom surface located on one side of the first plane is connected to the first side surface and a projection of an end point where the bottom surface located on the other side of the first plane is connected to the first side surface; In each portion, the upper surface of one field plate sub-portion is a surface away from the gate portion, the lower surface of one field plate sub-portion is a surface close to the gate portion, and on the same side of the same field plate sub-portion, one leading point is an end point close to the first plane of the surface of the field plate sub-portion, and the terminal point is an end point away from the first plane of the surface of the field plate sub-portion.

16. A method for manufacturing the semiconductor device according to claim 13 or 14, comprising the steps of: forming a semiconductor layer on one side of a substrate; forming a passivation layer on a side of the semiconductor layer away from the substrate; a first photoresist is applied to the passivation layer using photoresist, and the passivation layer is etched to form a first layer opening in the passivation layer, the opening size of the photoresist before etching is L0 in a direction perpendicular to a direction from the substrate to the passivation layer, the opening size of the photoresist after etching is L0+M0+M0', and the size of the first layer opening in a direction from the substrate to the passivation layer is D0; The photoresist is widened by selective etching, and an opening size of the widened photoresist is L1+L1'+L0+M0+M0' in a direction perpendicular to a direction from the substrate to the passivation layer; Using the widened photoresist, a second photoresist is applied to the passivation layer based on the first layer aperture, and the passivation layer is etched to move the first layer aperture entirely downward toward the substrate, forming a second layer aperture in the passivation layer located above the first layer aperture, such that the opening size of the widened photoresist after etching is L1+L1'+L0+M0+M0'+M1+M1' in a direction perpendicular to the direction from the substrate to the passivation layer, and the size of the second layer aperture is D1 in a direction from the substrate to the passivation layer, exposing the semiconductor layer through the first layer aperture; depositing a gate structure to form a gate portion and a field plate portion, the gate portion completely filling the first-layer aperture and the field plate portion covering the gate portion and completely filling the second-layer aperture; in a direction from the gate portion to the field plate portion, the field plate portion includes at least two field plate sub-portions, the gate portion and the field plate portion being separated into two portions by a first plane; In the two portions, on a plane on which a bottom surface of the gate portion is located, M0 is the distance between a projection of an end point where the gate portion located on one side of the first plane is connected to a field plate sub-portion adjacent to the gate portion and a projection of an end point where the bottom surface of the gate portion is connected to a first side surface of the gate portion; M0' is the distance between a projection of an end point where the gate portion located on the other side of the first plane is connected to a field plate sub-portion adjacent to the gate portion and a projection of an end point where the bottom surface is connected to the first side surface; and M1 is the distance between a projection of an end point of a bottom surface of a field plate sub-portion adjacent to the gate portion located on one side of the first plane and a projection of a tip point of a bottom surface of a field plate sub-portion connected to the field plate sub-portion adjacent to the gate portion, M1' is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on the other side of the first plane and adjacent to the gate portion and a projection of an end point of a lower surface of a field plate sub-portion connected to the field plate sub-portion adjacent to the gate portion; L1 is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on one side of the first plane and adjacent to the gate portion and a projection of the end point; L1' is the distance between a projection of an end point of a lower surface of a field plate sub-portion located on the other side of the first plane and adjacent to the gate portion and a projection of the end point; and L0 is the distance between a projection of an end point where the bottom surface located on one side of the first plane is connected to the first side surface and a projection of an end point where the bottom surface located on the other side of the first plane is connected to the first side surface, In each portion, the upper surface of one field plate sub-portion is a surface away from the gate portion, the lower surface of one field plate sub-portion is a surface close to the gate portion, and on the same side of the same field plate sub-portion, one leading point is an end point close to the first plane of the surface of the field plate sub-portion, and the terminal point is an end point away from the first plane of the surface of the field plate sub-portion.

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