Field plating of P-GAN high electron mobility transistors

Abstract

A high electron mobility transistor (HEMT) of the present invention has a source disposed on a surface, a drain disposed on the surface, a gate disposed between the source and drain, and a first field plate disposed on the surface between the gate and drain. In some embodiments, the first field plate comprises p-type doped GaN (P-GAN). In some embodiments, the first field plate has a doping concentration, doping material, geometric shape, and / or location configured to minimize an increase in the on-resistance of the HEMT. In some embodiments, the first field plate extends continuously between and parallel to the source and drain regions such that any path from the source to the drain passes under, through, or over the first field plate. In some embodiments, the first field plate extends continuously across the entire width of the surface between the source and drain.

Description

[Technical Field]

[0001] The present invention relates to field plating for transistor devices, and more particularly for high electron mobility transistor (HEMT) devices. [Background technology]

[0002] A HEMT is a field-effect transistor (EFT) that incorporates a junction between two materials with different bandgaps as the channel. Such a junction can also be called a heterojunction, and a HEMT can be called a heterostructure FET (HEFT). A HEMT can also be called a modulation-doped FET (MODFET), in contrast to the doped region typically used as the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET). General characteristics of HEMTs are relatively low on-resistance, high breakdown voltage, and low switching losses.

[0003] Typical applications for HEMTs include power amplifiers, wireless communication systems, and voltage converters.

[0004] When operating, HEMTs generate electromagnetic fields. In some cases, these fields can interfere with gate operation. Some HEMTs have metal structures, also called field plates, that mitigate the effects of the electromagnetic fields. [Brief explanation of the drawings]

[0005] The invention will be better understood from the following description, taken in conjunction with the accompanying drawings, which show by way of example only the drawings. [Figure 1] FIG. 1 is a cross-sectional view illustrating a HEMT. [Figure 2] FIG. 2 is a cross-sectional view of the exemplary HEMT of FIG. 1, showing the electric field distribution. [Figure 3A] FIG. 3A is a cross-sectional view illustrating another HEMT. [Figure 3B]FIG. 3B is an enlarged view of a portion of FIG. 3A, showing details of the HEMT illustrated in FIG. 3A. [Figure 4] FIG. 4 is a cross-sectional view of the HEMT illustrated in FIGS. 3A and 3B, showing the electric field distribution. [Figure 5] FIG. 5 is a line graph showing the electric field strength in the AlGaN region of the HEMT illustrated in FIGS. 1 and 2, corresponding to the electric field illustrated in FIG. [Figure 6] FIG. 6 is a line graph showing the electric field strength in the AlGaN region of the HEMT illustrated in FIGS. 3A, 3B, and 4, corresponding to the electric field illustrated in FIG. [Figure 7] FIG. 7 is a line graph showing the electric field strength in the two-dimensional electron gas (2DEG) region illustrated in FIGS. 1 and 2, corresponding to the electric field illustrated in FIG. [Figure 8] FIG. 8 is a line graph showing the electric field strength in the 2DEG region of the HEMT illustrated in FIGS. 3A, 3B, and 4, corresponding to the electric field illustrated in FIG. [Figure 9] FIG. 9 is a plan view showing the HEMT illustrated in FIGS. 3A, 3B, and 4. In FIG. [Figure 10] FIG. 10 is a flowchart illustrating an example process for fabricating an exemplary HEMT. Summary of the Invention

[0006] The present invention relates to a high electron mobility transistor (HEMT) having a source at a surface, a drain at the surface, a gate at the surface between the source and drain, and a first field plate at the surface between the gate and drain. In some embodiments, the first field plate comprises p-type doped GaN (P-GaN). In some embodiments, the first field plate has a doping concentration, doping material, geometry, and / or location configured to minimize an increase in the on-resistance of the HEMT. In some embodiments, the first field plate extends continuously between and parallel to the source and drain regions, such that any path from the source to the drain passes under, through, or over the first field plate. In some embodiments, the first field plate extends continuously across the entire width of the surface between the source and drain. DETAILED DESCRIPTION

[0007] Some embodiments of the present invention relate to a high electron mobility transistor (HEMT) having a source at a surface, a drain at the surface, a gate at the surface between the source and drain, and a first field plate at the surface between the gate and drain.

[0008] In some embodiments, the first field plate comprises doped gallium nitride (GaN). In some embodiments, the first field plate is in a floating voltage state. In some embodiments, the first field plate is not electrically connected to a voltage source. In some embodiments, a second field plate is located at a surface between the gate and the first field plate. In some embodiments, the second field plate is electrically connected to a voltage source. In some embodiments, the second field plate is electrically connected to the source. In some embodiments, the first field plate comprises GaN and has a different dopant concentration, a different type of dopant, or a different dopant material than the gate. In some embodiments, the first field plate has a doping concentration, doping material, geometry, and / or location configured to minimize an increase in the on-resistance of the HEMT. In some embodiments, the first field plate is continuous. In some embodiments, the first field plate extends continuously between and parallel to the source and drain regions such that any path from the source to the drain passes under, through, or over the first field plate. In some embodiments, the first field plate extends continuously across the entire width of the surface between the source and drain. In some embodiments, the first field plate is closer to the gate than to the drain. In some embodiments, the first field plate comprises p-type doped GaN (P-GAN). In some embodiments, the first field plate comprises p-type doped aluminum gallium nitride GaN (AlGaN) or n-type doped AlGaN.

[0009] Some embodiments of the present invention relate to a method for fabricating a high electron mobility transistor (HEMT), wherein a gate material is deposited at a surface between a source and a drain, and a first field plate material is deposited at a surface between the gate material and the drain.

[0010] In some embodiments, the gate material and the first field plate material comprise doped gallium nitride (GaN). In some embodiments, the first field plate material extends continuously between surfaces between the source and drain such that any path from the source to the drain passes under, through, or over the first field plate material. In some embodiments, the first field plate material comprises p-type doped GaN (P-GAN). In some embodiments, the first field plate comprises p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN.

[0011] DETAILED DESCRIPTION OF THE INVENTION The following detailed description of various embodiments of the present invention, examples of which are illustrated in the accompanying drawings, will be given. While the present invention will be described with reference to these embodiments, it is not intended that the present invention be limited to these embodiments. On the contrary, the present invention is intended to cover alternatives, modifications, and equivalents included within the spirit and scope of the present invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will recognize that the present invention may be practiced without these specific details. Furthermore, descriptions of well-known methods, procedures, components, and circuits are omitted to avoid unnecessarily obscuring aspects of the present invention.

[0012] Certain terminology and predicates are used in the following description for convenience only and are not intended to be limiting. Terms such as "right," "left," "top," and "bottom" are used to indicate directions in the drawings to which reference is made. Furthermore, the singular terms "a," "the," "the," and the like, used in the claims and corresponding parts of the specification, unless otherwise specified, include one or more of the referenced items. These terms include the specifically described terms, derivatives of these terms, and similar expressions. For example, "at least one" preceding two or more items, such as "A, B, or C," may refer to A, B, or C alone or any combination thereof. Furthermore, some of the drawings may be shown partially transparent for purposes of explanation, illustration, and illustration only; however, this does not imply that the illustrated elements themselves will be transparent in their final manufactured form.

[0013] Although terms such as "first" and "second" are used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present invention. Furthermore, the term "and / or" can refer to the corresponding listed items alone or to a combination of one or more of these items.

[0014] Furthermore, when an element, such as a layer, region, substrate, lead, clip, pad, or contact, is described as being "on" or "extending" another element, this means that it is directly on or extends onto the other element, or that it is on or extends through intervening elements. In contrast, when an element is described as being "directly on" or "extending directly onto" another element, this means that there are no intervening elements present. Furthermore, when an element is described as being "connected" or "coupled" to another element, this means that it is directly connected to or may be directly coupled to the other element. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, this means that there are no intervening elements present. These terms are intended to encompass different orientations of the elements in addition to any orientations shown in the figures.

[0015] Relative terms such as "below," "above," "upper," or "bottom," or "horizontal" or "vertical," are used herein to describe the relationship of an element, layer, or region to another element, layer, or region. These terms encompass different orientations of the elements in addition to any orientation shown in the drawings.

[0016] The accompanying drawings are not to scale and depict only portions of the structures and only some of the various layers forming those structures. The accompanying drawings generally depict structures in a symbolic and simplified manner to facilitate understanding of the invention, without attempting to reproduce the physical structures in detail. Furthermore, manufacturing processes and operations can be implemented according to the processes and operations disclosed herein. That is, there are numerous process operations before, during, and / or after the operations shown and described herein. Furthermore, embodiments of the present invention can be implemented according to other (possibly conventional) processes and operations without significantly impacting them. Overall, embodiments of the present invention can replace and / or supplement conventional process portions, all without significantly impacting the surrounding processes and operations.

[0017] The term "HEMT" is generally synonymous with the terms "heterostructure FET (HFET)" and "modulation doped FET (MODFET)." The term "HEMT" includes devices traditionally known as HEMTs, HFETs, or MODFETs.

[0018] The term "MOSFET" is generally synonymous with the term "insulated gate field effect transistor (IGFET)," as many currently utilized MOSFETs are constructed with non-metal gates and / or non-oxide gate dielectrics. As used herein, the term "MOSFET" does not necessarily imply or require FETs with metal gates and / or oxide gate dielectrics. Rather, the term "MOSFET" includes devices commonly known or referred to as "MOSFETs."

[0019] The term "substantially equal" in this specification and claims refers to design intent, not physical results. The semiconductor industry has made effective use of the ability to measure various aspects of semiconductors with high precision. Thus, when measured with available precision, the physical aspects of semiconductors are generally not as accurate as they were when designed. Furthermore, measurement techniques can easily reveal differences in structures intended to be identical. Therefore, terms such as "substantially equal" should be interpreted as being equal at the time of design, but susceptible to manufacturing variations and measurement precision.

[0020] FIG. 1 illustrates a cross-sectional view of an exemplary HEMT 100. HEMT 100 includes source contact 105, drain contact 110, gate 115, substrate 120, buffer layer 125, channel layer 130, barrier layer 135, dielectric 140, gate contact 150, and field plate 160. While HEMT 100 is an exemplary enhancement-mode device, the principles disclosed herein are also applicable to depletion / depletion-mode HEMT devices. Some HEMT embodiments include a subset of the exemplary components and additional components described with reference to FIG. 1. For example, some HEMT embodiments include a source, gate, and drain on a substrate that combines different layers or omits a field plate.

[0021] In the embodiment of FIG. 1 , HEMT 100 is in the off state when both gate contact 150 and source contact 105 are at ground potential and in the on state when gate contact 150 is at or above a threshold voltage. The wider bandgap of barrier layer 135 than channel layer 130 facilitates the formation of 2DEG 170. In the on state, drain contact 110 is at a higher potential relative to source contact 105, so an electric field forces high-mobility electrons in 2DEG 170 to flow from source contact 105 to drain contact 110, resulting in current flow. The presence of 2DEG 170 beneath gate contact 150 depends on the voltage applied to gate contact 150. Above a threshold gate voltage, 2DEG 170 is continuous between source contact 105 and drain contact 110. Below the threshold gate voltage, the 2DEG 170 is depleted until there is an interruption / break in the 2DEG 170 underneath the gate contact 150 between the source contact 105 and the drain contact 110. When the gate contact 150 drops below the threshold gate voltage, the 2DEG 170 is interrupted from flowing between the drain contact 110 and the source contact 105, current stops flowing, and the HEMT 100 is in an off state.

[0022] Substrate 120 can be formed of any suitable material, such as silicon (Si), an engineered substrate (e.g., QST®), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination thereof, such as materials capable of supporting the growth of III-nitride materials. In this example, substrate 120 is manufactured by QST. In some embodiments, a nucleation layer (not shown) can be formed on substrate 120 to, for example, minimize lattice mismatch between the substrate and buffer layer 125 of HEMT 100. The nucleation layer can comprise any suitable material and can be formed on substrate 120 using any suitable semiconductor growth technique, such as metal oxide chemical vapor deposition / metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0023] Buffer layer 125 can be formed on substrate 120 (or a corresponding nucleation layer). In some embodiments, buffer layer 125 is or includes a highly resistive material, meaning a material with a resistivity that does not cause leakage current in the device to exceed a desired amount (e.g., a threshold leakage current). In some embodiments, such a material has a doping concentration (whether intentional or unintentional) of 1×10 15 / cm 3 In some embodiments, buffer layer 125 comprises a doped or undoped layer of a III-nitride material. In this example, buffer layer 125 is a single or multiple layer of AlGaN, although any suitable III-nitride material can be used. In some embodiments, buffer layer 125 is doped with iron, carbon, or other suitable dopants, for example, to reduce trap density. Buffer layer 125 can be formed on substrate 120 (or a corresponding nucleation layer) using any suitable semiconductor growth technique, such as AlN or metal oxide chemical vapor deposition / metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0024] The channel layer 130 can be formed on the buffer layer 125. In some embodiments, the channel layer 130 is any suitable doped or undoped III-nitride material. In this example, the channel layer is GaN, but any suitable III-nitride material can be used. The channel layer 130 can be formed on the buffer layer 125 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE.

[0025] In some embodiments, the channel layer 130 has a thickness suitable for reducing wafer bow. In some embodiments, the channel layer 130 has a minimum thickness suitable for reducing wafer bow. In some embodiments, the thickness of the channel layer 130 ranges from a few hundred nanometers. In some embodiments, the channel layer 130 is a high-resistivity layer that can be formed from unintentionally doped or lightly doped materials. Note that a high-resistivity material refers to a material that has a resistance that does not cause undesired leakage current (e.g., above a threshold leakage current) within the device. In some embodiments, the doping concentration of such materials (whether intentional or unintentional doping) is greater than 1×10 15 / cm 3 In some embodiments, the channel layer 130 is or includes an n-type III-nitride material. Conceptually, in some embodiments, a p-type III-nitride material can be used when the device is configured to operate using a two-dimensional hole gas (2DHG).

[0026] A barrier layer 135 may be formed on the channel layer 130. Similar to the buffer layer 125, the barrier layer 135 may comprise a doped or undoped layer of a III-nitride material. The barrier layer 135 may be formed on the channel layer 130 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In this example, the barrier layer 135 is composed of AlGaN with an Al mole fraction of 0.18 to 0.23 and a thickness in the range of 12 to 25 nm. In some embodiments, the thickness of the barrier layer 135 may vary between different regions of the device (e.g., the barrier layer 135 may have different thicknesses under the gate 115, and / or in the drain access region, and / or under the source contact 105 and / or drain contact 110).

[0027] Gate 115 may be disposed on the surface of barrier layer 135. In some embodiments, gate 115 comprises any suitable III-nitride material. In this example, gate 115 is formed of doped GaN (here, p-type GaN) grown on barrier layer 135. In some embodiments, gate 115 (here, p-type) does not have a uniform doping concentration. For example, such a non-uniform doping concentration may be selected to create specific field and depletion regions within gate 115.

[0028] Gate 115 can be formed on the surface of barrier layer 135 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, gate 115 is formed of GaN (e.g., p-type GaN). In some embodiments, gate 115 has a doping concentration range of 1×10 16 ~1×10 20 cm 3 (e.g., 2-3×10 19 cm 3 ) and the thickness range is 50 to 150 nm.

[0029] Gate contact 150 is an electrode that makes Schottky or ohmic contact to gate 115 and is formed using any suitable metal deposition technique. Gate contact 150 is formed from aluminum, another suitable metal, a metal stack, or any other conductor or conductor layer(s). In some embodiments, these materials are configured to make an ohmic or Schottky contact. In some embodiments, gate contact 150 extends onto barrier layer 135 in the direction of drain contact 110 shown in FIG. 1 but does not contact it (e.g., separated by a dielectric). In some embodiments, the extended portion of gate contact 150 can function as a field plate to shield gate 115 from electric fields (e.g., high electric fields, such as electric fields having a strength above a threshold electric field strength or higher than the critical electric field (Ec) of one or more of the layer materials; in some embodiments, Ec is typically equal to or about 4 MV / cm).

[0030] The drain contact 110 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 135, forming the drain region. The drain contact 110 comprises one or more metal layers disposed on the barrier layer 135, forming the drain region of the HEMT 100. The drain contact 110 may be formed from aluminum or any other suitable metal, metal stack, or other conductor. The drain contact 110 comprises one or more contact metal layers disposed on the barrier layer 135.

[0031] The source contact 105 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 135, forming the source region. The source contact 105 is formed of aluminum or other suitable metal, metal stack, or other conductor. The source contact 105 comprises one or more contact metal layers disposed on the barrier layer 135. In some embodiments, the source contact 105 extends onto, but does not contact, the barrier layer 135 in the direction of the drain contact 110 shown in FIG. 1. In some embodiments, the extension of the gate contact 150 can function as a field plate to shield the gate 115 from electric fields (e.g., high electric fields, such as electric fields having a strength exceeding a threshold electric field strength, or electric fields higher than the critical electric field (Ec) of one or more of the layer materials; in some embodiments, Ec is typically equal to or about 4 MV / cm). In some embodiments, several metal layers are deposited to form source contact 105, with portions of each metal layer extending toward drain contact 110 and over, but not contacting, barrier layer 135, as shown in FIG. 1. In such embodiments, the extensions of source contact 105 can function as field plates to shield gate 115 from electric fields (e.g., high electric fields, such as electric fields having a strength above a threshold electric field strength, or electric fields higher than the Ec of one or more of the layer materials; in some embodiments, Ec is typically equal to or about 4 MV / cm). In some embodiments, a dielectric 140 is deposited between the extensions of each metal layer of source contact 105 that form the field plates, between the field plate and gate contact 115, and between the field plate and barrier layer 135, as shown in FIG. 1.

[0032] Dielectric 140 may be a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO), aluminum oxide (AlO), or other suitable dielectric material, or a combination of these or other dielectric materials. As shown in FIG. 1 , dielectric 140 is deposited over HEMT 100 to electrically and physically isolate the HEMT 100 structures from the environment and from each other. In some embodiments, dielectric 140 is deposited in multiple layers. For example, as shown in FIG. 1 , dielectric 140 is deposited in a first layer over barrier layer 135 and gate 115. In this example, first layer of dielectric 140 is patterned and etched or otherwise processed to expose gate 115, and gate contact 150 is deposited over gate 115, and a second layer of dielectric 140 is deposited such that gate contact 150 is deposited and a second layer of dielectric 140 covers gate contact 150 and the first layer of dielectric 140. The two dielectric layers 140 can be patterned and etched or otherwise processed so that a first layer of source contact 105 is deposited on barrier layer 135, and a portion of source contact 105 is deposited on the second layer of dielectric 140 to form field plate 160. The process of patterning, etching, and depositing multiple layers of dielectric 140 can be repeated to obtain multiple dielectric layers and other structures for HEMTs such as that shown in FIG. 1, or any other suitable HEMT structure.

[0033] Figure 2 is a cross-sectional view of the exemplary HEMT 100 shown in and described with reference to Figure 1. Figure 2 details the electric fields present in the off-state of the HEMT 100. The HEMT 100 in this example is an enhancement-mode device. Thus, in the off-state, the gate contact 150 and the source contact 105 are both at ground potential, while the drain contact 110 is at a relatively high potential.

[0034] In this example, in the off-state, the ground potential of the gate 115 prevents current from flowing from the source contact 105 through the channel layer 130 to the drain contact 110. As shown by the shaded and overlaid HEMT 100 in FIG. 2 , in the off-state with a positive voltage applied to the drain contact 110, the electric field is strong in the area immediately adjacent to the gate 115 (e.g., at the edge of the gate 115). This is true even when the field plate 160 provides some electric field relief. In some cases, the strong electric field at the edge of the gate 115 can cause undesirable operating characteristics of the HEMT 100 and / or promote electron or hole trapping, which can lead to gate and device failure. For example, such electric fields can degrade the device threshold voltage of the HEMT 100, cause drain-source and / or gate-source-drain leakage within the HEMT 100, and / or promote gate failure during aging or burn-in of the HEMT 100.

[0035] 3A is a cross-sectional view of an exemplary HEMT 300. HEMT 300 includes source contact 305, drain contact 310, gate 315, substrate 320, buffer layer 325, channel layer 330, barrier layer 335, dielectric 340, gate contact 350, and field plate 360. HEMT 300 also includes field plate 380 and field plate 390.

[0036] HEMT 300 is substantially similar in structure and materials to HEMT 100 shown in and described with reference to Figures 1 and 2, except for the inclusion of two field plates, field plate 380 and field plate 390, at the surface of barrier layer 335 and the structural integration of field plate 380 and field plate 390. While HEMT 300 has two such field plates, in other embodiments, the HEMT may have only one such plate, or more than two such plates.

[0037] While HEMT 300 is an enhancement-mode device for illustrative purposes, the principles described herein also apply to depletion-mode HEMT devices. Some embodiments have a subset of the example components described with reference to FIG. 3A or additional components. For example, some embodiments have a different layer combination or have a source, gate, and drain on a substrate without using a field plate.

[0038] In the embodiment of FIG. 3A, the HEMT 300 is in an off state when both the gate contact 350 and the source contact 305 are at ground potential and in an on state when the gate contact 350 is at or above a threshold voltage. The wider bandgap of the barrier layer 335 than the channel layer 330 facilitates the formation of the 2DEG 370. In the on state, the drain contact 310 is at a higher potential relative to the source contact 305, so an electric field forces high-mobility electrons in the 2DEG 370 to flow from the source contact 305 to the drain contact 310, resulting in current flow. The presence of the 2DEG 370 beneath the gate contact 350 depends on the voltage applied to the gate contact 350. Above a threshold gate voltage, the 2DEG 370 is continuous between the source contact 305 and the drain contact 310. Below the threshold gate voltage, the 2DEG 370 is depleted until a break occurs in the 2DEG 370 underneath the gate contact 350 between the source contact 305 and the drain contact 310. When the gate contact 150 drops below the threshold gate voltage, the 2DEG 370 is blocked from flowing between the drain contact 310 and the source contact 305, current ceases to flow, and the HEMT 300 transitions to an off state.

[0039] Substrate 320 may be formed of any suitable material, such as silicon (Si), an engineered substrate (e.g., QST®), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination thereof, such as materials capable of supporting the growth of III-nitride materials. In this example, substrate 320 is manufactured by QST. In some embodiments, a nucleation layer (not shown) may be formed on substrate 320 to, for example, minimize lattice mismatch between the substrate and buffer layer 325 of HEMT 300. The nucleation layer may comprise any suitable material and may be formed on substrate 320 using any suitable semiconductor growth technique, such as metal oxide chemical vapor deposition / metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0040] Buffer layer 325 can be formed on substrate 320 (or a corresponding nucleation layer). In some embodiments, buffer layer 325 is or includes a high-resistivity material, meaning a material with a resistivity that does not cause leakage current in the device to exceed a desired amount (e.g., threshold leakage current). In some embodiments, such a material has a doping concentration (whether intentional or unintentional) of 1×10 15 / cm 3 In some embodiments, buffer layer 325 comprises a doped or undoped layer of a III-nitride material. In this example, buffer layer 325 is a single or multiple layer of AlGaN, although any suitable III-nitride material can be used. Buffer layer 325 can be formed on substrate 320 (or a corresponding nucleation layer) using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE.

[0041] Channel layer 330 may be formed on buffer layer 325. In some embodiments, channel layer 330 is any suitable doped or undoped III-nitride material. In this example, channel layer 330 may be formed from GaN, although any suitable III-nitride material may be used. Channel layer 330 may be formed on buffer layer 325 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE.

[0042] Field plate 380 can be formed on the surface of barrier layer 335 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, field plate 380 is formed from GaN (e.g., p-type GaN). In some embodiments, field plate 380 can function as a field plate to protect and shield gate 315 from electric fields (e.g., high electric fields, such as electric fields having a strength above a threshold electric field strength).

[0043] In some embodiments, field plate 380 is formed from the same layer of GaN (eg, by patterning and / or etching) used to form gate 315 .

[0044] In some embodiments, the doping concentration of field plate 380 is different from the doping concentration of gate 315. In some embodiments, field plate 380 is doped with a dopant material that is different from the dopant material of gate 315. In some embodiments, the doping concentration of field plate 380 ranges from 1×10 16 ~1×10 20 cm 3 (e.g., 2-3×10 19 cm 3). In some embodiments, field plate 380 is significantly thinner than gate 315. In some embodiments, field plate 380 is approximately one-third or one-half the thickness of gate 335. In some embodiments, the dimensions (length, height, width, etc.) of field plate 380 differ from the dimensions of gate 335. In some embodiments, the reduced thickness or different dimensions of field plate 380 relative to gate 315 are achieved by subjecting field plate 380 to a mask and etch process. In some embodiments, field plate 380 is electrically connected or communicated to source contact 305 through metal or is held at the same potential as source contact 305 using other means. In some embodiments, field plate 380 is formed from a material different from the material used to form gate 315. For example, if gate 315 is formed from PGaN, field plate 380 may be formed from AlGaN.

[0045] Field plate 390 may be formed on the surface of barrier layer 335. In some embodiments, field plate 390 comprises any suitable III-nitride material. In this example, field plate 390 is formed of doped GaN (here, p-type GaN) grown on barrier layer 335. In some embodiments, field plate 390 (here, p-type) does not have a uniform doping concentration. For example, such a non-uniform doping concentration may be selected to create specific electric field and depletion regions within field plate 390.

[0046] Field plate 390 can be formed on the surface of barrier layer 335 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, field plate 390 is formed from GaN (e.g., p-type GaN). In some embodiments, field plate 380 functions as a field plate to protect and shield gate 315 from electric fields (e.g., high electric fields, such as electric fields having a strength above a threshold electric field strength).

[0047] In some embodiments, field plate 390 is formed from the same layer of GaN (e.g., P-GaN) material used to form gate 315 and / or field plate 380 (e.g., by patterning and / or etching). In some embodiments, the doping concentration of field plate 390 is different from the doping concentration of gate 315. In some embodiments, field plate 390 is doped with a dopant material that is different from the dopant material of gate 315. In some embodiments, the doping concentration of field plate 390 ranges from 1×10 16 ~1×10 20 cm 3 (e.g., 2-3×10 19 cm 3 ) In some embodiments, field plate 390 is significantly thinner than gate 315. In some embodiments, field plate 390 is about one-third or one-half the thickness of gate 335. In some embodiments, the dimensions (length, height, width, etc.) of field plate 390 are different from the dimensions of gate 335. In some embodiments, the reduced thickness or different dimensions of field plate 390 relative to gate 315 are achieved by applying a mask and etching process to field plate 390.

[0048] In some embodiments, field plate 390 is floating and not electrically connected to source contact 105 through metal, or is held at the same potential as source contact 105 through other means. Note that field plate 390 is closer to drain 110 than field plate 380. In some embodiments using more than one such field plate, the field plate closest to the drain is floating and not electrically connected to ground or through metal. In some embodiments using only one such field plate, this single field plate is floating and not electrically connected to ground or through metal.

[0049] Gate contact 350 is an electrode that makes Schottky or ohmic contact to gate 315 and is formed using any suitable metal deposition technique. Gate contact 350 is formed from aluminum, another suitable metal, a metal stack, or any other conductive layer(s). In some embodiments, these materials are configured to provide an ohmic or Schottky contact. In some embodiments, gate contact 350 extends onto barrier layer 335 toward drain contact 310 shown in FIG. 3A but does not contact it (e.g., separated by a dielectric). In some embodiments, the extended portion of gate contact 350 can function as a field plate to shield gate 315 from electric fields (e.g., high electric fields, such as those having a strength above a threshold electric field strength).

[0050] Drain contact 310 is an electrode that exhibits ohmic properties at the barrier interface with barrier layer 335, forming the drain region. Drain contact 310 comprises one or more metal layers disposed on barrier layer 335, forming the drain region of HEMT 300. Drain contact 310 may be formed from aluminum or other suitable metal or other conductor. Drain contact 310 comprises one or more contact metal layers disposed on barrier layer 335.

[0051] The source contact 305 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 335, forming the source region. The source contact 305 is formed of aluminum or another suitable metal or other conductor. The source contact 305 comprises one or more contact metal layers disposed on the barrier layer 335. In some embodiments, the source contact 305 extends over, but does not contact, the barrier layer 335 in the direction of the drain contact 310 shown in FIG. 3A. In some such embodiments, the extension of the gate contact 350 can function as a field plate to shield the gate 315 from electric fields (e.g., high electric fields, such as those having a strength above a threshold electric field strength).

[0052] In some embodiments, several metal layers are deposited to form source contact 305. A portion of each metal layer extends onto, but does not contact, barrier layer 335 toward drain contact 310, as shown in FIG. 3A. In some embodiments, the extended portions of source contact 305 can function as field plates to provide protective shielding from electric fields (e.g., high electric fields, such as electric fields having strengths above a threshold electric field strength). In some embodiments, a dielectric 340 is deposited between the extended portions of each metal layer of source contact 305 that form the field plates, between the field plate and gate contact 315, and between the field plate and barrier layer 335, as shown in FIG. 3A.

[0053] Note that in some embodiments, field plates 380 and 390 may provide better electric field shielding to gate 315 (e.g., more effective control of peak electric fields at the edges of gate 315) than the field plate provided by field plate 360, e.g., due to their proximity to gate 315. Therefore, in some embodiments, field plate 360 is not used. Eliminating field plate 360 may have the advantage of reducing the parasitic capacitance between the metals of source contact 305 and drain contact 310.

[0054] Dielectric 340 may be a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO), aluminum oxide (AlO), or other suitable dielectric material. For example, as shown in FIG. 3A, dielectric 340 is deposited over HEMT 300 to electrically and physically isolate the HEMT 300 structures from the environment and from each other. In some embodiments, dielectric 340 is deposited in multiple layers. For example, as shown in FIG. 3A, dielectric 340 is deposited in a first layer over barrier layer 335 and gate 315. The first layer of dielectric 340 is patterned and etched or otherwise processed to expose gate 315, and gate contact 350 is deposited over gate 315, and a second layer of dielectric 340 is deposited such that gate contact 350 is deposited and a second layer of dielectric 340 covers gate contact 350 and the first layer of dielectric 340. The two dielectric layers 340 can be patterned and etched or otherwise processed so that a first layer of source contact 305 is deposited on barrier layer 335 and a portion of source contact 305 is deposited on the second layer of dielectric 340 to form field plate 360. The process of patterning, etching, and depositing multiple layers of dielectric 340 can be repeated to obtain multiple dielectric layers and other structures for HEMTs such as that shown in FIG. 3A or any other suitable HEMT structure.

[0055] 3B is an enlarged view of HEMT 300, illustrating another structural feature. As shown in FIG. 3B, metal contact 385 is deposited on field plate 380. This metal contact 385 electrically connects field plate 380 to source contact 305 via a metal layer (or layers, not shown).

[0056] 4 is a cross-sectional view of the exemplary HEMT of FIG. 3, illustrating the electric fields that exist in the off-state of HEMT 300. In this example, HEMT 300 is an enhancement-mode device. Thus, in the off-state, gate contact 350 and source contact 305 are both at ground potential, while drain contact 310 is at a relatively high potential.

[0057] In this example, in the off-state, gate 315 is at ground potential, preventing current from flowing from 2DEG 370 through channel layer 330 from drain contact 310 to source contact 305. As shown in FIG. 4 for the shaded and overlayed HEMT 300 in the off-state with drain contact 310 at a positive voltage, the electric field in the region immediately adjacent to field plate 390 is strong, while the electric field from the region of gate 315 is substantially absent. In some cases, this is due to the shielding effect of field plates 390 and / or 380. In some cases, this can have the effect of reducing or preventing undesirable operating characteristics of HEMT 300 and / or electron or hole trapping caused by or resulting from the strong electric fields present at the edge of gate 315. For example, depending on the case, the effect can be achieved of suppressing electron trapping or hole trapping, which can cause degradation of the device threshold voltage of the HEMT 300, drain-source leakage and / or gate-source-drain leakage within the HEMT 300, gate damage during aging or burn-in of the HEMT 300, and / or gate and device failure.

[0058] FIG. 5 is a line graph showing the electric field strength within HEMT 100 at the border of barrier layer 135 and dielectric 140 due to the electric field shown in FIG. 2. The electric field strength is plotted against the distance from the edge of gate 115 in the direction of drain 110. The peak electric field strength is shown at 500. FIG. 6 is a line graph showing the electric field strength within HEMT 300 at the border of barrier layer 335 and dielectric 340 due to the electric field shown in FIG. 4. The electric field strength is plotted against the distance from the edge of gate 315 in the direction of drain 310. The peak electric field strength is shown at 600.

[0059] Note that the distance between gate 315 and the electric field at peak electric field strength 600 is greater than the distance between gate 115 and the electric field at peak electric field strength 500. Peak electric field strength 600 is less than peak electric field strength 500. In some embodiments, this difference is due to the shielding effect of field plates 390 and / or 380. In some embodiments, the longer distance from gate 315 to peak electric field strength 600 can be advantageous in preventing or reducing undesirable operating characteristics of HEMT 300 caused by or resulting from the strong electric fields present at the edges of gate 315.

[0060] FIG. 7 is a line graph showing the electric field strength in the HEMT 100 generated in the 2DEG 170 by the electric field shown in FIG. 2. The electric field strength is plotted against the distance from the edge of the gate 115 toward the drain 110. The peak electric field strength is shown at 700. FIG. 8 is a line graph showing the electric field strength in the 2DEG 170 in the HEMT 300 generated by the electric field shown in FIG. 4. The electric field strength is plotted against the distance from the edge of the gate 315 toward the drain 310. The peak electric field strength is shown at 800.

[0061] Note that the distance between gate 315 and the electric field at peak electric field strength 800 is greater than the distance between gate 115 and the electric field at peak electric field strength 700. In some embodiments, this difference is due to the shielding effect of field plates 390 and / or 380. In some embodiments, the greater distance from gate 315 to peak electric field strength 800 can be advantageous in preventing or reducing undesirable operating characteristics of HEMT 300 caused by or resulting from the strong electric fields present at the edges of gate 315. In some embodiments, this can be true even if peak electric field strength 800 is greater than peak electric field strength 700, e.g., due to the greater distance from gate 315.

[0062] FIG. 9 is a plan view of HEMT 300 as shown in and described with reference to FIGS. 3A, 3B, and 4. Cross-section A corresponds to FIGS. 3A, 3B, and 4. For clarity of illustration in FIG. 9, some features of HEMT 300 have been omitted. As shown in FIG. 9, field plates 380 and 390 extend continuously and entirely across HEMT 300 (in the vertical direction as viewed in FIG. 9), such that any path along HEMT 300 between source 305 and drain 310 extends below, within, or above field plates 380 and 390. In some implementations, the continuity of field plates 380 and 390 can effectively prevent or inhibit a strong electric field from being applied to gate 315 when HEMT 300 is in the off state and the voltage on drain 310 is rising.

[0063] 10 is a flowchart illustrating an exemplary process 1000 for fabricating an exemplary HEMT. For example, the HEMT 300 shown and described above can be fabricated using all or some of the steps in process 1000.

[0064] In this example, the HEMT is formed on a substrate, which may be a silicon (Si) substrate, an engineered substrate (such as QST®), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination thereof, such as a material capable of supporting the growth of III-nitride materials. In some embodiments, substrate 120 of HEMT 300 corresponds to this substrate.

[0065] Step 1005 forms a nucleation layer on the substrate material. In some embodiments, this formation can be beneficial in preventing lattice mismatch between the substrate and subsequent layers in the HEMT. The nucleation layer may comprise any suitable material, such as aluminum nitride (AlN), and may be formed using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, this step corresponds to a nucleation layer formed on the substrate 120 of the HEMT 300.

[0066] Step 1010 forms a buffer layer on the nucleation layer. In some embodiments, the buffer layer is a high-resistivity material that may have doped or undoped layers of III-nitride materials. In some embodiments, the buffer layer is comprised of multiple AlGaN layers. The buffer layer can be formed on the nucleation layer using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, buffer layer 125 of HEMT 300 corresponds to this step.

[0067] In step 1015, a channel layer is formed on the buffer layer. The channel layer may be composed of a doped or undoped III-nitride material. In some embodiments, the channel layer is composed of GaN. The channel layer may be formed on the buffer layer using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, the channel layer has a thickness in the range of several hundred nanometers. In some embodiments, the channel layer is a highly resistive layer that may be unintentionally doped or composed of a lightly doped material. In some embodiments, the channel layer is or includes an n-type III-nitride material. The channel layer 130 of the HEMT 300 corresponds to this step.

[0068] Step 1020 forms a barrier layer on the channel layer. The barrier layer can be a doped or undoped III-nitride material layer and can be formed on the channel layer using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. The thickness and composition of the barrier layer can be selected to provide a positive threshold voltage. In some embodiments, the thickness and composition of the barrier layer can be selected to provide a wider bandgap than the channel layer, which is made of AlGaN, with an Al mole fraction typically in the range of 0.18-0.23. In this example, the barrier layer is made of AlGaN with a thickness in the range of 12-25 nm. In some embodiments, the barrier layer 135 of the HEMT 300 corresponds to this step.

[0069] Step 1025 forms a GaN layer on the barrier layer. In some embodiments, the GaN layer comprises any suitable III-nitride material. In this example, the GaN layer comprises doped GaN (here, p-type GaN) grown on the barrier layer. In some embodiments, the GaN layer (here, p-type) has a non-uniform doping concentration. In some embodiments, the non-uniform doping concentration is selected to form specific electric field and depletion regions within the GaN layer.

[0070] The GaN layer can be formed on the barrier layer 135 using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In step 1030, the GaN layer is etched to form a gate region and one or more field plate regions adjacent to, but not connected to, the gate. In some embodiments, a mask layer is formed and a mask / etch process is performed to make the field plate GaN region substantially thinner than the gate GaN region. In some embodiments, the field plate GaN is 1 / 2 to 1 / 3 the thickness of the gate GaN. In some embodiments, the doping concentration of the gate GaN region ranges from 1×10 16 ~1×10 20 cm 3 (e.g., 2-3×10 19 cm3 ) with a thickness range of 50-150 nm. In some embodiments, gate region 315 and field plates 380 and 390 of HEMT 300 correspond to this step.

[0071] Step 1035 electrically isolates the HEMT from other inactive areas of the device or other devices on the substrate. In some embodiments, this is done based on ion implantation, such as nitrogen or argon, or mesa etching performed outside the active HEMT.

[0072] In step 1040, a dielectric layer is deposited on the surface of the structure. In some embodiments, the dielectric layer is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO), aluminum oxide (AlO), or any suitable dielectric material. In some embodiments, the dielectric layer is deposited over the entire HEMT, electrically and physically isolating the HEMT structures from the environment and from each other. In some embodiments, the dielectric layer is deposited in several layers. In some embodiments, dielectric 340 of HEMT 300 corresponds to this step.

[0073] Step 1045 forms metal source and drain electrodes and ohmic contacts them to the barrier layer after masking and etching the dielectric layer. In some embodiments, pre-growth, post-growth, and annealing processes may be performed. In some embodiments, source contact 305 and drain contact 310 of HEMT 300 correspond to this step.

[0074] Step 1050 forms a metal gate electrode on the GaN gate region. In some embodiments, the metal gate electrode is a Schottky or ohmic gate metal contact that forms the GaN gate region after masking and etching the dielectric layer. In some embodiments, pre-deposition, post-deposition, and annealing processes may be performed. In some embodiments, gate contact 350 of HEMT 300 corresponds to this step. Note that the order of forming the source, drain, and gate metal contacts (e.g., performing steps 1045 and 1050) may be reversed in some embodiments.

[0075] Step 1055 forms one or more field plates on the barrier layer. In some embodiments, the field plates comprise any suitable III-nitride material, such as GaN or AlGaN. For example, in some embodiments, the field plates comprise doped GaN (in this example, p-type GaN) grown on the barrier layer. In some embodiments, the field plates do not have a uniform doping concentration. In some embodiments, the non-uniform doping concentration is selected to create specific electric field and depletion regions within the field plate.

[0076] In some embodiments, the field plate can be formed on the barrier layer using any suitable semiconductor growth technique, such as MOCVD, HVPE, or MBE. In some embodiments, the field plate is comprised of GaN (e.g., p-type GaN). In some embodiments, the field plate shields the gate region and / or gate connection from electric fields (e.g., high electric fields, such as electric fields having strengths above a threshold electric field strength). In some embodiments, the field plate is formed (e.g., by patterning and / or etching) from the same layer of GaN (e.g., P-GaN) material used to form the GaN gate region.

[0077] In some embodiments, the doping concentration of the field plate is different from the doping concentration of the gate region. In some embodiments, the dopant material of the field plate is different from the dopant material of the gate region. In some embodiments, the doping concentration of the field plate is in the range of 1×10 16 ~1×10 20 cm 3 (e.g., 2-3×10 19 cm 3 ) In some embodiments, the field plate is substantially thinner than the gate region. In some embodiments, the thickness of the field plate is about 1 / 3 to 1 / 2 the thickness of the gate region. In some embodiments, the dimensions (length, height, width, etc.) of the field plate are different from the dimensions of the gate region. In some embodiments, the reduced thickness or different dimensions of the field plate relative to the gate region are achieved by applying a mask and etching process to the field plate.

[0078] In some embodiments, field plates 380 and 390 of HEMT 300 correspond to this step.

[0079] In step 1060, one or more of the field plates are electrically connected to a voltage reference. In some embodiments, some of the field plates are electrically connected to or communicate with the source connection 305 via metal or are held at the same potential as the source connection 305. The remaining field plates are floating and not connected to a constant voltage source or voltage reference. In some embodiments, one of the field plates closest to the drain region is floating, while one or more of the remaining field plates are electrically connected to a voltage reference, such as the source or ground. In some embodiments, only one field plate is floating. In some embodiments, the field plate closest to the gate is grounded (i.e., at source potential), so that the field plate does not attain too high a potential.

[0080] In step 1065, a dielectric layer (e.g., a SiN, SiO2, or Al2O3 layer) is deposited over the barrier regions between the gate and source, between the gate and field plate, between the field plate and drain, and partially over the source and drain. In some embodiments, this dielectric layer electrically and physically isolates the HEMT structures from their environment and from each other. In some embodiments, the dielectric layer is deposited as multiple layers. In some embodiments, dielectric 340 of HEMT 300 corresponds to this step.

[0081] It should be noted that many embodiments are possible based on this disclosure, and although specific combinations of features and elements have been described above, each feature and element can also be used alone or in combination with other features and elements. [Explanation of symbols]

[0082] 100, 300 HEMT 105, 305 Source contact 110, 310 Drain contact 110, 310 Drain Gates 115 and 315 315 Gate Area 120, 320 board 125, 325 buffer layer 130, 330 channel layer 135, 335 Barrier layer 140, 340 Dielectric 150, 350 Gate contact 160, 360, 380, 390 Field Plate 170, 370 2DEG 500, 600, 700, 800 Peak Field Strength 1005, 1010, 1015, 1020, 1025, 1030, 1035, 1040, 1045, 1050, 1055, 1060, 1065 process A. Cross section

Claims

1. Sauce placed on the surface, a drain disposed on the surface; a gate disposed on the surface between the source and the drain; and a first field plate disposed on the surface between the gate and the drain; A high electron mobility transistor (HEMT) comprising:

2. The HEMT of claim 1 , wherein the first field plate comprises doped gallium nitride (GaN).

3. The HEMT of claim 1 , wherein the first field plate is in a floating voltage state.

4. The HEMT of claim 1 , wherein the first field plate is not electrically connected to a voltage source.

5. 10. The HEMT of claim 1, further comprising a second field plate disposed at said surface between said gate and said first field plate.

6. The HEMT of claim 5 , wherein the second field plate is electrically connected to a voltage source.

7. The HEMT of claim 5 , wherein the second field plate is electrically connected to the source.

8. The HEMT of claim 1 , wherein the first field plate is made of GaN and has a dopant concentration, dopant type, or dopant material different from that of the gate.

9. 10. The HEMT of claim 1, wherein the first field plate has a doping concentration, doping material, geometry, and / or location configured to minimize an increase in the on-resistance of the HEMT.

10. The HEMT of claim 1 , wherein the first field plate is of continuous configuration.

11. 2. The HEMT of claim 1, wherein the first field plate extends continuously between and parallel to the source and drain regions such that any path from the source to the drain passes under, through, or over the first field plate.

12. 2. The HEMT of claim 1, wherein said first field plate extends continuously across the entire width of the surface between said source and said drain.

13. The HEMT of claim 1 , wherein the first field plate is adjacent to the gate rather than the drain.

14. The HEMT of claim 1 , wherein the first field plate is made of p-type doped GaN (P-GaN).

15. 2. The HEMT of claim 1, wherein the first field plate is made of p-type doped aluminum GaN (AlGaN) or n-type doped AlGaN.

16. depositing a gate material on the surface between the source and drain; and depositing a first field plate material on the surface between the gate material and the drain; 1. A method for manufacturing a high electron mobility transistor (HEMT), comprising:

17. The method of claim 16 , wherein the gate material and the first field plate are comprised of doped gallium nitride (GaN).

18. 17. The method of claim 16, wherein the first field plate material extends continuously across the surface between the source and the drain such that any path from the source to the drain passes under, through, or over the first field plate material.

19. The method of claim 16 , wherein the first field plate material comprises p-type doped GaN (P-GaN).

20. The method of claim 16, wherein the first field plate material comprises p-type doped aluminum GaN (AlGaN) or n-type doped AlGaN.

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