Optoelectronic devices and methods for processing same

Abstract

The present invention relates to an optoelectronic device having a semiconductor stack with a mesa structure, including at least one of an n-doped layer and a p-doped layer and an active region disposed on one of the n-doped layer and the p-doped layer. A regrown conductive barrier layer covers the boundary of the active region with a material having a large bandgap. Each contact layer is electrically coupled to at least one of the n-doped layer and the p-doped layer, with one contact layer being in electrical contact with the regrown conductive barrier layer covering the structured boundary of the active region. A portion of the regrown conductive barrier layer extends substantially parallel to one of the n-doped layer and the p-doped layer and surrounds the active region. A structured first current blocking layer is disposed between the portion of the regrown conductive barrier layer and one of the n-doped layer and the p-doped layer, and the first current blocking layer has an opening filled with a conductive material.

Description

[Technical Field]

[0001] This application claims priority from German application DE102022122480.5, filed September 5, 2022, the contents of which are incorporated herein by reference.

[0002] The present invention relates to optoelectronic devices and methods for their processing. [Background technology]

[0003] Mesa etching of μ-LEDs is performed to optically and electrically isolate individual devices, or to separate the individual devices that form the pixels in an array. Mesa etching causes damage at the etch boundaries, resulting in crystal defects, dangling bonds, and other crystal structure irregularities. These irregularities lead to nonradiative recombination (NRR) of carriers at the mesa edges.

[0004] In large pixels, with a large ratio of total area to its perimeter, the defects described above do not substantially degrade device performance. However, in smaller devices, the impact of such defects increases. Current spreading through the layers above and below the active region and through the active region can affect carriers at the pixel edges, which can then recombine nonradiatively, reducing the quantum efficiency of the device.

[0005] This effect is particularly pronounced in InGaAlP-based μLEDs, which are typically used for red emission, due to the long diffusion lengths and high surface recombination velocities of charge carriers in the size range of μ-LED devices. Summary of the Invention [Problem to be solved by the invention]

[0006] The purpose of the present application is to overcome these and other problems, particularly with respect to μLEDs. [Means for solving the problem]

[0007] This and other objects are addressed by the subject matter of the independent claims. Features and further aspects of the proposed principle are outlined in the dependent claims.

[0008] To reduce the number of defects and improve performance, different methods of passivating the mesa edge are employed depending on the material system. In the InGaAlP material system, typically used for yellow / red emission, there are two main approaches to reducing the NRR at the mesa facets: they are called quantum well intermixing (QWI) and regrowth.

[0009] QWI is a method of intentionally scattering impurities or vacancies (impurity-free QWI) into the active region. The impurities and vacancies cause intermixing of quantum wells in the active region with adjacent high-bandgap barriers, resulting in an overall increase in the local bandgap. When applied to the active region and the edges of the device, it creates a lateral potential barrier for charge carriers to prevent leakage from the inner core of the active region to its periphery.

[0010] However, quantum well intermixing has technological limitations, especially when processing small device sizes.

[0011] Alternatively, a so-called multi-step epitaxy (regrowth approach) can be performed. Typically, a first epi including the active region is grown, and then the top surface is covered with a structured hard mask. The hard mask is used to etch the wafer surface, removing part of the active region and leaving a QW island in the center of the device that will be defined later. Then, on the same wafer, a structure is regrown using a high-bandgap material, enveloping the QW island. Further etching may be performed outside the QW island to form pixels larger than the island.

[0012] In this way, a potential barrier appears between the pixel core and the mesa facet, preventing charge carriers from scattering to the surface. For GaN / InGaN-based μLEDs, passivating dielectrics such as Al2O3 or SiO2 applied by atomic layer deposition (ALD) are used to reduce the NRR at the pixel sidewalls. Pre-passivating etching and cleaning methods, for example to remove native oxides and defects, are also employed to reduce the NRR.

[0013] Alternatively, the high-bandgap material used to encase the QW island can be made of a doped semiconductor material, specifically the same material used for the n-doped or p-doped layers. As a result, the high-bandgap material is conductive and in electrical contact with either of the doped layers. The conductive high-bandgap material may extend along the exposed sidewalls, forming an artificial p-n junction with the other layers surrounding the QW island. The p-n junction is forward biased, resulting in leakage current during device operation. The inventors propose an additional blocking layer made of a semiconductor material between the high-barrier material and the layer configured to transport carriers to the active region to block leakage current.

[0014] In some embodiments, the inventors propose an optoelectronic device comprising a mesa-structured semiconductor stack, the semiconductor stack comprising at least one of an n-doped layer and a p-doped layer, and a structured active region disposed in one of the n-doped layer and the p-doped layer, respectively, the structured active region being configured to emit light. Processing of the structured stack can follow conventional techniques, i.e., whole-wafer epitaxial processing.

[0015] The device further includes a regrown conductive barrier layer covering the structured boundary of the active region. The regrown conductive barrier layer includes a material having a larger bandgap than the active region adjacent to the active region. Respective contact layers are provided, each electrically coupled to at least one of the n-doped layer and the p-doped layer, with one of the contact layers in electrical contact with the regrown conductive barrier layer covering the structured boundary of the active region.

[0016] As described above, a portion of the regrown conductive barrier layer extends substantially parallel to one of the n-doped layer and the p-doped layer and surrounds the active region. The optoelectronic device thus includes a structured first current blocking layer disposed between the portion of the regrown conductive barrier layer and one of the n-doped layer and the p-doped layer, the first current blocking layer having an opening. One of the n-doped layer and the p-doped layer is in conductive contact with the active region through the opening in the current blocking layer.

[0017] The regrown conductive barrier layer corresponds to a high bandgap material and is in contact with one of the contact layers, which supplies charge carriers toward the active region. The device forms a vertical μLED structure with conductive, and in some embodiments metallic, contact regions facing each other at opposing locations. Therefore, further processing can follow conventional techniques, reducing the number of required modifications in the manufacturing process. The resulting optoelectronic device exhibits improved performance and quantum efficiency, but can be further processed using well-established processes.

[0018] The proposed concept is independent of the structure of the active region; that is, the active region can include a quantum well structure, one or more quantum dots, or a multi-quantum well structure. Heterostructures are also possible. To prevent diffusion of doping materials into the active region, the active region may be covered with one or more cladding layers, particularly undoped cladding layers. Some of these cladding layers may be adjacent to a current-blocking layer. In some embodiments, the material of the contact layer is in electrical contact with a regrown conductive barrier layer covering the structured boundary.

[0019] In some embodiments, the contact layer and other layers are absorptive to some extent. To reduce absorption of light from the main emission surface, it may be suitable in some embodiments to further create a reflective layer, particularly a dielectric layer, deposited on the first current blocking layer. Such a layer may be in the form of a DBR structure to reflect incident light generated in the active region. In this regard, the material of the contact layer may also be reflective, or a reflective metal may be at least partially disposed on the contact layer.

[0020] In some embodiments, the regrown conductive barrier layer has a multilayer structure of at least two semiconductor layers. It is suitable to utilize the same doped semiconductor material as the other of the p-doped and n-doped layers in the stack. This allows the material of the other of the n-doped and p-doped layers to be reused in the regrowth process to form the regrown conductive barrier layer at the edge of the active region and on the doped layer above the blocking layer. The thickness of the regrown conductive barrier layer can be as thin as a few tens of nanometers, for example, between 20 nm and 100 nm or between 20 nm and 50 nm. As a result, the overall size of the device can be kept small, while the regrown layer provides a sufficiently high barrier to significantly reduce diffusion.

[0021] Further, some aspects relate to materials for the regrown conductive barrier layer, particularly the materials for the multilayer structure. As described above, some of the materials correspond to the other of the n-doped and p-doped layers. The regrown conductive barrier layer may include an InAlP layer adjacent to the active region, particularly a doped InAlP layer. Alternatively, a ZnSSe layer can be grown adjacent to the active region because ZnSSe can be lattice-matched.

[0022] In some examples, the conductive barrier layer has a multilayer structure including at least a doped InGaAlP layer and a doped InAlP layer, the doped InAlP layer being grown on the boundary material of the active region. In some examples, the first current blocking layer has a semiconductor multilayer structure. The multiple layers have different doping types. The multiple layers are particularly an npnp multilayer structure when viewed from the direction of the active region.

[0023] The contact layer includes a metal and / or a conductive oxide in some examples.

[0024] Some embodiments relate to a lateral thickness of the regrown conductive barrier layer. In some embodiments, a portion of the regrown conductive barrier layer extends substantially parallel to one of the n-doped layer and the p-doped layer. The lateral thickness of this portion may be about 100 nm to 500 nm, particularly 400 nm or less.

[0025] Some embodiments relate to a regrown conductive barrier layer and further embodiments thereof. The regrown conductive barrier layer may be in electrical contact with the contact layer and cover the structured boundary of the active region. In particular, the regrown conductive barrier layer covers the edge of the active region. The regrown conductive barrier layer can also be used to inject charge carriers into the active region along the edge and boundary of the active region, while the regrown conductive barrier layer material, which has a large bandwidth, prevents charge carriers from reaching the NRR center.

[0026] Injection into the active region from the edge, rather than from the top (or bottom), can reduce NRR. Therefore, the optoelectronic device further includes a second current blocking layer adjacent to the active region and surrounded by the material of the regrown conductive barrier layer, and a contact layer in electrical contact with the regrown conductive barrier layer is optionally disposed at least partially on the current blocking layer. The second current blocking layer prevents charge carrier injection into the active region from the top or bottom. Carrier injection occurs laterally through the conductive barrier material.

[0027] The second current blocking layer can also have a semiconductor multilayer structure with multiple layers of different doping types. The second current blocking layer can have the same structure as the first current blocking layer. Such multilayers can be epitaxially grown, simplifying device processing. The second current blocking layer can have a pnpn multilayer structure, particularly when viewed from the direction of the active region.

[0028] In some examples, the thickness of the first current blocking layer and / or the second current blocking layer may be in the range of 50 nm to 300 nm, particularly less than 250 nm. In some embodiments, the thicknesses of the different layers may be substantially equal. The thickness of each layer of the multiple layers may be as thin as a few tens of nanometers. The various layers may be based on the same material system but with different doping to form the above-mentioned pnpn and npnp multilayers, respectively. Furthermore, in some examples, the multilayer material of the current blocking layer is the same as one of the n-doped layer and the p-doped layer, particularly the layer in conductive contact with the regrown conductive material. More specifically, one or more doped layers of the current blocking layer are based on AlInP semiconductor material.

[0029] The doping concentration of the material of the first current blocking layer and / or the second current blocking layer is 1×10 15 / cm 3 (1E15 / cm 3 ) to 1×10 19 / cm 3 (1E19 / cm 3 ) which is optimized in each layer to maximize current block.

[0030] In some examples, the optoelectronic device further comprises a dielectric layer, in particular one of Al2O3 and SiO2, covering a portion of the regrown conductive barrier layer away from the active region. Additionally, the optoelectronic device may further comprise a structured sloped sidewall extending from one of the contact layers in electrical contact with the regrown conductive barrier layer toward the other contact layer along a first portion having a first angle and along a second portion having a second angle.

[0031] Another aspect relates to the processing of optoelectronic devices. After providing a growth substrate, e.g., a GaAs substrate, a semiconductor stack is epitaxially grown on the growth substrate. This includes providing one of an n-doped layer or a p-doped layer on the growth substrate. A first current blocking layer is then epitaxially grown on one of the n-doped layer or the p-doped layer. The first current blocking layer is structured, for example, by applying a photomask to the layer and then etching the exposed surface of the first current blocking layer. As a result of the structuring, a central opening is formed. The opening is then filled with a conductive material. An active region is grown on the structured first blocking layer.

[0032] A mask layer may then be provided on the active region and then structured to cover portions thereof. Using the structured mask, a first etch is performed to form a mesa structure that exposes the boundary of the active region. The etching process is stopped at the first current blocking layer so that the first current blocking layer remains intact. The resulting mesa structure with the exposed sidewalls of the active region is then overgrown with a conductive barrier layer. The regrown conductive barrier layer is adjacent to the active region and includes a material with a larger bandgap than the active region. Finally, a contact layer is deposited that is electrically coupled to the regrown conductive barrier layer that covers the structured boundary of the active region. The contact layer is at least partially disposed on the first current blocking layer.

[0033] The proposed method provides a current-blocking layer that prevents charge carriers from flowing from the conductive barrier layer to one of the n-doped and p-doped layers through the artificial p-n junction. This is achieved by the current-blocking layer itself containing a conductive material, forming an electrical barrier that creates a potential in the reverse direction. The regrown conductive barrier layer reduces the amount of NRR at the boundary of the active region. The proposed method improves the overall performance of optoelectronic devices, especially at very small dimensions in the range of a few microns.

[0034] In some examples, growing the active region includes forming a quantum well or multiple quantum well structure. Alternatively, a heterostructure can be formed, or multiple quantum dots can be grown. In some examples, growing the active region includes growing one or more cladding layers, particularly undoped cladding layers, one of which is adjacent to a current blocking layer.

[0035] In some embodiments, filling the opening with a conductive material includes growing a doped layer in the opening, the doping type of which may be similar to one of the n-doped layer and the p-doped layer, and the doping concentration may be similar to each other. An active region is then grown on the doped layer and the structured first current blocking layer.

[0036] A contact layer can be deposited at least partially on the regrown conductive barrier layer that covers the boundary of the active region. The contact layer material can extend into the current blocking layer. Alternatively or additionally, a reflective dielectric layer can be deposited on the first current blocking layer, the reflective dielectric layer having at least one of a DBR structure and / or a reflective material. The DBR structure can be configured to reflect light emitted from the active region, thereby improving overall performance and optical efficiency.

[0037] Some embodiments relate to a conductive barrier layer. An InAlP layer, particularly a doped InAlP layer, can be grown adjacent to the active region. Alternatively, a lattice-matched ZnSSe layer can also be grown adjacent to the active region. Alternatively, a multilayer structure can be grown having at least a doped InGaAlP layer and a doped InAlP layer.

[0038] In some instances, a doped GaP layer is grown, optionally adjacent to a contact layer. Because GaP is lattice-mismatched, other layers are suitable for lattice matching, as described above.

[0039] In some embodiments, the re-growth of the conductive barrier layer is followed by a second etch that removes portions of the re-grown conductive barrier layer surrounding the stack, leaving portions of the re-grown conductive barrier layer extending substantially parallel to the first current blocking layer, to electrically isolate, and later optically isolate, each pixel.

[0040] In some embodiments, carrier injection into the active region occurs from the side edges through the conductive barrier layer, rather than from the top. Therefore, the proposed method further comprises growing a second current blocking layer on the active region. This second current blocking layer is then structured by a first mesa etching process and then covered.

[0041] The first and second current blocking layers can be of similar structure and materials, including multiple differently doped layers. For example, the first current blocking layer can have an npnp multilayer structure when viewed from the direction of the active region. The second current blocking layer can have a pnpn multilayer structure when viewed from the direction of the active region. The multilayer structures are epitaxially grown using different doping types and then structured. The doping is optimized to increase blocking.

[0042] In some examples, the thickness of the first current blocking layer and / or the second current blocking layer is in the range of 100 nm to 300 nm, particularly less than 250 nm. Alternatively or additionally, the thickness of each layer of the multiple layers is as thin as a few tens of nanometers.

[0043] In some other examples, the same material is used as in one of the n-doped and p-doped layers, particularly the layer in conductive contact with the regrown conductive material. For example, the first current blocking layer and / or the second current blocking layer may include multiple layers of differently doped AlInP semiconductor material. In other examples, the first current blocking layer and / or the second current blocking layer may include a dielectric material. [Brief explanation of the drawings]

[0044] Further aspects and embodiments in accordance with the proposed principles will become apparent in connection with the various embodiments and examples described in detail in conjunction with the accompanying drawings. [Figure 1] 1 illustrates a first embodiment of an optoelectronic device according to some aspects of the proposed principles. [Figure 2] 1 illustrates a second embodiment of an optoelectronic device according to some aspects of the proposed principles. [Figure 3] 1 illustrates a third embodiment of an optoelectronic device according to some aspects of the proposed principles. [Figure 4] FIG. 10 illustrates a fourth embodiment of an optoelectronic device according to some aspects of the proposed principles. [Figure 5A] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5B] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5C] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5D]1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5E] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5F] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5G] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5H] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5I] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5J] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5K] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 5L] 1 illustrates an embodiment of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 6A] 10A-10C illustrate further aspects of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 6B] 10A-10C illustrate further aspects of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 6C] 10A-10C illustrate further aspects of a method for processing an optoelectronic device in accordance with some aspects of the proposed principles. [Figure 7] 1 illustrates an embodiment of a current blocking layer according to some aspects of the proposed principles. DETAILED DESCRIPTION OF THE INVENTION

[0045] The following embodiments and examples disclose various aspects and combinations thereof in accordance with the proposed principles. The embodiments and examples are not necessarily drawn to scale. Similarly, different elements may be shown enlarged or reduced to emphasize individual aspects. It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be easily combined with one another without contradicting the principles of the invention. Some aspects exhibit regular structures or shapes. It should be noted that in practice, slight variations or deviations from the ideal shapes may occur. However, this does not contradict the ideas of the invention.

[0046] Additionally, the individual figures and aspects are not necessarily drawn to scale, nor are the proportions between individual elements necessarily accurate in nature. Some aspects are emphasized by enlargement. However, terms such as "top," "upper," "lower," "below," "large," "small," and the like are properly expressed with respect to elements in the figures. Thus, such relationships between elements can be inferred based on the figures.

[0047] It should be noted that the substrate systems described herein, such as InAlP and InGaAlP, may vary in content. This is an illustrative example system and does not limit the proposed principles to such systems. For example, the material InGaAlP can contain different In, Ga, and Al content ratios and can be expressed as Iny(GaxAl1-x)P, where x and y are corresponding parameters that can be varied depending on the desired wavelength of emitted light and / or the appropriate barrier difference in bandgap. For example, in a multiple quantum well heterostructure, the Al content is varied between 0 and 1 to provide quantum well or barrier layers. A parameter x of 0, i.e., x=0, corresponds to an InAlP layer. Changing the In content typically changes the lattice constant, and such a change can be used to induce strain in the crystal, which also changes the bandgap. Therefore, using different In contents tunes the emitted light to a desired wavelength.

[0048] FIG. 1 illustrates a first embodiment in accordance with some aspects of the proposed principles. Note that the embodiment of FIG. 1 and further embodiments illustrate optoelectronic devices with current blocking layers on each p-doped side. However, those skilled in the art will recognize that each current blocking layer proposed in this application can also be implemented on the n-doped side. Variations in the structure of the n-doped and p-doped layers, with respect to material composition and doping concentration, and the structure of the optoelectronic device can be implemented without departing from the proposed ideas.

[0049] The optoelectronic device has a carrier wafer substrate 10, which may be used as a wafer for further processing of the optoelectronic device, but in other implementations may also include circuitry to support the optoelectronic devices and provide current and voltage to each during operation. The optoelectronic devices are embedded in a mirror and adhesion metal 11 that surrounds the semiconductor stack layers, including the active region 41. The mirror and adhesion layer 11 not only serves the purpose of providing electrical contact to the stack, but also provides a reflective surface to improve overall emission efficiency. During device processing, a mirror and adhesion metal layer 11 is deposited over the stack to ensure re-adhesion and a stable structure. Layer 11 is then left in place.

[0050] The semiconductor stack has sloping sidewalls that resemble pyramidal structures when viewed from the direction of the contact holes 12. The sloping sidewalls and pyramidal structures are formed by two mesa etching processes, as will be explained in the following figures.

[0051] The optoelectronic device comprises a bottom opening 12 connecting the reflective and conductive metal of the mirror and adhesion metal stack 11 to a conductive contact layer 14 of the stack. In this embodiment, the contact layer 14 is made of a transparent conductive oxide. The contact layer 14 extends up from the bottom contact opening 12 along the sidewalls of the stack and is covered with a dielectric layer 13 that separates the mirror and adhesion metal 11 from the n-doped layer 50 structure.

[0052] The contact layer 14 is electrically connected to a conductive barrier layer 20 having a GaP layer 23, a p-doped indium gallium aluminum phosphide (InGaAlP) layer 22, and a p-doped indium aluminum phosphide (InAlP) barrier layer 21. Thus, the conductive barrier layer 20 includes a multilayer structure of several p-doped and undoped layers for transporting the respective charge carriers induced by the contact layer 14 to the active region 41. As shown, the conductive barrier layer 20 extends to the sidewalls and bottom of the stack (the bottom being the smallest diameter portion of the stack).

[0053] In accordance with the present invention, an undoped cladding layer of indium gallium aluminum phosphide, InGaAlP 40, is provided, followed by an undoped active region 41. A second cladding layer 42 made of the same material is grown on the opposite side of the active region 41 from the first cladding layer 40. Both cladding layers are optional, but in this embodiment they prevent unwanted dopant diffusion into the active region 41. The thickness of both cladding layers is in the range of tens of nanometers.

[0054] The active region 41 has an undoped quantum well or undoped multiple quantum well structure made of indium gallium aluminum phosphide (InGaAlP) with varying aluminum content, providing alternating barrier and quantum well layers. The cladding layer 42 also extends partially over a portion of the barrier layer 21 that extends substantially parallel to the n-doped layer structure 50.

[0055] As shown, the conductive barrier layer 20, specifically layer 21, wraps around the active region along its sloped sidewalls, but extends at least partially parallel to the n-doped layers 52 and 53 in the outer regions of the device. This extension of the conductive barrier layer 20 is due to the mesa etching process and subsequent regrowth process. In particular, the second mesa etch, which etches the conductive barrier layer material, requires higher tolerances to accommodate possible misalignment, resulting in the illustrated configuration with a small portion extending parallel to the n-doped layer. This conductive connection between this portion of layer 21 and the n-doped layer creates a p-n or p-i junction, which, although small, can generate leakage current and degrade overall device performance. To prevent this leakage current due to the artificial p-i junction, a first blocking layer 60 is positioned between the p-doped barrier layer 21 and the n-doped layer 52. When viewed from the direction of the active region, the first blocking layer 60 has an npnp multilayer structure. The npnp multilayer structure creates an electrical blocking barrier and acts as a thyristor (without a gate connection) preventing current flow.

[0056] An opening is provided in the first blocking layer 60 and filled with a conductive indium aluminum phosphide InAlP barrier material 51. Thus, charge carriers from the n-doped current spreading layers 52 and 53, respectively, are injected into the active region 41 through layer 51, while holes are injected by the conductive barrier layer 20 onto the top and along the sidewalls of the active region 41. At the same time, the npnp structure of the first blocking layer 60 prevents artificial currents from flowing from the conductive barrier layer to the n-doped layers, bypassing the active region.

[0057] As previously mentioned, when viewed from the bottom, a conductive indium aluminum phosphide (InAlP) barrier layer 51 is disposed on the second cladding layer 42 and is laterally limited by the dielectric layer 13. Two current spreading layers, namely layers 52 and 53, corresponding to the n-doped layer structure 50, are disposed on the undoped indium aluminum phosphide (InAlP) barrier layer 51 and the dielectric layer 13. The n-doped layer structure 50 includes an n-doped indium aluminum phosphide diffusion layer 52 and an n-doped indium gallium aluminum phosphide contact layer 53. Finally, a grid structure 54 for carrier injection is provided.

[0058] Conductive barrier layer 20 includes a multi-layer structure of three distinct layers 21, 22, and 23 made of different materials, as shown, which increase the bandgap of each layer compared to the bandgap of active region 41. For example, while the bandgap of active region 41 is approximately 2.0 eV, the bandgap of indium aluminum phosphide (InAlP) barrier material of layer 21 is already higher at approximately 2.2 eV. The bandgap of third layer 23, made of gallium phosphide (GaP), is even higher at approximately 2.3 eV.

[0059] Instead of using the materials shown here for the conductive barrier layer, other suitable crystal-matched materials can be used. Examples of such materials include ZnSSe and AlAs, which have approximately the same crystal lattice but a higher bandgap. The thickness of the barrier layer depends on the size of the pixel and can be as thin as tens of nanometers. The thickness of the first current blocking layer 60 ranges from about 100 nm or more, depending on each individual layer of the multilayer structure. When using an npnp structure, each layer can be tens of nanometers or more thick, with each layer optimized to maximize blocking. 15 / cm 3 From 1×10 19 / cm 3 The doping concentration ranges from 0.1 to 0.25.

[0060] A current blocking layer may also be provided between the conductive barrier and the active region, which forces carrier injection into the sidewalls of the active region as well.

[0061] FIG. 2 illustrates a corresponding embodiment. A second current blocking layer 30 is disposed between the conductive barrier layer 20 and the active region 41. An undoped cladding layer made of indium gallium aluminum phosphide (InGaAlP) 40 is disposed between the current blocking layer 30 and the active region 41. The second current blocking layer 30 includes a pnpn doped multilayer structure when viewed from the direction of the active region 41. This structure prevents charge carriers from layers 23, 22, and 21 from being injected into the active region 41 through its major surface. Instead, the charge carriers flow along the sloping sidewalls of the conductive barrier layer 20 and into the active region 41 along their respective side edges. In other words, the conductive barrier layer provides efficient lateral injection and diffusion of charge carriers into the active region from the side, while injection from above or below is prevented by the current blocking layer 30. The current blocking layer 30 thereby prevents or significantly reduces vertical electron overflow, which can cause non-radiative recombination.

[0062] FIG. 3 shows a further alternative example of an optoelectronic device with two current blocking layers 30 and 60. In this embodiment, the overall height of the optoelectronic device is further reduced by applying the contact layer 14 directly on the second current blocking layer 30. In this respect, the second current blocking layer 30 is optional here; the device can be processed without such a structure of layer 30, further reducing the overall height. As a result, very thin optoelectronic devices can be implemented. During regrowth, the conductive barrier layer 20 is grown on top of the blocking layer 30 and on the mesa-etched sidewalls of the stack. However, since the current blocking layer 30 prevents carrier injection into the active region through its respective major surface (the main top or bottom of the active region 41), the material of the conductive barrier layer 20 does not have to be on top of the current blocking layer 30 and can be replaced by the material of the contact layer 14.

[0063] This embodiment is shown in Figure 3, in which the transparent conductive oxide contact layer 14 is deposited directly on the second current-blocking layer 30. This structure is achieved by using a dielectric etch and selective area regrowth mask (not shown) for the mesa etching and conductive barrier layer regrowth, with no regrowth occurring on the blocking layer but only on the sidewalls of the structure. The mask is then removed, and the contact layer 14 can be deposited. This structure can also be achieved without the selective regrowth mask by additional etching or polishing processes. After the regrowth of the conductive barrier layer 20, the material of the conductive barrier layer 20 is covered with a structured mask layer (in the case of etching, but not polishing) that exposes portions of the conductive barrier layer 20 above the current-blocking layer 30. These exposed portions are then removed in a subsequent etching process. Similarly, the top layer 20 can be removed by polishing, and after removal of the mask material, the contact layer 14 is deposited on the sidewalls of the remaining conductive barrier layer 20 and on top of the current-blocking layer 30.

[0064] In this embodiment, the dielectric material 13 is typically made of silicon dioxide (SiO2) or other transparent, non-conductive material. During device operation, the active region 41 emits photons in each direction. The metallic material of layer 11 is partially used to reflect light emitted toward the bottom of the stack (the bottom is the smallest diameter portion of the stack). However, photons emitted by the active region 41 may subsequently be absorbed by the contact layer 14 or the conductive material barrier layer 20. To reduce such unwanted photon absorption and improve overall emission efficiency, a reflective layer 70 may be provided on top of the current-blocking layer 30 and on the adjacent side of the conductive barrier layer 20. This reflective additional layer 70 improves reflective properties and reduces the likelihood of absorption of photons emitted toward the bottom.

[0065] FIG. 4 illustrates a corresponding embodiment. The optoelectronic device 1 includes the stack described in detail above, grown on the active region 41, and includes a second current blocking layer 30 surrounded by a conductive barrier layer material 20. The contact layer 14 contacts the metal contact 12 through a central opening in the dielectric material 13 covering the stack and extends along the sidewalls of the conductive barrier layer 20. According to this embodiment, a reflective layer portion 70 is provided between the contact layer 14 and the current blocking layer 30, extending to the edge surfaces of the blocking layer 30 and the surrounding conductive barrier layer 20. In some embodiments, the reflective layer 70 is a remnant of a hard mask used in the mesa etching and regrowth process of layer 20. In some examples, the reflective layer 70 is a DBR structure (which can also be used as a hard mask in the mesa etching and regrowth process) to reflect light emitted toward the bottom region of the device, thereby reducing absorption in the contact layer 14. In this regard, in some embodiments, the second current blocking layer 30 may be omitted and a reflective layer disposed directly on the active region and any cladding layers 41 in the form of a DBR structure.

[0066] 5A through 5L illustrate several steps for processing an optoelectronic device according to some embodiments of the proposed principles. Figure 5A illustrates the initial step of growing multiple n-doped layers 53 and 52 on a corresponding growth substrate 54. The growth substrate may comprise, for example, GaAs. This substrate supports the growth of subsequent layers and reduces crystalline mismatches and defects during the growth of the various layers.

[0067] Layers 53 and 52 are doped n-type with different or constant doping profiles to provide good contact to metal layers for conductive contact with subsequent semiconductor stacks and to provide current spreading. For example, layer 53 may have a doping profile of 1×10 17 atoms / cm 3 The subsequently grown layer 52 comprises an indium aluminum phosphide diffusion layer, also doped to a range of 1×10 17 atoms / cm 3The substrate is doped n-type to a concentration greater than 52. Other layers can be applied to the growth substrate before growing the two n-doped layers 53 and 52, and can also be applied between or on top of the doped layers. An additional growth adjustment layer can be used between the substrate 54 and the n-doped layer 53 to adjust the crystal structure and reduce lattice mismatch.

[0068] Continuing to FIG. 5B, a first current blocking structure 60 based on the indium aluminum phosphide InAlP material system is grown on top of the n-doped current spreading layer 52. The current blocking layer 60 comprises multiple layers with different doping types. Considering the growth direction, the different doping types may be, for example, 1×10 17 1 / cm 3 From 1×10 19 1 / cm 3 The first current blocking layer 60 prevents leakage current between the n-doped layer and a different p-doped layer of the subsequently regrown stack, thus reducing current leakage through the optoelectronic device during operation.

[0069] In FIG. 5C, the first current blocking layer 60 is structured by applying a structured resist or dielectric mask layer 601 to the surface of the current blocking layer 60 and etching portions of the current blocking layer 60 to expose the underlying n-doped current spreading layer 52. The exposed area then forms the seed for the optoelectronic device stack. The opening is then covered with an indium aluminum phosphide (InAlP) layer 51, as shown in FIG. 5D. The mask 601 can optionally be removed before or after (only in the case of a dielectric mask) the regrowth of layer 51. FIG. 5D shows the case where the mask 601 is a dielectric and is removed after the regrowth of layer 51.

[0070] Conductive layer 51 ensures the transport of charge carriers from n-doped current spreading layer 52 to current blocking layer 60 and to an active region subsequently grown on the surface of layer 51, as shown in FIG.

[0071] As shown in particular in Figure 5E, a thin undoped cladding layer 42 (several tens of nanometers thick) is grown on top, followed by a multi-quantum well structure 41 consisting of multiple barrier and quantum well layers. The substrate used for the multi-quantum well structure can be ternary or quaternary, such as indium gallium aluminum phosphide (InGaAlP) with different aluminum contents in the barrier and quantum well layers. A second cladding layer 40 is grown on top of the active region 41. Both cladding layers 42 and 40 comprise undoped indium gallium aluminum phosphide (InAlGaP). Their thicknesses range from several tens of nanometers. The Ga, Al, and In composition of the cladding layers 40 and 42 on the one hand and the active region on the other hand may be varied to achieve specific bandgap transitions within the structure and trap internal charge carriers. The undoped cladding layer is optionally added, for example, to prevent dopants from diffusing into the active region during processing and subsequent operation.

[0072] We then proceed to the next process step shown in Figure 5F, namely the growth of a separate but optional current blocking layer 30 based on the indium aluminum gallium phosphide, InGaAlP, material system. Thus, in some embodiments, this step can be omitted, providing, for example, an optoelectronic device according to Figure 1. The multilayer structure also comprises a number of differently doped layers. In this case, a pnpn multilayer structure is grown when viewed from the active region 41. The doping levels of the multilayer structure, i.e., p-type and n-type doping, are between 1 x 10 and 1 x 10 in each layer. 15 atoms / cm 3 From 1×10 19 / cm 3 In this range, the doping concentration and thickness are set such that no or substantially no tunneling of charge carriers occurs.

[0073] In the next processing step, shown in FIG. 5G, a hard mask material is deposited over the current blocking layer 30 and then structured to provide pillars of mask layer material 301 located approximately in the middle of the areas of the undoped layer 51.

[0074] In the next step, a first mesa etch step is performed using mask layer 301 down to first current blocking layer 60, exposing the sidewalls of active region 40, second blocking layer 30, and two cladding layers 41 and 42. In top view, the mesa etch is performed in a pyramidal structure exposing the sidewalls. The resulting structure is shown in Figure 5H.

[0075] After removing hard mask 301 in this embodiment, a regrowth process is performed in Figure 5I to form a layer of p-doped material 21 on the top surface of current blocking layer 30 and on the sidewalls of exposed active region 40, extending partially onto the top surface of first current blocking layer 60. Layer 21 forms the first layer of conductive barrier layer 20, as shown.

[0076] More specifically, the material of layer 21 comprises a p-type doped indium aluminum phosphide (InAlP) barrier material. A second layer 22 of p-type doped indium gallium aluminum phosphide (InGaAlP) is grown on top of layer 21, which is then covered with a gallium phosphide (GaP) layer 23, which is also a semiconductor contact layer. The three layers 21, 22, and 23 form a conductive barrier and contact layer 20 that connects the active region 40 from its side edges. Finally, as shown in FIG. 5J, a contact layer 14 made of a transparent conductive oxide is deposited on top of the gallium phosphide (GaP) layer 23, extending partially over the top, sidewalls, and second current blocking layer 60.

[0077] 5J, the above structure is then partially covered with a structured mask layer 230 that extends over the entire stack, covering its sidewalls and portions of the conductive barrier material and contact layer 14 parallel to the current blocking layer 60. The lateral dimensions of the mask layer 230 are set to cover the stack even with misalignment of the mask layer 230, while leaving some room so that charge carriers scattering in the conductive barrier material are substantially away from the outer side edges (which will be subsequently formed by etching) of the conductive barrier material.

[0078] In the next step, shown in Figure 5K, a second mesa etch is performed to form second sidewalls that expose the conductive barrier layers 21, 22, and 23, and the contact layer 14. The second mesa etch is performed until the top surface of the n-doped layer 52 is exposed. The slopes of both mesa etches can be the same, as shown in this exemplary method, or can be different, as shown, for example, in the embodiments of Figures 1 to 4. A dielectric material 13, for example made of SiO2, is deposited over the n-doped layer 52 and over the respective exposed sidewall portions and contact layer 14.

[0079] The resulting structure is shown in Figure 5L. After creating an opening in the dielectric material layer 13 to expose a portion of the transparent conductive oxide 14, a reflective metal stack is deposited to provide contact to the conductive layer 14. The metal stack also stabilizes the structure and facilitates rebonding and removal of the growth substrate 54. After removing the growth substrate 54 (not shown), additional processing can be performed, such as applying a metal contact grid.

[0080] The resulting structure is similar to and corresponds to the embodiment of Figure 2. By omitting the growth and structuring of the current blocking layer 30, the structure of the embodiment of Figure 1 can be achieved.

[0081] 6A-6B show two further steps for processing an optoelectronic device according to the embodiment of FIG. 4. In this particular case, a mask layer 301′ is provided on top of the current blocking layer 30. However, in this case, the mask layer 301′ has a DBR structure, which is a multilayer structure of materials with different refractive indices that reflects light emitted in the active region toward the heterostructure 301′. After structuring the mask layer 301′ and the active layer, similar steps are performed to grow the conductive barrier material layers 21, 22, and 23. In this example, the growth of the respective materials is selective, meaning that the materials grow mainly on the exposed sidewalls of the active region 41 and the cladding layers 40 and 42, as well as on top of the current blocking layer 60. This can be achieved, for example, by carefully adjusting the growth parameters during the regrowth process.

[0082] In another embodiment, mask layer 301' is omitted and the exposed surface of cladding layer 41 is directly covered by a layer of barrier layer 20, resulting in the embodiment of FIG.

[0083] 6B shows the result of the regrowth process, in which the material of conductive barrier layer 20 is grown primarily on the top surface of first current blocking layer 60 and the exposed sidewalls of the semiconductor stack comprising active region 41, two cladding layers 40 and 42, and current blocking layer 30, but not on mask layer 301'. Finally, conductive transparent oxide or metal layer 14 is deposited on top of conductive barrier 20 and mask layer 301'. Mask layer 301' thus remains in the optoelectronic device, forming the DBR structure or other reflective structure described above, improving the extraction of light generated in the active region.

[0084] 6C shows a slightly different process step during and after the regrowth process. In this example, the mask layer 301′ covering the top of the current blocking layer 30 is removed after the regrowth process of the conductive barrier layer 20, and a transparent conductive oxide layer 14 is deposited on the sidewalls of the conductive barrier and on top of the current blocking layer 30. This embodiment corresponds to the embodiment of FIG. 3 and, compared to the embodiment of FIG. 1, reduces the vertical dimension of the optoelectronic device and reduces absorption due to the omission of layer 20 above the blocking layer. As in the previous embodiment, charge carriers provided by the contact layer 14 are injected along the sidewalls through the conductive barrier 20 into the active region 40.

[0085] By omitting the previous step of growing multiple layers of blocking layer 30 shown in Figure 5F, contact layer 14 can be deposited directly onto cladding layer 40. At this point, the thickness of cladding layer 40 is adjusted.

[0086] 7 shows examples of multilayer structures for current blocking layers, such as an npnp stack grown as current blocking layer 60 and a pnpn stack for current blocking layer 30. The npnp or pnpn stack has several differently doped layers, each tens of nanometers thick. The structure resembles a thyristor without a gate connection. [Explanation of symbols]

[0087] 1. Optoelectronic devices 10. Career 11 Mirror and adhesive layer 12 Contact 13 Dielectric Materials 14 Contact layer 20 Conductive barrier layer 21 Barrier Layer 22,23 Barrier layer 30 Current-blocking layer 40 cladding layer 41 Quantum well layer, light-emitting region 42 Cladding layer 50 n-doped layer 51 Doped layer 52 Current diffusion layer 53 Contact layer 54 Grid Structure 60 Second current blocking layer 70 DBR structure

Claims

1. a semiconductor stack having a mesa structure, the semiconductor stack having at least one of an n-doped layer and a p-doped layer, and a structured active region disposed in one of the n-doped layer and the p-doped layer, the structured active region being configured to emit light; a regrown conductive barrier layer covering a structured boundary of the active region, the regrown conductive barrier layer being adjacent to the active region and comprising a material having a larger bandgap than the active region; contact layers electrically coupled to at least one of the n-doped layer and the p-doped layer, one of the contact layers being in electrical contact with the regrown conductive barrier layer covering a structured boundary of the active region; An optoelectronic device comprising: a portion of the regrown conductive barrier layer extending substantially parallel to one of the n-doped layer and the p-doped layer and surrounding the active layer; the optoelectronic device further comprising a structured first current blocking layer disposed between the portion of the regrown conductive barrier layer and one of the n-doped layer and the p-doped layer, the first current blocking layer having an opening; one of the n-doped layer and the p-doped layer is in conductive contact with the active region through the opening in the current blocking layer; Optoelectronic devices.

2. The active region is quantum wells, Multiple quantum wells, heterostructure, one or more quantum dots, and one or more cladding layers, in particular undoped cladding layers; one of the cladding layers is adjacent to the current blocking layer; The optoelectronic device of claim 1 .

3. 3. The optoelectronic device of claim 1, wherein the material of the contact layer, which is in electrical contact with the regrown conductive barrier layer covering the structured boundary, is deposited on the regrown conductive barrier layer.

4. 4. An optoelectronic device according to claim 1, further comprising a reflective dielectric layer deposited between the active region and the contact layer, the contact layer being in electrical contact with the regrown conductive barrier layer.

5. The optoelectronic device according to any one of claims 1 to 4, wherein the regrown conductive barrier layer has a multi-layer structure of at least two semiconductor layers with different material compositions and dopings.

6. An optoelectronic device according to any one of claims 1 to 5, wherein the thickness of the regrown conductive barrier layer is in the range of several tens of nanometers.

7. the regrown conductive barrier layer is a GaP layer optionally adjacent said contact layer; an InAlP layer adjacent to the active region, in particular a doped InAlP layer; a ZnSSe layer adjacent the active region; and a heterostructure having at least a doped InGaAlP layer and a doped InAlP layer; An optoelectronic device according to any one of claims 1 to 6.

8. 8. An optoelectronic device according to any one of claims 1 to 7, wherein the lateral thickness of the portion of the regrown conductive barrier layer extending substantially parallel to one of the n-doped layer and the p-doped layer is between about 50 nm and 500 nm, in particular less than 400 nm.

9. 9. An optoelectronic device according to claim 1, wherein the first current blocking layer has a semiconductor multilayer structure with several layers of different doping type, in particular an npnp stack when viewed in the direction of the active region.

10. 10. The optoelectronic device of claim 1, further comprising a second current blocking layer disposed adjacent to the active region and surrounded by material of the regrown conductive barrier layer, and a contact layer in electrical contact with the regrown conductive barrier layer.

11. An optoelectronic device according to any one of claims 1 to 10, wherein the second current blocking layer comprises a semiconductor stack with several layers of different doping type, in particular a pnpn stack when viewed in the direction of the active region.

12. The first current blocking layer and / or the second current blocking layer are a thickness of about 100 nm or greater; for each layer of the plurality of layers, a thickness in the range of several tens of nanometers; the same material as one of the n-doped layer and the p-doped layer, in particular the layer in conductive contact with the regrown conductive material; and one or more layers of doped AlInP semiconductor material; An optoelectronic device according to any one of claims 1 to 11.

13. The doping concentration of the material of the first current blocking layer and / or the second current blocking layer is 1×10 １５ atoms / cm ３ From 1 x 10 １９ atoms / cm ３ The optoelectronic device according to any one of claims 1 to 12, wherein

14. a dielectric layer, particularly Al, covering the portion of the regrown conductive barrier layer away from the active region; ２ O ３ and SiO ２ 14. An optoelectronic device according to any one of claims 1 to 13, further comprising a dielectric layer which is one of:

15. 15. The optoelectronic device of claim 1, further comprising a structured sloping sidewall extending from one of the contact layers, in electrical contact with the regrown conductive barrier layer, towards the other of the contact layers along a first portion having a first angle and along a second portion having a second angle.

16. providing a growth substrate; providing one of an n-doped layer and a p-doped layer on the growth substrate; growing a first current blocking layer on one of the n-doped layer and the p-doped layer; structuring the first current blocking layer to form a central opening; filling the opening with a conductive layer; growing an active region on the structured first insulating layer and the conductive layer; performing a first etch to form a mesa structure exposing a boundary of the active region, the mesa etch stopping at the first current blocking layer; regrowing a conductive barrier layer at a structured boundary of the active region, the regrown conductive barrier layer comprising a material adjacent to the active region and having a larger bandgap than the active region; providing a contact layer electrically coupled to the regrown conductive barrier layer overlying the structured boundary of the active region; A method for processing an optoelectronic device.

17. growing the active region growing a quantum well structure; growing a multiple quantum well structure; growing a heterostructure; growing one or more quantum dots; and growing one or more cladding layers, in particular undoped cladding layers; The method of claim 16 , wherein one of the cladding layers is adjacent to the current blocking layer.

18. filling the opening with a conductive material; growing a doped layer in the opening, the doping type being the same as one of the n-doped layer and the p-doped layer; growing the active region on the doped layer and the structured first current blocking layer; 18. The method of claim 16 or 17.

19. 19. The method according to any one of claims 16 to 18, wherein the step of providing the contact layer comprises at least partially depositing a contact layer material, in particular a metal or a transparent conductive oxide, on the regrown conductive barrier layer covering the border of the active area.

20. 20. The method of claim 16, further comprising, before the step of providing the contact layer, forming a reflective dielectric layer, the reflective dielectric layer having at least one of a DBR structure and / or a reflective material.

21. regrowing the conductive barrier layer growing an InAlP layer adjacent to the active region, in particular a doped InAlP layer; growing a ZnSSe layer adjacent to the active region; growing a multilayer structure having at least a doped InGaAlP layer and a doped InAlP layer; and optionally growing a GaP layer adjacent to the contact layer.

21. The method of any one of claims 16 to 20.

22. regrowing the conductive barrier layer performing a second etch to remove a portion of the regrown conductive barrier layer surrounding the stack so that a portion of the regrown conductive barrier layer extends substantially parallel to the first current blocking layer.

22. The method of any one of claims 16 to 21.

23. providing a semiconductor stack, growing a second current blocking layer on the active region; 23. The method of any one of claims 18 to 22.

24. 24. The method according to any one of claims 16 to 23, wherein growing the first and / or second current blocking layer comprises growing a plurality of layers of different doping, in particular an npnp and / or pnpn multilayer structure when viewed in the direction of the active region.

25. The first current blocking layer and / or the second current blocking layer are a thickness of about 100 nm or greater; for each layer of the plurality of layers, a thickness in the range of several tens of nanometers; the same material as one of the n-doped and p-doped layers, in particular the layer in conductive contact with the regrown conductive material; and one or more layers of doped AlInP semiconductor material; 25. The method of any one of claims 16 to 24.

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