T-gate transistor with mini-field plate and angled gate stem

Abstract

A transistor comprising: a channel layer; an epitaxial barrier layer on the channel layer; an epitaxial cap layer on the epitaxial barrier layer; a dielectric layer on the epitaxial cap layer having an opening through the epitaxial barrier layer; a gate (301) with angled sidewalls in the opening in the dielectric layer; a mini-field plate (303) on the gate having angled sidewalls; and a gate top (305) on the mini-field plate, wherein the gate, mini-field plate, and gate top form a "T" shape, and a method for fabricating such a transistor.

Description

[Technical Field]

[0001] The present invention relates to a T-gate transistor with a mini-field plate and an angled gate stem. [Background technology]

[0002] One of the most common gate structures for semiconductor transistors is the T-gate 100 shown in Figure 1. The T-gate 100 structure consists of a gate stem 101 (e.g., a few nanometers to a few hundred nanometers) that contacts an epitaxial layer on a semiconductor substrate, and a wider top (e.g., a gate top 103 in the shape of the letter "T") that is away from the epitaxial layer. The gate stem improves the frequency response of the transistor, and the wider gate top 103 lowers the gate resistance of the transistor.

[0003] The problem with transistors with T-gates is that they can have difficulty operating under high power and high electric field conditions, which can lead to increased current collapse effects in gallium nitride (GaN) high electron mobility transistor (HEMT) devices.

[0004] Another gate structure commonly used in transistors is the gamma gate 200 shown in Figure 2. The gamma gate 200 also consists of a gate stem 201 and a gate top 203, but the gate stem 201 in a gamma gate transistor is typically buried in a dielectric or cap layer, and the gate top 203 is located much closer to the transistor substrate. The sidewalls of the gate stem 201 and the overhang of the gate top 203 act as field plates 205 that buffer the electric field near the gate stem 201.

[0005] The problem with gamma-gated transistors is that as the gate top approaches the substrate, capacitive loading increases the effective gate length, so gamma-gated transistors can be difficult to make efficient at high frequencies. Summary of the Invention [Problem to be solved by the invention]

[0006] In accordance with the concepts described herein, exemplary transistors with mini-field plates and angled gate stems (eg, mini-field plate gate transistors) and methods are provided.

[0007] In accordance with the concepts described herein, the exemplary transistor with a mini-field plate and angled gate stem and method provides a transistor with a gate structure having three sections: a gate stem, a mini-field plate, and a gate top. [Means for solving the problem]

[0008] In one aspect, a transistor comprises a channel layer, an epitaxial barrier layer on the channel layer, an epitaxial cap layer on the epitaxial barrier layer, a dielectric layer on the epitaxial cap layer having an opening to the epitaxial barrier layer, a gate with angled sidewalls in the opening in the dielectric layer, a mini-field plate with angled sidewalls on the gate, and a gate top on the mini-field plate, wherein the gate, mini-field plate, and gate top form a "T" shape.

[0009] The transistor may further include one or more of the following features: the gate has a length in a range from about 20 nanometers (nm) to about 500 nm, the mini-field plate has a width in a range from about 1.5 to 4 times the length of the gate stem, and / or the angled sidewalls of the gate have an exterior angle at their horizontal base in a range from about 45 degrees to 89 degrees, and the angled sidewalls of the mini-field plate have an exterior angle at their horizontal base in a range from about 45 degrees to 89 degrees.

[0010] In another aspect, a transistor comprises a channel layer, an epitaxial barrier layer on the channel layer, an epitaxial cap layer on the epitaxial barrier layer having an opening to the epitaxial barrier layer, a dielectric layer on the epitaxial cap layer having openings to the epitaxial cap layer and the epitaxial barrier layer, a gate with angled sidewalls at the openings in the epitaxial cap layer and the dielectric layer, a mini-field plate on the gate with angled sidewalls, and a gate top on the mini-field plate, wherein the gate, mini-field plate, and gate top form a "T" shape.

[0011] In another aspect, a transistor comprises a channel layer, an epitaxial barrier layer on the channel layer, an epitaxial cap layer on the epitaxial barrier layer having an opening to the epitaxial barrier layer, a dielectric layer on the epitaxial cap layer having openings to the epitaxial cap layer and the epitaxial barrier layer, a gate with angled sidewalls in the opening in the epitaxial cap layer, a first mini-field plate with angled sidewalls on the gate in the opening in the dielectric layer, a second mini-field plate with angled sidewalls on the first mini-field plate, and a gate top on the second mini-field plate, wherein the first mini-field plate, the second mini-field plate, and the gate top form a "T" shape.

[0012] In another aspect, a transistor comprises a channel layer, an epitaxial barrier layer on the channel layer, a first dielectric layer on the epitaxial barrier layer having an opening thereon to the epitaxial barrier layer, a second dielectric layer on the first dielectric layer having openings thereon to the first dielectric layer and the epitaxial barrier layer, a gate with angled sidewalls in the first dielectric layer and the opening in the second dielectric layer, a mini-field plate on the gate having angled sidewalls, and a gate top on the mini-field plate, wherein the gate, mini-field plate, and gate top form a "T" shape.

[0013] In another aspect, a transistor comprises a channel layer, an epitaxial barrier layer on the channel layer, a first dielectric layer on the epitaxial barrier layer having an opening thereon to the epitaxial barrier layer, a second dielectric layer on the first dielectric layer having openings thereon to the first dielectric layer and the epitaxial barrier layer, a gate with angled sidewalls in the opening in the first dielectric layer, a first mini-field plate with angled sidewalls on the gate in the opening in the second dielectric layer, a second mini-field plate with angled sidewalls on the first mini-field plate, and a gate top on the second mini-field plate, wherein the gate, first mini-field plate, second mini-field plate, and gate top form a "T" shape. [Brief explanation of the drawings]

[0014] The methods and processes for making and using the disclosed embodiments may be understood by reference to the accompanying drawing figures. It should be understood that the components and structures shown in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the concepts described herein. Like reference characters designate corresponding parts throughout the different views. Moreover, embodiments are illustrated in the drawings by way of example, and not by way of limitation.

[0015] [Figure 1] 1 is a cross-sectional photograph of a prior art transistor with a T-gate. [Figure 2] 1 is a cross-sectional photograph of a prior art transistor with a gamma gate. [Figure 3] 1A and 1B are photographs of an exemplary embodiment of a transistor with a T-gate having an angled gate stem. [Figure 4] FIG. 1 illustrates an exemplary embodiment of a cross section of a transistor with a T-gate having an angled gate stem contacting an epitaxial cap layer and a mini-field plate. [Figure 5]FIG. 1 is a diagram of an exemplary embodiment of a cross section of a transistor with a T-gate having an angled gate stem contacting an epitaxial barrier layer through an epitaxial cap layer and a mini-field plate. [Figure 6] FIG. 1 is a diagram of an exemplary embodiment of a cross section of a transistor with a T-gate having an angled gate stem contacting an epitaxial barrier layer and having two mini-field plates. [Figure 7] FIG. 1 is a diagram of an exemplary embodiment of a cross section of a transistor with a T-gate having an angled gate stem contacting an epitaxial barrier layer through two dielectric layers and a mini-field plate. [Figure 8] FIG. 1 is a diagram of an exemplary embodiment of a cross section of a transistor with a T-gate having an angled gate stem contacting an epitaxial barrier layer through two dielectric layers and having two mini-field plates. [Figure 9] 5A-5G are diagrams of exemplary process steps for forming the transistor of FIG. [Figure 10] 6A-6H are diagrams of exemplary process steps for forming the transistor of FIG. [Figure 11] 1 is an exemplary method for forming a transistor with a T-gate having an angled gate stem and a mini-field plate. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present disclosure provides exemplary methods and apparatus for transistors with at least one mini-field plate and angled gate stem (e.g., mini-field plate gate transistors). The present disclosure applies to HEMT devices and all lateral field effect transistors (FETs) or transistors.

[0017] 3 is a photograph of an exemplary embodiment of a transistor 300 with a T-gate having an angled gate stem 301. The transistor 300 comprises a gate structure having three sections: the gate stem 301, a mini-field plate 303 (e.g., a mini-FP), and a gate top 305.

[0018] 4 is a diagram of an exemplary embodiment of a cross section of a transistor 300 with a T-gate having an angled gate stem 301 contacting an epitaxial (epi)cap layer 403 (e.g., an epitaxial layer that overlies or "caps" another epitaxial layer). The transistor 300 comprises a channel layer 400, an epitaxial barrier layer 401 on the channel layer 400, an epitaxial cap layer 403 on the epitaxial barrier layer 401, a dielectric layer 405 on the epitaxial cap layer 403, a gate stem 301 on the epitaxial cap layer 403, a mini-field plate 303 on the gate stem 301, and a gate top 305 on the mini-field plate 303. In an exemplary embodiment, the gate stem 301, the mini-field plate 303, and the gate top 305 comprise the metals nickel (Ni), platinum (Pt), and gold (Au), respectively. However, the present disclosure is not limited thereto. In the exemplary embodiment, the substrate includes a channel layer 400 .

[0019] The epitaxial cap layer 403 may be lattice-matched to the epitaxial barrier layer 401 or may be mislattice-matched to the epitaxial barrier layer 401. The epitaxial cap layer 403 may comprise any semiconducting Group III nitride.

[0020] The gate stem 301 contacts the epitaxial cap layer 403. In exemplary embodiments in which the substrate includes the channel layer 400, the substrate includes gallium nitride (GaN). However, the disclosure is not limited thereto. In exemplary embodiments in which the substrate includes the channel layer 400, the substrate may also include gallium arsenide (GaAs), sapphire, indium phosphide (InP), silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), or indium antimony (InSb).

[0021] The size (e.g., gate length) of the gate stem 301 may range from a few nanometers (e.g., about 20-30 nm) to hundreds of nanometers (e.g., 300-500 nm or more). The angled sidewalls of the gate stem 301 may be formed by etching the dielectric layer 405. In an exemplary embodiment, the dielectric layer 405 includes silicon nitride (SiN), and the epitaxial cap layer 403 includes aluminum gallium nitride (AlGaN). However, the present disclosure is not limited thereto. The gate stem 301 may have an exterior angle of 45-89 degrees at the base of the gate stem 301. The closer the metal is to the substrate 400, the higher the capacitance and the stronger the electric field between the metal and the substrate 400. Controlling the angle of the gate stem 301 controls the effect of the electric field. Reducing the angle of the gate stem 301 reduces the effect of the electric field. Increasing the angle of the gate stem 301 increases the effect of the electric field. The gate stem 301 may be formed using lithography and etching steps.

[0022] The mini-FP 303 may be on a dielectric layer 405, which may be on an epitaxial cap layer 403. The mini-FP 303 may be wider than the length of the gate stem 301. In an exemplary embodiment, the mini-FP 303 may be 1.5 to 4 times wider than the length of the gate stem 301. However, the disclosure is not limited in this respect. The wider the mini-FP 303, the lower the lateral electric field on the gate stem 301. The narrower the mini-FP 303, the higher the lateral electric field on the gate stem 301. The width of the mini-FP 303 does not affect the vertical electric field on the gate stem 301.

[0023] The angled sidewalls of the mini-FP 303 may be formed at an angle relative to the base of the mini-FP 303. In an exemplary embodiment, the outer angle of the mini-FP 303 may be between 45 degrees and 89 degrees. The closer the metal is to the channel layer 400, the higher the capacitance and the stronger the electric field between the metal and the channel layer 400. Controlling the angle of the mini-FP 303 controls the effect of the electric field. Reducing the angle of the mini-FP 303 increases the effect of the electric field. Increasing the angle of the mini-FP 303 decreases the effect of the electric field. If the outer angle of the mini-FP 303 is too large, the gate top 305 may become unstable and collapse. The mini-FP 303 may be formed simultaneously with the gate top 305 and may be self-aligned to the gate top 305. The center of the mini-FP 303 may be aligned with the center of the gate stem 301 or may be offset to either side of the center of the gate stem 301.

[0024] The gate top 305 may be the largest feature of the gate of the transistor 300 in terms of cross-sectional area and may connect to the mini-FP 303. The gate top 305 may not directly contact the dielectric layer 405, the epitaxial cap layer 403, or the epitaxial barrier layer 401. The gate top 305 may be wider than the mini-FP 303 and may have two wings branching off from either side of the mini-FP 303. The dimensions of the gate top 305 may be equal to or greater than the dimensions of the mini-FP 303. In an exemplary embodiment, the width of the gate top 305 may be approximately 400-1000 nm. If the gate top 305 is too wide or thick, it may become unstable and detach from the mini-FP 303 and the gate stem 301.

[0025] Transistor 300 with angled gate stem 301, mini-FP 303, and gate top 305 combines the advantages of both prior art T-gate and gamma-gate transistors. The gate structure of transistor 300 is controlled by the angle of gate stem 301, the width of mini-FP 303, and the contact angle between mini-FP 303 and dielectric layer 405. The angle of gate stem 301 across dielectric layer 405 can be customized by an etching process. The width of mini-FP 303 can be customized by lithography. The contact angle between mini-FP 303 and dielectric layer 405 can be customized by photoresist and lithography. Transistor 300 can operate at higher frequencies and voltages than prior art T-gate transistors.

[0026] 5 is a diagram of an exemplary embodiment of a cross section of a transistor 500 with a T-gate having an angled gate stem 509 contacting an epitaxial barrier layer 503. The transistor 500 comprises a channel layer 501, an epitaxial barrier layer 503 on the channel layer 501, an epitaxial cap layer 505 on the epitaxial barrier layer 503, a dielectric layer 507 on the epitaxial cap layer 505, a gate stem 509 on the epitaxial barrier layer 503, a mini-field plate 511 on the gate stem 509, and a gate top 513 on the mini-field plate 511. In an exemplary embodiment, the gate stem 509, the mini-field plate 511, and the gate top 513 comprise the metals Ni, Pt, and Au, respectively. However, the present disclosure is not limited in this respect. In an exemplary embodiment, a substrate comprises the channel layer 501.

[0027] Gate stem 509 contacts epitaxial barrier layer 503. In an exemplary embodiment in which a substrate includes channel layer 501, the substrate includes GaN. However, the disclosure is not limited in this respect. The substrate may also include GaAs, sapphire, InP, Si, SiC, AlN, or InSb.

[0028] The size (e.g., gate length) of the gate stem 509 may range from a few nanometers (e.g., about 20-30 nm) to hundreds of nanometers (e.g., 300-500 nm or more). The angled sidewalls of the gate stem 509 may be formed by etching the dielectric layer 507 and the epitaxial cap layer 505. In an exemplary embodiment, the dielectric layer 507 comprises SiN and the epitaxial cap layer 505 comprises AlGaN. However, the present disclosure is not limited in this respect. The gate stem 509 may have an exterior angle of 45 to 89 degrees at the base of the gate stem 509. The gate stem 509 may be formed using lithography and etching steps.

[0029] The mini-FP 511 may be on the dielectric layer 507, which may be on the epitaxial cap layer 505. The mini-FP 511 may be wider than the length of the gate stem 509. In an exemplary embodiment, the mini-FP 511 may be 1.5 to 4 times wider than the length of the gate stem 509. However, the present disclosure is not limited in this respect.

[0030] The angled sidewalls of the mini-FPs 511 may be formed at an angle relative to the base of the mini-FPs 511. In an exemplary embodiment, the outer angle of the mini-FPs 511 may be between 45 degrees and 89 degrees. If the outer angle of the mini-FPs 511 is too large, the gate top 513 may become unstable and may collapse. The mini-FPs 511 may be formed simultaneously with the gate top 513 and may be self-aligned to the gate top 513. The center of the mini-FPs 513 may be aligned with the center of the gate stem 509 or may be offset to either side of the center of the gate stem 509.

[0031] The gate top 513 may be the largest feature of the gate of the transistor 500 in terms of cross-sectional area and may be connected to the mini-FP 511. The gate top 513 may not directly contact the dielectric layer 507, the epitaxial cap layer 505, or the epitaxial barrier layer 503. The gate top 513 may be wider than the mini-FP 511 and have two wings branching off on either side of the mini-FP 511. The dimensions of the gate top 513 may be equal to or greater than the dimensions of the mini-FP 511. In an exemplary embodiment, the width of the gate top 513 may be approximately 400-1000 nm. If the gate top 513 is too wide or thick, the gate top 513 may become unstable and may become detached from the mini-FP 511 and the gate stem 509.

[0032] Transistor 500 with angled gate stem 509, mini-FP 511, and gate top 513 combines the advantages of both prior art T-gate and gamma-gate transistors. The gate structure of transistor 500 is controlled by the angle of gate stem 509, the width of mini-FP 511, and the contact angle between mini-FP 511 and dielectric layer 507. The angle of gate stem 509 across dielectric layer 507 and epicap layer 505 can be customized by etching processes. The width of mini-FP 511 can be customized by lithography. The contact angle between mini-FP 511 and dielectric layer 507 can be customized by photoresist and lithography. Transistor 500 can operate at higher frequencies and voltages than prior art T-gate transistors.

[0033] 6 is a diagram of an exemplary embodiment of a cross section of a transistor 600 with a T-gate having an angled gate stem 609 in contact with an epitaxial barrier layer 603 and having a first mini-field plate 611 and a second mini-field plate 613. The transistor 600 comprises a channel layer 601, an epitaxial barrier layer 603 on the channel layer 601, an epitaxial cap layer 605 on the epitaxial barrier layer 603, a dielectric layer 607 on the epitaxial cap layer 605, a gate stem 609 on the epitaxial barrier layer 603, a first mini-field plate 611 on the gate stem 609, a second mini-field plate 613 on the first mini-field plate 611, and a gate top 615 on the second mini-field plate 613. In an exemplary embodiment, the gate stem 609, the first mini-field plate 611, the second mini-field plate 613, and the gate top 615 comprise the metals Ni, Pt, and Au, respectively. However, the present disclosure is not limited in this respect. In an exemplary embodiment, the substrate comprises a channel layer 601.

[0034] Gate stem 609 contacts epitaxial barrier layer 603. In an exemplary embodiment in which a substrate includes channel layer 601, the substrate may be GaN. However, the disclosure is not limited in this respect. The substrate may also include GaAs, sapphire, InP, Si, SiC, AlN, or InSb.

[0035] The size (e.g., gate length) of the gate stem 609 may range from a few nanometers (e.g., about 20-30 nm) to hundreds of nanometers (e.g., 300-500 nm or more). The angled sidewalls of the gate stem 609 may be formed by etching the epitaxial cap layer 605. In an exemplary embodiment, the epitaxial cap layer 605 comprises AlGaN. However, the present disclosure is not limited thereto. The gate stem 609 may have an exterior angle of 45-89 degrees at the base of the gate stem 609. The gate stem 609 may be formed using lithography and etching steps.

[0036] The angled sidewalls of the first mini-field plate 611 may be formed by etching the dielectric layer 607. In an exemplary embodiment, the dielectric layer 607 includes SiN. However, the present disclosure is not limited thereto. The first mini-field plate 611 may have an exterior angle of 45 to 89 degrees at the base of the first mini-field plate 611. The first mini-FP 611 may be on the epicap layer 605. The first mini-FP 611 may be wider than the length of the gate stem 609. In an exemplary embodiment, the first mini-FP 611 may be 1.5 to 4 times the width of the length of the gate stem 609. However, the present disclosure is not limited thereto. The advantages of having a first mini FP611 and a second mini FP613 include reduced leakage current, reduced dispersion, improved breakdown voltage, improved current density, and better control of tuning / grading performance by setting a fixed width difference between the first mini FP611 and the second mini FP613.

[0037] If the outer angle of the first mini-FP 611 is too small, the second mini-field plate 613 and gate top 615 may become unstable and collapse. The first mini-FP 611 may be formed simultaneously with the second mini-FP 613 and gate top 615 and may be self-aligned to the second mini-FP 613 and gate top 615. The center of the first mini-FP 611 may be aligned with the center of the gate stem 609 or may be offset to either side of the center of the gate stem 609.

[0038] The angled sidewalls of the second mini-field plate 613 may be formed by etching a photoresist deposited on the dielectric layer 607. In an exemplary embodiment, the photoresist may be polymethyl methacrylate (PMMA), Zeon electron-beam positive-tone resist (ZEP), polydimethylglutarimide (PMGI), methyl methacrylate (MMA), or other resist compatible with electron-beam lithography. In an exemplary embodiment, the dielectric layer 607 includes SiN. However, the present disclosure is not limited thereto. The second mini-field plate 613 may have an exterior angle of 45 to 89 degrees at the base of the second mini-field plate 613. The second mini-FP 613 may be on the dielectric layer 607. The second mini-FP 613 may be wider than the length of the gate stem 609 and wider than the width of the first mini-FP 611. In an exemplary embodiment, the second mini-FP 613 may be 1.5 to 4 times as wide as the length of the gate stem 609 and may be larger than the first mini-FP, although the present disclosure is not limited in this respect.

[0039] If the outer angle of the second mini FP 613 is too large, the gate top 615 may become unstable and collapse. The second mini FP 613 may be formed simultaneously with the gate top 615 and may be self-aligned to the gate top 615. The center of the second mini FP 613 may be aligned with the center of the gate stem 609 or may be offset to either side of the center of the gate stem 609.

[0040] The gate top 615 may be the largest feature of the gate of the transistor 600 in terms of cross-sectional area and may connect to the mini-FP 613. The gate top 615 may not directly contact the dielectric layer 607, the epitaxial cap layer 605, or the epitaxial barrier layer 603. The gate top 615 may be wider than the second mini-FP 613 and may have two wings branching off on either side of the second mini-FP 613. The dimensions of the gate top 615 may be equal to or greater than the dimensions of the second mini-FP 613. In an exemplary embodiment, the width of the gate top 615 may be approximately 400-1000 nm. If the gate top 615 is too wide or thick, it may become unstable and detach from the mini-FP 613 and the gate stem 609.

[0041] Transistor 600, with its angled gate stem 609, first mini-FP 611, second mini-FP 613, and gate top 615, combines the advantages of both prior art T-gate and gamma-gate transistors. The gate structure of transistor 600 is controlled by the angle of gate stem 609, the width of first mini-FP 611, the width of second mini-FP 613, the contact angle of first mini-FP 611, the contact angle of second mini-FP 613, and dielectric layer 607. The angle of gate stem 609 across epicap layer 605 can be customized by an etching process. The widths of first mini-FP 611 and second mini-FP 613 can be customized by lithography. The contact angles of first mini-FP 611, second mini-FP 613, and dielectric layer 607 can be customized by photoresist and lithography. Transistor 600 can operate at higher frequencies and voltages than prior art T-gate transistors.

[0042] 7 is a diagram of an exemplary embodiment of a cross section of a transistor 700 comprising a T-gate with an angled gate stem 709 contacting an epitaxial barrier layer 703. The transistor 700 comprises a channel layer 701, an epitaxial barrier layer 703 on the channel layer 701, a first dielectric layer 705 on the epitaxial barrier layer 703, a second dielectric layer 707 on the first dielectric layer 705, a gate stem 709 on the epitaxial barrier layer 703, a mini-field plate 711 on the gate stem 709, and a gate top 713 on the mini-field plate 711. In an exemplary embodiment, the gate stem 709, the mini-field plate 711, and the gate top 713 comprise the metals Ni, Pt, and Au, respectively. However, the present disclosure is not limited in this respect. In an exemplary embodiment, a substrate comprises the channel layer 701.

[0043] Gate stem 709 contacts epitaxial barrier layer 703. In an exemplary embodiment in which a substrate includes channel layer 701, the substrate includes GaN. However, the disclosure is not limited in this respect. The substrate may also include GaAs, sapphire, InP, Si, SiC, AlN, or InSb.

[0044] The size (e.g., gate length) of the gate stem 709 may range from a few nanometers (e.g., about 20-30 nm) to hundreds of nanometers (e.g., 300-500 nm or more). The angled sidewalls of the gate stem 709 may be formed by etching the second dielectric layer 707 and the first dielectric layer 705. In an exemplary embodiment, the first dielectric layer 705 and the second dielectric layer 707 may be the same or different. In an exemplary embodiment, the first dielectric layer 705 and the second dielectric layer 707 each comprise an oxide, a nitride, a silicon nitride, an aluminum silicon nitride, or silicon dioxide. However, the present disclosure is not limited thereto. The gate stem 709 may have an exterior angle of 45 to 89 degrees at the base of the gate stem 709. The gate stem 709 may be formed using lithography and etching steps.

[0045] The mini FP 711 may be on the second dielectric layer 707, which may be on the first dielectric layer 705. The mini FP 711 may be wider than the length of the gate stem 709. In an exemplary embodiment, the mini FP 711 may be 1.5 to 4 times wider than the length of the gate stem 709. However, the present disclosure is not limited in this respect.

[0046] The angled sidewalls of the mini-FP711 may be formed at an angle relative to the base of the mini-FP711. In an exemplary embodiment, the outer angle of the mini-FP711 may be between 45 degrees and 89 degrees. If the outer angle of the mini-FP711 is too large, the gate top713 may become unstable and may collapse. The mini-FP711 may be formed simultaneously with the gate top713 and may be self-aligned to the gate top713. The center of the mini-FP711 may be aligned with the center of the gate stem709 or may be offset to either side of the center of the gate stem709.

[0047] The gate top 713 may be the largest feature of the gate of the transistor 700 in terms of cross-sectional area and may connect to the mini-FP 711. The gate top 713 may not directly contact the second dielectric layer 707, the first dielectric layer 705, or the epitaxial layer 703. The gate top 713 may be wider than the mini-FP 711 and may have two wings branching off on either side of the mini-FP 711. The dimensions of the gate top 713 may be equal to or greater than the dimensions of the mini-FP 711. In an exemplary embodiment, the width of the gate top 713 may be approximately 400-1000 nm. If the gate top 713 is too wide or thick, the gate top 713 may become unstable and may become dislodged from the mini-FP 711 and the gate stem 709.

[0048] Transistor 700, with its angled gate stem 709, mini-FP 711, and gate top 713, combines the advantages of both prior art T-gate and gamma-gate transistors. The gate structure of transistor 700 is controlled by the angle of gate stem 709, the width of mini-FP 711, and the contact angle between mini-FP 711 and dielectric layer 707. The angle of gate stem 709 across second dielectric layer 707 and first dielectric layer 705 can be customized by an etching process. The width of mini-FP 711 can be customized by lithography. The contact angle between mini-FP 711 and second dielectric layer 707 can be customized by photoresist and lithography. Transistor 700 can operate at higher frequencies and voltages than prior art T-gate transistors.

[0049] 8 is a diagram of an exemplary embodiment of a cross section of a transistor 800 with a T-gate having an angled gate stem 809 in contact with an epitaxial barrier layer 803 and having a first mini-field plate 811 and a second mini-field plate 813. Transistor 800 comprises a channel layer 801, an epitaxial barrier layer 803 on the channel layer 801, a first dielectric layer 805 on the epitaxial barrier layer 803, a second dielectric layer 807 on the first dielectric layer 805, a gate stem 809 on the epitaxial barrier layer 803, a first mini-field plate 811 on the gate stem 809, a second mini-field plate 813 on the first mini-field plate 811, and a gate top 815 on the second mini-field plate 813. In an exemplary embodiment, the gate stem 809, the first mini-field plate 811, the second mini-field plate 813, and the gate top 815 comprise the metals Ni, Pt, and Au, respectively. However, the present disclosure is not limited in this respect. In an exemplary embodiment, the substrate comprises a channel layer 801.

[0050] Gate stem 809 contacts epitaxial barrier layer 803. In an exemplary embodiment in which a substrate includes channel layer 801, the substrate includes GaN. However, the disclosure is not limited in this respect. The substrate may also include GaAs, sapphire, InP, Si, SiC, AlN, or InSb.

[0051] The size (e.g., gate length) of the gate stem 809 may range from a few nanometers (e.g., about 20-30 nm) to hundreds of nanometers (e.g., 300-500 nm or more). The angled sidewalls of the gate stem 809 may be formed by etching the first dielectric layer 805. In an exemplary embodiment, the first dielectric layer 805 comprises SiN. However, the present disclosure is not limited in this respect. The gate stem 809 may have an exterior angle of 45 to 89 degrees at the base of the gate stem 809. The gate stem 809 may be formed using lithography and etching steps.

[0052] The angled sidewalls of the first mini-field plate 811 may be formed by etching the second dielectric layer 807. In an exemplary embodiment, the second dielectric layer 807 comprises SiN. However, the present disclosure is not limited thereto. The first mini-field plate 811 may have an exterior angle of 45 to 89 degrees at the base of the first mini-field plate 811. The first mini-FP 811 may be on the first dielectric layer 805. The first mini-FP 811 may be wider than the length of the gate stem 809. In an exemplary embodiment, the first mini-FP 811 may be 1.5 to 4 times the width of the length of the gate stem 809. However, the present disclosure is not limited thereto.

[0053] If the outer angle of the first mini-FP 811 is too large, the second mini-field plate 813 and the gate top 815 may become unstable and collapse. The first mini-FP 811 may be formed simultaneously with the second mini-FP 813 and the gate top 815 and may be self-aligned to the second mini-FP 813 and the gate top 815. The center of the first mini-FP 811 may be aligned with the center of the gate stem 809 or may be offset to either side of the center of the gate stem 809.

[0054] The angled sidewalls of the second mini-field plate 813 may be formed by etching a photoresist deposited on the second dielectric layer 807. In an exemplary embodiment, the photoresist may be PMMA, ZEP, PMGI, or MMA. In an exemplary embodiment, the second dielectric layer 807 includes SiN. However, the present disclosure is not limited thereto. The second mini-field plate 813 may have an exterior angle of 45 to 89 degrees at the base of the second mini-field plate 813. The second mini-FP 813 may be on the second dielectric layer 807. The second mini-FP 813 may be wider than the length of the gate stem 809 and wider than the width of the first mini-FP 811. In an exemplary embodiment, the second mini-FP 813 may be 1.5 to 4 times the length of the gate stem 809. However, the present disclosure is not limited thereto.

[0055] If the outer angle of the second mini FP 813 is too large, the gate top 815 may become unstable and collapse. The second mini FP 813 may be formed simultaneously with the gate top 815 and may be self-aligned to the gate top 815. The center of the second mini FP 813 may be aligned with the center of the gate stem 809 or may be offset to either side of the center of the gate stem 809.

[0056] The gate top 815 may be the largest feature of the gate of the transistor 800 in terms of cross-sectional area and may be connected to the mini-FP 813. The gate top 815 may not directly contact the second dielectric layer 807, the first dielectric layer 805, or the epitaxial layer 803. The gate top 815 may be wider than the second mini-FP 813 and may have two wings branching off on either side of the second mini-FP 813. The dimensions of the gate top 815 may be equal to or greater than the dimensions of the second mini-FP 813. In an exemplary embodiment, the width of the gate top 815 may be approximately 400-1000 nm. If the gate top 815 is too wide or thick, the gate top 815 may become unstable and may become detached from the mini-FP 813 and the gate stem 809.

[0057] Transistor 800, with its angled gate stem 809, first mini-FP 811, second mini-FP 813, and gate top 815, combines the advantages of both prior art T-gate and gamma-gate transistors. The gate structure of transistor 800 is controlled by the angle of gate stem 809, the width of first mini-FP 811, the width of second mini-FP 813, the contact angle of first mini-FP 811, the contact angle of second mini-FP 813, and dielectric layer 807. The angle of gate stem 809 is customizable through an etching process across dielectric layer 805. The widths of first mini-FP 811 and second mini-FP 813 are customizable through lithography. The contact angles of first mini-FP 811, second mini-FP 813, and second dielectric layer 807 are customizable through photoresist and lithography. Transistor 800 can operate at higher frequencies and voltages than prior art T-gate transistors.

[0058] 9A, 9B, 9C, 9D, 9E, 9F, and 9G are diagrams of exemplary process steps for forming transistor 300 of FIG.

[0059] 9A, a channel layer 400 may be fabricated or obtained, an epitaxial barrier layer 401 may be grown on the channel layer 400, an epitaxial cap layer 403 may be grown on the epitaxial barrier layer 401, and a dielectric layer 405 may be deposited on the epitaxial cap layer 403. The channel layer 400 may be GaN, GaAs, sapphire, InP, Si, SiC, AlN, or InSb. The epitaxial cap layer 403 may include an AlGaN barrier layer. The dielectric layer 405 may be formed using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD). The dielectric layer 405 may be an oxide (e.g., aluminum oxide (AlO) or silicon dioxide (SiO)) or a nitride (e.g., silicon nitride (SiN)).

[0060] 9B, a first photoresist layer 407 may be deposited and patterned (e.g., portions of the first photoresist layer 407 are selectively removed) on the dielectric layer 405. The first photoresist layer 407 may be PMMA, ZEP, PMGI, or MMA. The first photoresist layer 407 may be patterned by electron beam (e-beam). The pattern removed from the first photoresist layer 407 may be used to define the gate stem 301 of the transistor 300.

[0061] 9C, the pattern in the first photoresist layer 407 may be used to etch away the pattern from the dielectric layer 405. The etching may be done by dry etching or wet etching. For dry etching, fluorine (e.g., carbon tetrafluoride (CF4)) or chlorine may be used.

[0062] In FIG. 9D , the first photoresist layer 407 may be removed. A solvent bath may be used to remove the first photoresist layer 407. In FIG. 9E , a second photoresist layer 409 may be deposited and patterned on the dielectric layer 405. The second photoresist layer 409 may be any of the materials used for the first photoresist layer 407 described above. The second photoresist layer 409 may be deposited, etched, and removed using any of the materials and methods described above for depositing, etching, and removing the first photoresist layer 407. The second photoresist layer 409 may be used to define the mini-FP 303 of the transistor 300.

[0063] 9F, a third photoresist layer 411 may be deposited and patterned on the second photoresist layer 409. The third photoresist layer 411 may be any of the materials used for the first photoresist layer 407 described above. The third photoresist layer 411 may be deposited, etched, and removed using any of the materials and methods described above for depositing, etching, and removing the first photoresist layer 407. The third photoresist layer 411 may be used to define the gate top 305 of the transistor 300.

[0064] In FIG. 9G, a metal may be deposited to simultaneously form the gate stem 301, the mini FP 303, and the gate top 305, and the third photoresist layer 411 may be removed. The metal may be nickel (Ni), titanium (Ti), platinum (Pt), tungsten (W), tantalum (TaN), titanium nitride (TiN), or gold (Au). The deposition method may include thermal evaporation, chemical vapor deposition, or atomic layer deposition. In alternative embodiments, the gate stem 301, the mini FP 303, and the gate top 305 may be formed of the same or different metals in any suitable combination. In an exemplary embodiment, the gate stem 301 may be a metal having a high work function (e.g., Pt), and the mini FP 303 and the gate top 305 may be a metal having a low resistivity (e.g., Au). The metal deposited on the third photoresist layer 411 may be removed by a solvent in a metal lift-off process. The solvent may be acetone, isopropyl alcohol, or a positive resist stripper (PRS).

[0065] 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H are diagrams of exemplary process steps for forming the transistor 500 of FIG.

[0066] 10A , a substrate 501 including a channel layer may be manufactured or obtained, an epitaxial barrier layer 503 may be grown on the channel layer 501, an epitaxial cap layer 505 may be grown on the epitaxial barrier layer 503, and a dielectric layer 507 may be deposited on the epitaxial cap layer 505. In an exemplary embodiment, the substrate includes GaN, GaAs, sapphire, InP, Si, SiC, AlN, or InSb. The epitaxial cap layer 505 may include an AlGaN barrier layer. The dielectric layer 507 may be formed using CVD, PECVD, or ALD. The dielectric layer 507 may be Al2O3, SiN, or SiO2.

[0067] 10B, a first photoresist layer 508 may be deposited on the dielectric layer 507 and patterned (e.g., portions of the first photoresist layer 508 are selectively removed). The first photoresist layer 508 may be PMMA, ZEP, PMGI, or MMA. The first photoresist layer 508 may be patterned by electron beam (e-beam). The pattern removed from the first photoresist layer 508 may be used to define the gate stem 509 of the transistor 500.

[0068] In Figure 10C, the pattern in the first photoresist layer 508 may be used to etch away a pattern from the dielectric layer 507. In Figure 10D, the pattern in the first photoresist layer 508 may be used to etch away a pattern from the epitaxial cap layer 505. The etching may be done by dry etching or wet etching. Fluorine (e.g., carbon tetrafluoride (CF4)) or chlorine may be used for dry etching.

[0069] In FIG. 10E, the first photoresist layer 508 is removed. A solvent bath may be used to remove the first photoresist layer 508. In FIG. 10F, a second photoresist layer 508A is deposited and patterned on the dielectric layer 507. The second photoresist layer 508A may be any of the materials used for the first photoresist layer 508 described above. The second photoresist layer 508A may be deposited, etched, and removed using any of the materials and methods described above for depositing, etching, and removing the first photoresist layer 508. The second photoresist layer 508A may be used to define the mini-FP 511 of the transistor 500.

[0070] 10G, a third photoresist layer 508B is deposited and patterned on the second photoresist layer 508A. The third photoresist layer 508B may be any of the materials used for the first photoresist layer 508 described above. The third photoresist layer 508B may be deposited, etched, and removed using any of the materials and methods described above for depositing, etching, and removing the first photoresist layer 508. The third photoresist layer 508B may be used to define the gate top 513 of the transistor 500.

[0071] In FIG. 10H, a metal is deposited to simultaneously form the gate stem 509, the mini FP 511, and the gate top 513, and the third photoresist layer 508B is removed. The metal may be Ni, Ti, Pt, W, TaN, TiN, or Au. The deposition method may include thermal evaporation, chemical vapor deposition, or atomic layer deposition. In alternative embodiments, the gate stem 509, the mini FP 511, and the gate top 513 may be formed of the same or different metals in any suitable combination. In an exemplary embodiment, the gate stem 509 may be a metal having a high work function (e.g., Pt), and the mini FP 511 and the gate top 513 may be a metal having a low resistivity (e.g., Au). Any metal deposited on the third photoresist layer 508B may be removed by a solvent in a metal lift-off process. The solvent may be acetone, isopropyl alcohol, or PRS. Transistors 600, 700, and 800 of Figures 6, 7, and 8 may be processed similarly to Figures 9A, 9B, 9C, 9D, 9E, 9F, 9G, 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H, with appropriate modifications due to structural differences between the transistors.

[0072] 11 is an exemplary method for forming a transistor with a T-gate having an angled gate stem and a mini-field plate. In an exemplary embodiment, method 1100 includes obtaining a channel layer in step 1101. The channel layer may be obtained by fabricating or growing a channel layer or by purchasing a substrate with a channel layer. In an exemplary embodiment in which the channel layer includes a substrate, the substrate includes GaN, GaAs, sapphire, InP, Si, SiC, AlN, or InSb.

[0073] Step 1103 includes growing an epitaxial barrier layer on the channel layer. If the obtained substrate includes an epitaxial barrier layer, this step may be optional. Step 1105 includes growing an epitaxial cap layer on the epitaxial barrier layer. The epitaxial cap layer may include an AlGaN barrier layer.

[0074] Step 1107 includes depositing a dielectric layer on the epitaxial cap layer. The dielectric layer may be formed using CVD, PECVD, or ALD. The dielectric layer may be Al2O3, SiN, or SiO2.

[0075] Step 1109 includes depositing a first photoresist layer over the dielectric layer, which may be PMMA, ZEP, PMGI, or MMA.

[0076] Step 1111 includes patterning a first photoresist layer on the dielectric layer (e.g., selectively removing portions of the first photoresist layer). The first photoresist layer may be patterned by an electron beam. The pattern removed from the first photoresist layer may be used to define the gate stem 301 of the transistor 300.

[0077] Step 1113 includes etching the pattern of the first photoresist layer away from the dielectric layer. The etching may be performed by dry etching or wet etching. Dry etching may use fluorine (e.g., carbon tetrafluoride (CF4)) or chlorine.

[0078] Step 1115 includes removing the first photoresist layer. A solvent bath may be used to remove the first photoresist layer.

[0079] Step 1117 includes depositing a second photoresist layer on the dielectric layer. The second photoresist layer may be any of the materials used for the first photoresist layer described above. The second photoresist layer may be deposited, etched, and removed using any of the materials and methods described above for depositing, etching, and removing the first photoresist layer.

[0080] Step 1119 includes patterning a second photoresist layer on the dielectric layer. The second photoresist layer may be used to define the mini-FP 303 of the transistor 300.

[0081] Step 1121 includes depositing a third photoresist layer on the second photoresist layer. The third photoresist layer may be any of the materials used for the first photoresist layer described above. Any of the materials and methods described above for depositing, etching, and removing the first photoresist layer may be used to deposit, etch, and remove the third photoresist layer.

[0082] Step 1123 includes patterning a third photoresist layer over the second photoresist layer. The third photoresist layer may be used to define the gate top 305 of the transistor 300.

[0083] Step 1125 includes depositing a metal to simultaneously form the gate stem, mini-FP, and gate top (e.g., gate stem 301, mini-FP 303, and gate top 305 of transistor 300). The metal may be Ni, Ti, Pt, W, TaN, TiN, or Au. The deposition method may include thermal evaporation, chemical vapor deposition, or atomic layer deposition. In alternative embodiments, gate stem 301, mini-FP 303, and gate top 305 may be formed of the same or different metals in any suitable combination. In an exemplary embodiment, gate stem 301 may be a metal having a high work function (e.g., Pt), and mini-FP 303 and gate top 305 may be a metal having a low resistivity (e.g., Au).

[0084] Step 1127 includes removing the second and third photoresist layers. The metal deposited on the third photoresist layer may be removed by a solvent in a metal lift-off process. The solvent may be acetone, isopropyl alcohol, or PRS.

[0085] Although illustrative embodiments of the present disclosure have been described, it will be apparent to those skilled in the art that other embodiments incorporating these concepts may also be used. The embodiments contained herein should not be limited to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

[0086] Elements of different embodiments described herein can be combined to form other embodiments not specifically described above. Various elements described in the context of a single embodiment may be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

[0087] Various embodiments of the concepts, systems, devices, structures, and techniques for which protection is sought are described herein with reference to the associated drawings. As noted above, in embodiments, the concepts and features described herein may be embodied in a digital multi-beam beamforming system. Alternative embodiments may be contemplated without departing from the scope of the concepts, systems, devices, structures, and techniques described herein.

[0088] It should be noted that in the above description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the described concepts, systems, devices, structures, and techniques are not intended to be limiting in this regard. Thus, coupling of entities can refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships.

[0089] As an example of an indirect positional relationship, reference in this description to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layer(s). The following definitions and abbreviations shall be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or other elements inherent to such composition, mixture, process, method, article, or device.

[0090] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "one or more" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include indirect and direct "connections."

[0091] References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed to be within the knowledge of one of ordinary skill in the art that such feature, structure, or characteristic also affects such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0092] For purposes of this description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom" (to name a few) and their derivatives refer to the structures and methods described, as well as the orientation of the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, and intervening elements, such as interfacial structures, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without intervening elements. Such terms may also be referred to as directional or positional terms.

[0093] The use of ordinal numbers such as "first," "second," "third," etc. in the claims to modify claim elements does not, in itself, imply a priority, precedence, or ordering of one claim element relative to other claim elements, or a chronological order in which method actions are performed, but is merely used as a label to distinguish one claim element with a particular name from another element with the same name (other than the use of the ordinal number) to distinguish between claim elements.

[0094] The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and even in some embodiments within ±2% of a target value. The terms "approximately" and "about" may include the target value. The term "substantially equal" may be used to refer to values ​​that are in some embodiments within ±20% of each other, in some embodiments within ±10% of each other, in some embodiments within ±5% of each other, and even in some embodiments within ±2% of each other.

[0095] The term "substantially" may be used in some embodiments to refer to values ​​within ±20%, in some embodiments within ±10%, in some embodiments within ±5%, and even in some embodiments within ±2% of a comparison measurement. For example, a first direction that is "substantially" perpendicular to a second direction may in some embodiments refer to a first direction that is within ±20% of a 90° angle with the second direction, in some embodiments within ±10% of a 90° angle with the second direction, in some embodiments within ±5% of a 90° angle with the second direction, and even in some embodiments within ±2% of a 90° angle with the second direction.

[0096] It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings, as the disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways.

[0097] It is also to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. Thus, those skilled in the art will appreciate that the conception underlying the present disclosure may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out some of the purposes of the disclosed subject matter. Accordingly, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0098] While the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that the disclosure is made by way of example only and that numerous changes may be made in the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter.

Claims

1. a channel layer; an epitaxial barrier layer on the channel layer; an epitaxial cap layer on the epitaxial barrier layer; a dielectric layer on the epitaxial cap layer, the dielectric layer having an opening leading to the epitaxial barrier layer; a gate having angled sidewalls within the opening in the dielectric layer; a mini-field plate on the gate with angled sidewalls; a gate top on the mini-field plate, wherein the gate, the mini-field plate, and the gate top form a "T" shape.

2. 10. The transistor of claim 1, wherein the gate comprises a length in a range from about 20 nanometers (nm) to about 500 nm.

3. 10. The transistor of claim 1, wherein the mini-field plate has a width in the range of approximately 1.5 to 4 times the length of the gate stem.

4. 2. The transistor of claim 1 , wherein the angled sidewalls of the gate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees, and the angled sidewalls of the mini-field plate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees.

5. a channel layer; an epitaxial barrier layer on the channel layer; an epitaxial cap layer on the epitaxial barrier layer, the epitaxial cap layer having an opening leading to the epitaxial barrier layer; a dielectric layer on the epitaxial cap layer, the dielectric layer having an opening communicating with the epitaxial cap layer and the epitaxial barrier layer; a gate having angled sidewalls within the opening in the epitaxial cap layer and the dielectric layer; a mini-field plate on the gate with angled sidewalls; a gate top on the mini-field plate, wherein the gate, the mini-field plate, and the gate top form a "T" shape.

6. The transistor of claim 5 , wherein the gate has a length in a range from about 20 nanometers (nm) to about 500 nm.

7. 6. The transistor of claim 5, wherein the mini-field plate has a width in the range of about 1.5 to 4 times the length of the gate stem.

8. 6. The transistor of claim 5, wherein the angled sidewalls of the gate have an exterior angle at a horizontal base in the range of approximately 45 degrees to 89 degrees, and the angled sidewalls of the mini-field plate have an exterior angle at a horizontal base in the range of approximately 45 degrees to 89 degrees.

9. a channel layer; an epitaxial barrier layer on the channel layer; an epitaxial cap layer on the epitaxial barrier layer, the epitaxial cap layer having an opening leading to the epitaxial barrier layer; a dielectric layer on the epitaxial cap layer, the dielectric layer having an opening communicating with the epitaxial cap layer and the epitaxial barrier layer; a gate having angled sidewalls within the opening in the epitaxial cap layer; a first mini-field plate having angled sidewalls on the gate in the opening in the dielectric layer; a second mini-field plate on the first mini-field plate, the second mini-field plate having angled sidewalls; a gate top on the second mini-field plate, wherein the gate, the first mini-field plate, the second mini-field plate, and the gate top form a "T" shape.

10. 10. The transistor of claim 9, wherein the gate comprises a length in a range from about 20 nanometers (nm) to about 500 nm.

11. 10. The transistor of claim 9, wherein the first mini-field plate and the second mini-field plate each have a width in a range of about 1.5 to 4 times the length of a gate stem, the second mini-field plate being larger than the first mini-field plate.

12. 10. The transistor of claim 9, wherein the angled sidewalls of the gate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees, and the angled sidewalls of the first mini-field plate and the second mini-field plate each have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees.

13. a channel layer; an epitaxial barrier layer on the channel layer; a first dielectric layer on the epitaxial barrier layer, the first dielectric layer having an opening leading to the epitaxial barrier layer; a second dielectric layer on the first dielectric layer, the second dielectric layer having an opening communicating with the first dielectric layer and the epitaxial barrier layer; a gate having angled sidewalls within the opening in the first and second dielectric layers; a mini-field plate on the gate with angled sidewalls; a gate top on the mini-field plate, wherein the gate, the mini-field plate, and the gate top form a "T" shape.

14. 14. The transistor of claim 13, wherein the gate comprises a length in a range from about 20 nanometers (nm) to about 500 nm.

15. 14. The transistor of claim 13, wherein the mini-field plate has a width in the range of about 1.5 to 4 times the length of the gate stem.

16. 14. The transistor of claim 13, wherein the angled sidewalls of the gate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees, and the angled sidewalls of the mini-field plate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees.

17. a channel layer; an epitaxial barrier layer on the channel layer; a first dielectric layer on the epitaxial barrier layer, the first dielectric layer having an opening leading to the epitaxial barrier layer; a second dielectric layer on the first dielectric layer, the second dielectric layer having an opening communicating with the first dielectric layer and the epitaxial barrier layer; a gate having angled sidewalls within the opening in the first dielectric layer; a first mini-field plate having angled sidewalls on the gate in the opening in the second dielectric layer; a second mini-field plate on the first mini-field plate, the second mini-field plate having angled sidewalls; a gate top on the second mini-field plate, wherein the gate, the first mini-field plate, the second mini-field plate, and the gate top form a "T" shape.

18. 20. The transistor of claim 17, wherein the gate comprises a length in a range from about 20 nanometers (nm) to about 500 nm.

19. 18. The transistor of claim 17, wherein the first mini-field plate and the second mini-field plate each have a width in a range of about 1.5 to 4 times the length of a gate stem, the second mini-field plate being larger than the first mini-field plate.

20. 18. The transistor of claim 17, wherein the angled sidewalls of the gate have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees, and the angled sidewalls of the first mini-field plate and the second mini-field plate each have an exterior angle at a horizontal base in a range of approximately 45 degrees to 89 degrees.

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