Ultra-low power and high speed polyfuse EPROM

Abstract

One example includes an integrated circuit (100) comprising a sense amplifier (105) including a first inverter (110) having a first positive power terminal, a first input, and a first output, and a second inverter (115) having a second positive power terminal, a second input connected to the first output, and a second output connected to the first input. The integrated circuit also includes a reference resistor (R ref A fuse (120) is connected between the positive voltage rail and the first positive power terminal.

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates to the field of semiconductor devices, and more particularly, but not exclusively, to memory cells. [Background technology]

[0002] Electrically programmable memory cells are used in many contexts, including adjusting various analog circuits to account for manufacturing variations. Such cells consume valuable space on an IC die and can contribute to reliability issues. Summary of the Invention

[0003] One example includes an integrated circuit with a sense amplifier including a first inverter having a first positive power terminal, a first input, and a first output, and a second inverter having a second positive power terminal, a second input connected to the first output, and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between the positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

[0004] Another example provides a method of forming an integrated circuit. First and second inverters are formed extending within a semiconductor substrate. A fuse and a resistor are formed on the semiconductor substrate. The fuse is connected between an upper power rail and a positive power terminal of the first inverter. The resistor is connected between the upper power rail and a positive power terminal of the second inverter. An output of the first inverter is connected to an input of the second inverter, and an output of the second inverter is connected to the input of the first inverter.

[0005] Yet another example provides an integrated circuit. The integrated circuit includes a first NMOS transistor and a first PMOS transistor formed on a semiconductor substrate, the first NMOS transistor and the first PMOS transistor connected to form a first inverter having a first output node and a first input node. The integrated circuit also includes a second NMOS transistor and a second PMOS transistor formed on the semiconductor substrate, the second NMOS transistor and the second PMOS transistor connected to form a second inverter having a second output node and a second input node. The first output node is connected to the second input node, and the second output node is connected to the first input node. A reference resistor is connected between a positive voltage rail and a source of the first PMOS transistor, and a fuse is connected between the positive voltage rail and a source of the second PMOS transistor. [Brief explanation of the drawings]

[0006] [Figure 1] 1 illustrates a fuse memory cell circuit according to the present disclosure.

[0007] [Figure 2] 1 illustrates a fuse memory cell circuit such as that shown in FIG. 1 with additional components.

[0008] [Figure 3] 1 and 2. Timing diagrams illustrating aspects of the operation of the fuse memory cell circuits of FIGS.

[0009] [Figure 4] 3 illustrates a fuse memory cell circuit such as that shown in FIG. 2 including a current sink connected to a fuse and a reference resistor.

[0010] [Figure 5] 3 illustrates the implementation of a fuse memory cell circuit such as that shown in FIG. 2 on a semiconductor die.

[0011] [Figure 6] 6 illustrates an array of fuse memory cell circuits such as that shown in FIG. 5.

[0012] [Figure 7] 1 illustrates a method of forming an integrated circuit, in accordance with various examples. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present disclosure will be described with reference to the accompanying drawings. The drawings may not be drawn to scale and are provided solely to illustrate the present disclosure. Several aspects of the present disclosure are described below with reference to illustrative applications, where like features correspond to like reference numerals. It should be understood that numerous specific details, relationships, and methods are shown to provide an understanding of the present disclosure. The present disclosure is not limited by the described order of acts or events, as some acts may occur in different orders and / or concurrently with other acts or events. Additionally, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.

[0014] This application discloses various methods and devices that may be beneficially applied to integrated circuits (ICs), such as those containing electrically programmable fuse memory cells, for example, by reducing static current, providing short read times, etc. While such embodiments may be expected to provide improvements such as reduced overall IC power requirements, no particular result is a requirement of the described invention unless expressly recited in a particular claim.

[0015] Referring to FIG. 1, an electrically programmable memory cell 100 is shown schematically. The memory cell 100 includes a sense amplifier 105, which includes a latch having a first inverter 110 and a second inverter 115. The inverters 110 and 115 are cross-coupled in a manner that allows for quasi-static bit value storage. For ease of explanation, the output of inverter 115 is referred to as the "D-node" and the output of inverter 110 is referred to as the inverse of the D-node, or "DZ-node." The inverters 110 and 115 are configured symmetrically with the other components of the memory cell 100. The "left leg" of the memory cell 100 includes a PMOS transistor MPSWL, whose source is connected to a fuse 120 and whose drain is connected to the positive power terminal of the inverter 110. An NMOS transistor MNSWL has its drain connected to the D-node and its source connected to a lower power rail, referred to as VSS. Similarly, the "right leg" includes a PMOS transistor MPSWL, whose source is connected to a fuse 120 and whose drain is connected to the positive power terminal of the inverter 110. ref and a PMOS transistor MPSWR having its drain connected to the DZ node and its source connected to VSS. During the positive phase of the CLKZ signal, transistor MNSWL conductively connects the D node to VSS, and transistor MNSWR conductively connects the DZ node to VSS. During the negative phase of CLKZ, transistor MPSWL conductively connects the positive power terminal of inverter 110 to fuse 120, and transistor MPSWR conductively connects the positive power terminal of inverter 115 to R ref Connect the power supply to the

[0016] The negative power terminals of inverters 110 and 115 are connected in a non-switching manner to the lower power rail. Conversely, inverter 110 is connected to the upper power rail, designated VDD, through transistor MPSWL and fuse 120, and inverter 115 is connected to the upper power rail, designated VDD, through transistor MPSWR and fuse 120. ref The transistor MPSWL is connected directly to the first terminal of the fuse 120, and the transistor MPSWR is connected to the reference resistor R ref The second terminal of fuse 120 and R refThe second terminals of both are connected to VDD.

[0017] Fuse 120 may be formed from any material that can be patterned to form a current path that can be selectively broken to create a high resistance state between a first fuse terminal and a second fuse terminal. In various examples, as described but not limited to, fuse 120 is formed from polysilicon. In various examples, fuse 120 has an "hourglass" or "dogbone" shape, with wide terminal portions having relatively low resistance initially connected by narrow conductive paths having an initial resistance. A sufficiently high current, generating a correspondingly high current density, can damage portions of the narrow conductive paths, resulting in a programmed resistance that is typically much greater than the initial resistance. For example, fuse 120 may have a resistance R that has an initial unprogrammed value of approximately 100 Ω and a programmed value greater than 50 kΩ. fuse may have:

[0018] Reference resistor R ref has a resistance greater than the unprogrammed resistance of fuse 120 and less than the programmed resistance of fuse 120. In one example, R ref is the R in the programmed state fuse may be approximately half the minimum expected value of R, e.g., 25 kΩ. ref is significantly larger than the unprogrammed resistance of fuse 120, eg, >100x.

[0019] In the non-read or quiescent state, CLK is not asserted, MNSWL and MNSWR are switched on, and the D and DZ nodes are pulled to VSS. In the read state, CLK is asserted, allowing D and DZ to settle to their active states. In this state, there is little power dissipated by the memory cell 100. The value of the D node in the active state is R fuse and R ref As detailed below, R fuse <R refFor example, in an unprogrammed state, the D node settles to an unasserted value, such as a digital "0" or FALSE state, and the DZ node settles to an asserted value, such as a digital "1" or TRUE state. Conversely, for R fuse >R ref For example, in the programmed state, the D node settles to the TRUE state and the DZ node settles to the FALSE state. After settling to the active state, a small amount of power is consumed by the memory cell 100.

[0020] 2 illustrates an example of a memory cell 200 in which inverter 110 is implemented by a PMOS transistor MPSAL and an NMOS transistor MNSAL, and inverter 115 is implemented by a PMOS transistor MPSAR and an NMOS transistor MNSAR. MPSAL and MNSAL are connected at a first output node that serves as the DZ node, and MPSAR and MNSAR are connected at a second output node that serves as the D node. The gate terminals of MPSAL and MNSAL are connected to a first input node that is connected to the D node, and the gate terminals of MPSAR and MNSAR are connected at a second input node that is connected to the DZ node.

[0021] As previously mentioned, in the quiescent state (e.g., CLK=FALSE and CLKZ=TRUE), transistors MNSWL and MNSWR are switched on, holding the D and DZ node values ​​at VSS. In the read state (e.g., CLK=TRUE and CLKZ=FALSE), MNSWL and MNSWR are switched off and MPSWL and MPSWR are switched on. Immediately after the transition from the quiescent state to the active state, due to the previous VSS state of the D and DZ nodes, MPSAL and MPSAR are switched on and MNSAL and MNSAR are switched off. The state to which the D and DZ nodes settle is determined by the race between the left and right legs. The combined resistance and capacitance of the left leg components is determined by a first time constant t that determines the rate at which the DZ node voltage increases from VSS.R and the combined resistance and capacitance of the right leg components provides a second time constant that determines the rate at which the D-node voltage increases from VSS. L <t R (unprogrammed state), DZ will increase to a value sufficient to switch on MNSAR before D can increase to a value sufficient to switch on MNSAR, and the D and DZ nodes will settle to values ​​of 0 and 1, respectively. L >t R In this case (as programmed), D increases to a value sufficient to switch MNSAL on, and the D and DZ nodes settle to values ​​of 1 and 0, respectively, before DZ can increase to a value sufficient to switch MNSAR on.

[0022] The read operation is illustrated in Figure 3, where R fuse = 100Ω (unprogrammed) and R ref For the example of .DELTA.=25 kΩ, simulated potentials and currents at various nodes of memory cell 100 versus time t are shown. Before t=250 ns, CLK is not asserted (CLKZ is asserted), and fuse 120 and R ref The current through the fuse 120 is zero and the voltage at the D and DZ nodes is zero. CLK is asserted at t=250 ns, causing a peak current of approximately 55 μA through the fuse 120 and a reference resistor R ref This results in a peak current of approximately 15 μA through fuse 120. Initially, the voltages at the D and DZ nodes increase at the same rate, but within 2-3 ns, the voltage at the DZ node exceeds the voltage at the D node, and the state of memory cell 100 settles to an unprogrammed state. The current through fuse 120 decreases to R ref Return to zero. Hence, the static current is found to be very low, e.g., ≦75 nA, and the readout time is very short, e.g., <17 ns.

[0023] Note that the voltages shown in Figure 3 are merely an example, provided without implied constraints. In this example, the circuit uses 5V transistors and operates between 0.9V and 5.5V, where 0.9V is determined by the threshold voltage of the transistors and 5.5V is determined as the reliable operating limit of the 5V transistors. The voltage range of operation can be extended, for example, by using low threshold voltage (LVT) devices in some other examples.

[0024] 2, in various examples, transistors MPSWL and MPSWR are matched, e.g., have approximately the same resistance and capacitance (within manufacturing tolerances). For example, each of these transistors may have the same gate length (or channel length) and the same gate width (or drive current). Similarly, in various examples, MPSAL and MPSAR are matched, and MNSAL and MNSAR are matched. In some examples, all of the transistors in memory cell 100 are closely spaced on a semiconductor substrate, such that manufacturing variations between matched transistors are negligible.

[0025] Other components of memory cell 200 include transistors MNBLOW and MNDUMMY. During programming operations, MNBLOW is switched by an asserted PROG signal and, when in an unprogrammed state, acts to sink current through fuse 120. The drive current capacity of MNBLOW is selected to support a current sufficient to damage the narrow conductive path of fuse 120, increasing its resistance from an unprogrammed value to a programmed value. Connection of MNBLOW to the fuse 120 terminal may increase the capacitance associated with the left leg of memory cell 100, altering the timing of operation during the aforementioned settling period without compensation. In some examples, MNDUMMY is a dummy transistor matched to the MNBLOW transistor to provide such compensation. In such examples, the source and drain of MNDUMMY are connected, and therefore this transistor does not provide an active electrical function.

[0026] In an additional example, a shunt resistor R0 is connected to the terminals of fuse 120 to inhibit the growth of a low-resistance path between the terminals after fuse 120 is blown. Such regrowth may result from an electric field between the terminals in the absence of the shunt resistor. In various examples, R0 has a resistance at least twice the predetermined minimum resistance of fuse 120 in the programmed state. It may be desirable for R0 to have a resistance at least ten times the predetermined minimum resistance of fuse 120 in the programmed state, e.g., approximately 500 kΩ.

[0027] FIG. 4 shows a first bias current sink 410 connected to fuse 120 and a second bias current sink 420 connected to R ref 1 illustrates memory cell 100 connected to a resistor R. This configuration can be used to test the operating margin of memory cell 100 after programming fuse 120. In one example, the minimum desired resistance of fuse 120 after programming can be predetermined to be 50 kΩ. R ref In the example where I has a value of 25 kΩ, the second bias current sink 420 will have a bias current I drawn by the first bias current sink 410. bias The bias current I is twice that of the ref R ref This configuration can be used to test the operating margin of memory cell 100 after programming fuse 120. In another example, the minimum desired resistance of fuse 120 after programming may be predetermined to be 100 kΩ, in which case I ref I bias It can be four times as large as I. bias I as a multiple of ref The configuration of R ref can be less than the minimum desired resistance of the fuse in its programmed state, and R ref Reduces the die area required to implement R ref As becomes smaller, R refTo produce the desired voltage drop across I ref may be increased, and the current sink 420 and / or R ref The size of the components implementing the interconnection to R may be increased, or ref The risk of damaging the I bias vs. I ref The minimum ratio of may be 2 to limit the size of such components.

[0028] When CLK is not asserted and current sinks 410, 420 are activated, a voltage V fuse Similarly, R ref and transistor MPSWR and V ref is generated. R ref is 25kΩ, and I ref =4×I fuse Under the exemplary condition, V fuse <V ref In the case of R fuse can be estimated to be greater than 100 kΩ. Conversely, V fuse >V ref In the case of R fuse may be estimated to be less than a predetermined minimum of 100 kΩ. In response to this condition, which may result in a failure to meet desired margin specifications, the IC on which memory cell 100 is implemented may be discarded.

[0029] The principle explained is ref I bias This can be generalized such that the second bias current sink 420 is configured to be n times V. fuse is R fuse =n×R ref When V ref or R ref = 25kΩ, it becomes n × 25kΩ. Also, usually, the ratio I ref / I bias does not have to be an integer value.

[0030] Current sinks 410, 420 may be provided by current sinks integrated into the IC, or may be provided external to the IC, such as in a multi-probe test configuration. If integrated into the IC, current sinks 410, 420 provide the ability to determine whether predetermined operating margins are met, including after the resistance of fuse 120 has unfolded within the electronic system, independent of an external tester. On the other hand, if one or both of current sinks 410, 420 are provided externally, I bias and / or I ref can be varied as desired to determine any operating margin ratio, e.g., R fuse To determine the actual value of , multiple test measurements can be made.

[0031] 5 illustrates, in various examples, a memory cell 500 implemented on a silicon substrate 501. The various names of features of memory cell 500 may correspond to the features described above. Memory cell 500 includes a fuse structure 505 and a shunt resistor 510, exemplified by fuse 120 and shunt resistor R0, respectively, in FIG. 2. Resistor R0 in FIG. 2 refis disposed below the shunt resistor 510. The fuse structure 505 may be at least partially formed in a polysilicon layer or a metal interconnect layer above the substrate 501. The resistors 510, 515 may be formed in a polysilicon layer above the substrate 501 or in diffusion regions extending within the substrate 501. Transistors 520 and 525 illustrate transistors MNSAR and MNSAL of FIG. 2, transistors 530 and 535 illustrate transistors MNSAR and MNSAL of FIG. 2, transistors 540 and 545 illustrate transistors MPSWR and MPSWL of FIG. 2, and transistors 550 and 555 illustrate transistors MPSAR and MPSAL of FIG. 2. Each of transistors 520, 525, 530, 535, 540, 545, 550, and 555 may be formed on and extend into substrate 501 by any present or future discovered method. In various examples, transistors 520 and 525 are matched, transistors 530 and 535 are matched, transistors 540 and 545 are matched, and / or transistors 550 and 555 are matched. Logic functions 560 associated with other operational characteristics of memory cell 500 are located between fuse structure 505, resistors 510, 515, and transistors 520...555.

[0032] 6 illustrates an array 600 of memory cells 500 that may be formed within an integrated circuit. Any number of memory cells 500 may be formed on and extend within a semiconductor substrate 601. In the illustrated example, a plurality of memory cells 500, e.g., 16, are formed in a two-dimensional array. In other examples, the array of memory cells 500 may be one-dimensional or may be arranged arbitrarily within an integrated circuit design.

[0033] 7 illustrates a method 700 for forming an integrated circuit as described in this disclosure. At step 710, first and second inverters are formed extending into a semiconductor substrate. The first inverter has a first positive power terminal, a first output at a first output node, and a first input node. The second inverter has a second positive power terminal, a second output at a second output node, and a second input node.

[0034] At step 720, fuses and resistors are formed on a semiconductor substrate.

[0035] In step 730, a fuse is connected between the upper power rail and the first positive power terminal of the first inverter.

[0036] In step 740, a resistor is connected between the upper power rail and the second positive power terminal of the second inverter.

[0037] In step 750, the output node of the first inverter is connected to the input node of the second inverter, and the output node of the second inverter is connected to the input node of the first inverter.

[0038] In step 760, a first switch is connected between the fuse and the positive power terminal of the first inverter, and a second switch is connected between the resistor and the positive power terminal of the second inverter.

[0039] At step 770, a third switch is connected between the output node of the first inverter and the lower power rail, and a fourth switch is connected between the output node of the second inverter and the lower power rail, the first and second switches configured to provide a low resistance during a first phase of the control signal, and the third and fourth switches configured to provide a low resistance during a second phase of the control signal.

[0040] A fifth switch is connected between the fuse and the negative power rail and a sixth switch is connected to the reference resistor, in step 780. The fifth switch is configured to provide a low resistance in response to a programming signal.

[0041] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous modifications can be made to the disclosed embodiments in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Instead, the scope of the present disclosure is defined according to the following claims and their equivalents.

Claims

1. It is an integrated circuit, A sensing amplifier, A first inverter having a first positive power terminal, a first input, and a first output, A second inverter having a second positive power terminal, a second input coupled to the first output, and a second output coupled to the first input, The sensing amplifier includes, A reference resistor coupled between the positive voltage rail and the second positive power terminal, A fuse coupled between the positive voltage rail and the first positive power terminal, A first switch transistor coupled between the fuse and the first positive power terminal, A second switch transistor coupled between the reference resistor and the second positive power terminal, A third switch transistor coupled between the first output and the lower voltage rail, A fourth switch transistor coupled between the second output and the lower voltage rail, An integrated circuit, including

2. The integrated circuit according to claim 1, An integrated circuit further comprising a programming transistor coupled to the fuse and a dummy transistor coupled to the reference resistor.

3. The integrated circuit according to claim 1, An integrated circuit further comprising a shunt resistor coupled in parallel with the fuse.

4. The integrated circuit according to claim 1, An integrated circuit configured such that the first output is set to a FALSE state and the second output is set to a TRUE state, provided that the resistance of the fuse is greater than the resistance of the reference resistor.

5. The integrated circuit according to claim 1, An integrated circuit in which the fuse is a polysilicon fuse.

6. The integrated circuit according to claim 1, An integrated circuit further comprising a first current sink coupled to the fuse.

7. The integrated circuit according to claim 6, An integrated circuit further comprising a second current sink coupled to the reference resistor.

8. The integrated circuit according to claim 7, An integrated circuit in which the first current sink is configured to generate a first current, and the second current sink is configured to generate a second current that is at least twice the first current.

9. A method for forming an integrated circuit, To form first and second inverters extending within a semiconductor substrate, Forming a fuse and a resistor on the semiconductor substrate, The fuse is connected between the upper power rail and the positive power terminal of the first inverter, The resistor is connected between the upper power rail and the positive power terminal of the second inverter. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, A first switch transistor is connected between the fuse and the positive power terminal of the first inverter, a second switch transistor is connected between the resistor and the positive power terminal of the second inverter, a third switch transistor is connected between the output of the first inverter and the lower voltage rail, and a fourth switch transistor is connected between the output of the second inverter and the lower voltage rail. Methods that include...

10. The method according to claim 9, A method further comprising connecting a shunt resistor in parallel with the fuse between the upper power rail and the positive power terminal of the first inverter.

11. The method according to claim 9, A first transistor is connected between the fuse and the positive power terminal of the first inverter. A second transistor is connected between the resistor and the positive power terminal of the second inverter. Methods that further include the above.

12. The method according to claim 10, A method configured such that the output of the second inverter is set to the TRUE state, provided that the first and second transistors are in a low-resistance state and the resistance of the fuse is greater than the resistance of the resistor.

13. The method according to claim 9, A method wherein the first and second inverters are each implemented by a PMOS transistor and an NMOS transistor, respectively.

14. The method according to claim 9, A method wherein the fuse is a polysilicon fuse.

15. The method according to claim 9, A method further comprising connecting a programming transistor to the fuse.

16. The method according to claim 15, A method comprising connecting a dummy transistor to the resistor, further comprising connecting a dummy transistor such that the dummy transistor is matched to the programming transistor.

17. The method according to claim 9, Connecting a first current sink configured to generate a first current to the fuse, Connecting a second current sink configured to generate a second current that is at least twice the first current to the resistor, Methods that further include the above.

18. It is an integrated circuit, A first NMOS transistor and a first PMOS transistor formed on a semiconductor substrate, connected to form a first inverter having a first input node, a first output node, and a first power terminal, A second NMOS transistor and a second PMOS transistor formed on the semiconductor substrate, connected to form a second inverter having a second input node, a second output node and a second power terminal, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node, A reference resistor coupled between the positive voltage rail and the first PMOS transistor, A fuse is coupled between the positive voltage rail and the second PMOS transistor, A third NMOS transistor is coupled between the fuse and the first power terminal, A fourth NMOS transistor coupled between the reference resistor and the second power terminal, A fifth NMOS transistor is coupled between the first output and the low-side voltage rail, A sixth NMOS transistor coupled between the second output and the low-side voltage rail, An integrated circuit, including

Images