Staggered-Pitch Stacked Vertical Transport Field-Effect Transistors

Abstract

Disclosed is a technique for forming a semiconductor structure comprising a staggered pitch stacked vertical transport field effect transistor, the semiconductor structure comprising a first plurality of vertical transport field effect transistors in a lower semiconductor layer and a second plurality of vertical transport field effect transistors in an upper semiconductor layer, the second plurality of vertical transport field effect transistors being horizontally offset from the first plurality of vertical transport field effect transistors by a horizontal distance that is half the contact gate pitch between adjacent vertical transport field effect transistors in the same semiconductor layer.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor device technology, and more particularly to vertical transport field effect transistors formed in different semiconductor device layers, and more particularly to adjacent vertical transport field effect transistors on different semiconductor layers with half gate contact pitch. [Background technology]

[0002] With the continuing pressure to increase semiconductor chip performance while maintaining the ability to drive more functions and more semiconductor devices per semiconductor chip for a similar semiconductor chip size, various means are being considered to provide more semiconductor chip functionality without impacting wafer utilization. One means of providing more semiconductor chip functionality and more semiconductor devices per chip is stacking semiconductor logic devices. Vertically stacking semiconductor devices, particularly memory devices, has emerged as a common technique to provide both increased semiconductor device functionality and improved wafer utilization by bringing semiconductor devices closer together. A new approach to vertically stacking semiconductor logic devices, in which one high-performance semiconductor logic device resides directly above another, may improve semiconductor chip performance and provide effective wafer utilization. Summary of the Invention

[0003]

[0009] Embodiments of the present invention disclose a semiconductor structure with a first plurality of vertical transport field effect transistors in a lower semiconductor layer and a second plurality of vertical transport field effect transistors in an upper semiconductor layer, where each of the second plurality of vertical transport field effect transistors is horizontally offset from at least one of the first plurality of vertical transport field effect transistors by a horizontal distance that is half the contact gate pitch between adjacent transistors in the same semiconductor layer.

[0010] Embodiments of the present invention disclose a semiconductor structure in which adjacent transistors of the second plurality of vertical transport field effect transistors in the upper semiconductor layer are each horizontally separated by the contact gate pitch.

[0011] Embodiments of the present invention provide a linear vertical contact that connects the vertical transport field effect transistor in the lower semiconductor layer to interconnect wiring above the vertical transport field effect transistor in the upper semiconductor layer.

[0012] Providing a linear vertical gate contact in the lower semiconductor layer results in better electrical performance of the first vertical transport field effect transistor in the lower semiconductor layer and provides a simplified manufacturing process for forming the linear vertical gate contact without requiring a lateral etching process. Additionally, embodiments of the present invention provide a semiconductor structure in which the first vertical transport field effect transistor has a gate contact over the active gate (COAG), which can reduce the cell area of ​​the transistor.

[0004]

[0006] Embodiments of the present invention disclose a semiconductor structure including a first vertical transport field effect transistor in a lower semiconductor layer and a second vertical transport field effect transistor in an upper semiconductor layer, where the second vertical transport field effect transistor in the upper semiconductor layer is horizontally offset by half a contact gate pitch from the first vertical transport field effect transistor in the lower semiconductor layer.

[0007] Embodiments of the present invention provide a linear vertical contact connecting the vertical transport field effect transistor in the lower semiconductor layer to interconnect wiring above the vertical transport field effect transistor in the upper semiconductor layer. Providing a linear vertical gate contact in the lower semiconductor layer results in better electrical performance of the first vertical transport field effect transistor in the lower semiconductor layer and provides a simplified manufacturing process for forming the linear vertical gate contact without requiring a lateral etching process. Furthermore, embodiments of the present invention provide a vertical transport field effect transistor in the lower semiconductor layer with a first type of field effect transistor and a vertical transport field effect transistor in the upper semiconductor layer with a second type of field effect transistor.

[0005] Embodiments of the present invention disclose a semiconductor structure with one or more vertical transport field effect transistors in an upper semiconductor layer separated by one contact gate pitch and one or more vertical transport field effect transistors in a lower semiconductor layer also separated by one contact gate pitch. The vertical transport field effect transistors in the lower semiconductor layer are field effect devices of a first type, and the vertical field effect transistors in the upper semiconductor layer are field effect devices of a second type. Embodiments of the present invention provide vertical transport field effect transistors in the upper semiconductor layer that are offset from the vertical transport field effect transistors in the lower semiconductor layer by half a contact gate pitch. Each of the vertical transport field effect transistors has a linear vertical contact that connects to interconnect wiring above the vertical transport field effect transistor in the upper semiconductor layer. Because the vertical transport field effect transistors in the upper semiconductor layer are horizontally offset by half the contact gate pitch from the vertical transport field effect transistors in the lower semiconductor layer, allowing for separation between adjacent vertical transport field effect transistors in the upper semiconductor layer directly above each vertical transport field effect transistor in the lower semiconductor layer, embodiments of the present invention provide a linear vertical contact to each of the vertical transport field effect transistors. Providing a linear vertical contact from the vertical transport field effect transistor improves manufacturing yield and improves the electrical performance of the vertical transport field effect transistors. Additionally, embodiments of the present invention provide a semiconductor structure in which the first vertical transport field effect transistor has a gate contact on the active gate (COAG), which can reduce the cell area of ​​the transistor.

[0006] An embodiment of the present invention discloses a semiconductor structure with a first pair of vertical transport field effect transistors in a lower semiconductor layer and a second pair of vertical transport field effect transistors in an upper semiconductor layer, where each transistor of the second pair of vertical transport field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate pitch from at least one vertical transport field effect transistor in the lower semiconductor layer. Furthermore, an embodiment of the present invention provides a semiconductor structure in which the second pair of vertical transport field effect transistors in the upper semiconductor layer are field effect transistors of a first type connected in series and the first pair of vertical transport field effect transistors in the lower semiconductor layer are field effect transistors of a second type connected in parallel. An embodiment of the present invention provides the first pair of vertical transport field effect transistors in the lower semiconductor layer and the second pair of vertical transport field effect transistors to form a two-input NOR circuit. Each of the vertical transport field effect transistors in the lower semiconductor layer has a linear vertical contact to an interconnect wire on the second pair of vertical transport field effect transistors. The ability to provide straight vertical contacts improves both the manufacturing process and electrical performance of vertical transport field effect transistors when compared to conventional stacked vertical transport field effect transistors, which require horizontal or lateral jogs to avoid having a vertical transport field effect transistor directly above each of the lower vertical transport field effect transistors. Additionally, embodiments of the present invention provide a bottom conduction surface that connects to at least one of the first pair of vertical transport field effect transistors in the lower semiconductor layer, and an upper power rail that connects to at least one of the second pair of vertical transport field effect transistors in the upper semiconductor layer. By providing contacts from the first pair of vertical transport field effect transistors in the lower semiconductor layer to the bottom conduction surface and providing connections from the second pair of vertical transport field effect transistors in the upper semiconductor layer to the power rail, the electrical performance of the vertical transport field effect device is improved.

[0007] Embodiments of the present invention provide a semiconductor structure with a first pair of vertical transport field effect transistors in a lower semiconductor layer and a second pair of vertical transport field effect transistors in an upper semiconductor layer, where each of the second pair of vertical transport field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate pitch from at least one vertical transport field effect transistor in the lower semiconductor layer. Embodiments of the present invention provide the first pair of vertical transport field effect transistors in the lower semiconductor layer connected in series and the second pair of vertical transport transistors in the upper semiconductor layer connected in parallel. Embodiments of the present invention provide the first pair of vertical transport field effect transistors in the lower semiconductor layer and the second pair of vertical transport field effect transistors in the upper semiconductor layer forming a two-input NAND circuit. Additionally, embodiments of the present invention provide linear vertical contacts connecting the vertical transport field effect transistors in the lower semiconductor layer to interconnect wiring above the vertical transport field effect transistors in the upper semiconductor layer. Providing a straight vertical gate contact in the lower semiconductor layer results in better electrical performance of the first vertical transport field effect transistor in the lower semiconductor layer and provides a simpler manufacturing process for forming the straight vertical gate contact without requiring a lateral etching process. [Brief explanation of the drawings]

[0008] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor structure of a conventional vertically stacked vertical transport semiconductor device according to an embodiment of the present invention.

[0010] [Figure 2A]FIG. 1 is a cross-sectional view of a semiconductor structure after forming two stacked vertical transport field effect transistors (VTFETs) on different semiconductor structure layers with a half-pitch contact gate pitch (CGP) misalignment according to an embodiment of the present invention.

[0011] [Figure 2B] FIG. 1 is a cross-sectional view of a semiconductor structure with four stacked VTFETs, where each upper VTFET has a horizontal spacing of half a CGP from an adjacent lower VTFET, according to an embodiment of the invention.

[0012] [Figure 3] FIG. 1 is a top view of a semiconductor structure of an inverter formed using two stacked VTFETs with a half-pitch CGP offset between the top and bottom VTFETs, according to an embodiment of the invention.

[0013] [Figure 4] 4 is a cross-sectional view of the semiconductor structure taken through X1-X1 shown in FIG. 3 according to an embodiment of the present invention.

[0014] [Figure 5] 4 is a cross-sectional view of the semiconductor structure through X2-X2 of the inverter shown in FIG. 3 according to an embodiment of the present invention.

[0015] [Figure 6] 4 is a cross-sectional view of a semiconductor structure through X3-X3 of the inverter shown in FIG. 3 according to an embodiment of the present invention.

[0016] [Figure 7] 4 is a cross-sectional view of a semiconductor structure through Y1-Y1 of the inverter shown in FIG. 3 according to an embodiment of the present invention.

[0017] [Figure 8] 4 is a cross-sectional view of the semiconductor structure through Y2-Y2 of the inverter shown in FIG. 3 according to an embodiment of the present invention.

[0018] [Figure 9] FIG. 2 is a circuit schematic diagram of a single-transistor enhanced device consisting of a two-input NOR circuit, according to an embodiment of the present invention.

[0019] [Figure 10A] FIG. 10 is a top view of the single reinforcement transistor structure of FIG. 9, in accordance with an embodiment of the present invention.

[0020] [Figure 10B] 10 is a bottom view of the single reinforcement transistor structure of FIG. 9, in accordance with an embodiment of the present invention.

[0021] [Figure 11] FIG. 1 is a circuit schematic diagram of a single-transistor enhanced transistor consisting of two input NAND circuits, according to an embodiment of the present invention.

[0022] [Figure 12A] FIG. 12 is a top view of the single reinforcement transistor structure of FIG. 11 in accordance with an embodiment of the present invention.

[0023] [Figure 12B] FIG. 12 is a bottom view of the single enhancement transistor structure of FIG. 11 in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Embodiments of the present invention recognize that a three-dimensional monolithic directly stacked vertical field-effect transistor (VTFET) is typically a device including an n-channel FET (FET) and a p-channel FET (PFET). Embodiments of the present invention recognize that stacked VTFETs are typically stacked directly above or below each other in different semiconductor layers to form a three-dimensional monolithic directly stacked VTFET. Embodiments of the present invention recognize that in conventional vertically stacked VTFETs, the pitch between gates of adjacent devices in the same semiconductor layer is commonly known as the contact gate pitch (CGP) or contact poly pitch (CPP). In conventionally formed vertically stacked VTFETs, adjacent VTFETs in the same semiconductor layer have a gate-to-gate pitch of 1 CGP, and VTFETs directly above or below adjacent VTFETs in different semiconductor layers also have a horizontal gate-to-gate pitch of 1 CGP. Thus, in conventional vertically stacked VTFETs, the horizontal distance between adjacent VTFETs in different semiconductor layers is also 1 CGP.

[0025] An embodiment of the present invention provides a semiconductor structure with adjacent semiconductor devices in different semiconductor layers, where a first semiconductor device in an upper semiconductor layer is horizontally separated or offset from a second semiconductor device in a lower semiconductor layer by a distance of half a CGP. An alternative embodiment of the present invention provides a semiconductor structure with adjacent semiconductor devices in different semiconductor layers, where the first semiconductor device in the upper semiconductor layer is horizontally separated or offset from a second semiconductor device in a lower semiconductor layer by a distance in the range of 0.3 to 0.7 CGP. The horizontal distance between the first semiconductor device and a third semiconductor device in the same semiconductor layer is 1 CGP, gate to gate. Although an embodiment of the present invention discloses the first semiconductor device and the second semiconductor device to be vertical transport field effect (VTFET) devices, in other embodiments of the present invention, the first semiconductor device can be a memory device or another type of logic device, and the second semiconductor device can be one of a memory device or a logic device.

[0026] Embodiments of the present invention further provide semiconductor structures with four or more VTFETs residing in two different semiconductor layers, where each VTFET residing in the lower semiconductor layer is horizontally separated from each adjacent upper VTFET by half a CGP. Alternative embodiments of the present invention further provide semiconductor structures with four or more VTFETs residing in two different semiconductor layers, where each VTFET residing in the lower semiconductor layer is horizontally separated from each adjacent upper VTFET by a range of 0.3 to 0.7 CGP. Embodiments of the present invention provide four VTFET devices, where the top two VTFET devices residing in the upper semiconductor layer and the bottom two VTFET devices in the lower semiconductor layer each have a CGP of 1 relative to adjacent VTFET devices in the same semiconductor layer. Embodiments of the present invention provide semiconductor structures with increased semiconductor device density when compared to conventional planar VTFET device layouts.

[0027] Embodiments of the present invention provide VTFET devices with 1 CGP in the same semiconductor layer, but VTFET devices in different semiconductor layers are offset by a smaller horizontal distance of ½ CGP from VTFET devices in different semiconductor layers above or below them. In this manner, VTFET devices in lower semiconductor layers are horizontally separated by ½ CGP from adjacent VTFET devices in upper semiconductor layers. Additionally, because the VTFET devices in the lower semiconductor layer are horizontally offset by ½ CGP from the VTFET devices in the upper semiconductor layer, gate contacts from the lower VTFET devices can be formed with vertically etched vias to contact interconnect wiring structures or other semiconductor device elements formed above the upper VTFET devices. Embodiments of the present invention create linear vertical gate contacts that directly connect to semiconductor interconnect wiring or semiconductor elements above the upper VTFET devices. A straight vertical gate contact that directly contacts the interconnect wiring above the upper VTFET device provides better electrical performance than the gate contact in conventional vertically stacked VTFET devices, where the gate contact from the lower VTFET device must jog around the VTFET device directly above it to connect with the interconnect wiring above the upper VTFET device. The straight vertically etched gate contact provided by embodiments of the present invention provides a shorter signal path without the horizontal jog connecting the lower VTFET device to the interconnect wiring above the upper semiconductor device.

[0028] Additionally, by providing vertically etched vias that form the gate contacts, gate contact formation steps are reduced compared to conventional vertically stacked VTFET devices, which may require horizontal and lateral etching to form gate contacts with a jog for routing around the upper VTFET device directly above each of the lower VTFET devices. Thus, in addition to providing improved electrical performance of the lower VTFET devices compared to conventional vertically stacked VTFET devices, embodiments of the present invention provide semiconductor structures and methods for forming semiconductor structures that improve manufacturing yields (e.g., require fewer gate contact formation processes). Forming gate contacts from lower VTFET devices that connect to interconnect wiring above upper VTFET devices using vertical etching processes is easier than the semiconductor manufacturing processes used to form bottom gate contacts in conventional vertically stacked VTFET devices. Conventional vertically stacked VTFET devices are typically formed by using lateral etching and vertical via etching processes to form bottom gate contacts that jog around the upper VTFET device directly above the lower VTFET device and connect to the interconnect wiring above the upper VTFET device. Furthermore, compared to conventional vertically stacked VTFETs, where a wiring block is formed above the fin of the lower VTFET device by a lateral element or via for the gate contact of the lower VTFET device, the linear vertical gate contact reduces the wiring block above the lower VTFET device, resulting in improved wiring capability above the fin in the lower VTFET device.

[0029] Embodiments of the present invention also disclose an optional etch stop between the gate contact and either the upper source / drain or gate of a VTFET device. The optional etch stop provides the option to form a larger upper source / drain that can be used as an enlarged landing pad for the gate contact. The enlarged landing pad provides improved yield during gate contact formation.

[0030] Embodiments of the present invention also provide a semiconductor structure in which a gate contact may be formed directly above the active area of ​​the gate and fin in the channel region. As known to those skilled in the art, forming the gate contact directly above the gate on the active area of ​​a VTFET device is advantageous for device electrical performance.

[0031] Additionally, embodiments of the present invention disclose a semiconductor structure consisting of a two-input NAND circuit formed by a pair of p-type (PFET) VTFET devices in an upper semiconductor layer connected in parallel above and offset by ½ CGP from a pair of n-type (NFET) VTFET devices in a lower semiconductor layer connected in series. Embodiments of the present invention disclose a semiconductor structure consisting of a two-input NOR circuit with a pair of PFET VTFET devices connected in series and two NFET VTFET devices connected in parallel. Embodiments of the present invention also disclose a single CGP stacked transistor inverter layout using two VTFET devices.

[0032] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The embodiments can be implemented in conjunction with integrated circuit manufacturing techniques currently used in the art for semiconductor chips, and only limited process steps commonly performed are included as necessary for understanding the described embodiments. The figures represent cross-sectional portions of a semiconductor chip with one or more vertically stacked semiconductor devices after fabrication and are not drawn to scale but are intended to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously use the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0033] References in the specification to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one of ordinary skill in the art to operate such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0034] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the drawings. The terms "on," "above," "on top," "on top of," "disposed on," or "disposed on" mean that a first element is on a second element, and that intervening elements, such as interfacial structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without any intervening conductive, insulating, or semiconducting layers at the interface of the two elements.

[0035] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0036] In the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for purposes of presentation and illustration, and in some instances may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. Additionally, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other instances, some known processing steps or operations may not be described. It should be understood that the following description instead focuses on the unique features or elements of various embodiments of the present invention.

[0037] FIG. 1 is a cross-sectional view of a semiconductor structure 100 of a conventional VTFET device according to an embodiment of the present invention. FIG. 1 is an illustration of a prior art configuration of four vertically stacked VTFET devices, in which each adjacent VTFET has a CGP of 1 relative to an adjacent VTFET in the same semiconductor layer. In addition, each of the four vertically stacked VTFET devices (VTFETs 8A-D) has a horizontal distance of 1 CGP relative to another adjacent VTFET in the same semiconductor layer. For example, VTFET 8A has a CGP of 1 relative to adjacent VTFET 8C, and VTFET 8B has a CGP of 1 relative to adjacent VTFET 8D. In addition, each of the four vertically stacked VTFET devices (VTFETs 8A-D) has a horizontal distance of 1 CGP relative to another adjacent VTFET in the semiconductor layer above or below. For example, VTFET 8A has a CGP of 1 relative to adjacent VTFET 8D in the semiconductor layer below, and VTFET 8C has a CGP of 1 relative to adjacent VTFET 8B in the semiconductor layer below.

[0038] As known to those skilled in the art, gate contact pitch (CGP) is the distance between adjacent gates in two adjacent semiconductor devices, typically in the same semiconductor layer. In some cases, CGP may be the same distance as contact poly pitch (CPP). As will be shown later, CGP may also be considered the horizontal distance between fins under a gate in the same semiconductor layer. For purposes of the present invention, CGP is also used for the horizontal distance between gates or fins for semiconductor devices residing in different semiconductor layers.

[0039] As shown, FIG. 1 includes VTFET 8A, VTFET 8B, VTFET 8C, and VTFET 8D. In FIG. 1, VTFET 8A and VTFET 8C reside in the same upper semiconductor layer and have a contact gate pitch or CGP (i.e., the gate-to-gate horizontal distance on adjacent devices) of 1. In FIG. 1, each of VTFETs 8A, 8B, 8C, and 8D consists of a source / drain (S / D) 1, a fin 2, a gate 3, and a gate contact 6. VTFET 8B and VTFET 8D reside in the same lower semiconductor layer and also have a CGP of 1 between them. As shown in FIG. 1, VTFET 8A is vertically stacked directly above VTFET 8B, and VTFET 8C is directly above VTFET 8D. As shown in FIG. 1, the four conventional vertically stacked VTFETs are each directly above or below each other in the upper and lower semiconductor layers. As shown in prior art FIG. 1, there is no horizontal offset or distance between VTFET 8A and VTFET 8B or VTFET 8C and VTFET 8D in different semiconductor layers (ie, they are directly above or below each other).

[0040] Furthermore, in the four conventional vertically stacked VTFET devices, VTFET 8B and VTFET 8D cannot have a direct, straight-line vertical connection from their gate contacts 6 to any wiring level (not shown in FIG. 1 ) above VTFET 8A or VTFET 8C due to the interference or physical block formed by VTFET 8A or VTFET 8C, respectively. In the conventional vertically stacked VTFETs shown in FIG. 1 , if VTFET 8B and VTFET 8D do not connect directly to the VTFET above them, the gate contacts 6 from VTFET 8B and VTFET 8D must have a jog or lateral extension (not shown), such as a horizontal via-like element, connecting to the vertical portion of the gate contact to bypass VTFET 8A or VTFET 8C and reach the wiring level (not shown in FIG. 1 ) above VTFET 8A or VTFET 8C, respectively.

[0041] 2A is a cross-sectional view of a semiconductor structure 200A after forming VTFET 11A and VTFET 11B in different semiconductor layers in accordance with an embodiment of the present invention. For purposes of the present invention, the terms "CGP" and "pitch" may refer to the horizontal distance between adjacent VTFETs in the same semiconductor layer, and the terms "stagger," "stagger," and "CGP" may refer to the horizontal distance between adjacent VTFETs that reside in different semiconductor layers. As shown, FIG. 2A includes VTFET 11A and VTFET 11B connected by back-end-of-line (BEOL) or middle-of-line (MOL) interconnect wiring, labeled as interconnect wire 7.

[0042] In FIG. 2A, a CGP of 1 is shown above wire 7, where the CGP of 1 is relative to an adjacent VTFET (not shown) in the same semiconductor layer. FIG. 2A also shows the horizontal distance or offset as half the CGP between VTFET 11A in the upper semiconductor layer and VTFET 11B in the lower semiconductor layer. As previously described, in alternative embodiments, the horizontal distance or offset can be 0.3 to 0.7 of the CGP between VTFET 11A in the upper semiconductor layer and VTFET 11B in the lower semiconductor layer. As shown in FIG. 2A, the ½ CGP for the horizontal distance between fin 2T and fin 2B is essentially the same as the ½ CGP offset or stagger between the left-most edge of gate 3T in VTFET 11A and the left-most edge of gate 3B in VTFET 11B, which resides in a different semiconductor layer or level. VTFET11A and VTFET11B in different semiconductor layers have a stagger or horizontal offset of ½ CGP for both the horizontal distance from fin 2T to fin 2B and from gate 3T to gate 3B.

[0043] In FIG. 2A , VTFET 11A includes at least a bottom source / drain 21, a fin 2T, a gate 3T, and a gate contact 6T that connects to a portion of the interconnect wire 7, while VTFET 11B includes at least a bottom source / drain 21, a fin 2B, a gate 3B, an etch stop 5, and a gate contact 6B that connects to a portion of the interconnect wire 7. In FIG. 2A , the two fins 2T and 2B each reside in a different semiconductor layer. As shown in FIG. 2A , VTFET 11A resides in a semiconductor layer above VTFET 11B. In embodiments, the different semiconductor layers are adjacent to each other, and no other semiconductor devices exist between VTFET 11A and VTFET 11B. In various embodiments, VTFET 11A resides in a semiconductor layer above VTFET 11B's semiconductor layer, and VTFET 11A is horizontally offset by ½ CGP from VTFET 11B.

[0044] As shown, semiconductor structure 200A also provides gate contacts 6T and 6B that can be directly connected to interconnect wire 7 using straight, vertically etched via holes or contact holes that are filled with metal to form gate contacts 6B and 6T. In other words, by horizontally offsetting VTFET 11B from VTFET 11A by ½ CGP, gate contact 6B can be directly connected to interconnect wire 7 using a vertically etched via without any horizontal jogs or additional horizontal wiring elements. Forming gate contact 6B using a vertically etched and filled gate contact via in semiconductor structure 200A provides advantages in both electrical performance (e.g., shorter electrical path) and manufacturing yield (e.g., less process and no lateral etching) when compared to conventional vertically stacked VTFET devices that require a horizontal jog to directly connect to the interconnect wire on the upper vertically stacked VTFET. As previously explained, unlike VTFET 11B shown in FIG. 2A, the bottom VTFETs 8B and VTFET 8D in FIG. 1 cannot use gate contact 6 to directly connect to the interconnect wires above VTFET 8A or VTFET 8C.

[0045] 1 does not include an etch stop 5 between the gate 3B and the gate contact 6B in VTFET 11B. As will be explained in more detail below, the etch stop 5 is an optional VTFET element that aids in the formation of the gate contact 6B in VTFET 11B.

[0046] 2A shows VTFET 11A and VTFET 11B, in other embodiments, VTFET 11A and VTFET 11B can each be another type of semiconductor device. For example, the semiconductor device in place of VTFET 11A can be a memory device, and the semiconductor device in place of VTFET 11B can be another memory device or another logic device (e.g., a planar FET).

[0047] 2B is a cross-sectional view of a semiconductor structure 200B with four VTFETs, where VTFET 11A and VTFET 11C each have a horizontal distance of ½ CGP from adjacent lower VTFETs 11B and VTFET 11D, respectively. As shown, FIG. 2B includes ground 4, interconnect wire 7, VTFET 11A, VTFET 11B, VTFET 11C, and VTFET 11D, where VTFET 11A and VTFET 11C are formed in a semiconductor structure layer above the semiconductor structure layer of VTFET 11B and VTFET 11D. As shown, the horizontal distance between VTFET 11A and VTFET 11B is ½ CGP.

[0048] In FIG. 2B , VTFET 11A and VTFET 11C each include one bottom S / D 21, one fin 2T, one gate 3T, and one gate contact 6T connecting to interconnect wire 7, and VTFET 11B and VTFET 11D each include one bottom S / D 21, one fin 2B, one gate 3B, one etch stop 5, and one gate contact 6B connecting to interconnect wire 7. As shown, FIG. 2B includes four fins (e.g., two fins 2T and two fins 2B), with a VTFET formed on each fin. For example, in FIG. 2B , gate contact 6T may provide an input signal to gate 3T in VTFET 11A, and gate contact 6B may provide an output signal to interconnect wire 7, although in other examples, the locations of the signal input and output may differ. Interconnect wire 7 may be a wire in interconnect wiring of either a middle-of-line (MOL) or back-end-of-line (BEOL) interconnect wiring structure. As shown in FIG. 2B, there are two wire 7 sections.

[0049] The top two devices, VTFET 11A and VTFET 11C, are in a semiconductor layer or level above and adjacent to the semiconductor layer with VTFET 11B and VTFET 11D (e.g., no other semiconductor devices are present between VTFET 11A and VTFET 11B). Additionally, as shown in FIG. 2B, VTFET 11A in the upper semiconductor layer has a pitch of 1 CGP relative to VTFET 11C in the same semiconductor layer (the left edge of gate 3T in VTFET 11A is 1 CGP from the left edge of gate 3T in VTFET 11C). Similarly, VTFET 11B in the lower semiconductor layer has a CGP of 1 (not shown in FIG. 2B) relative to VTFET 11D. For example, a CGP of 1 can typically range from 30 nm to 100 nm in advanced process nodes. In an illustrative example, as shown here, a CGP of 1 is 40 nm. 2B also shows a horizontal distance of ½ CGP between gate 3T in VTFET 11A and gate 3B in VTFET 11B, which is in the semiconductor layer below VTFET 11A. For example, VTFET 11A in the upper level of semiconductor structure 200B has a horizontal distance (e.g., gate 3T minus gate 3B) of 20 nm for the shown ½ CGP distance from VTFET 11B to VTFET 11A, although this horizontal distance or offset from VTFET 11A to VTFET 11B is not limited to 20 nm in other examples. Using the horizontal distances labeled in FIG. 2B (i.e., ½ CGP and 1 CGP), VTFET 11B in the upper semiconductor layer has a horizontal distance or offset of ½ CGP from VTFET 11C in the lower semiconductor layer. In other words, each adjacent VTFET in Figure 2B in a different layer of semiconductor structure 200B has a horizontal distance or offset of ½ CGP from each adjacent VTFET in another semiconductor layer, and each adjacent VTFET in Figure 2B in the same layer of semiconductor structure 200B has a horizontal distance or offset of 1 CGP. Although Figure 2B shows two VTFETs in each semiconductor layer, in other examples, more than two VTFETs are present in each semiconductor layer.

[0050] Additionally, in various embodiments of the present invention, VTFET 11A, VTFET 11B, VTFET 11C, and VTFET 11D each have a straight vertical gate contact to wire 7 (i.e., gate contact 6T in VTFET 11A and VTFET 11C, and gate contact 6B in VTFET 11C and VTFET 11D, each are straight vertical connections to interconnect wiring shown as wire 7). As shown in FIG. 2A , gate contact 6T and gate contact 6B do not require a horizontal jog or horizontal portion of gate contact 6B or 6T to connect to a semiconductor feature or wire above VTFET 11A or VTFET 11C. As previously described, because no lateral jogs or elements are required in the gate contacts of VTFET 11B and VTFET 11D, the straight vertical gate contact provides both improved electrical performance and an improved manufacturing process for lower VTFET 11B and VTFET 11D.

[0051] FIG. 3 is a top view 300 of a semiconductor structure forming a 1CGP inverter with VTFETs 33 and 34, according to an embodiment of the present invention. As shown, FIG. 3 includes Vdd 20, ground 24, ground connection 54, VTFET 33 with gate contact 26T and output connection 28T, VTFET 34 with gate contact 26B and output connection 28B, wire 27, and wire 29. VTFETs 33 and 34 are each identified by arrows. Additionally, FIG. 3 illustrates the locations of cross sections X1-X1, X2-X2, X3-X3, Y1-Y1, and Y2-Y2, which are shown later in FIGS. 4-8. As known to those skilled in the art, an inverter is a NOT gate that inverts an input, for example, from an input 1 to an output 0 (or vice versa).

[0052] FIG. 3 shows VTFET 33 formed on upper fin 22T and offset by ½ CGP from VTFET 34 on fin 22B. As shown in FIG. 3 , the left edge of gate 23T on fin 22T of VTFET 33 in the upper semiconductor layer and the left edge of gate 23B on fin 22B of VTFET 34 are horizontally separated or offset by half the contact gate pitch (e.g., ½ CGP). As shown, VTFET 33 and VTFET 34 include lower S / D 31 and upper S / D 41. In various embodiments, VTFET 33 is an n-type field effect (NFET) device and VTFET 34 is a p-type field effect (PFET) device. In embodiments, VTFET 33 is a PFET and VTFET is an NFET.

[0053] FIG. 4 is a cross-sectional view 400 through X1-X1 of the inverter shown in FIG. 3 in accordance with an embodiment of the present invention. As shown, FIG. 4 includes VTFET 33 and VTFET 34 with ground 24, wire 27, and gate contacts 26T and 26B, respectively. As shown, fin 22B resides in a lower device layer of the semiconductor structure relative to fin 22T (e.g., the lower device layer is directly below the semiconductor layer of fin 22T without any additional semiconductor devices existing between VTFET 33 and VTFET 34). In semiconductor structure 400, VTFET 33 is adjacent to and above VTFET 34, where the horizontal distance or offset between VTFET 33 and VTFET 34 in different semiconductor layers is half the CGP (e.g., a CGP of 1 is the distance between the gates of VTFETs in the same semiconductor layer).

[0054] 4, VTFET 33 includes gate contact 26T that connects to wire 27, gate 23T on fin 22T, which resides on lower S / D 31. As shown, VTFET 34 includes lower S / D 31, gate contact 26B, gate 23B on fin 22B, gate contact 26B that connects to wire 27, and etch stop 35. Etch stop 35, an optional element in VTFET 34, resides above gate 23B and below gate contact 26B. In some examples (not shown), etch stop 35 is not present in VTFET 34. In an embodiment, VTFET 33 is a PFET formed on fin 22T that can receive a signal from gate contact 26T, and VTFET 34 is an NFET formed on fin 22B that can receive a signal from gate contact 26B.

[0055] FIG. 5 is a cross-sectional view 500 through X2-X2 of the inverter shown in FIG. 3 in accordance with an embodiment of the present invention. As shown, FIG. 5 includes ground 24, wire 29, output connection 28T, output connection 28B, VTFET 33, and VTFET 34 with top S / D 41 above fin 22B and below etch stop 35. As shown, fin 22B may reside on a lower device layer of the semiconductor structure relative to fin 22T. In semiconductor structure 500, VTFET 33 is adjacent to and above VTFET 34, where the horizontal distance or offset between gate 23T in VTFET 33 and gate 23B in VTFET 34 is ½ CGP.

[0056] 5, VTFET 33 includes output connection 28T contacting wire 29, top S / D 41, fin 22T on bottom S / D 31, and gate 23T. As shown in FIG. 5, VTFET 34 includes output connection 28B connecting to wire 29, etch stop 35 on top S / D 41, fin 22B, gate 23B, and bottom S / D 31 on ground 24.

[0057] Etch stop 35 is an optional element of VTFET 34. As shown, top S / D 41 is an enlarged contact landing pad. The enlarged contact landing pad (e.g., top S / D 41) below etch stop 35 facilitates fabrication of VTFET 34 and helps improve device yield. The enlarged contact landing pad is an optional feature of the semiconductor structure shown in FIG. 5. Forming etch stop 35, which is also an optional element of the present invention, aids in the formation of an enlarged contact landing pad for top S / D 41.

[0058] Figure 6 is a cross-sectional view 600 through X3-X3 of the inverter shown in Figure 3 in accordance with an embodiment of the present invention. As shown, Figure 6 includes Vdd20, ground connection 54, upper S / D 31 below Vdd20, and lower S / D 31 above ground connection 54 and ground 24. In cross-sectional view 600 through X3-X3 of the inverter of Figure 3, Vdd20 resides above ground 24. In some embodiments, Vdd20 is the Vdd power rail.

[0059] FIG. 7 is a cross-sectional view 700 through Y1-Y1 of the inverter shown in FIG. 3 in accordance with an embodiment of the present invention. As shown, FIG. 7 includes VTFET 33, wire 27, wire 29, and Vdd 20 above a portion of ground 24 below VTFET 33. VTFET 33 includes a lower S / D 31 below fin 22T, a gate 23T that contacts and surrounds a portion of fin 22T, a gate contact 26T that connects to wire 27 and contacts gate 23T, and an upper S / D 41 that contacts an output connection 28T over a portion of fin 22T and connects to wire 29. FIG. 7 illustrates a portion of the inverter as extending along fin 22T and above ground 24 (e.g., cross-sectional view 700 bisects or passes through VTFET 33). 7 illustrates an example of a contact on the active area, also known as a contact or gate contact on active gate (COAG), where a contact such as gate contact 26T may be formed on gate 23T on fin 22T in VTFET 33. As known to those skilled in the art, COAG may reduce the cell area of ​​a vertical transport field effect transistor (e.g., reduce the device size).

[0060] FIG. 8 is a cross-sectional view 800 through Y2-Y2 of the inverter shown in FIG. 3 in accordance with an embodiment of the present invention. As shown, FIG. 8 includes wire 27, wire 29, ground connection 54, ground 24, VTFET 34 with top S / D 41 below optional etch stop 35 on the right side of VTFET 34, bottom S / D 31, gate 23B around it and contacting a portion of fin 22B, gate contact 26B on etch stop 35 at the left portion of gate 23B, gate contact 26B connecting to wire 27, and output connection 28B contacting etch stop 35 on the right edge. Output connection 28B connects to wire 29. In FIG. 8, VTFET 34 is above and connected to ground 24. As previously described, top S / D 41 may be an enlarged landing pad under optional etch stop 35, where the enlarged landing pad and etch stop 35 aid in the formation of output connection 28B (e.g., may provide improved yield in the formation of output connection 28B). In some embodiments, etch stop 35 acts as an intermediate contact with the enlarged landing pad for gate contact 26B and output connection 28B. As shown in FIG. 8 , etch stop 35 underlies gate contact 26B and output connection 28B.

[0061] FIG. 8 illustrates VTFET 34 as extending along fin 22B. VTFET 34 connects to ground 24 by ground connection 54. Similar to the semiconductor structure illustrated in FIG. 7, the semiconductor structure illustrated in FIG. 8 also allows for COAG, where a contact, such as gate contact 26B, can be formed to gate 23B on fin 22B in the active area of ​​VTFET 34. Thus, in various embodiments, COAG can be provided on fin 22T (e.g., the top fin) in VTFET 33 and on a lower semiconductor device layer, shown as VTFET 34 of the inverter. Additionally, as shown, wiring on each of the active fins is open for cell-to-cell connection.

[0062] 9, 10A, and 10B show three views (e.g., circuit schematic, top view, and bottom view) of four VTFETs formed on two different semiconductor layers to create a two-input NOR circuit using two PFET VTFETs (i.e., VTFET 92A and VTFET 92C shown in FIG. 10A) connected in series in the upper semiconductor layer and two NFET VTFETs (i.e., VTFET 92B and VTFET 92D shown in FIG. 10B) connected in parallel in the lower semiconductor layer. As shown in FIGS. 10A and 10B, each of VTFETs 92A and 92C (top PFETs VTFETs) is offset by ½ CGP from VTFETs 92B and 92D (adjacent PFETs VTFETs) that reside on fins in the semiconductor layer below VTFETs 92A and 92C, respectively.

[0063] As shown in Figures 10A and 10B, when Figure 10A is overlaid on Figure 10B, the four VTFETs forming the two-input NOR circuit of Figure 9 cover or use 2 CGP horizontal spacings in the combined surface of Figures 10A and 10B. In one example, the area of ​​the two-input NOR circuit of Figure 9, shown later in Figures 10A and 10B, can be 80 nm (cell height) x 80 nm when 1 CGP is 40 nm. In other examples, the areas of the two-input NOR circuits can be different.

[0064] FIG. 9 is a circuit schematic 900 of a single transistor strength device composed of a two-input NOR circuit according to an embodiment of the present invention. Circuit schematic 900 shows an example of a 1X or single strength transistor composed of a two-input NOR circuit formed using four VTFETs. The two-input NOR circuit shown in circuit schematic 900 is composed of two PFETs VTFETs connected in series and two NFETs VTFETs connected in parallel. The two PFETs VTFETs are formed in the upper semiconductor layer and are shown in more detail below in FIG. 10A. The two NFETs VTFETs are formed below the PFETs VTFETs, offset by ½ CGP from each of the PFETs VTFETs, and are shown in more detail below in FIG. 10B. In other embodiments, the top VTFET device is an NFET VTFET and the bottom two VTFETs are PFET VTFETs, or the top VTFET device is a mix of NFET and PFET devices and the bottom VTFET is a mix of NFET and PFET devices.

[0065] As shown, FIG. 9 includes a supply voltage, labeled Vdd, connected to a first PFET VTFET. The first PFET VTFET receives an input signal A, as shown. In FIG. 9, the first PFET VTFET is connected in series with a second PFET VTFET. In FIG. 9, the second PFET VTFET receives an input signal B and is connected to the first and second NFET VTFETs. The first NFET VTFET shown in FIG. 9 is connected in parallel with the second NFET VTFET, where the first NFET VTFET receives input signal A and the second NFET VTFET receives input signal B. As shown in FIG. 9, both the output of the second PFET VTFET and the output of the NFET VTFET are connected to form an output signal C. The two NFETs VTFET are connected to a ground voltage or ground, labeled Vss in FIG. 9.

[0066] The first PFET VTFET in Figure 9 is later shown in Figure 10A as PFET VTFET 92A, and the second PFET VTFET in Figure 9 is later shown in Figure 10A as PFET VTFET 92C. Also shown in Figure 10B are the first NFET VTFET, labeled 92B in Figure 10B, and the second NFET VTFET, labeled 92D in Figure 10B.

[0067] FIG. 10A is a top view 1000A of the single enhancement transistor of FIG. 9, configured from a two-input NOR circuit, in accordance with an embodiment of the present invention. As shown, top view 1000A includes two portions of wire 87, wire 89, ground 84, Vdd 80, contact 95, two gate contacts 86T, two gate contacts 86B, output connection 88T, output connection 88B, PFET VTFET 92A, and PFET VTFET 92C. PFET VTFET 92A and PFET VTFET 92C are above NFET VTFET 92B and NFET VTFET 92D in a lower semiconductor layer and are offset by ½ CGP. NFET VTFET 92C and NFET VTFET 92D are shown later in FIG. 10B. In FIG. 10A, PFET VTFET 92A and PFET VTFET 92C in the same semiconductor layer are separated by 1 CGP.

[0068] In FIG. 10A , PFET VTFET 92A is comprised of a gate 83T in contact with a fin 82T in contact with a bottom S / D 81, with a top S / D 61 above the fin 82T. PFET VTFET 92A receives a signal input A (shown in FIG. 9 ) at a gate contact 86T from a left-most portion of wire 87. Another right-most portion of wire 87 also connects gate contact 86T to gate contact 86B. PFET VTFET 92A may transmit an output signal C, as described with reference to FIG. 9 , to PFET VTFET 92C via the shared bottom S / D 81 and to an output connection 88T associated with PFET VTFET 92C. As will be described later with reference to FIG. 10B , gate contact 86B provides signal input A to NFET VTFET 92B, which resides in the lower semiconductor layer. Contact 95 connects top S / D 61 to Vdd 80 (Vdd 80 may also be known as the Vdd power rail).

[0069] In Figure 10A, PFET VTFET 92C is shown to the right of PFET VTFET 92A. The PFET VTFET 92C shown is composed of a right-most gate 83T on a right-most fin 82T, with a bottom source / drain 81 below the right-most fin 82T and a top source / drain 61 above the fin 82T. In various embodiments, the top source / drain 61 in PFET VTFET 92A connects to a contact 95 that connects to Vdd 80 (the Vdd power rail). PFET VTFET 92B and PFET VTFET 92A, previously described with respect to Figure 9, are connected in series.

[0070] A gate contact 86T on PFET VTFET 92C is above the right-most gate 83T and receives signal input B. Gate contact 86T connects to a second portion of wire 87. As shown, gate contact 86T on PFET VTFET 92C is connected through wire 87 to gate contact 86B (not shown in FIG. 10A ) that contacts gate 83B of NFET VTFET 92D. Gate contact 86B may provide signal input B to NFET VTFET 92D (shown in FIG. 10B ). As shown, gate contact 86B is midway between PFET VTFET 92A and PFET VTFET 92C, where PFET VTFET 92A and PFET VTFET 92C are separated by one CGP, as shown. In other words, each of the gate contacts 86T is horizontally spaced ½ CGP from at least one outer edge of the gate 83T of PFET VTFET 92A or PFET VTFET 92C. As previously explained, PFET VTFET 92A is connected in series with PFET VTFET 92C such that the output of PFET VTFET 92A is supplied to PFET VTFET 92C, and the output of PFET VTFET 92C is supplied to output connection 88T. Output connection 88T is connected by wire 89 to output connection 88B.

[0071] Also, as shown in FIG. 10A, the distance between gate 83T of PFET VTFET 92A and gate 83T of PFET VTFET 92C, which are present on the same semiconductor layer, is 1 CGP. PFET VTFET 92A has a horizontal distance of ½ CGP from the edge of the frame around FIG. 10A. The frame around FIG. 10A is directly above the frame around FIG. 10B. In other words, FIG. 10A is directly above FIG. 10B, and the combination of VTFET 92A and VTFET 92C in the upper semiconductor device layer shown in FIG. 10A and VTFET 92B and VTFET 92D in the lower semiconductor device layer shown in FIG. 10B forms the two-input NOR circuit of FIG. 9.

[0072] FIG. 10B is a bottom view 1000B of the single enhancement transistor of FIG. 9 configured from a two-input NOR circuit, in accordance with an embodiment of the present invention. As shown, FIG. 10B includes ground connection 85, ground 84, NFETs VTFETs 92B and 92D with gate contact 86B, and output connection 88B. As previously described, NFET VTFET 92B and NFET VTFET 92D are formed in a semiconductor layer below PFET VTFET 92A and PFET VTFET 92D (e.g., PFET VTFET 92A and PFET VTFET 92C are formed in a semiconductor layer directly above the semiconductor layer including NFET VTFET 92B and NFET VTFET 92D). As shown, VTFET 92B and VTFET 92D, which are spaced apart by 1 CGP, are horizontally offset by ½ CGP from VTFET 92A and VTFET 92C, respectively.

[0073] As shown in FIG. 10B, the left-most edge of gate 83B of NFET VTFET92B is spaced 1 CGP from gate 83B of NFET VTFET92D. Additionally, as shown, NFET VTFET92B is 1 CGP from the edge of the box that indicates where the adjacent NFET VTFET may be formed. As previously described, the edge of the box in FIG. 10B is directly below and aligned with the box in FIG. 10A. In this case, the horizontal distance or offset from PFET VTFET92A to NFET VTFET92B is 1 / 2 CGP (i.e., 1 CGP as shown in FIG. 10B minus 1 / 2 CGP as shown in FIG. 10A).

[0074] In FIG. 10B, NFET VTFET 92B is to the left of NFET VTFET 92D. NFET VTFET 92B, which contacts bottom S / D 91, consists of gate 83B, which contacts left-most fin 82B, and top S / D 71. The left end of gate contact 86B receives signal input A from wire 87, as described above. Output connection 88B contacts a portion of NFET VTFET 92B and connects to a portion of NFET VTFET 92D, as shown. Output connection 88B may receive an output signal from top S / D 71.

[0075] Also shown in Figure 10B, NFET VTFET 92D is comprised of gate 83B contacting the right-most fin 82B above bottom S / D 91. Fin 82B is below top S / D 71, where the right end of gate contact 86B resides on gate 83B of NFET VTFET 92D and receives signal input B (e.g., provided by upper wire 87 in Figure 10A). As previously described with respect to Figure 9, NFET VTFET 92B and NFET VTFET 92D are connected in parallel and both output to output connection 88B.

[0076] FIG. 11 is a circuit schematic 1100 of a single-transistor enhanced device consisting of a two-input NAND circuit, according to an embodiment of the present invention. Circuit schematic 1100 illustrates an example of a 1X or single-enhanced transistor consisting of a two-input NAND circuit formed using four VTFETs, shown later in FIGS. 12A and 12B as PFET VTFET 122A, PFET VTFET 122C, NFET VTFET 122B, and NFET VTFET 122D. The two-input NAND circuit shown in circuit schematic 1100 is composed of two PFET VTFETs connected in parallel and two NFET VTFETs connected in series. The two PFET VTFETs are formed in the upper semiconductor layer and are shown in more detail later in FIG. 12A. The two NFET VTFETs are formed below the two PFET VTFETs and are horizontally offset from the two PFET VTFETs by a horizontal distance of ½ CGP, as described with respect to FIGS. 12A and 12B. The two NFETs VTFETs are shown in more detail later in FIG. 12B.

[0077] As shown, FIG. 11 illustrates a circuit in which a supply voltage labeled Vdd is connected to a first PFET VTFET via input signal A and to a second PFET VTFET via input signal B, where the first PFET VTFET and the second PFET VTFET are connected in parallel as shown. As shown in FIG. 11, the first NFET VTFET receives input signal A, and the second NFET VTFET receives input signal B, where the first and second NFET VTFETs are connected in series as shown in FIG. 11. As previously explained, the first NFET VTFET is connected in series with the second NFET VTFET, so that the output from each of the two PFETs VTFET and the output from the first NFET VTFET are transmitted to output signal C by the second NFET VTFET, as shown in FIG. 11. In other words, output signal C includes the output from each of the four VTFETs. The first NFET VTFET is connected to a ground voltage, labeled Vss in FIG. 11.

[0078] The first PFET VTFET in Figure 11 is later shown in Figure 12A as PFET VTFET 122A, and the second PFET VTFET in Figure 11 is later shown in Figure 12A as PFET VTFET 122C. Also shown in Figure 12B are the first NFET VTFET labeled 122B in Figure 12B and the second NFET VTFET labeled 122D in Figure 12B.

[0079] 12A is a top view 1200A of a single enhancement transistor with two input NAND circuit shown in FIG. 11 in accordance with an embodiment of the present invention. Top view 1200A is a top view through various semiconductor layers (e.g., through an interlayer dielectric material). As shown, top view 1200A includes ground 94, Vdd 90, two gate contacts 96B, two output connections 98T, gate contact 96T, output connection 98B, two portions of wire 97, wire 99, PFET VTFET 122A, and PFET VTFET 122C. PFET VTFET 122A and PFET VTFET 122C are connected in parallel as shown in FIG. 11, where the top S / D 121 connected to PFET VTFET 122A and the output connection 98T connected to PFET VTFET 122C are connected by wire 99. PFET VTFET 122A and PFET VTFET 122D reside in a semiconductor layer above NFET VTFET 122B and NFET VTFET 122D. Output signal C, previously described with respect to Figure 9, comes from wire 99 and includes outputs from two of output connections 98T and 98B shown in Figure 12A.

[0080] Also shown in Figure 12A is the distance 1 CGP between PFET VTFET122A and PFET VTFET122C, and the distance 1 / 2 CGP from PFET VTFET122A to the edge of the frame shown in Figure 12A. Like Figures 10A and 10B, Figures 12A and 12B show views of different semiconductor layers directly above and below each other, where the edges of the frame around Figure 12A and the edges of the frame around Figure 12B are vertically aligned and directly above and below each other.

[0081] In FIG. 12A, PFET VTFET 122A in contact with bottom S / D 101 comprises gate 93T in contact with left-most fin 192T and top S / D 121 above fin 92T. Left-most gate contact 96T receives signal input A from a portion of wire 97, where a second portion of wire 97 connects to gate contact 96B. In PFET VTFET 122A, top S / D 121 is below output connection 98T. As shown in FIG. 12A, output signal C shown in FIG. 9 receives output from two output connections 98T and 98B, all connected by wire 99, from NFET VTFET 122D.

[0082] Also in FIG. 12A , PFET VTFET 122C is to the right of PFET VTFET 122A. As shown, PFET VTFET 122C includes gate 93T that contacts right-most fin 192T that contacts bottom S / D 101, and a portion of the right end of gate contact 96T contacts gate 93T. As shown in FIG. 12A , gate contact 96B connects to a portion of interconnect wire 97. As shown in FIGS. 12A and 11 , the top right-most gate contact 96T of PFET VTFET 122C receives signal input B from interconnect wire 97. Because PFET VTFET 122A and PFET VTFET 122C are connected in parallel (i.e., as previously shown and described with respect to FIG. 11 ), PFET VTFET 122C sends an output to output connection 98T using interconnect wire 99 that connects from PFET VTFET 122C to output connection 98T. Additionally, as shown in Figure 12A, wire 99 also connects to output connection 98B. As shown, the top S / D 121 in each of PFET VTFET 122A and PFET VTFET 122C connects to Vdd 90, which may be a shared Vdd power rail.

[0083] Figure 12B is a bottom view 1200B of a single enhancement transistor with two input NAND circuit of Figure 11 in accordance with an embodiment of the present invention. As shown, Figure 12B includes ground connection 105, ground 94, contact 95B, NFET VTFET122B, and NFET VTFET122D with gate contact 96B and output connection 98B. Figure 12B shows NFET VTFET122B and NFET VTFET122D formed in a semiconductor level below PFET VTFET122A and PFET VTFET122C shown in Figure 12A.

[0084] 12B, NFET VTFET122B in contact with bottom S / D 111 includes gate 93B in contact with the left edge of fin 192B, gate contact 96B for receiving signal input A, and contact 95B on top of top S / D 131 that connects to ground connection 105 that connects to ground 94. In some embodiments, ground connection 105 is the bottom conductive plane. As described with reference to FIG. 11, NFET VTFET122B and NFET VTFET122D are connected in series, and output connection 98B connects to NFET VTFET122D as shown.

[0085] The methods described herein can be used in the manufacture of integrated circuit chips or semiconductor chips. The resulting semiconductor chips can be distributed by manufacturers as bare die, in raw wafer form (i.e., a single wafer with multiple unpackaged chips), or in packaged form. In the latter case, the semiconductor chips are mounted in a single-chip package (such as a plastic carrier or other higher-level carrier with leads affixed to a motherboard) or a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the semiconductor chips are then integrated with other semiconductor chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing semiconductor chips, ranging from toys and other low-end applications to advanced computer products with displays, memory, keyboards or other input devices, and central processors.

[0086] In a preferred embodiment of the invention described herein, a semiconductor structure is provided, the semiconductor structure comprising: a first vertical transport field effect transistor in a lower semiconductor layer; and a second vertical transport field effect transistor in an upper semiconductor layer, wherein the first vertical transport field effect transistor is offset from the second vertical transport field effect transistor by half the contact gate pitch of the second vertical transport field effect transistor. Preferably, the first vertical transport field effect transistor has a linear vertical contact, and the second vertical transport field effect transistor has a linear vertical contact. Preferably, the first vertical transport field effect transistor is a first type field effect transistor, and the second vertical transport field effect transistor is a second type field effect transistor. Preferably, the offset is half the contact gate pitch of the second vertical transport field effect transistor. Preferably, the offset is in the range of 0.3 to 0.7 of the contact gate pitch of the second vertical transport field effect transistor.

[0087] In another preferred embodiment of the invention described herein, a semiconductor structure is provided, comprising: one or more vertical transport field effect transistors in an upper semiconductor layer, wherein the one or more vertical transport field effect transistors in the first semiconductor layer are spaced apart by one contact gate pitch; and one or more vertical transport field effect transistors in a lower semiconductor layer, wherein the one or more vertical transport field effect transistors in the lower semiconductor layer are spaced apart by one contact gate pitch; wherein the one or more vertical transport field effect transistors in the upper semiconductor layer are offset from the one or more vertical transport field effect transistors in the lower semiconductor layer. Preferably, the one or more vertical transport field effect transistors in the lower semiconductor layer have linear vertical contacts connecting to interconnect wiring above the one or more vertical transport field effect transistors in the upper semiconductor layer. Preferably, the one or more vertical transport field effect transistors in the lower semiconductor layer each have a contact on active gate (COAG). Preferably, the one or more vertical transport field effect transistors in the lower semiconductor layer are field effect transistors of a first type, and the one or more vertical transport field effect transistors in the upper semiconductor layer are field effect transistors of a second type. Preferably, the offset is in the range of 0.3 to 0.7 of the contact gate pitch. In another preferred embodiment of the invention described herein, a semiconductor structure is provided, comprising: a first pair of vertical transport field effect transistors in the lower semiconductor layer; a second pair of vertical transport field effect transistors in the upper semiconductor layer, wherein each of the second pair of vertical transport field effect transistors in the upper semiconductor layer is horizontally offset by half the contact gate pitch from at least one vertical transport field effect transistor in the lower semiconductor layer; and wherein the first pair of vertical transport field effect transistors in the lower semiconductor layer are vertical transport field effect transistors of a first type connected in parallel, and the second pair of vertical transport field effect transistors in the upper semiconductor layer are vertical transport field effect transistors of a second type connected in series.Preferably, each of the first pair of vertical transport field effect transistors in the lower semiconductor layer and each of the second pair of vertical transport field effect transistors in the upper semiconductor layer have linear vertical contacts to interconnect wires on the second pair of vertical transport field effect transistors. The structure may further comprise: a lower conductive surface connecting to at least one of the first pair of first type vertical transport field effect transistors in the lower semiconductor layer; and a power rail overlying and connected to at least one of the second pair of second type vertical transport field effect transistors in the upper semiconductor layer. Preferably, the first pair of vertical transport field effect transistors and the second pair of vertical transport field effect transistors in the lower semiconductor layer form two input NOR circuits. The structure may further comprise: a first pair of vertical transport field effect transistors in the lower semiconductor layer; a second pair of vertical transport field effect transistors in the upper semiconductor layer, wherein each of the second pair of vertical transport field effect transistors in the upper semiconductor layer is horizontally offset by half a contact gate pitch from at least one vertical transport field effect transistor in the lower semiconductor layer; and wherein the first pair of vertical transport field effect transistors in the lower semiconductor layer are vertical transport field effect transistors of a first type connected in series and the second pair of vertical transport field effect transistors in the upper semiconductor layer are vertical transport field effect transistors of a second type connected in parallel. Preferably, each of the first pair of vertical transport field effect transistors in the lower semiconductor layer and each of the second pair of vertical transport field effect transistors in the upper semiconductor layer have a linear vertical contact to an interconnect wire on the second pair of vertical transport field effect transistors. Preferably, the first pair of vertical transport field effect transistors and the second pair of vertical transport field effect transistors in the lower semiconductor layer form two input NAND circuits.

Claims

1. a first plurality of vertical transport field effect transistors in the lower semiconductor layer; and a second plurality of vertical transport field effect transistors in the upper semiconductor layer, wherein the second plurality of vertical transport field effect transistors are offset from the first plurality of vertical transport field effect transistors; A semiconductor structure comprising:

2. 2. The semiconductor structure of claim 1, wherein the second plurality of vertical transport field effect transistors in the upper semiconductor layer are each horizontally offset from the first plurality of vertical transport field effect transistors in the lower semiconductor layer by half a contact gate pitch.

3. 2. The semiconductor structure of claim 1, wherein each of the second plurality of vertical transport field effect transistors in the upper semiconductor layer has a horizontal distance of one contact gate pitch relative to an adjacent vertical transport field effect transistor of the second plurality of vertical field effect transistors in the upper semiconductor layer.

4. 2. The semiconductor structure of claim 1, wherein the first plurality of vertical transport field effect transistors in the lower semiconductor layer each have one or more contacts with direct linear vertical connections.

5. 5. The semiconductor structure of claim 4, wherein each of the one or more contacts with the direct linear vertical connection is between two adjacent vertical transport field effect transistors of the second plurality of vertical transport field effect transistors in the upper semiconductor layer.

6. 2. The semiconductor structure of claim 1, wherein the first plurality of vertical transport field effect transistors in the lower semiconductor layer each have a gate contact on an active gate (COAG).

7. 10. The semiconductor structure of claim 1, wherein the second plurality of vertical transport field effect transistors have a gate contact on at least one active gate (COAG).

8. 2. The semiconductor structure of claim 1, wherein the second plurality of vertical transport field effect transistors in the upper semiconductor layer are each horizontally offset from the first plurality of vertical transport field effect transistors in the lower semiconductor layer by a distance in the range of 0.3 to 0.7 contact gate pitch.

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