Light-emitting diode chip structure

Abstract

Light-emitting diodes (LEDs), and more specifically, LED chip structures, are disclosed. The LED chip structures include one or more contacts, interconnects, contact structures, and / or reflective layer arrangements that effectively route conductive paths while reducing instances of oppositely charged metals being placed in close proximity. Particular LED chip structures include electrically isolated metal-containing layers at various chip locations, allowing for the presence of vertically positioned n-contact interconnects below or near the p-contact. Particular contact structures include various arrangements that include segmented contact structures that extend laterally to electrically couple groups of n-contact interconnects across various LED chip portions.

Description

[Technical Field]

[0001]

[0001] The present disclosure relates to light emitting diodes, and more particularly to LED chip structures. [Background technology]

[0002]

[0002] Solid-state light-emitting devices, such as light-emitting diodes (LEDs), are increasingly used in both consumer and commercial applications. Advances in LED technology have resulted in highly efficient, mechanically robust, and long-life light sources. Modern LEDs are therefore enabling a variety of new display applications and are increasingly being used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0003]

[0003] LEDs are solid-state devices that convert electrical energy into light and typically contain one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the active layer(s), where they recombine to produce light emission, such as visible or ultraviolet light. The active region may be fabricated, for example, from silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials, and / or from organic semiconductor materials. Photons generated by the active region are emitted in all directions.

[0004]

[0004] It is typically desirable to operate an LED at the highest light emission efficiency, which can be measured in terms of radiant intensity (e.g., lumens per watt) relative to output power. A practical goal for increasing emission efficiency is to maximize the extraction of light emitted from the active region in the desired light transmission direction. The light extraction and external quantum efficiency of an LED can be limited by many factors, including internal reflection and current injection. To increase current spreading within the LED chip, especially for large-area LED chips, it has been found useful to add a highly conductive layer above one or more epitaxial layers of the LED. In addition, the electrodes of the LED can have a large surface area and may include various electrode configurations configured to route and evenly distribute current throughout the LED.

[0005] As modern LED technology advances, the art continues to seek improved LEDs and solid state light emitting devices with desirable lighting characteristics that can overcome the challenges associated with conventional light emitting devices. Summary of the Invention [Means for solving the problem]

[0006]

[0006] This disclosure relates to light-emitting diodes (LEDs), and more particularly to LED chip structures. The LED chip structures include one or more contacts, interconnects, contact structures, and / or reflective layer arrangements that effectively route conductive paths while also reducing the occurrence of adjacently placed metals with opposite polarity charges. Certain LED chip structures include electrically isolated metal-containing layers at various chip locations, allowing for vertically placed n-contact interconnects below or near the p-contacts. Certain contact structures include various arrangements that include segmented contact structures that extend laterally to electrically couple groups of n-contact interconnects across various LED chip portions.

[0007] In one aspect, an LED chip comprises an active LED structure including an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; an n-contact electrically coupled to the n-type layer; a p-contact electrically coupled to the p-type layer; and a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contact, wherein one or more of the plurality of n-contact interconnects are vertically disposed between the p-contact and the n-type layer. In a specific embodiment, one or more of the plurality of n-contact interconnects are electrically coupled to an n-contact structure electrically coupled to the n-contact. In a specific embodiment, the n-contact structure is disposed to extend laterally from a position vertically registered with the n-contact to a position vertically registered with the p-contact, whereby the n-contact structure is electrically coupled to one or more of the plurality of n-contact interconnects vertically disposed between the p-contact and the n-type layer.

[0008] The LED chip may further include a peripheral n-contact interconnect electrically coupled to a portion of the n-type layer outside the mesa sidewall of the active LED structure, the mesa sidewall including the sidewall of the p-type layer, the active layer, and a portion of the n-type layer, the n-contact structure being positioned to extend laterally from a position vertically overlapping the n-contact to the mesa sidewall, thereby electrically coupling the n-contact structure to the peripheral n-contact interconnect. In a specific embodiment, the peripheral n-contact interconnect is electrically coupled to one or more n-contact interconnects among a plurality of n-contact interconnects vertically disposed between the p-contact and the n-type layer. In a specific embodiment, the peripheral n-contact interconnect is electrically coupled to a portion of the n-type layer outside the mesa sidewall in a continuous manner adjacent two or more peripheral edges of the active LED structure. In a particular embodiment, the peripheral n-contact interconnect is discontinuously electrically coupled to a portion of the n-type layer outside the mesa sidewall, such that a portion of the peripheral n-contact interconnect contacts the n-type layer and another portion of the peripheral n-contact interconnect is separated from the n-type layer by a passivation layer.

[0009] In certain embodiments, the LED chip further comprises a reflective structure on the active LED structure, the reflective structure comprising a first reflective layer that is insulating, a second reflective layer that is conductive, and a plurality of reflective layer interconnects that extend through the first reflective layer and electrically couple a first portion of the second reflective layer to the p-type layer. In certain embodiments, the second portion of the second reflective layer is electrically isolated from the active LED structure. In certain embodiments, the second portion of the second reflective layer is vertically disposed between the n-contact structure and the active LED structure. In certain embodiments, the second portion of the second reflective layer is completely isolated from the p-type layer by a passivation layer, and the second portion of the second reflective layer is electrically coupled to the n-contact.

[0010]

[0010] The LED chip further comprises a passivation layer on the active LED structure, wherein the multiple n-contact interconnects extend through a portion of the passivation layer, and a first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer disposed within the passivation layer, each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer being electrically isolated from the n-contact and the p-contact.

[0011] In a particular embodiment, the n-contact and p-contact are contact pads positioned to receive external electrical connections when the LED chip is flip-chip mounted.

[0012] In another embodiment, the LED chip comprises an active LED structure including an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer, a passivation layer on the active LED structure, and first, second, and third metal-containing interlayers at least partially within the passivation layer, each of the first, second, and third metal-containing interlayers being electrically isolated from the active LED structure. The LED chip may further comprise a reflective structure on the active LED structure, the reflective structure comprising a first insulating reflective layer, a second conductive reflective layer, and a plurality of reflective layer interconnects extending through the first reflective layer and electrically coupling a first portion of the second reflective layer to the p-type layer, the second metal-containing interlayer comprising a second portion of the second reflective layer being electrically isolated from the active LED structure. The LED chip may further include an n-contact electrically coupled to the n-type layer, a p-contact electrically coupled to the p-type layer, a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contact, and an n-contact structure electrically coupled to one or more of the plurality of n-contact interconnects, the n-contact structure being arranged to extend laterally within the passivation layer. In certain embodiments, the third metal-containing interlayer comprises the same material as the n-contact structure. In certain embodiments, the second metal-containing interlayer is arranged vertically between the n-contact structure and the active LED structure. The LED chip may further include a reflective structure on the active LED structure, the reflective structure comprising a first reflective layer that is insulating and a second reflective layer that is conductive, the first reflective layer being between the second reflective layer and the p-type layer, and the second metal-containing interlayer comprising a portion of the second reflective layer electrically isolated from the active LED structure. In certain embodiments, the portion of the second reflective layer electrically isolated from the active LED structure is arranged vertically between the n-contact structure and the active LED structure. In certain embodiments, the first metal-containing interlayer, the second metal-containing interlayer, and the third metal-containing interlayer are vertically disposed within the passivation layer.

[0012]

[0013] In another aspect, an LED chip includes an active LED structure including an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a plurality of n-contact interconnects electrically coupled to the n-type layer; and an n-contact structure electrically coupled to the plurality of n-contact interconnects, the n-contact structure including a first segment connected to a first group of the plurality of n-contact interconnects and a second segment connected to a second group of the plurality of n-contact interconnects. In certain embodiments, the first segment of the n-contact structure is discontinuous with the second segment of the n-contact structure. In certain embodiments, the first segment of the n-contact structure is positioned to extend continuously from one end of the active LED structure to the opposite end of the active LED structure. In certain embodiments, the second segment of the n-contact structure is positioned to extend continuously without extending to at least one end of the active LED structure. The LED chip may further comprise an n-contact electrically coupled to the n-contact structure and a p-contact electrically coupled to the p-type layer, the plurality of n-contact interconnects being disposed vertically outside a peripheral edge of the p-contact. In certain embodiments, the p-contact comprises a first portion disposed vertically between a boundary of a first segment of the n-contact structure and an outer periphery of the active LED structure, and a second portion disposed vertically between another boundary of the first segment of the n-contact structure and a boundary of a second segment of the n-contact structure, the first portion of the p-contact being discontinuous with the second portion of the p-contact.

[0013]

[0014] In other aspects, any of the aforementioned aspects may be used individually or together, and / or in combination with various individual aspects and features described herein to provide additional advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless indicated to the contrary herein.

[0014]

[0015] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0015] [Figure 1A]

[0017] FIG. 1A is a top view of a typical light emitting diode (LED) chip with a flip-chip configuration that includes an active LED structure and n-contact interconnects disposed along or within certain portions of the active LED structure. [Figure 1B]

[0018] FIG. 1B is a bottom view of the LED chip of FIG. 1A illustrating the location of the p-contact and n-contact. [Figure 2A]

[0019] FIG. 2A is a top view of an LED chip having a flip-chip configuration with n-contact interconnects disposed over an expanded area of ​​the active LED structure in accordance with the principles of the present disclosure. [Figure 2B]

[0020] FIG. 2B is a bottom view of the LED chip of FIG. 2A illustrating the location of the p-contact and n-contact pads. [Figure 3]

[0021] FIG. 3 is a generalized cross-sectional view of a portion of an LED chip similar to that of FIGS. 2A and 2B. [Figure 4A]

[0022] FIG. 4A is a cross-sectional view of a portion of an LED chip in a manufacturing process after an active LED structure has been formed on a substrate and a number of first openings have been defined in the p-type layer, the active layer, and a portion of the n-type layer of the active LED structure. [Figure 4B]

[0023] FIG. 4B is an example top view of the LED chip of FIG. 4A illustrating how the first openings are arranged in an array across the LED chip. [Figure 5A]

[0024] FIG. 5A is a cross-sectional view of a portion of the LED chip of FIG. 4A during manufacturing after a current spreading layer is formed on the p-type layer. [Figure 5B]

[0025] FIG. 5B is an example top view of the LED chip of FIG. 5A illustrating how the current spreading layer is disposed relative to each first opening. [Figure 6A]

[0026] 6A is a cross-sectional view of a portion of the LED chip of FIG. 5A during manufacturing after a first reflective layer has been formed and multiple second and third openings have been formed through the first reflective layer. [Figure 6B]

[0027] FIG. 6B is an example top view of the LED chip of FIG. 6A illustrating how the second opening and the third opening are positioned relative to the first opening. [Figure 7A]

[0028] FIG. 7A is a cross-sectional view of a portion of the LED chip of FIG. 6A during manufacturing after a second reflective layer has been formed on the first reflective layer. [Figure 7B]

[0029] FIG. 7B is an example top view of the LED chip of FIG. 7A illustrating how the second reflective layer is disposed relative to the first and second openings. [Figure 8]

[0030] FIG. 8 is a cross-sectional view of a portion of the LED chip of FIG. 7A during manufacturing after a portion of the passivation layer has been formed on the second reflective layer. [Figure 9A]

[0031] 9A is a cross-sectional view of a portion of the LED chip of FIG. 8 during manufacturing after the n-contact structure, n-contact interconnect, and third intermediate layer have been formed. [Figure 9B]

[0032] FIG. 9B is an example top view of the LED chip of FIG. 9A illustrating the layout pattern of the n-contact structures, n-contact interconnects, and third intermediate layer throughout the active LED structure. [Figure 10A]

[0033] FIG. 10A is a cross-sectional view of a portion of the LED chip of FIG. 9A during manufacturing after additional portions of the passivation layer and first intermediate layer have been formed. [Figure 10B]

[0034] FIG. 10B is an example top view of the LED chip of FIG. 10A illustrating a layout pattern of the first intermediate layer. [Figure 11]

[0035] FIG. 11 is a cross-sectional view of a portion of the LED chip of FIG. 10A during manufacturing after an additional portion of the passivation layer has been formed above the first intermediate layer and eighth and ninth openings have been formed through the sixth and seventh openings, respectively. [Figure 12]

[0036] 12 is a cross-sectional view of a portion of the LED chip of FIG. 11 during manufacturing after the p-contact, p-contact via, n-contact, and n-contact via have been formed. [Figure 13A]

[0037] FIG. 13A is a cross-sectional view of a portion of an LED chip similar to that of FIG. 12A, where the n-contact structure further includes a peripheral n-contact interconnect that traverses along the peripheral edge of the LED chip. [Figure 13B]

[0038] FIG. 13B is an example top view of the LED chip of FIG. 13A illustrating the layout pattern of the n-contact interconnects, peripheral n-contact interconnects, and n-contacts relative to the p-contacts. [Figure 14A]

[0039] FIG. 14A is an illustrative top view of an LED chip similar to that of FIGS. 13A and 13B and further illustrating an embodiment in which the electrical connection between the peripheral n-contact interconnects and the n-type layer is segmented along the periphery of the LED chip. [Figure 14B]

[0040] 14B is a cross-sectional view of the LED chip of FIG. 14A taken along section line 14B-14B of FIG. 14A. [Figure 14C]

[0041] 14C is a cross-sectional view of the LED chip of FIG. 14A taken along section line 14C-14C of FIG. 14A. [Figure 15]

[0042] FIG. 15 is an exemplary top view of an LED chip similar to that of FIGS. 13A and 13B, but including an alternative arrangement in which the n-contact interconnect is not vertically superimposed below the p-contact. [Figure 16]

[0043] FIG. 16 is an exemplary top view of an LED chip similar to that of FIG. 15, but including an arrangement in which the p-contact covers a larger area of ​​the LED chip. [Figure 17A]

[0044] FIG. 17A is a top view of an LED chip with segmented p-contacts in a manufacturing process after elements such as reflective layer interconnects, n-contact interconnects, n-contact structures, peripheral n-contact interconnects, and openings have been formed. [Figure 17B]

[0045] FIG. 17B is a top view of the LED chip of FIG. 17A at a subsequent manufacturing stage after elements such as the segmented p-contact, p-contact via, and n-contact have been formed. [Figure 18]

[0046] FIG. 18 is a top view of an LED chip with a pattern of n-contact interconnects and reflective layer interconnects in accordance with the principles disclosed herein. [Figure 19]

[0047] FIG. 19 is a top view of an LED chip similar to that of FIG. 18, but with a higher density of n-contact interconnects and reflective layer interconnects. [Figure 20]

[0048] FIG. 20 is a top view of an LED chip similar to that of FIG. 18, except that the n-contact interconnect is not superimposed between the boundary of the p-contact and the active LED structure. [Figure 21]

[0049] FIG. 21 is a cross-sectional view of a portion of an LED chip similar to that of FIG. 13A for an embodiment in which a particular portion of the second reflective layer is electrically coupled to the n-contact. DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0050] The embodiments set forth below represent the information necessary to enable one skilled in the art to practice the embodiments and illustrate the best modes for practicing the embodiments. Upon reading the following description in conjunction with the accompanying drawings, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0017]

[0051] As used herein, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018]

[0052] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "over" another element, it will be understood that the element can be directly on or extending directly above the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly above" another element, there are no intervening elements. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "above" or extending "over" another element, it will be understood that the element can be directly on or extending directly above the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly above" another element, there are no intervening elements. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0019]

[0053] Relative terms such as "bottom" or "top" or "upper" or "below" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0020]

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. Furthermore, it will be understood that the terms "comprises," "comprising," "including," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021]

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Furthermore, terms used herein should be interpreted as having a meaning consistent with the meaning in the context of the present specification and related art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0022]

[0056] Embodiments are described herein with reference to schematic diagrams of embodiments of the present disclosure. Accordingly, actual dimensions of layers and elements may vary, and variations from the shapes of the figures are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular may have rounded or curved features, and regions illustrated as straight lines may have slight irregularities. Accordingly, regions illustrated in the figures are schematic, and the shapes of those regions are not intended to illustrate the exact shape of a region of a device or to limit the scope of the disclosure. Additionally, the size of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, therefore, are provided to illustrate the general structure of the inventive subject matter and may or may not be drawn to scale. Elements common between figures may be identified herein with common element numbers and may not be described again later.

[0023]

[0057] The present disclosure relates to light-emitting diodes (LEDs), and more particularly to LED chip structures. The LED chip structures include one or more contacts, interconnects, contact structures, and / or reflective layer arrangements that effectively route conductive paths while reducing the likelihood of oppositely charged metals being placed in close proximity. Particular LED chip structures include electrically isolated metal-containing layers at various chip locations, allowing for vertically positioned n-contact interconnects beneath or near the p-contacts. Particular contact structures include various arrangements that include segmented contact structures that extend laterally to electrically couple groups of n-contact interconnects across various LED chip portions.

[0024]

[0058] An LED chip typically comprises an active LED structure or region that can have many different semiconductor layers arranged in different ways. The fabrication and operation of LEDs and their active structures are generally known in the art and will be briefly discussed herein. The layers of the active LED structure can be fabricated using known processes, with a suitable process being fabrication using metalorganic chemical vapor deposition. The layers of the active LED structure can comprise many different layers, and generally comprise an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all formed in sequence on a growth substrate. It is understood that additional layers and elements in the active LED structure can also include, but are not limited to, buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current spreading layers, light extraction layers, and the like. The active layer can comprise a single quantum well, multiple quantum wells, double heterostructure, or superlattice structure.

[0025]

[0059] The active LED structure can be fabricated from different material systems, some of which are III-nitride-based. III-nitrides refer to semiconductor compounds formed between nitrogen (N) and elements from group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. III-nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For III-nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Thus, the active, n-type, and p-type layers may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN, undoped or doped with Si or Mg, in III-nitride-based material systems. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0026]

[0060] The active LED structure can be grown on a growth substrate, which can include many materials, such as sapphire, SiC, aluminum nitride (AlN), and GaN. A suitable substrate is the 4H polytype of SiC, although other SiC polytypes, such as the 3C, 6H, and 15R polytypes, can also be used. SiC has certain advantages, such as a closer crystal lattice match with III-nitrides than other substrates, resulting in high-quality III-nitride films. SiC also has very high thermal conductivity, so the total output power of III-nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for III-nitrides and offers certain advantages, such as low cost, an established manufacturing process, and excellent optical properties with excellent light transmission.

[0027]

[0061] Different embodiments of the active LED structure can emit light of different wavelengths depending on the composition of the active layer, n-type layer, and p-type layer. In certain embodiments, the active LED structure can emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure may emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure may emit red light with a peak wavelength range of 600 nm to 650 nm. In certain embodiments, the active LED structure may be configured to emit light outside the visible spectrum, including one or more portions of the ultraviolet (UV), infrared (IR), or near-IR spectrum. The UV spectrum is typically divided into three wavelength range categories, designated by the letters A, B, and C. Thus, UV-A light is typically defined as having a peak wavelength range of 315 nm to 400 nm, UV-B is typically defined as having a peak wavelength range of 280 nm to 315 nm, and UV-C is typically defined as having a peak wavelength range of 100 nm to 280 nm. The near-IR and / or IR wavelengths of the LED structures of the present disclosure can have wavelengths greater than 700 nm, such as in the range of 750 nm to 1100 nm or greater.

[0028]

[0062] The LED chip can be coated with one or more luminescent or other conversion materials, such as phosphors, whereby at least a portion of the light from the LED chip is absorbed by the one or more phosphors and converted to one or more different wavelength spectra according to the characteristic emissions from the one or more phosphors. In some embodiments, the combination of the LED chip and one or more phosphors emits a combination of approximately white light. The one or more phosphors can be selected from yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Ca i-x-y Sr x EU y The luminescent material may include one or more of the following: a phosphor, a scintillator, a luminescent ink, a quantum dot material, a daylight tape, and the like. The luminescent material may be provided by any suitable means, such as, for example, a coating directly on one or more surfaces of the LED, a dispersion in an encapsulant configured to cover one or more LEDs, and / or a coating (e.g., by powder coating, inkjet printing, etc.) on one or more optical or support elements. In certain embodiments, the luminescent material may be downconverted or upconverted, or a combination of both downconverting and upconverting materials may be provided. In certain embodiments, multiple different (e.g., different composition) luminescent materials arranged to produce different peak wavelengths may be arranged to receive the emitted light from one or more LED chips. In some embodiments, the one or more phosphors may be a yellow phosphor (e.g., YAG:Ce), a green phosphor (e.g., LuAg:Ce), and a red phosphor (e.g., Ca i-x-y Sr x EU y AlSiN3), and combinations thereof. One or more luminescent materials may be provided on one or more portions of the LED chip and / or submount in various configurations.

[0029]

[0063] Light emitted by the active layer or region of an LED chip may typically travel in a variety of directions. For targeted applications, an internal mirror or external reflective surface may be applied to redirect as much light as possible into the desired emission direction. The internal mirror may include a single layer or multiple layers. Some multilayer mirrors include a metallic reflective layer and a dielectric reflective layer, with the dielectric reflective layer disposed between the metallic reflective layer and multiple semiconductor layers. A passivation layer is disposed between the metallic reflective layer and first and second electrical contacts, with the first electrical contact disposed in conductive communication with the first semiconductor layer and the second electrical contact disposed in conductive communication with the second semiconductor layer. For single-layer or multilayer mirrors that include surfaces with reflectivity less than 100%, some light may be absorbed by the mirror. In addition, light redirected through the active LED structure may be absorbed by other layers or elements internal to the LED chip.

[0030]

[0064] As used herein, a layer or region of a light-emitting device may be considered “transparent” if at least 80% of the light emitted that strikes the layer or region passes through the layer or region and emerges. Additionally, as used herein, a layer or region of an LED may be considered “reflective” or embody a “mirror” or “reflector” if at least 80% of the light emitted that strikes the layer or region is reflected. In some embodiments, the light emitted comprises visible light, such as blue and / or green LEDs, with or without a light-emitting material. In other embodiments, the light emitted may comprise non-visible light. For example, in the case of GaN-based blue and / or green LEDs, silver (Ag) may be considered a reflective material (e.g., at least 80% reflective). In the case of UV LEDs, appropriate materials may be selected to achieve high reflectivity in some desired embodiments and / or low absorption in some desired embodiments. In certain embodiments, a “light-transmitting” material may be configured to transmit at least 50% of the light emitted at a desired wavelength.

[0031]

[0065] The present invention may be useful for LED chips having various shapes, including flip-chip shapes. Flip-chip LED chip configurations typically include anode and cathode connections made from the same side or surface of the LED chip. The anode and cathode sides are typically configured as mounting surfaces of the LED chip for flip-chip mounting to another surface, such as a printed circuit board. In this regard, the anode and cathode connections on the mounting surface serve to mechanically mount and electrically couple the LED chip to another surface. For flip-chip mounting, the opposite side or surface of the LED chip corresponds to the light-emitting surface, which faces the intended direction of light emission. In certain embodiments, during flip-chip mounting, the growth substrate of the LED chip can form and / or be adjacent to the light-emitting surface. During chip fabrication, the active LED structure may be epitaxially grown on the growth substrate. When electrically activated, light from the active LED structure may pass through the growth substrate in the desired emission direction. In certain embodiments, a growth substrate may not be present in flip-chip LEDs.

[0032]

[0066] During operation, the quantum efficiency of an LED chip may be related to various factors, such as current injection efficiency and thermal management. Such factors may be particularly important for large LED chips, e.g., with lateral dimensions of 500 microns (μm) or greater, which require current to be spread over a larger surface area and may generate more heat, although the principles disclosed herein are readily applicable to smaller LED chips with lateral dimensions less than 500 μm. Current injection throughout the active LED structure may be provided by electrical connection structures providing anode and cathode connections for the active LED structure. The anode and cathode connections may include LED chip bond pads positioned to receive external electrical connections for the LED chip, and conductive paths between the LED chip bond pads and the active LED structure may be routed by various conductive layers and via structures.

[0033]

[0067] In an exemplary flip-chip LED structure, the anode and cathode bond pads are typically located on the mounting surface of the LED chip, along with separate internal electrical connections, such as metal layers and via structures, that provide electrical coupling between the active LED structure and each of the anode and cathode bond pads. If internal electrical connections of opposite polarity are located too close to each other, strong electromotive forces may cause electromigration of metal between them. For example, a sufficiently strong electromotive force may cause breakdown of the dielectric material that is supposed to provide electrical isolation between the opposite-polarity electrical connections. In addition, metal may migrate through defects present in the dielectric material, thereby increasing the possibility of electrical shorts. For these reasons, flip-chip LED structures typically avoid placing electrical connections to n-type layers between the anode bond pad and the active LED structure.

[0034]

[0068] According to an aspect of the present disclosure, a flip-chip LED arrangement is disclosed that takes into account the above-mentioned electromotive forces and enables electrical connection to the n-type layer between the anode bond pad and the active LED structure. By providing such an arrangement, where the n-type electrical connection may be provided along a larger LED chip area, improved current spreading and / or current injection may be achieved. Additionally, the surface area of ​​the anode contact pad may be increased, thereby allowing the anode and cathode contact pads to be similar in relative size. In this regard, a more uniform surface area for attaching the anode and cathode contact pads may improve the integrity of the attachment to external electrical connections, such as traces on the substrate to which the LED chip is flip-chip attached.

[0035]

[0069] FIG. 1A is a top view of a typical LED chip 10 with a flip-chip configuration, including an active LED structure 12 and an n-contact interconnect 14 disposed along or within a particular portion of the active LED structure 12. FIG. 1B is a bottom view of the LED chip 10 of FIG. 1A, illustrating the location of the p-contact 16 or p-contact pad and the n-contact 18 or n-contact pad. The top view of FIG. 1A represents the light-emitting side of the LED chip 10, while the bottom view of FIG. 1B represents the mounting side of the LED chip 10. As illustrated in FIG. 1B, the p-contact 16 occupies a relatively small area compared to the n-contact 18. Referring back to FIG. 1A, the region on the left side of the LED chip 10 corresponding to the region of the p-contact 16 in FIG. 1B is free of the n-contact interconnect 14, avoiding the aforementioned problems associated with electromotive forces between adjacent internal electrical connections of opposite polarity.

[0036]

[0070] FIG. 2A is a top view of an LED chip 20 having a flip-chip configuration in which n-contact interconnects 14 are disposed over an expanded area of ​​the active LED structure 12 in accordance with the principles of the present disclosure. FIG. 2B is a bottom view of the LED chip 20 of FIG. 2A , illustrating the locations of the p-contacts 16 and n-contact pads 18. As illustrated in FIG. 2A , the n-contact interconnects 14 may be disposed along a location corresponding to the area of ​​the p-contact 16 from FIG. 2B . As described in detail below, various arrangements of the electrical connections between the p-contacts 16 and the p-type layers of the active LED structure 12 and between the n-contacts 18 and the n-type layers of the active LED structure 12 are disclosed, which reduce the formation of electromotive forces between adjacent internal electrical connections of opposite polarity. In this manner, one or more of the n-contact interconnects 14 may be disposed between the p-contacts 16 and the n-type layers of the active LED structure 12.

[0037]

[0071] FIG. 3 is a schematic cross-sectional view of a portion of an LED chip 22 similar to the LED chip 20 of FIGS. 2A and 2B . The active LED structure 12 is formed on a substrate 24, such as an epitaxial growth substrate. The LED chip 22 may incorporate a flip-chip configuration so that it can be mounted in the reverse orientation illustrated in FIG. 3 . In this regard, the mounting surface 22′ of the LED chip 22 is positioned on the top side of the illustration in FIG. 3 , and the primary light-emitting surface 22″ of the LED chip 22 is formed by the surface of the substrate 24. The active LED structure 12 generally comprises a p-type layer 25, an n-type layer 26, and an active layer 28 formed on the substrate 24. In certain embodiments, the n-type layer 26 is disposed between the active layer 28 and the substrate 24. In other embodiments, the doping order may be reversed, such that layer 26 is p-type doped and layer 25 is n-type doped. Substrate 24 can comprise many different materials, such as sapphire or SiC, and may have one or more surfaces that are shaped, textured, or patterned to enhance light extraction. In certain embodiments, substrate 24 is optically transmissive (preferably transparent) to the wavelengths of light produced by active LED structure 12.

[0038]

[0072] The LED chip 22 may include a first reflective layer 30 disposed on the p-type layer 25. In certain embodiments, a current spreading layer 32, such as a thin layer of a transparent conductive oxide such as indium tin oxide (ITO) or a metal such as platinum (Pt), may be disposed between the p-type layer 25 and the first reflective layer 30. The first reflective layer 30 can comprise many different materials, preferably a material that exhibits a refractive index step with the materials comprising the active LED structure 12 to promote total internal reflection (TIR) ​​of light generated from the active LED structure 12. Light that undergoes TIR may be redirected without absorption or loss, thereby contributing to useful or desired LED chip light emission. In certain embodiments, the first reflective layer 30 comprises a material having a refractive index lower than that of the material of the active LED structure 12. The first reflective layer 30 may comprise many different materials, some of which have a refractive index less than 2.3, others less than 2.15, less than 2.0, or even less than 1.5. In certain embodiments, the first reflective layer 30 comprises a dielectric material comprising, in certain embodiments, silicon dioxide (SiO2) and / or silicon nitride (SiN). SiN, SiN x , Si3N4, Si, Germanium (Ge), SiO2, SiO x , titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), ITO, magnesium oxide (MgO x It will be appreciated that many dielectric materials may be used, such as silicon dioxide (SiO2), zinc oxide (ZnO), and combinations thereof. By providing the first reflective layer 30 as a dielectric layer, the first reflective layer 30 may advantageously be disposed over the active LED structure 12 without concern for electrical shorting between the anode and cathode electrical connections. In certain embodiments, the first reflective layer 30 may include multiple alternating layers of different dielectric materials, for example, symmetrically repeated or asymmetrically arranged alternating layers of SiO2 and SiN.

[0039]

[0073] The LED chip 22 may further include a second reflective layer 34 on the first reflective layer 30 such that the first reflective layer 30 is disposed between the active LED structure 12 and the second reflective layer 34. The second reflective layer 34 may include a metal layer configured to reflect light from the active LED structure 12 that may pass through the first reflective layer 30. The second reflective layer 34 may comprise a number of different materials, such as Ag, gold (Au), Al, or combinations thereof. As illustrated, the second reflective layer 34 may include one or more reflective layer interconnects 38 that provide a conductive path through the first reflective layer 30 to electrically couple the second reflective layer 34 to the p-type layer 25. In certain embodiments, the reflective layer interconnects 38 comprise reflective layer metal vias. Thus, the first reflective layer 30, the second reflective layer 34, and the reflective layer interconnects 38 form the reflective structure of the LED chip 22. In certain embodiments, the reflective layer interconnect 38 comprises the same material as the second reflective layer 34 and is formed simultaneously with the second reflective layer 34. In other embodiments, the reflective layer interconnect 38 may comprise a different material than the second reflective layer 34. The LED chip 22 may optionally include a barrier layer on a portion of the second reflective layer 34 opposite the reflective layer interconnect 38 to prevent migration of material from the second reflective layer 34, such as Ag, into other layers. Such a barrier layer may comprise a conductive material, with suitable materials including, but not limited to, a bulk material formed by sputtering Ti / Pt followed by Au or a bulk material formed by sputtering Ti / Ni followed by Ti / Au. A passivation layer 40 is included on the second reflective layer 34. The passivation layer 40 is disposed to protect the LED chip 22 and provide electrical isolation for the LED chip 22 and may comprise many different materials, such as a dielectric material. In certain embodiments, passivation layer 40 is a single layer, while in other embodiments, passivation layer 40 comprises multiple layers. Suitable materials for passivation layer 40 include, but are not limited to, silicon nitride, silicon dioxide, aluminum oxide, and silicon oxynitride. In certain embodiments, passivation layer 40 includes a first metal-containing intermediate layer 42 disposed therein, which may comprise Al or other suitable metal.In particular, the first interlayer 42 is embedded within the passivation layer 40 and is electrically isolated from the active LED structure 12. In application, the first interlayer 42 may act as a crack stop layer against cracks that may propagate through the passivation layer 40.

[0040]

[0074] 3 , p-contact 16 and n-contact 18 are disposed on passivation layer 40 and are configured to receive external electrical connections and provide a portion of a conductive path to active LED structure 12. P-contact 16, which may also be referred to as an anode contact, may include one or more p-contact vias 44 that extend through passivation layer 40 and provide a conductive path to p-type layer 25 via second reflective layer 34 and reflective layer interconnect 38. In certain embodiments, one or more p-contact vias 44 may be referred to as p-feeds of p-contact 16. N-contact 18, which may also be referred to as a cathode contact, may include one or more n-contact vias 46 that extend through passivation layer 40 and are electrically coupled to n-contact interconnect 14 to provide an electrical path to n-type layer 26.

[0041]

[0075] The n-contact interconnect 14 may be formed as part of an n-contact structure 48 embedded within the passivation layer 40. The n-contact structure 48 is positioned so as to be electrically coupled between the n-contact 18 and the n-type layer 26. The n-contact structure 48 may embody a continuous metal structure including both the n-contact interconnect 14 and a lateral extension that crosses around the p-contact via 44. Because FIG. 3 is a cross-sectional view, the n-contact structure 48 is understood to be continuous from the plane of the cross-section of FIG. 3 through the portion that extends around the p-contact via 44. In this manner, the portion of the n-contact structure 48 illustrated between the p-contact 16 and the active LED structure 12 is continuous and electrically coupled to the portion of the n-contact structure 48 illustrated between the n-contact 18 and the active LED structure 12. The n-contact structure 48 is positioned so as to extend laterally across the LED chip 22, routing a conductive path between the n-contact 18 and many different regions of the n-type layer 26 to enhance current spreading. At certain locations where the n-contact via 46 connects with the n-contact structure 48, such locations may be vertically aligned, i.e., overlapped, with the locations of some of the n-contact interconnects 14. Lateral extensions of the n-contact structure 48 may extend from the n-contact via 46 to locations on the LED chip 22 outside the area of ​​the n-contact 18 to electrically connect with other n-contact interconnects 14. For example, a portion of the n-contact structure 48 is positioned to extend from a location vertically overlapping the area of ​​the n-contact 18 to a region of the LED chip 22 vertically overlapping the area of ​​the p-contact 16. In this manner, one or more of the n-contact interconnects 14 are vertically positioned between the p-contact 16 and the n-type layer 26. Although only one n-contact interconnect 14 is illustrated between the p-contact 16 and the active LED structure 12, in practice there may be an array of n-contact interconnects 14 to effectively spread current along a wider area of ​​the LED chip 22 below the p-contact 16.

[0042]

[0076] As previously mentioned, if internal electrical connections of opposite polarity (i.e., from the n-contact and p-contact) are located too close to each other, strong electromotive forces may cause electromigration of metal between them, thereby increasing the likelihood of dielectric breakdown and / or electrical shorting. In this manner, a specific portion 34', i.e., the second portion, of the second reflective layer 34 is formed to be electrically isolated or decoupled from the p-contact 16. Such portion 34' of the second reflective layer 34 may be positioned near the n-contact interconnect 14 and n-contact structure 48, which are vertically superimposed with one or both of the p-contact 16 and the n-contact 18. The portion 34' of the second reflective layer 34 may form an electrically isolated metal layer embedded in a dielectric material, such as the combination of the first reflective layer 30 and the passivation layer 40. In certain embodiments, such electrical isolation may be provided by patterning the portion 34' discontinuously from the remainder of the second reflective layer 34. The electrically isolated portion 34' of the second reflective layer 34 may also be referred to as a second intermediate layer or a second metal-containing intermediate layer of the LED chip 22. In certain embodiments, the electrically isolated portion 34' of the second reflective layer 34, which is vertically overlaid with the p-contact 16 and the n-contact structure 48, may be free of the reflective layer interconnect 38. In this manner, metal migration between the electrically activated n-contact structure 48 and the electrically isolated portion 34' of the second reflective layer 34 may not create a short-circuit path to the p-contact 16 via the current spreading layer 32.

[0043]

[0077] In certain embodiments, the third interlayer 50 may be formed by electrically isolating a portion of the n-contact structure 48 from the active LED structure 12. In this manner, the third interlayer 50 may be formed simultaneously and of the same material as the n-contact structure 48, and the third interlayer 50 is electrically floating within the LED chip 22 in a manner similar to the first and second interlayers (i.e., 42 and 34′). In certain embodiments, the third interlayer 50 may be formed in a portion of the LED chip 22 vertically overlapping the n-contact 18 and / or in a region of the LED chip 22 extending between the p-contact 16 and the n-contact 18. For example, in a certain region, such as between the n-contact 18 and the active LED structure 12, the first interlayer 42, the electrically isolated portion 34′ of the second reflective layer 34 (or second interlayer), and the third interlayer 50 may all be vertically overlapping each other within the passivation layer 40. Thus, charging is not initiated on any of the interlayers, providing a multi-layer structure for enhancing crack arrest within the passivation layer 40. In certain embodiments, the first interlayer 42, the electrically isolated portion 34' of the second reflective layer 34 (or second interlayer), and the third interlayer 50 are all disposed at least partially within the passivation layer 40. In this manner, a portion of the passivation layer 40 may be disposed to provide vertical separation between the first interlayer 42, the electrically isolated portion 34' of the second reflective layer 34 (or second interlayer), and the third interlayer 50.

[0044]

[0078] 4A through 12 illustrate cross-sectional views and corresponding top views of a manufacturing process sequence for an LED chip 52 similar to the LED chip 22 of FIG. 3. For illustrative purposes, the cross-sectional views represent a general illustration showing the arrangement of various features of the LED chip 52, and the corresponding top views are provided to illustrate an exemplary layout of the features illustrated in the cross-sectional views. As such, the cross-sectional views are not necessarily cut from the top views. Rather, the cross-sectional views provide detailed structures, and the top views provide a general layout of how such structures are arranged across a larger area of ​​the LED chip 52. Additionally, it will be understood that the manufacturing process sequence may represent various steps, and intermediate manufacturing processes may also be provided.

[0045]

[0079] 4A is a cross-sectional view of a portion of an LED chip 52 during manufacturing after LED structure 12 has been formed on substrate 24, including p-type layer 25, active layer 28, and a portion of n-type layer 26, and multiple first openings 54 have been formed. The first openings 54 may be formed by a pattern removal process, such as pattern etching of the active LED structure 12. FIG. 4B is an exemplary top view of the LED chip 52 of FIG. 4A illustrating how the first openings 54 are arranged in an array across the LED chip 52. As will be described below, the first openings 54 define areas of n-type layer 26 where n-contact interconnects 14 of FIG. 3 will later be formed.

[0046]

[0080] 5A is a cross-sectional view of a portion of the LED chip 52 of FIG. 4A during manufacturing after the current spreading layer 32 is formed on the p-type layer 25. FIG. 5B is an exemplary top view of the LED chip 52 of FIG. 5A illustrating how the current spreading layer 32 is disposed relative to each of the first openings 54. The current spreading layer 32 may be selectively formed along the p-type layer 25 without extending completely into each of the first openings 54. In this manner, a lateral setback is formed between the end of the current spreading layer 32 and the first openings 54, preventing the conductive material of the current spreading layer 32 from causing an electrical short along the sidewalls of the p-type layer 25 and the n-type layer 26 within the first openings 54.

[0047]

[0081] FIG. 6A is a cross-sectional view of a portion of the LED chip 52 of FIG. 5A during manufacturing after the first reflective layer 30 has been formed and multiple second and third openings 56 and 58 have been formed therethrough. FIG. 6B is an exemplary top view of the LED chip 52 of FIG. 6A illustrating how the second and third openings 56 and 58 are positioned relative to the first openings 54. As illustrated, the second openings 56 are positioned to be vertically aligned with the first openings 54, thereby providing a composite opening to the exposed portion of the n-type layer 26. In certain embodiments, the second openings 56 may be provided with a narrower diameter than the first openings 54 to reduce the chance of electrical shorting when subsequent elements are formed. The third openings 58 may be formed over another portion of the first reflective layer 30, exposing a portion of the current spreading layer 32. As will be described below, the third openings 58 define areas where the reflective layer interconnects 38 of Figure 3 will be formed to make electrical connection to the p-type layer 25 through the current spreading layer 32. As best illustrated in Figure 6B, the first openings 54 and second openings 56 may be formed in spaced-apart arrays across the LED chip 52, and the third openings 58 may be formed in another array across the LED chip 52. In this manner, future n-type and p-type electrical connections may be located across the LED chip 52 for effective current spreading.

[0048]

[0082] FIG. 7A is a cross-sectional view of a portion of the LED chip 52 of FIG. 6A during manufacturing after the second reflective layer 34 has been formed on the first reflective layer 30. FIG. 7B is an exemplary top view of the LED chip 52 of FIG. 7A illustrating how the second reflective layer 34 is positioned relative to the first openings 54 and the second openings 56. As illustrated, the second reflective layer 34 may be formed on the portion of the active LED structure 12 between the first openings 54. In this manner, the second reflective layer 34 may be formed over a portion of the p-type layer 25. During deposition, the second reflective layer 34 may fill the third openings 58 of FIG. 6A to provide the reflective layer interconnects 38. Additionally, an electrically isolated portion 34′ of the second reflective layer 34 may be formed on a portion of the first reflective layer 30 that is absent from the third openings 58 of FIG. 6A. As best illustrated in the top view of FIG. 7B, the portion 34′ may be formed between adjacent first openings 54. As will be described in more detail below, such regions are areas where portion 34' laterally extends a portion of n-contact structure 48 of Figure 3 to electrically couple adjacent n-contact interconnects 14 of Figure 3. In this way, having metal layers carrying opposite polarity charges in such regions may be avoided.

[0049]

[0083] 8 is a cross-sectional view of a portion of the LED chip 52 of FIG. 7A during manufacturing after a portion of the passivation layer 40 has been formed on the second reflective layer 34. The passivation layer 40 may be blanket deposited, and a fourth opening 60 may be defined in an area vertically aligned with the center of the first opening 54. In this manner, a conductive path to the n-type layer 26 is provided.

[0050]

[0084] 9A is a cross-sectional view of a portion of the LED chip 52 of FIG. 8 during manufacturing after the n-contact structures 48, n-contact interconnects 14, and third interlayer 50 have been formed. FIG. 9B is an exemplary top view of the LED chip 52 of FIG. 9A illustrating the layout pattern of the n-contact structures 48, n-contact interconnects 14, and third interlayer 50 throughout the active LED structure 12. As illustrated, the n-contact interconnects 14 may be formed within each of the fourth openings 60 of FIG. 8. The n-contact structures 48 may form conductive paths between adjacent pairs of the n-contact interconnects 14. The third interlayer 50 may be formed along other portions of the passivation layer 40 outside the n-contact structures 48. A plurality of fifth openings 62 may be formed along the portion of the third interlayer 50 that defines the location of the p-contact via 44 of FIG. 3. The fifth openings 62 may be arranged in many different shapes, such as circular. In FIG. 9B, the fifth opening 62 is illustrated as the letter P to the indicated location of the conductive path of the p contact 16 to be formed later.

[0051]

[0085] FIG. 10A is a cross-sectional view of a portion of the LED chip 52 of FIG. 9A during manufacturing after additional portions of the passivation layer 40 and the first intermediate layer 42 have been formed. FIG. 10B is an exemplary top view of the LED chip 52 of FIG. 10A illustrating a layout pattern for the first intermediate layer 42. The first intermediate layer 42 may be blanket deposited on the passivation layer 40 with a sixth opening 64 and a seventh opening 66 defined therein. The sixth opening 64 is superimposed with the fifth opening 62 to define a conductive path for the subsequently formed p-contact 16. The seventh opening 66 defines an area in which the subsequently formed n-contact via 46 will be formed. As illustrated in FIG. 10B, the sixth openings 64 and the seventh openings 66 may be formed in respective arrays spaced apart from one another along the LED chip 52, thereby defining areas in which the subsequently formed p-contact 16 and n-contact 18 may be formed. 10B, exemplary areas of p-contact 16 and n-contact 18 are provided by the added dashed boxes. In this manner, the area of ​​p-contact 16 can be increased regardless of the location of n-contact interconnect 14.

[0052]

[0086] 11 is a cross-sectional view of a portion of the LED chip 52 of FIG. 10A during manufacturing after additional portions of the passivation layer 40 have been formed above the first intermediate layer 42 and eight openings 68 and ninth openings 70 have been formed through the sixth opening 64 and the seventh opening 66, respectively. Eight openings 68 are formed through central portions of the sixth opening 64 and through the passivation layer 40 to define the location of a subsequently formed p-contact via 44. Similarly, a ninth opening 70 is formed through a central portion of the seventh opening 66 and through the passivation layer 40 to define the location of a subsequently formed n-contact via 46.

[0053]

[0087] FIG. 12 is a cross-sectional view of a portion of the LED chip 52 of FIG. 11 during manufacturing after the p-contact 16, p-contact via 44, n-contact 18, and n-contact via 46 have been formed. The LED chip 52 is thus positioned for flip-chip mounting with another surface. In this manner, the p-contact 16 and n-contact 18 may be disposed on a mounting surface 52' of the LED chip 52, and the surface of the substrate 24 may form the primary light-emitting surface 52'' of the LED chip 52. Similar to the LED chip 22 of FIG. 3, the second reflective layer 34 or an electrically isolated portion 34' of the second interlayer may be disposed between the electrically active portion of the n-contact structure 48 and the active LED structure 12. The third interlayer 50 or an electrically inactive portion of the n-contact structure 48 may be disposed at a location on the LED chip 52 above the electrically active portion of the second reflective layer 34. In this manner, the LED chip 52 may be provided with a structure that reduces electromotive forces and corresponding metal electromigration associated with oppositely charged metal layers being in close proximity to each other.

[0054]

[0088] 13A is a cross-sectional view of a portion of an LED chip 72 similar to the LED chip 52 of FIG. 12A in which the n-contact structures 48 further include peripheral n-contact interconnects 74 that traverse along the peripheral edge of the LED chip 72. Similar to the LED chip 52 of FIG. 12, an electrically isolated portion 34' of the second reflective layer 34 may be disposed between the electrically active portion of the n-contact structures 48 and the active LED structure 12, and the third interlayer 50 may be disposed at a location on the LED chip 72 above the electrically active portion of the second reflective layer 34. Depending on the layout of the n-contact interconnects 14 of the LED chip 72, one or more peripheral n-contact interconnects 74 may be disposed near the peripheral mesa sidewalls 12' of the active LED structure 12. The peripheral n-contact interconnects 74 may be formed through a portion of the passivation layer 40 and the first reflective layer 30 in a manner similar to the n-contact interconnects 14. The peripheral n-contact interconnect 74 may be electrically coupled to a portion of the n-type layer 26 outside the peripheral mesa sidewall 12′, thereby providing an additional conductive path into the active LED structure 12 for enhanced current spreading and injection. To avoid short circuits, a portion of the passivation layer 40 and / or the first reflective layer 30 may be disposed between the peripheral mesa sidewall 12′ and the peripheral n-contact interconnect 74. In certain embodiments, a portion of the n-contact structure 48 may be positioned to electrically couple the peripheral n-contact interconnect 74 to one or more of the n-contact interconnects 14 disposed inside the peripheral mesa sidewall 12′. In certain embodiments, the peripheral n-contact interconnect 74 may be electrically coupled to the n-type layer 26 continuously near two or more, or all, peripheral edges of the active LED structure 12.

[0055]

[0089] 13B is an exemplary top view of the LED chip 72 of FIG. 13A illustrating the layout pattern of the n-contact interconnects 14, peripheral n-contact interconnects 74, and n-contacts 18 relative to the p-contact 16. In a particular embodiment, the peripheral n-contact interconnects 74 are a single continuous structure across the periphery of the LED chip 72. The peripheral n-contact interconnects 74 and portions of the n-contact structure 48 may effectively route current between the n-contacts 18 and the n-contact interconnects 14 that are between the n-contacts 18 and the p-contact 16 and / or vertically overlap the p-contact 16. As an example, the first n-contact interconnect 14-1 is vertically overlapped and electrically coupled to the n-contact 18. The first portion 48-1 of the n-contact structure 48 is positioned to extend laterally and electrically couple the first n-contact interconnect 14-1 to the second n-contact interconnect 14-2 that is vertically disposed between the n-contact 18 and the p-contact 16. The second portion 48-2 of the n-contact structure 48 is positioned to electrically couple the first n-contact interconnect 14-1 to the peripheral n-contact interconnects 74, and the third portion 48-3 of the n-contact structure 48 electrically couples the third n-contact interconnect 14-3 to the peripheral n-contact interconnects 74. In another example, a fourth n-contact interconnect 14-4 is vertically superimposed and electrically coupled to the n-contact 18, and the fourth portion 48-4 of the n-contact structure 48 electrically couples the fourth n-contact interconnect 14-4 to a fifth n-contact interconnect 14-5 that is vertically superimposed with the p-contact 16. In this manner, a conductive path is provided between the n-contact 18 and the plurality of n-contact interconnects 14-1 through 14-5 regardless of their position relative to the n-contact 18 and the p-contact 16.

[0056]

[0090] FIG. 14A is an exemplary top view of an LED chip 76 similar to the LED chip 72 of FIGS. 13A and 13B , further illustrating an embodiment in which the electrical connection between the peripheral n-contact interconnect 74 and the n-type layer 26 is segmented along the periphery of the LED chip 76. Rather than continuously contacting the n-type layer 26 outside the mesa sidewall 12′, portions of the passivation layer 40 may remain along the periphery of the LED chip 76 between the peripheral n-contact interconnect 74 and the n-type layer 26, thereby forming a pattern of localized areas without direct contact. For illustrative purposes, the localized areas of the passivation layer 40 are illustrated as rectangular boxes along the periphery of the LED chip 76. FIG. 14B is a cross-sectional view of the LED chip 76 of FIG. 14A taken along section line 14B-14B of FIG. 14A , which does not intersect one of the portions of the passivation layer 40 remaining along the periphery. As illustrated, the peripheral n-contact interconnects 74 extend to and make electrical connection with the n-type layer 26. In contrast, FIG. 14C is a cross-sectional view of the LED chip 76 of FIG. 14A taken along section line 14C-14C in FIG. 14A , which intersects one of the portions of the passivation layer 40 remaining along the periphery. Thus, in such regions, the passivation layer 40 remains between the peripheral n-contact interconnects 74 and the n-type layer 26. Such a structure may be provided to control the amount of direct contact and associated current injection provided along the periphery of the LED chip between the peripheral n-contact interconnects 74 and the n-type layer 26. By reducing the amount of direct contact, local current spreading and corresponding light emission may be tailored along the periphery of the LED chip 76.

[0057]

[0091] FIG. 15 is an exemplary top view of an LED chip 78 similar to the LED chip 72 of FIGS. 13A and 13B but including an alternative arrangement in which the n-contact interconnects 14 are not vertically overlapped below the p-contact 16. Thus, the principles described above for the peripheral n-contact interconnects 74 may not be limited to embodiments in which the n-contact interconnects 14 are vertically overlapped with the p-contact 16. In this manner, the peripheral n-contact interconnects 74 may route conductive paths between the n-contacts 18 and the n-contact interconnects 14 that are adjacent to or surround the p-contact 16, without directly intervening between the p-contact 16 and the remainder of the LED chip 78. Such an arrangement may be beneficial for increasing the number of electrically activated paths between the p-contact 16 and the portion of the LED chip 78 that is vertically overlapped with the p-contact 16.

[0058]

[0092] FIG. 16 is an exemplary top view of an LED chip 80 similar to the LED chip 78 of FIG. 15 , but including an arrangement in which the p-contact 16 covers a larger area of ​​the LED chip 80. For embodiments in which the n-contact interconnects 14 are not vertically superimposed below the p-contact 16, an arrangement of the n-contact interconnects 14 and n-contact structures 48 may be provided to increase the area of ​​the p-contact 16 while still providing effective current spreading. By way of example, the p-contact 16 may include a lateral protrusion 16′ extending toward the n-contact 18. FIG. 16 illustrates a particular arrangement of the n-contact structures 48 and peripheral n-contact interconnects 74 that routes conductive paths between the n-contact 18 and the various n-contact interconnects 14 that laterally surround the p-contact 16.

[0059]

[0093] 17A-17C illustrate top views of a sequence of manufacturing processes for an LED chip 82 similar to the LED chips 78, 80 of FIGS. 15 and 16, but further including an arrangement in which the p-contact 16 is discontinuously segmented across the LED chip 82. It will be understood that the sequence of manufacturing processes may represent various steps, and that intermediate manufacturing processes may also be provided.

[0060]

[0094] FIG. 17A is a top view of an LED chip 82 during manufacturing after elements such as the reflective layer interconnect 38, n-contact interconnects 14, n-contact structures 48, peripheral n-contact interconnects 74, and openings 62 have been formed. As illustrated, the n-contact structures 48 may electrically couple a linear arrangement of n-contact interconnects 14 (e.g., a column or row depending on the orientation). In this regard, the n-contact structures 48 may form multiple discontinuous segments, each coupled to a separate group of n-contact interconnects 14. A particular segment, or first segment, of the n-contact structure 48 may extend continuously from one end of the active LED structure 12 to the opposite end and may electrically couple between portions of the peripheral n-contact interconnects 74 at the opposite end. As used herein, the opposite end of the active LED structure 12 may embody a mesa sidewall 12′, as illustrated, for example, in FIG. 13A . The other segment, or second segment, of the n-contact structure 48 may extend continuously into a region of the LED chip 82 that does not extend to one or more of the opposite ends. For example, in FIG. 17A , two such segments of the n-contact structure 48 are illustrated near the center of the LED chip 82. In this manner, one or more continuous portions of the active LED structure 12 may extend between particular segments of the n-contact structure 48. The opening 62 corresponds to the fifth opening 62, as described and illustrated with respect to FIG. 9A . The opening 62 therefore defines the region in which the subsequently formed p-contact via 44 will be formed.

[0061]

[0095] FIG. 17B is a top view of the LED chip 82 of FIG. 17A at a later manufacturing stage, after elements such as the p-contact 16, p-contact via 44, and n-contact 18 have been formed. The p-contact via 44 effectively fills the opening 62 of FIG. 17A to provide a conductive path between the p-contact 16 and the underlying active LED structure 12 (i.e., the p-type layer). The p-contact 16 may be provided in discontinuous portions or segments relative to the n-contact structure 48 and n-contact interconnect 14, thereby avoiding adjacent metal layers from having opposite polarities when electrically activated. By way of example, the LED chip 82 includes outer segments, or first discontinuous portions, of the p-contact 16 that are peripherally disposed between the vertical boundaries of the segments of the n-contact structure 48 that extend continuously between the opposite ends of the active LED structure 12 and the other end of the active LED structure 12. The LED chip 82 further includes a central segment of the p-contact 16, or a second discontinuous portion that is peripherally continuous with the centrally located alternating segments of the n-contact structure 48. In this manner, the LED chip 82 may be arranged without the n-contact interconnect 14 vertically superimposed with the p-contact 16, while still providing a conductive path from the n-contact 18 across the region of the active LED structure 12 that laterally surrounds each segment of the p-contact 16.

[0062]

[0096] As described herein, the principles of the present disclosure enable various configurations for effectively routing n-contact and p-contact electrical connections throughout the LED chip, while reducing instances where electrical connections of opposite polarity are placed too close to each other. The arrangement of contact and interconnect structures provides flexibility and control for tailoring current spreading and / or injection to various LED chip structures and sizes. Figures 18 through 20 illustrate various arrangements of n-contact interconnects and reflective layer interconnects that may be provided with any of the previously described embodiments, including at least the LED chips illustrated in Figures 3 through 17B.

[0063]

[0097] 18 is a top view of an LED chip 84 having a pattern of n-contact interconnects 14 and reflective layer interconnects 38 that may be implemented in accordance with an embodiment of the present disclosure. As illustrated, the reflective layer interconnects 38 and n-contact interconnects 14 are provided at a higher density near the peripheral edges of the LED chip 84 than in the central region of the LED chip 84. Such an arrangement may be advantageous for large area LED chips, such as those with edges greater than 0.5 μm, where current injection along the peripheral edges may be more difficult. This increased density of the reflective layer interconnects 38 and n-contact interconnects 14 may provide improved brightness along the peripheral edges and / or improved brightness uniformity across the LED chip 84.

[0064]

[0098] FIG. 19 is a top view of an LED chip 86 similar to the LED chip 84 of FIG. 18 but with a higher density of n-contact interconnects 14 and reflective layer interconnects 38. As illustrated, the density of n-contact interconnects 14 and reflective layer interconnects 38 at the peripheral edges of the LED chip 86 is higher than in FIG. 18. In addition, the density of n-contact interconnects 14 and reflective layer interconnects 38 along the central region is also higher than in the LED chip 84 of FIG. 18. As such, the LED chip 86 of FIG. 19 may be advantageous for increasing current spreading for larger chip areas with LED structures where current spreading is more difficult.

[0065]

[0099] Figure 20 is a top view of an LED chip 88 similar to the LED chip 84 of Figure 18, except that the n-contact interconnects 14 are not overlapped between the boundary of the p-contact 16 and the active LED structure 12. As illustrated, various ones of the n-contact interconnects 14 are located between the edge of the p-contact 16 and the edge of the active LED structure 12 closest to the p-contact 16. In this way, the electrical path from the n-contacts 18 may effectively cover a large area of ​​the LED chip 88, while avoiding instances where electrical connections of opposite polarity become positioned too close to each other.

[0066]

[0100] FIG. 21 is a cross-sectional view of a portion of an LED chip 90, similar to the LED chip 72 of FIG. 13A, for an embodiment in which a particular portion 34' of the second reflective layer 34 is electrically coupled to the n-contact 18. For example, the portion 34' of the second reflective layer 34 between the n-contact 18 and the active LED structure 12 may be electrically coupled to the n-contact 18 through another n-contact via 92. One or more of the portions 34' of the second reflective layer 34 may be decoupled or completely isolated from the current spreading layer 32, the p-type layer 25, and the remainder of the second reflective layer 34 via the passivation layer 40. As illustrated, the n-contact via 92 may extend through an opening in the passivation layer 40 and the first intermediate layer 42. By electrically coupling such a portion 34' to the n-contact 18, additional conductive material can be coupled to the electrical connection between the n-contact 18 and the n-type layer 26, which may effectively reduce the associated electrical resistance.

[0067]

[0101] It is contemplated that any of the foregoing aspects and / or various individual aspects and features described herein may be combined to further advantage. Any of the various embodiments disclosed herein may be combined with one or more of the other disclosed embodiments, unless indicated to the contrary herein.

[0068]

[0102] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A light emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; an n-contact electrically coupled to the n-type layer; a p-contact electrically coupled to the p-type layer; a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contacts; wherein one or more n-contact interconnects of the plurality of n-contact interconnects are vertically disposed between the p-contact and the n-type layer.

2. 10. The LED chip of claim 1, wherein the one or more n-contact interconnects of the plurality of n-contact interconnects are electrically coupled to an n-contact structure electrically coupled to the n-contact.

3. 3. The LED chip of claim 2, wherein the n-contact structure is positioned to extend laterally from a position vertically aligned with the n-contact to a position vertically aligned with the p-contact, whereby the n-contact structure is electrically coupled to the one or more n-contact interconnects of the plurality of n-contact interconnects vertically aligned between the p-contact and the n-type layer.

4. a peripheral n-contact interconnect electrically coupled to a portion of the n-type layer outside a mesa sidewall of the active LED structure, the mesa sidewall comprising a sidewall of the p-type layer, the active layer, and a portion of the n-type layer; 3. The LED chip of claim 2, wherein the n-contact structure is positioned to extend laterally from a position vertically overlapping the n-contact to the mesa sidewall, whereby the n-contact structure is electrically coupled to the peripheral n-contact interconnect.

5. 5. The LED chip of claim 4, wherein the peripheral n-contact interconnects are electrically coupled to the one or more n-contact interconnects of the plurality of n-contact interconnects vertically disposed between the p-contact and the n-type layer.

6. 5. The LED chip of claim 4, wherein the peripheral n-contact interconnects are electrically coupled to portions of the n-type layer outside the mesa sidewalls proximate and continuous to two or more peripheral edges of the active LED structure.

7. 5. The LED chip of claim 4, wherein the peripheral n-contact interconnects are discontinuously electrically coupled to a portion of the n-type layer outside the mesa sidewalls, such that a portion of the peripheral n-contact interconnects contacts the n-type layer and another portion of the peripheral n-contact interconnects is separated from the n-type layer by a passivation layer.

8. 10. The LED chip of claim 1, further comprising a reflective structure on the active LED structure, the reflective structure comprising: a first reflective layer that is insulating; a second reflective layer that is conductive; and a plurality of reflective layer interconnects that extend through the first reflective layer and electrically couple a first portion of the second reflective layer to the p-type layer.

9. 10. The LED chip of claim 8, wherein the second portion of the second reflective layer is electrically isolated from the active LED structure.

10. 10. The LED chip of claim 9, wherein the second portion of the second reflective layer is disposed vertically between an n-contact structure and the active LED structure.

11. 9. The LED chip of claim 8, wherein a second portion of the second reflective layer is completely separated from the p-type layer by a passivation layer, and the second portion of the second reflective layer is electrically coupled to the n-contact.

12. a passivation layer on the active LED structure, the plurality of n-contact interconnects extending through a portion of the passivation layer; a first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer disposed within the passivation layer; 10. The LED chip of claim 1, further comprising:

13. 10. The LED chip of claim 1, wherein the n-contact and the p-contact are contact pads positioned to receive external electrical connections when the LED chip is flip-chip mounted.

14. A light emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a passivation layer on the active LED structure; a first metal-containing intermediate layer, a second metal-containing intermediate layer, and a third metal-containing intermediate layer at least partially within the passivation layer; wherein each of the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer is electrically isolated from the active LED structure.

15. further comprising a reflective structure on the active LED structure, the reflective structure comprising a first reflective layer that is insulating, a second reflective layer that is conductive, and a plurality of reflective layer interconnects that extend through the first reflective layer and electrically couple a first portion of the second reflective layer to the p-type layer; 15. The LED chip of claim 14, wherein the second metal-containing intermediate layer comprises a second portion of the second reflective layer that is electrically isolated from the active LED structure.

16. an n-contact electrically coupled to the n-type layer; a p-contact electrically coupled to the p-type layer; a plurality of n-contact interconnects electrically coupled between the n-type layer and the n-contacts; an n-contact structure electrically coupled to one or more of the plurality of n-contact interconnects; 15. The LED chip of claim 14, further comprising: the n-contact structure disposed so as to extend laterally within the passivation layer.

17. 17. The LED chip of claim 16, wherein the third metal-containing intermediate layer comprises the same material as the n-contact structure.

18. 17. The LED chip of claim 16, wherein the second metal-containing intermediate layer is vertically disposed between the n-contact structure and the active LED structure.

19. a reflective structure on the active LED structure, the reflective structure comprising a first reflective layer that is insulating and a second reflective layer that is conductive, the first reflective layer being between the second reflective layer and the p-type layer; 17. The LED chip of claim 16, wherein the second metal-containing intermediate layer comprises a portion of the second reflective layer that is electrically isolated from the active LED structure.

20. 20. The LED chip of claim 19, wherein the portion of the second reflective layer electrically isolated from the active LED structure is disposed vertically between the n-contact structure and the active LED structure.

21. 15. The LED chip of claim 14, wherein the first metal-containing intermediate layer, the second metal-containing intermediate layer, and the third metal-containing intermediate layer are vertically disposed within the passivation layer.

22. A light emitting diode (LED) chip, comprising: an active LED structure comprising an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a plurality of n-contact interconnects electrically coupled to the n-type layer; an n-contact structure electrically coupled to the plurality of n-contact interconnects; wherein the n-contact structure comprises a first segment connected to a first group of n-contact interconnects of the plurality of n-contact interconnects and a second segment connected to a second group of n-contact interconnects of the plurality of n-contact interconnects.

23. 23. The LED chip of claim 22, wherein the first segment of the n-contact structure is discontinuous with the second segment of the n-contact structure.

24. 23. The LED chip of claim 22, wherein the first segment of the n-contact structure is arranged to extend continuously from one end of the active LED structure to an opposite end of the active LED structure.

25. 23. The LED chip of claim 22, wherein the second segment of the n-contact structure is arranged to extend continuously without extending to at least one edge of the active LED structure.

26. an n-contact electrically coupled to the n-contact structure; a p-contact electrically coupled to the p-type layer; Furthermore, 23. The LED chip of claim 22, wherein the plurality of n-contact interconnects are disposed vertically outside a peripheral edge of the p-contact.

27. The p-contact is a first portion disposed perpendicularly between a boundary of the first segment of the n-contact structure and an outer periphery of the active LED structure; a second portion disposed perpendicularly between another boundary of the first segment of the n-contact structure and a boundary of the second segment of the n-contact structure; Equipped with 27. The LED chip of claim 26, wherein the first portion of the p-contact is discontinuous with the second portion of the p-contact.

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