High electron mobility transistor with reduced drain current drift and method for fabricating the device

Abstract

The high electron mobility transistor includes a semiconductor layer structure including a channel layer and a barrier layer, and source and drain contacts on the semiconductor structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source and drain contacts. The multi-layer passivation structure includes at least first and second silicon nitride layers having different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. The material composition of the spacer passivation layer is different from the material composition of at least one of the layers of the multi-layer passivation structure.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 890,453, filed August 18, 2022, the entire contents of which are incorporated herein by reference as if set forth in their entirety.

[0002] The inventive concepts described herein relate to semiconductor devices, and in particular to high electron mobility transistors. [Background technology]

[0003] Electronic devices formed from low bandgap semiconductor materials such as silicon and gallium arsenide are widely used in low power and (in the case of silicon) low frequency applications. However, these semiconductor materials may be less suitable for high power and / or high frequency applications due to their relatively small band gap (e.g., 1.12 eV for silicon and 1.42 eV for gallium arsenide at room temperature) and / or relatively small breakdown voltage.

[0004] High-power, high-temperature, and / or high-frequency applications often use devices formed from wider bandgap semiconductor materials such as silicon carbide (2.996 eV bandgap for alpha silicon carbide at room temperature) and group III nitrides (e.g., 3.36 eV bandgap for gallium nitride at room temperature). These materials typically have higher electric field breakdown strengths and higher electron saturation velocities than gallium arsenide or silicon.

[0005] A device of particular interest for high-power and / or high-frequency applications is the high-electron mobility transistor (HEMT). A HEMT comprises a semiconductor layer structure with at least a channel layer and a barrier layer, each with different material compositions and bandgap energies (the channel layer's bandgap is smaller than the barrier layer's). When the HEMT is in the "on" or conducting state, a two-dimensional electron gas (2DEG) forms at the heterojunction between the channel and barrier layers. The channel layer (formed of a material with a smaller bandgap) has a higher electron affinity. The 2DEG is an accumulation layer in a material with a smaller bandgap and can have a very high sheet electron concentration. Furthermore, electrons from the wider bandgap barrier layer migrate to the 2DEG layer, enabling high electron mobility due to reduced ionized impurity scattering. This combination of high carrier concentration and high carrier mobility can give HEMTs very large transconductance, providing a significant performance advantage over metal oxide semiconductor field effect transistors (MOSFETs) in high-frequency applications.

[0006] High electron mobility transistors fabricated in III-nitride material systems have the potential to generate large amounts of radio frequency (RF) power due to a combination of material properties, including the aforementioned high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity. As used herein, the term "III-nitride" refers to semiconductor compounds formed between nitrogen (N) and elements from group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary (or higher) compounds, such as AlGaN and AlInGaN. As is well understood by those skilled in the art, group III elements can combine with nitrogen to form binary compounds (e.g., GaN), ternary compounds (e.g., AlGaN, AlInN), and quaternary compounds (e.g., AlInGaN). All of these compounds have the empirical formula of one mole of nitrogen combined with one mole of total group III elements.

[0007] FIG. 1A is a schematic plan view of a conventional gallium nitride-based high electron mobility transistor 100, and FIG. 1B is a schematic cross-sectional view of the high electron mobility transistor 100 taken along line 1B-1B in FIG. 1A. As shown in FIGS. 1A-1B, the high electron mobility transistor 100 may be formed on a substrate 110, such as a silicon carbide substrate. An optional buffer layer 120 may be formed on the substrate 110, and a channel layer 130 is formed on the buffer layer 120 on the opposite side of the substrate 110. A barrier layer 140 is formed on the channel layer 130 on the opposite side of the substrate 110. As used herein, when a first layer is referred to as being on the "opposite side" of a third layer, this means that the second layer is between the first and third layers. Thus, the buffer layer 120 is between the channel layer 130 and the substrate 110. The channel layer 130 and the barrier layer 140 may comprise III-nitride based materials, with the channel layer 130 having a bandgap smaller than that of the barrier layer 140. The substrate 110, the buffer layer 120, the channel layer 130, and the barrier layer 140 may together form the semiconductor layer structure 102. A source contact 150 and a drain contact 152 are formed on the upper surface of the barrier layer 140 and are laterally spaced apart from one another. A gate contact 154 is formed on the upper surface of the barrier layer 140 between the source contact 150 and the drain contact 152. A passivation layer 160 covers the exposed portion of the upper surface of the barrier layer 140. A field plate 156 is formed on the passivation layer 160 between the drain contact 152 and the gate contact 154. The field plate 156 may be electrically connected to the source contact 150 via a source contact extension 151. A 2DEG layer 132 is formed at the junction of the channel layer 130 and the barrier layer 140 when the HEMT device 100 is biased to a conductive or "on" state. The 2DEG layer 132 acts as a highly conductive layer, allowing current to flow between the source and drain regions of the device underlying the source and drain contacts 150 and 152, respectively. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Patent Publication No. 2003 / 0102482A1 Summary of the Invention [Means for solving the problem]

[0009] According to some embodiments of the present invention, a high electron mobility transistor is provided, comprising: a semiconductor layer structure including a channel layer and a barrier layer on the channel layer; a source contact on the semiconductor layer structure; a drain contact on the semiconductor layer structure; a gate contact on the semiconductor layer structure between the source contact and the drain contact; a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers including at least a first silicon nitride layer and a second silicon nitride layer having a material composition different from that of the first silicon nitride layer; and spacer passivation layers on sidewalls of both the first silicon nitride layer and the second silicon nitride layer, the material composition of the spacer passivation layer being different from that of at least one of the layers of the multi-layer passivation structure.

[0010] In some embodiments, a first silicon nitride layer is in direct contact with the barrier layer, and a second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, and the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

[0011] In some embodiments, the multi-layer passivation structure further includes a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

[0012] In some embodiments, the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

[0013] In some embodiments, the spacer passivation layer is in direct contact with all three sidewalls of the first through third silicon nitride layers.

[0014] In some embodiments, the spacer passivation layer comprises a silicon-rich silicon nitride layer.

[0015] In some embodiments, a spacer passivation layer is between the multi-layer passivation structure and the gate contact.

[0016] In some embodiments, the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

[0017] In some embodiments, the spacer passivation layer includes an inner surface facing the multi-layer passivation structure and an outer surface opposite the inner surface, the outer surface having a concave profile.

[0018] In some embodiments, the spacer passivation layer has a generally triangular shape, the longest side of which has a concave profile.

[0019] In some embodiments, a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

[0020] In some embodiments, the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

[0021] In some embodiments, the spacer passivation layer includes a fourth silicon nitride layer and a fifth silicon nitride layer between the fourth silicon nitride layer and the multi-layer passivation structure.

[0022] In some embodiments, the fourth silicon nitride layer and the fifth silicon nitride layer are each more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

[0023] In some embodiments, the fifth silicon nitride layer is an L-shaped layer that directly contacts the sidewalls of the multi-layer passivation structure.

[0024] According to a further embodiment of the present invention, there is provided a high electron mobility transistor comprising: a semiconductor layer structure including a channel layer and a barrier layer on the channel layer, a source contact on the semiconductor layer structure, a drain contact on the semiconductor layer structure, a gate contact on the semiconductor layer structure between the source contact and the drain contact, a passivation structure on the semiconductor layer structure between the source contact and the drain contact, and a spacer passivation layer on sidewalls of the passivation layer, wherein an outer surface of the spacer passivation layer opposite the passivation layer has a concave profile.

[0025] In some embodiments, the passivation structure comprises a multi-layer passivation structure including at least a first silicon nitride layer directly contacting the barrier layer and a second silicon nitride layer on the first silicon nitride layer opposite the barrier layer, the second silicon nitride layer having a material composition different from the material composition of the first silicon nitride layer.

[0026] In some embodiments, the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

[0027] In some embodiments, the multi-layer passivation structure further includes a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

[0028] In some embodiments, the spacer passivation layer is in direct contact with all three sidewalls of the first through third silicon nitride layers.

[0029] In some embodiments, the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than the first silicon nitride layer.

[0030] In some embodiments, a spacer passivation layer is between the multi-layer passivation structure and the gate contact.

[0031] In some embodiments, the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

[0032] In some embodiments, a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

[0033] In some embodiments, the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

[0034] In some embodiments, the spacer passivation layer includes a fourth silicon nitride layer and a fifth silicon nitride layer between the fourth silicon nitride layer and the multi-layer passivation structure.

[0035] In some embodiments, the fourth silicon nitride layer and the fifth silicon nitride layer are each more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

[0036] In some embodiments, the fifth silicon nitride layer is an L-shaped layer that directly contacts the sidewalls of the multi-layer passivation structure.

[0037] According to an additional embodiment of the present invention, a high electron mobility transistor is provided, comprising: a semiconductor layer structure including a channel layer and a barrier layer on the channel layer, a source contact on the semiconductor layer structure, a drain contact on the semiconductor layer structure, a gate contact on the semiconductor layer structure between the source contact and the drain contact, a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a first silicon nitride layer in direct contact with the semiconductor layer structure, and a silicon nitride spacer passivation layer including at least one silicon nitride layer on sidewalls of the multi-layer passivation structure, wherein a silicon concentration of the at least one silicon nitride layer exceeds a silicon concentration of the first silicon nitride layer.

[0038] In some embodiments, a spacer passivation layer is disposed between the first silicon nitride layer and the gate contact such that the first silicon nitride layer does not contact the gate contact.

[0039] In some embodiments, the multi-layer passivation structure further includes a second silicon nitride layer on the first silicon nitride layer opposite the barrier layer, the second silicon nitride layer being more silicon-rich than the first silicon nitride layer.

[0040] In some embodiments, the multi-layer passivation structure further includes a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

[0041] In some embodiments, the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

[0042] In some embodiments, the spacer passivation layer is in direct contact with all three sidewalls of the first through third silicon nitride layers.

[0043] In some embodiments, the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

[0044] In some embodiments, an outer surface of the spacer passivation layer opposite the multi-layer passivation structure has a concave profile.

[0045] In some embodiments, the spacer passivation layer has a generally triangular shape, the longest side of which has a concave profile.

[0046] In some embodiments, a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

[0047] In some embodiments, the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

[0048] According to further embodiments of the present invention, methods for fabricating a high electron mobility transistor are provided. According to these methods, a semiconductor layer structure is provided, including a channel layer and a barrier layer on the channel layer. A first silicon nitride layer of a multi-layer passivation structure is formed on the semiconductor layer structure. An opening for a gate contact is patterned in the multi-layer passivation structure. A passivation layer is formed in the opening. The passivation layer is removed from a bottom of the opening, while portions of the passivation layer remain on first and second opposing sidewalls of the opening, forming respective first and second spacer passivation layers.

[0049] In some embodiments, the method further includes forming a second silicon nitride layer of a multi-layer passivation structure on the first silicon nitride layer, and patterning an opening for a gate contact in the multi-layer passivation structure includes patterning an opening extending through at least the first silicon nitride layer and the second silicon nitride layer.

[0050] In some embodiments, the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

[0051] In some embodiments, the method further includes forming a third silicon nitride layer of a multi-layer passivation structure on the second silicon nitride layer, and patterning an opening for a gate contact in the multi-layer passivation structure includes patterning an opening extending through at least the first through third silicon nitride layers.

[0052] In some embodiments, the method further includes patterning openings for source and drain contacts in both the first and second silicon nitride layers before forming the third silicon nitride layer.

[0053] In some embodiments, a first silicon nitride layer is in direct contact with the barrier layer, and a second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, and the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

[0054] In some embodiments, the first spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

[0055] In some embodiments, the first spacer passivation layer is in direct contact with all three sidewalls of the first through third silicon nitride layers.

[0056] In some embodiments, the method further includes forming a gate contact in the opening, the first spacer passivation layer being between the multi-layer passivation structure and the gate contact.

[0057] In some embodiments, an outer surface of the first spacer-passivation layer opposite the multi-layer passivation structure has a concave profile. [Brief explanation of the drawings]

[0058] [Figure 1A] FIG. 1 is a schematic plan view of a conventional HEMT. [Figure 1B] FIG. 1B is a schematic cross-sectional view taken along line 1B-1B of FIG. 1A. [Figure 2] FIG. 1C is a cross-sectional view of FIG. 1B showing various current paths. [Figure 3A] 1 is a schematic plan view of a HEMT according to an embodiment of the present invention. [Figure 3B] FIG. 3B is a schematic cross-sectional view taken along line 3B-3B of FIG. 3A. [Figure 3C] FIG. 3C is a greatly enlarged view of a portion of FIG. 3B. [Figure 3D] FIG. 3C is a schematic cross-sectional view of a modified version of the HEMT of FIG. 3B. [Figure 3E] FIG. 3C is a schematic cross-sectional view of another modified version of the HEMT of FIG. 3B. [Figure 4] 1 is a graph illustrating how the source-drain current of a HEMT can change over time due to drain current drift during steady state operation. [Figure 5A] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5B] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5C] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5D] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5E] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5F] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5G] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5H] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 5I] 1A to 1C are schematic cross-sectional views illustrating a method for fabricating a HEMT according to an embodiment of the present invention. [Figure 6A] 10 is a schematic cross-sectional view of another spacer passivation layer that can be used in a HEMT according to an embodiment of the present invention. [Figure 6B] 10 is a schematic cross-sectional view of another spacer passivation layer that can be used in a HEMT according to an embodiment of the present invention. [Figure 6C] 10 is a schematic cross-sectional view of another spacer passivation layer that can be used in a HEMT according to an embodiment of the present invention. [Figure 7A] 1 is a graph showing the measured quiescent drain current performance of a conventional HEMT. [Figure 7B] 1 is a graph showing the measured quiescent drain current performance of a HEMT according to an embodiment of the present invention. [Figure 8] 10 is a flow chart of a method of fabricating a HEMT in accordance with an additional embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0059] It should be noted that the dimensions of the various elements in the drawings (e.g., layer thicknesses and horizontal and vertical widths of elements / layers) are not necessarily drawn to scale in the figures, and various elements may be significantly enlarged relative to other elements in some drawings to better show the details of those elements.

[0060] Embodiments of the present invention are directed to HEMTs that may exhibit reduced drain current drift.

[0061] 2 is a cross-sectional view of FIG. 1B showing various current paths. As shown in FIG. 2, the primary on-state conduction path of the HEMT is a conduction path 190 formed in the 2DEG layer 132, which allows the drain-source current I DS 2, a conventional HEMT 100 may have additional current paths. These additional current paths include a current path 192 between the source contact 150 and the gate contact 154 along the interface between the semiconductor layer structure 102 and the passivation layer 160, and a current path 194 between the gate contact 154 and the drain contact 152 along the interface between the semiconductor layer structure 102 and the passivation layer 160. The current paths 192 and 194 contribute to the gate leakage current I of the device. G and drain leakage current I D The additional current paths 192, 194 shown in Figure 2 are generally undesirable current paths.

[0062] The HEMT 100 can be configured as a normally-on HEMT or a normally-off HEMT. A normally-off HEMT is configured such that when the source and drain contacts 150, 152 are appropriately biased and no bias voltage is applied to the gate contact 154, the device does not conduct current between the drain and source contacts 150, 152. In contrast, a normally-on HEMT is configured such that when the drain and source contacts 150, 152 are appropriately biased and no bias voltage is applied to the gate contact 154, the device conducts current between the source and drain contacts 150, 152. Thus, in other words, a normally-off HEMT can be turned on (i.e., conducting) by applying a bias voltage to the gate contact 154, and a normally-on HEMT can be turned off (i.e., non-conducting) by applying a bias voltage to the gate contact 154. The following discussion assumes that the HEMT 100 is a normally-on HEMT, although embodiments of the present invention are not limited thereto.

[0063] Unfortunately, charge can accumulate in the semiconductor layer structure 102, for example, due to defects on the top surface of the semiconductor layer structure 102 that act as electron traps. This charge accumulation can reduce current flow when the HEMT 100 switches from an off state to an on state. This behavior is referred to as RF dispersion. This behavior can, in turn, result in nonlinearity when the HEMT 100 is used as a transistor amplifier, which can cause passive intermodulation (PIM) distortion. As known in the art, PIM distortion refers to the generation of unwanted intermodulation products along the transmit path of a communication system, which can degrade the performance of the receive path of the communication system. The drain current drift performance of a HEMT is a measure of the degree to which the drain current changes, for example, due to charge accumulation, during the period from when the HEMT is turned on until the drain current reaches a steady state.

[0064] In accordance with embodiments of the present invention, a HEMT is provided that may exhibit improved drain current drift performance and / or improved gate and drain leakage current performance. The HEMT may be a gallium nitride-based device or other III-nitride-based device. Without being bound to a particular theory of operation, it is believed that defects along or near the top surface of the semiconductor layer structure 102 (defects at such locations are referred to herein as defects “at” the top surface of the semiconductor layer structure) may form electron traps that trap charge during operation of the HEMT. These trapped charges may collect at the interface between the passivation layer 160 and the barrier layer 140 in the regions between the source contact 150 and the gate contact 154 and between the gate contact 154 and the drain contact 152, and these trapped charges may reduce current flow through the 2DEG layer 132. HEMTs according to embodiments of the present invention may include features that reduce charge formation in the above-described electron traps and / or dissipate the charge trapped in these electron traps. As a result, the drain current drift performance of HEMTs according to embodiments of the present invention may be significantly improved, and therefore the PIM distortion performance may be improved.

[0065] A HEMT according to an embodiment of the present invention may include a semiconductor layer structure including a channel layer and a barrier layer on the channel layer. The HEMT further includes source, drain, and gate contacts formed on an upper surface of the semiconductor layer structure, with the gate contact between the source and drain contacts. A first multi-layer passivation structure is formed on the upper surface of the semiconductor layer structure between the gate contact and the source contact, and a second multi-layer passivation structure is formed on the upper surface of the semiconductor layer structure between the gate contact and the drain contact. A respective spacer passivation layer is formed on a sidewall of each multi-layer passivation structure to face the gate contact. The spacer passivation layer can separate each multi-layer passivation structure from the gate contact. Each spacer passivation layer can include a silicon nitride layer. In some embodiments, the spacer passivation layer can be a multi-layer structure (e.g., it can include two silicon nitride layers).

[0066] Each multi-layer passivation structure may include at least a first silicon nitride layer in direct contact with the semiconductor layer structure and a second silicon nitride layer on the first silicon nitride layer on the opposite side of the semiconductor layer structure. Each multi-layer passivation structure may further include a third silicon nitride layer on the second silicon nitride layer on the opposite side of the first silicon nitride layer. Thus, the first to third silicon nitride layers of each multi-layer passivation structure may be stacked in a "vertical" direction, which refers to a direction extending perpendicular to the major surfaces (top and bottom) of the semiconductor layer structure.

[0067] The material composition of the second silicon nitride layer may be different from the material composition of the first silicon nitride layer. For example, the second silicon nitride layer may be more silicon-rich than the first silicon nitride layer. The third silicon nitride layer may also be more silicon-rich than the first silicon nitride layer. The material composition of the spacer passivation layer may be different from the material composition of at least the first silicon nitride layer. For example, the spacer passivation layer may be more silicon-rich than the first silicon nitride layer. In some embodiments, the spacer passivation layer may be more silicon-rich than all three of the first, second, and third silicon nitride layers. The spacer passivation layer may be in direct contact with the sidewalls of all three of the first, second, and third silicon nitride layers.

[0068] In some embodiments, the spacer passivation layer can include a first side that contacts the multi-layer passivation structure, a second side that contacts the semiconductor layer structure, and a third side that contacts the gate contact. In some embodiments, the third side can be the longest side. In some embodiments, the third side can have a generally concave shape. In some embodiments, the spacer passivation layer can have a generally triangular shape, with the longest side of the triangle having a concave profile.

[0069] HEMTs according to embodiments of the present invention may exhibit significantly improved drain current drift performance. The drain current of a conventional HEMT typically drops by at least 25% from its initial value to its quiescent (steady-state) value. HEMTs according to embodiments of the present invention may have quiescent drain current values ​​that are within 10%, 5%, or even 3% of the initial drain current value. The location of the spacer / passivation layer, the thickness of the multilayer passivation structure, the materials of the multilayer passivation structure and spacer / passivation layer, and / or the shape of the spacer / passivation layer can contribute to improved drain current drift performance.

[0070] Next, an embodiment of the present invention will be described in more detail with reference to FIGS. 3A to 8. FIG.

[0071] Figure 3A is a schematic plan view of a gallium nitride based HEMT 200 according to an embodiment of the present invention, and Figure 3B is a schematic cross-sectional view of HEMT 200 taken along line 3B-3B in Figure 3A. Figure 3C is a greatly enlarged view of portion "3C" in Figure 3B.

[0072] As shown in Figures 3A-3B, HEMT 200 may be formed on substrate 210. Substrate 210 may include a semi-insulating silicon carbide substrate, which may be, for example, the 4H or 6H polytype of silicon carbide. Other candidate silicon carbide polytypes that may be used to form substrate 210 include the 3C, 6H, and 15R polytypes. The term "semi-insulating" is used descriptively rather than in an absolute sense. In a specific embodiment of the present invention, bulk silicon carbide crystals have a density of approximately 1 x 10 at room temperature. 5 The HEMT 200 has a resistivity of Ω-cm or greater. While silicon carbide can be used as the substrate material, embodiments of the present invention can utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc. The substrate 210 can be a silicon carbide wafer, and the HEMT 200 can be formed, at least in part, by wafer-level processing, after which the wafer can be diced to provide a plurality of individual HEMTs 200.

[0073] One or more optional layers 220, such as, for example, a buffer layer, a nucleation layer, and / or a transition layer, may be formed on the top surface of the substrate 210. For example, an aluminum nitride (AlN) buffer layer 220 may be formed on the top surface of the substrate 210 to provide a suitable crystal structure transition between the silicon carbide substrate 210 and the remainder of the device 200. Additionally, a strain-balance transition layer 220 may also and / or alternatively be provided, for example, as described in commonly assigned U.S. Patent Publication No. 2003 / 0102482 A1, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional layer 220 may be deposited by metal organic chemical vapor deposition (MOCVD) or other techniques known to those skilled in the art, such as molecular beam epitaxy (MBE) or high vapor pressure epitaxy (HVPE).

[0074] A channel layer 230 is formed on top of the substrate 210 (or optional layer 220), and a barrier layer 240 is formed on top of the channel layer 230. The channel layer 230 may have a bandgap smaller than that of the barrier layer 240, and the channel layer 230 may also have a greater electron affinity than the barrier layer 240. The channel layer 230 and the barrier layer 240 may include materials from the III-nitride system.

[0075] In some embodiments, the channel layer 230 is Al, provided that the energy of the conduction band edge of the channel layer 230 is less than the energy of the conduction band edge of the barrier layer 240 at the interface between the channel and barrier layers 230, 240. x Ga 1-xIn some embodiments of the present invention, x=0, indicating that the channel layer 230 is GaN. The channel layer 230 may also be other III-nitrides, such as InGaN, AlInGaN, etc. The channel layer 230 may be undoped (“unintentionally doped”) and grown to a thickness greater than about 20 Å. The channel layer 230 may also be a multi-layer structure, such as a superlattice or a combination of GaN, AlGaN, etc. In some embodiments, the channel layer 230 may be under compressive strain.

[0076] In some embodiments, the barrier layer 240 is AlN, AlInN, AlGaN, or AlInGaN, or a combination of layers thereof. The barrier layer 240 may consist of a single layer or may be a multi-layer structure. In particular embodiments of the present invention, the barrier layer 240 is sufficiently thick and has a sufficiently high aluminum (Al) composition and doping so that, when the barrier layer 240 is buried under an ohmic contact metal, a significant carrier concentration can be induced at the interface between the channel layer 230 and the barrier layer 240 due to the polarization effect. For example, the barrier layer 240 may be about 0.1 nm to about 30 nm thick, but not so thick as to form cracks or substantial defects therein. Barrier layer thicknesses in the range of 15 to 30 nm are common. In some embodiments, the barrier layer 240 is undoped or doped with an n-type dopant to a thickness of about 10 nm. 19 cm -3 In some embodiments of the present invention, the barrier layer 240 is doped to a concentration below Al x Ga 1-xIt is N, where 0 < x < 1. In a specific embodiment, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 240 includes AlGaN with an aluminum concentration of about 5% to 100%. In a specific embodiment of the present invention, the aluminum concentration is greater than about 10%. The channel layer 230 and / or the barrier layer 240 can be deposited, for example, by MOCVD, MBE, or HVPE. During the on-state operation, the 2DEG layer 232 is induced in the channel layer 230 at the junction between the channel layer 230 and the barrier layer 240. The 2DEG layer 232 functions as a highly conductive layer that enables conduction between the source region and the drain region of the device, which are respectively under the source contact 250 and the drain contact 252. The substrate 210, the buffer / nucleation / transition layer 220, the channel layer 230, and the barrier layer 240 form a semiconductor layer structure 202.

[0077] The source contact 250 and the drain contact 252 are formed on the upper surface of the barrier layer 240 and are arranged laterally spaced apart from each other. The gate contact 254 is formed on the upper surface of the barrier layer 240 between the source contact 250 and the drain contact 252. The material of the gate contact 254 can be selected based on the composition of the barrier layer 240. Conventional materials capable of creating Schottky contacts to gallium nitride-based semiconductor materials, such as Ni, Pt, NiSi x , Cu, Pd, Cr, W, and / or WSiN, etc. can be used. The source contact 250 and the drain contact 252 may contain a metal such as TiAlN that can form an ohmic contact to the gallium nitride-based semiconductor material.

[0078] A pair of multi-layer passivation structures 260 (or one large multi-layer passivation structure 260) are formed on the upper surface of the barrier layer 240. A first multi-layer passivation structure 260-1 is formed between the source contact 250 and the gate contact 254, and a second multi-layer passivation structure 260-2 is formed between the drain contact 252 and the gate contact 254. A respective spacer passivation layer 270 (see FIG. 3C) is formed on the sidewall of each multi-layer passivation structure 260 facing the gate contact 254. An additional passivation layer 261 is formed on the first multi-layer passivation structure 260-1. A field plate 256 is formed on the additional passivation layer 261 between the source contact 250 and the gate contact 254. As shown in FIG. 3A, the field plate 256 can be electrically connected to the source contact 250 via a source contact extension 251. An additional passivation layer 261 is provided to space the field plate 256 an appropriate distance above the semiconductor layer structure 202. The multi-layer passivation structure 260 and the spacer passivation layer 270 are discussed in more detail below.

[0079] As mentioned above, the HEMT can be configured as a normally-on HEMT or a normally-off HEMT. The following discussion assumes that the HEMT 200 is a normally-on HEMT, although embodiments of the present invention are not limited thereto.

[0080] As shown by the arrow labeled 290 in FIG. 3B, when no bias voltage is applied to the gate contact 254 (and appropriate bias voltages are applied to the source and drain contacts 250, 252), electrons flow down the barrier layer 240 beneath the source contact 250 to the 2DEG layer 232, then flow laterally along the 2DEG layer 232 to the portion of the semiconductor layer structure 202 beneath the drain contact 252, and then flow upward to the drain contact 252. However, when a sufficient bias voltage is applied to the gate contact 254, the region of the semiconductor material beneath the gate contact 254 becomes depleted of charge carriers. In FIG. 3B, the depletion region is shown as region 258 defined by the dotted curve, and the size of the depletion region 258 is a function of, among other things, the applied gate bias voltage. The absence of charge carriers in the depletion region 258 effectively blocks the flow of electrons through the 2DEG layer 232, and therefore application of a gate bias voltage turns the HEMT 200 off.

[0081] However, as described above with reference to FIGS. 1A and 1B, there is a gate leakage current I G path (see 192 in Figure 2) and the drain leakage current I DThere are various current paths, such as the drain-gate path (see 194 in FIG. 2 ). Gate and drain leakage current paths allow current to flow even when the HEMT 200 is biased in the off state. Additionally, as discussed above, electron traps, for example, associated with defects on the top surface of the barrier layer 240, can collect charge at the interface between the barrier layer 240 and the channel layer 230 and retain charge that can reduce or block current flow along the 2DEG layer 232 even when the gate contact 254 is unbiased (i.e., the HEMT 200 is biased in the on state). While these charges dissipate over time, for example, when the HEMT 200 is used as an RF amplifier, the gate bias voltage is rapidly cycled between the on and off states, so the charge from the electron traps may retain energy near the 2DEG layer 232. When the gate bias voltage is removed and the HEMT 200 is in the on state, the charge may have a “memory effect,” referred to herein as “drain lag,” and at least partially block current flow through the 2DEG layer 232 after the gate bias voltage is removed. Drain lag can introduce nonlinearities and produce passive intermodulation distortion, which can significantly degrade the performance of communication systems that include the HEMT200 as an RF transistor amplifier.

[0082] The drain current drift performance of a HEMT is one characteristic of the drain lag effect mentioned above. The drain current drift performance is measured by applying a direct current (DC) bias voltage to the HEMT to bias it to the on-state, and then measuring the drain current I DS This can be measured by looking at how the drain current I varies over time, as shown graphically in Figure 4. Theoretically, the drain current I DSA steady-state condition must be reached so that the drain current remains constant. However, mechanisms such as the charge accumulation described above can cause a depletion region to form that can partially block the 2DEG channel, causing the drain current to decrease over time, as shown by the curve labeled "with drain current drift" in Figure 4.

[0083] As described above, in accordance with embodiments of the present invention, HEMTs are provided that have improved passivation structures that may significantly improve drain current drift performance. These improved passivation structures can modulate electron traps on the top surface of semiconductor layer structure 202 to reduce the amount of charge that accumulates in the electron traps. Modulating the electron traps in this manner can improve the drain current drift performance of the HEMT.

[0084] Figure 3C is an enlarged view of the area labeled "3C" in Figure 3B. Figure 3C shows a portion of one of the multi-layer passivation structures 260 (here, multi-layer passivation structure 260-2) and one of the spacer passivation layers 270 (here, spacer passivation layer 270-2) on one side (here, the drain side) of the gate contact 254. It will be understood that the multi-layer passivation structure 260-1 and spacer passivation layer 270-1 on the opposite side (here, the source side) of the gate contact 254 may be mirror images of those shown in Figure 3C.

[0085] 3C , the multi-layer passivation structure 260 includes a first passivation layer 262, a second passivation layer 264, and a third passivation layer 266, which are stacked vertically in sequence on the semiconductor layer structure 202 (more specifically, the barrier layer 240). The first passivation layer 262 may be a first silicon nitride layer 262, the second passivation layer 264 may be a second silicon nitride layer 264, and the third passivation layer 266 may be a third silicon nitride layer 266. The first silicon nitride layer 262 may be in direct contact with the semiconductor layer structure 202, the second silicon nitride layer 264 may be in direct contact with the first silicon nitride layer 262, and the third silicon nitride layer 266 may be in direct contact with the second silicon nitride layer 264. The second silicon nitride layer 264 is between the first and third silicon nitride layers 262, 266. It will be appreciated that in other embodiments, the multi-layer passivation structure 260 may include only two passivation layers or more than three passivation layers. In some embodiments, for example, the second silicon nitride layer 264 or the third silicon nitride layer 266 may be omitted, or the second and third silicon nitride layers 264, 266 may be replaced by a single, thicker silicon nitride layer.

[0086] The first silicon nitride layer 262 may be formed by sputtering or physical vapor deposition (PVD) and may be a high-quality silicon nitride layer containing fewer electron traps than silicon nitride layers formed by chemical vapor deposition (CVD). Because the first silicon nitride layer 262 is formed by sputtering or PVD, the top surface of the semiconductor layer structure 202 is little or not damaged during the formation of the first silicon nitride layer 262. The first silicon nitride layer 262 may be a silicon-rich non-stoichiometric silicon nitride. The silicon-rich silicon nitride may include a charge dissipation material that acts to dissipate charge stored in electron traps along the top surface of the barrier layer 240. A charge dissipation material refers to a material that substantially dissipates charge trapped on the top surface of the underlying semiconductor layer. The charge dissipation material may neutralize charge in electron traps, provide a dissipation path for charge, or otherwise act to reduce the amount of charge that accumulates in the barrier layer 240. As a result, the amount of drain lag can be reduced due to a smaller amount of charge in semiconductor structure 202. First silicon nitride layer 262 can be a silicon-rich non-stoichiometric silicon nitride layer, but can be only moderately silicon-rich to avoid increasing leakage current and / or adversely affecting the off-state performance of HEMT 200. In an exemplary embodiment, first silicon nitride layer 262 can have a thickness of about 10 nm to about 40 nm.

[0087] The second silicon nitride layer 264 may be formed by CVD. The second silicon nitride layer 264 may also be formed of a silicon-rich non-stoichiometric silicon nitride and may be more silicon-rich than the first silicon nitride layer. In an exemplary embodiment, the thickness of the second silicon nitride layer 264 may be from about 10 nm to about 40 nm.

[0088] The third silicon nitride layer 266 may be formed by CVD. The third silicon nitride layer 266 may also be formed of a silicon-rich non-stoichiometric silicon nitride and may be more silicon-rich than the first silicon nitride layer. In an exemplary embodiment, the thickness of the third silicon nitride layer 266 may be from about 10 nm to about 40 nm.

[0089] In an exemplary embodiment, the multi-layer passivation structure 260 may have a thickness of approximately 50-80 nm, and each of the first through third silicon nitride layers 262, 264, 266 may have a thickness of 20%-45% of the total thickness of the multi-layer passivation structure 260.

[0090] The spacer passivation layer 270 is formed directly on the semiconductor layer structure 202 between the gate contact 254 and the multi-layer passivation structure 260. The spacer passivation layer 270 may be in direct contact with the semiconductor layer structure 202, the multi-layer passivation structure 260, and the gate contact 254. The spacer passivation layer 270 may completely cover the sidewalls of the multi-layer passivation structure 260 (i.e., it may cover all three of the first, second, and third silicon nitride layers 262, 264, and 266). Typically, the sidewalls of the multi-layer passivation structure 260 are slanted, and the spacer passivation layer 270 covers the slanted sidewalls and a portion of the top surface of the semiconductor layer structure 202. The outer wall of the spacer passivation layer 270 facing the gate contact 254 may have a concave profile resulting from partial etching of the fourth silicon nitride layer 268 (described below) that forms at least a portion of the spacer passivation layer. As shown in Figure 3C, the spacer passivation layer 270, in some embodiments, may have a generally triangular shape, with the long side of the triangle having a concave profile.

[0091] In some embodiments, spacer passivation layer 270 may be a single silicon nitride layer formed, for example, by etching fourth silicon nitride layer 268 described above. In such embodiments, spacer passivation layer 270 may have the shape shown in FIG. 3C. In other embodiments, spacer passivation layer 270 may be a multi-layer structure. For example, FIG. 3D illustrates a modified version of the device of FIG. 3C. Here, spacer passivation layer 270 is comprised of a two-layer structure including the remnants of fourth silicon nitride layer 268 and a fifth silicon nitride layer 272. In such embodiments, fifth silicon nitride layer 272 may be an L-shaped thin layer, as shown. It will be understood that other configurations are also possible. For example, in the embodiments of FIGS. 3C and / or 3D, the top of fourth silicon nitride layer 268 may be replaced with a silicon oxide layer, or in yet another embodiment, a silicon oxynitride layer. For example, Figure 3E is a schematic cross-sectional view of the HEMT of Figure 3C modified to replace a portion of the fifth silicon nitride layer 272 with a layer 273 comprising silicon and oxygen, such as a silicon oxide or silicon oxynitride layer. It will also be understood that in any of the embodiments described herein, the multi-layer passivation structure 260 may further include an additional layer comprising silicon and oxygen, such as a silicon oxide or silicon oxynitride layer, where the additional layer is sufficiently spaced apart from the semiconductor layer structure 202.

[0092] The spacer passivation layer 270 may include one or more silicon-rich non-stoichiometric silicon nitride layers and may be more silicon-rich than the first silicon nitride layer 262. The one or more silicon nitride layers included in the spacer passivation layer 270 may also be more silicon-rich than the second silicon nitride layer 264 and / or the third silicon nitride layer 266. In some embodiments, one or more layers forming the spacer passivation layer 270 may be formed by CVD. Alternatively, other deposition techniques may be used, such as physical vapor deposition ("PVD"), atomic layer deposition ("ALD"), plasma-enhanced ALD ("PEALD"), or plasma-enhanced PVD ("PEPVD").

[0093] The spacer passivation layer 270 may extend vertically along the entire length of the gate contact 254, as shown in FIG. 3A . In contrast, the spacer passivation layer 270 may extend only a short distance laterally (i.e., parallel to the top surface of the semiconductor layer structure 202 and perpendicular to the vertical axis of the gate contact 254, which corresponds to the horizontal direction in FIG. 3C ). For example, in some embodiments, the spacer passivation layer 270 may extend laterally by less than 10% of the distance between the gate contact 254 and the drain contact 252, while in other embodiments, the spacer passivation layer 270 may extend laterally by less than 5% of the distance between the gate contact 254 and the drain contact 252. In some embodiments, the bottom surface of the spacer passivation layer 270 may define the “width” of the spacer passivation layer 270. Because the lateral width of the spacer passivation layer 270 is small, the fact that it can be very silicon-rich silicon nitride does not result in any other adverse impact on performance. In exemplary embodiments, the lateral width of each spacer passivation layer may be 100 nm or less, 60 nm or less, or even 40 nm or less. In contrast, the distance between the gate and drain contacts may be greater than 3 microns. The lateral width of the gate contact 254 (conventionally referred to as the "gate length") may be, for example, about 0.25 microns.

[0094] As described above, the silicon nitride layers included in multi-layer passivation structure 260 and spacer passivation layer 270 can have different silicon and nitrogen concentrations. In some embodiments, each of these layers can be a silicon-rich silicon nitride layer. The chemical formula for stoichiometric silicon nitride is SixNy, where x=3 and y=4. In some embodiments of the invention, the silicon nitride layers included in multi-layer passivation structure 260 and spacer passivation layer 270 can have silicon-to-nitrogen ("Si:N") ratios as shown in the table below. The table shows both nominal values ​​for the Si:N ratios, ranges of variation for each Si:N ratio according to some embodiments, and wider ranges of variation for each Si:N ratio according to further embodiments of the invention. [Table 1]

[0095] The silicon-to-nitrogen ratio of each of the above layers can be determined, for example, using Rutherford backscattering. It will also be appreciated that refractive index can be used as a proxy for the silicon-to-nitrogen ratio of a silicon nitride layer. For CVD films, the higher the refractive index, the more silicon-rich the silicon nitride layer. Thus, in other embodiments, the silicon nitride layers included in multilayer passivation structure 260 and spacer passivation layer 270 can have refractive indices within the following ranges: [Table 2]

[0096] 3C, the gate contact 254 may extend onto the top surface of the spacer passivation layer 270. The spacer passivation layer 270 may not be perfectly triangular in shape due to the concave profile of its top and outer surfaces 278, but in some cases, two vertically extending sidewalls of the spacer passivation layer 270 may intersect or nearly intersect, causing the spacer passivation layer 270 to have only three sides and thus be more triangular in shape.

[0097] 3C, the gate contact 254 may be a multi-layer contact that includes a plurality of thin layers 282 conformally formed on the semiconductor layer structure 202 and the multi-layer passivation structure 260, and a bulk metal layer 280 formed on the thin conformal layers 282. The thin conformal layers 282 may comprise, for example, an adhesion layer, a diffusion barrier layer, and / or a contact layer.

[0098] 5A-5I illustrate a method of forming HEMT 200 according to the embodiment of the invention of FIGS. 3A-3C.

[0099] As shown in FIG. 5A, one or more optional buffer layers, nucleation layers, and / or transition layers 220 may be formed on a substrate 210, such as a silicon carbide substrate. The buffer layer / nucleation layer / transition layer 220 may be composed of, for example, a Group III nitride layer such as aluminum nitride, gallium nitride. The optional layer 220 can promote the growth of a high-quality Group III nitride layer on the substrate 210, despite the lattice mismatch between the substrate 210 and the channel layer 230 and barrier layer 240 formed above the device structure. The optional buffer layer / nucleation layer / transition layer 220 may be formed by metalorganic chemical vapor deposition (MOCVD), or other techniques known to those skilled in the art such as molecular beam epitaxy (MBE) and high vapor pressure epitaxy (HVPE).

[0100] As shown in FIG. 5B, the channel layer 230 may be formed on the upper surface of the buffer layer 220, and the barrier layer 240 may be formed on the upper surface of the channel layer 230. The channel layer 230 and / or the barrier layer 240 may be deposited, for example, by MOCVD, MBE, or HVPE. The channel layer 230 may have a bandgap smaller than that of the barrier layer 240, and the channel layer 230 may also have a larger electron affinity than the barrier layer 240. The channel layer 230 and the barrier layer 240 may include Group III nitride-based materials. For example, the channel layer 230 may be composed of a gallium nitride layer, and the barrier layer 240 may include Al x Ga 1-x N, where 0 < x < 1. The channel layer 230 is undoped (``unintentionally doped'') and can be grown to a thickness greater than about 20 Å. In an exemplary embodiment, the barrier layer 240 may be undoped or doped with an n-type dopant.

[0101] Referring to FIG. 5C , a first silicon nitride layer 262 may be blanket deposited on the barrier layer 240. As described above, the first silicon nitride layer 262 may be formed by sputtering or PVD and may be a silicon-rich non-stoichiometric silicon nitride. In an exemplary embodiment, the thickness of the first silicon nitride layer 262 may be about 10 nm to about 40 nm. Next, a second silicon nitride layer 264 may be blanket deposited on the first silicon nitride layer 262. The second silicon nitride layer 264 may be formed by CVD and may be a non-stoichiometric silicon nitride that is more silicon-rich than the first silicon nitride layer 262. In an exemplary embodiment, the thickness of the second silicon nitride layer 264 may be about 10 nm to about 40 nm.

[0102] Referring to FIG. 5D , an etch mask (not shown) may then be formed on the second passivation layer 264, and the etch mask may be patterned using standard photolithography techniques. The first and second silicon nitride layers 262, 264 may then be etched using the patterned etch mask to form openings therein (not shown, but located at the locations of the source and drain contacts 250, 252). One or more metal layers used to form the source and drain contacts 250, 252 may then be formed. The source and drain contacts 250, 252 may include a metal such as TiAlN that can form ohmic contacts to the gallium nitride-based semiconductor material. The ohmic metal may be blanket-deposited on the device, for example, by sputtering, followed by appropriate masking and etching steps to remove any remaining metal and form the source and drain contacts 250, 252.

[0103] Referring to FIG. 5E, a third silicon nitride layer 266 is blanket deposited on the second silicon nitride layer 264 and the source and drain contacts 250, 252. The third silicon nitride layer 266 is formed by CVD and may be a non-stoichiometric silicon nitride that is more silicon-rich than the first silicon nitride layer 262. In an exemplary embodiment, the thickness of the third silicon nitride layer 266 may be from about 10 nm to about 40 nm. In some embodiments, the third silicon nitride layer 266 may comprise the same material as the second silicon nitride layer 264. The boundary between the first and second silicon nitride layers 264, 266 may be detectable due to oxygen atoms collecting at the interface between them during the processing steps described above with reference to FIG. 5D.

[0104] 5F, an etch mask (not shown) may then be formed on the third passivation layer 266, and this etch mask may be patterned using standard photolithography techniques to form openings over the source contact 250, the drain contact 252, and where the gate contact 254 will be formed in a later processing step. The third silicon nitride layer 266 may then be etched using the patterned etch mask to form openings 263 that expose the source and drain contacts 250, 252 and expose a portion of the semiconductor layer structure 202. The etch mask may then be removed.

[0105] 5G, a fourth silicon nitride layer 268 is blanket deposited over the third silicon nitride layer 266, over the source and drain contacts 250, 252, and within the opening 263. In an exemplary embodiment, the fourth silicon nitride layer 268 may be formed by CVD. The fourth silicon nitride layer 268 may comprise a silicon-rich non-stoichiometric silicon nitride, and in some embodiments, may be more silicon-rich than all three of the first through third silicon nitride layers 262, 264, 266.

[0106] Referring to FIG. 5H, an isotropic etch is performed to substantially remove the fourth silicon nitride layer 268. The isotropic etch removes the fourth silicon nitride layer 268 from all generally planar surfaces. However, because the isotropic etch etches the planar regions of the fourth silicon nitride layer 268 much faster than the sidewall regions, the fourth silicon nitride layer 268 extending onto the sidewalls of the multi-layer passivation structure 260 is not completely removed, as best shown in the enlarged view of FIG. 3C above. The remaining portions of the fourth silicon nitride layer 268 after this etching step form a pair of spacer passivation layers 270 that are formed on the sidewalls of the opening 263 for the gate contact 254, as best shown in FIG. 3C.

[0107] Referring to Figure 5I, gate contact 254 is formed in opening 263. As described above with reference to Figure 3C, gate contact 254 is composed of multiple thin layers 282, which may include, for example, adhesion layers, diffusion barrier layers, and / or contact layers. Each of these thin layers 282 may be conformally formed on the underlying structure. A bulk metal layer 280 is formed on thin metal layer 282 (see Figure 3C).

[0108] The bottom of the gate contact 254 may be in direct contact with the semiconductor layer structure 202 and the spacer passivation layers 270-1 and 270-2, and the top of the gate contact 254 may be in direct contact with the top surface of the multi-layer passivation structure 260. Materials used to form the gate contact 254 include, for example, Ni, Pt, NiSi x The material may include Cu, Pd, Cr, W, and / or materials capable of making a Schottky contact to a gallium nitride-based semiconductor material such as WSiN.

[0109] 5A-5I illustrate a method of forming a device including a multi-layer passivation structure 260 having three silicon nitride layers and a spacer passivation layer 270 having a single silicon nitride layer. As noted above, in other embodiments, the multi-layer passivation structure 260 may have only two silicon nitride layers or more than three silicon nitride layers, and / or the spacer passivation layer may include multiple silicon nitride layers.

[0110] 6A-6C are schematic cross-sectional views of spacer passivation layers 370, 470, and 570, respectively, that can be used in place of spacer passivation layer 270 in HEMT 200. As shown in FIG. 6A, spacer passivation layer 370 is similar to spacer passivation layer 270, except that spacer passivation layer 370 is more concave than spacer passivation layer 270. As shown in FIG. 6B, spacer passivation layer 470 is similar to spacer passivation layer 270, except that an upper portion of spacer passivation layer 470 is slightly thicker than the corresponding portion of spacer passivation layer 270, and a lower portion of spacer passivation layer 470 is slightly thinner than the corresponding portion of spacer passivation layer 270. As shown in FIG. 6C, spacer passivation layer 570 is similar to spacer passivation layer 270, except that the concave sidewalls of spacer passivation layer 570 are less smooth and reflect the fact that etching does not occur evenly, and therefore in most practical implementations the concave sidewalls are somewhat "rough."

[0111] HEMTs according to embodiments of the present invention may exhibit significantly improved drain current drift performance. Figure 7A is a graph showing drain current as a function of time from device power-on for a conventional high-power, high-frequency gallium nitride-based HEMT. As shown in Figure 7A, the drain current of the conventional HEMT decreases by approximately 25-30% from its initial value within 5 minutes of device power-on, with nearly all of the decrease occurring within the first 50 seconds. As shown in Figure 7B, the drain current in HEMTs according to embodiments of the present invention may decrease by less than 10% from its initial value, and in some embodiments, may decrease by less than 5%, or even less than 3%. Maintaining a constant drain bias current during operation may significantly improve the performance of HEMT power amplifiers by improving drain efficiency, power-regulated efficiency, and output power.

[0112] The improved drain current drift performance achieved in HEMTs according to embodiments of the present invention can be directly attributed to aspects of the passivation structure formed on the semiconductor layer structure. For example, a spacer passivation layer formed from a silicon-rich silicon nitride layer is placed between the gate contact and the multi-layer passivation structure. This spacer passivation layer ensures that the first silicon nitride layer of the multi-layer passivation structure does not physically touch the gate contact, which can improve drain current drift performance. Furthermore, the concave sidewalls of the spacer passivation layer facilitate conformal formation of the gate contact on the spacer passivation layer, and the concave surface also advantageously directs the electric field in a desired direction. The height of the multi-layer passivation structure can also be optimized to improve drain current drift performance.

[0113] Furthermore, the deposition of a fourth silicon nitride layer (which is later etched to form the spacer / passivation layer) can repair electron traps formed on the top surface of the semiconductor layer structure. Furthermore, a second etch is performed to form the spacer / passivation layer, but this etch can be performed using gentler etching conditions that are less likely to create additional electron traps.

[0114] 8 is a flow chart illustrating a method for fabricating a HEMT according to an embodiment of the present invention. As shown in FIG. 8, a semiconductor layer structure (shown as SLS in FIG. 8) including a channel layer and a barrier layer, such as semiconductor layer structure 202, can be provided (step 600). The semiconductor layer structure can be comprised of, for example, a substrate on which multiple semiconductor epitaxial layers are formed.

[0115] A first passivation layer, such as a first silicon nitride layer of a multi-layer passivation structure (in FIG. 8, a multi-layer passivation structure (MLPS)), may be formed on top of the semiconductor layer structure (Step 605). A second passivation layer, such as a second silicon nitride layer of the multi-layer passivation structure, may then be formed on the first passivation layer (Step 610).

[0116] Openings can then be patterned in the multi-layer passivation structure for source and drain contacts (step 615), and the source and drain contacts can be formed in the respective openings (step 620).

[0117] A third passivation layer, such as a third silicon nitride layer of a multi-layer passivation structure, can then be formed over the second passivation layer (step 625). An opening can then be patterned in the multi-layer passivation structure for a gate contact (step 630). The opening can extend vertically through the multi-layer passivation structure to expose the semiconductor layer structure.

[0118] A fourth passivation layer, such as a fourth silicon nitride layer, can be formed in the gate contact opening (Step 635). An etch-back step can then be performed to remove most of the fourth passivation layer, leaving a portion of the fourth passivation layer on the sidewalls of the gate contact opening (Step 640). These remaining portions form first and second spacer passivation layers formed on the sidewalls of the multilayer passivation structure facing the gate contact opening. A gate contact can then be formed in the gate contact opening (Step 645), such that the first and second spacer passivation layers are located between the multilayer passivation structure (or structures) and the gate contact.

[0119] As described above, HEMTs according to embodiments of the present invention can be used as RF transistor amplifiers. RF transistor amplifiers according to embodiments of the present invention can include one or more amplification stages, with each stage typically implemented as a transistor amplifier. To increase output power and current handling capabilities, these RF transistor amplifiers can be implemented in a unit cell configuration, where multiple individual "unit cell" transistors are electrically arranged in parallel. RF transistor amplifiers can be implemented as a single integrated circuit chip, or "die," or can include multiple dies. When multiple RF transistor amplifier dies are used, they can be connected in series and / or parallel.

[0120] An RF transistor amplifier according to an embodiment of the present invention may include matching circuits such as (1) an impedance matching circuit designed to improve the impedance match (for RF signals at the fundamental operating frequency of the amplifier) ​​between the RF transistor amplifier die and a transmission line connected thereto, and (2) a harmonic termination circuit designed to at least partially terminate harmonics that may be generated during device operation, such as second or third harmonics or baseband intermodulation products. The RF transistor amplifier die, as well as the impedance matching circuit and harmonic termination circuit, may be enclosed in a package. Electrical leads may extend from the package to electrically connect the RF transistor amplifier to external circuit elements, such as input and output RF transmission lines and bias voltage sources.

[0121] RF transistor amplifiers according to embodiments of the present invention can be designed to operate in a variety of different frequency bands. In some embodiments, the RF transistor amplifiers may be configured to operate at frequencies greater than 1 GHz. In other embodiments, the RF transistor amplifier dies may be configured to operate at frequencies greater than 2.5 GHz. In still other embodiments, the RF transistor amplifier dies may be configured to operate at frequencies greater than 3.1 GHz. In still additional embodiments, the RF transistor amplifier dies may be configured to operate at frequencies greater than 5 GHz. In some embodiments, the RF transistor amplifier dies may be configured to operate in at least one of the following frequency bands, or subportions thereof: 2.5-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz.

[0122] Although embodiments of the present invention have been described above with reference to an RF transistor amplifier die implemented with HEMT devices, it will be appreciated that other types of semiconductor devices may be formed in semiconductor layer structure 202 without departing from the present invention. In other embodiments, for example, semiconductor layer structure 202 may include MOSFETs, DMOS transistors, MESFETs, and / or LDMOS transistors, etc.

[0123] Although terms such as "first" and "second" may be used herein to describe various elements, it will be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0124] Two-part reference numbers (i.e., two numbers separated by a dash, such as 100-1) may be used in the specification and figures to identify similar elements. When such a two-part reference number is used, the entire reference number may be used to refer to a specific instance of an element, and the first part of the reference number may be used to refer to the elements collectively.

[0125] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, as used herein, the terms "comprises," "comprising," "includes," and / or "including" will be understood to specify the presence of stated features, integers, steps, operations, elements, and / or components, but not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0126] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, it will be understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and the related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0127] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "upon" another element, it will be understood that the element may be directly on or extending directly onto the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" extending from another element, there are no intervening elements.

[0128] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0129] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the shapes of the particular regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0130] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. The scope of the invention is set forth in the following claims.

Claims

1. a semiconductor layer structure including a channel layer and a barrier layer on the channel layer; a source contact on the semiconductor layer structure; a drain contact on the semiconductor layer structure; a gate contact on the semiconductor layer structure between the source contact and the drain contact; a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers including at least a first silicon nitride layer and a second silicon nitride layer having a material composition different from a material composition of the first silicon nitride layer; a spacer passivation layer on the sidewalls of both the first silicon nitride layer and the second silicon nitride layer; Equipped with A high electron mobility transistor, wherein the material composition of the spacer passivation layer differs from the material composition of at least one of the layers of the multi-layer passivation structure.

2. 2. The high electron mobility transistor of claim 1, wherein the first silicon nitride layer is in direct contact with the barrier layer, the second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, and the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

3. 3. The high electron mobility transistor of claim 2, wherein the multi-layer passivation structure further comprises a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

4. 4. The high electron mobility transistor of claim 3, wherein the spacer passivation layer comprises a silicon-rich silicon nitride layer that is richer in silicon than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

5. 4. The high electron mobility transistor of claim 3, wherein the spacer passivation layer directly contacts all three sidewalls of the first through third silicon nitride layers.

6. The high electron mobility transistor of claim 1 , wherein the spacer passivation layer comprises a silicon-rich silicon nitride layer.

7. The high electron mobility transistor of claim 1 , wherein the spacer passivation layer is between the multi-layer passivation structure and the gate contact.

8. 8. The high electron mobility transistor of claim 7, wherein the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

9. 7. The high electron mobility transistor of claim 1, wherein the spacer passivation layer includes an inner surface facing the multilayer passivation structure and an outer surface opposite the inner surface, the outer surface having a concave profile.

10. 7. The high electron mobility transistor of claim 1, wherein the spacer passivation layer has a generally triangular shape, the longest side of which has a concave profile.

11. 11. The high electron mobility transistor of claim 1, wherein a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

12. 12. The high electron mobility transistor of claim 1, wherein the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

13. a semiconductor layer structure including a channel layer and a barrier layer on the channel layer; a source contact on the semiconductor layer structure; a drain contact on the semiconductor layer structure; a gate contact on the semiconductor layer structure between the source contact and the drain contact; a passivation structure on the semiconductor layer structure between the source contact and the drain contact; a spacer passivation layer on the sidewalls of the passivation layer; Equipped with an outer surface of the spacer passivation layer opposite the passivation layer having a concave profile;

14. 14. The high electron mobility transistor of claim 13, wherein the passivation structure comprises a multi-layer passivation structure including at least a first silicon nitride layer in direct contact with the barrier layer and a second silicon nitride layer on the first silicon nitride layer opposite the barrier layer, the second silicon nitride layer having a material composition different from a material composition of the first silicon nitride layer.

15. 15. The high electron mobility transistor of claim 14, wherein the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

16. 16. The high electron mobility transistor of claim 15, wherein the multi-layer passivation structure further comprises a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

17. 17. The high electron mobility transistor of claim 14, wherein the spacer passivation layer is in direct contact with all three sidewalls of the first, second, third, and third silicon nitride layers.

18. 17. The high electron mobility transistor of claim 14, wherein the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than the first silicon nitride layer.

19. 17. The high electron mobility transistor of claim 14, wherein the spacer passivation layer is between the multi-layer passivation structure and the gate contact.

20. 20. The high electron mobility transistor of claim 13, wherein the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

21. 21. The high electron mobility transistor of claim 13, wherein a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

22. 22. The high electron mobility transistor of claim 13, wherein the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

23. a semiconductor layer structure including a channel layer and a barrier layer on the channel layer; a source contact on the semiconductor layer structure; a drain contact on the semiconductor layer structure; a gate contact on the semiconductor layer structure between the source contact and the drain contact; a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a first silicon nitride layer in direct contact with the semiconductor layer structure; a silicon nitride spacer passivation layer including at least one silicon nitride layer on sidewalls of the multi-layer passivation structure; Equipped with a silicon concentration of the at least one silicon nitride layer that exceeds a silicon concentration of the first silicon nitride layer;

24. 24. The high electron mobility transistor of claim 23, wherein the spacer passivation layer is disposed between the first silicon nitride layer and the gate contact such that the first silicon nitride layer does not contact the gate contact.

25. 25. The high electron mobility transistor of claim 23, wherein the multi-layer passivation structure further comprises a second silicon nitride layer on the opposite side of the barrier layer and on the first silicon nitride layer, the second silicon nitride layer being more silicon-rich than the first silicon nitride layer.

26. 26. The high electron mobility transistor of claim 25, wherein the multi-layer passivation structure further comprises a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, the third silicon nitride layer being more silicon-rich than the first silicon nitride layer.

27. 27. The high electron mobility transistor of claim 26, wherein the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

28. 28. The high electron mobility transistor of claim 27, wherein the spacer passivation layer directly contacts all three sidewalls of the first through third silicon nitride layers.

29. 29. The high electron mobility transistor of any of claims 23 to 28, wherein the spacer passivation layer is in direct contact with both the multi-layer passivation structure and the gate contact.

30. 30. The high electron mobility transistor of claim 23, wherein an outer surface of the spacer passivation layer opposite the multi-layer passivation structure has a concave profile.

31. 31. The high electron mobility transistor of any of claims 23 to 30, wherein the spacer passivation layer has a generally triangular shape, the longest side of which has a concave profile.

32. 32. The high electron mobility transistor of claim 23, wherein a longitudinal axis of the gate contact extends in a first direction on the barrier layer, the multilayer passivation structure extends in a second direction perpendicular to the first direction on the barrier layer a first distance, and the spacer passivation layer extends in the second direction on the barrier layer a second distance that is less than 5 percent of the first length.

33. 33. The high electron mobility transistor of any of claims 23 to 32, wherein the quiescent drain current of the high electron mobility transistor is within 10% of the peak drain current of the high electron mobility transistor.

34. providing a semiconductor layer structure including a channel layer and a barrier layer on the channel layer; forming a first silicon nitride layer of a multi-layer passivation structure over the semiconductor layer structure; patterning an opening for a gate contact in the multi-layer passivation structure; forming a passivation layer in the opening; removing the passivation layer from a bottom of the opening while leaving portions of the passivation layer on first and second opposing sidewalls of the opening, with remaining portions of the passivation layer forming respective first and second spacer passivation layers; 1. A method for fabricating a high electron mobility transistor, comprising:

35. 35. The method of claim 34, further comprising forming a second silicon nitride layer of the multi-layer passivation structure on the first silicon nitride layer, and wherein patterning the opening for the gate contact in the multi-layer passivation structure comprises patterning an opening extending through at least the first silicon nitride layer and the second silicon nitride layer.

36. 36. The method of claim 35, wherein the second silicon nitride layer is more silicon-rich than the first silicon nitride layer.

37. 36. The method of claim 35, further comprising forming a third silicon nitride layer of the multi-layer passivation structure on the second silicon nitride layer, and wherein patterning the opening for the gate contact in the multi-layer passivation structure comprises patterning an opening extending through at least the first through third silicon nitride layers.

38. 38. The method of claim 37, further comprising patterning openings for source and drain contacts in both the first and second silicon nitride layers before forming the third silicon nitride layer.

39. 36. The method of claim 35, wherein the first silicon nitride layer is in direct contact with the barrier layer and the second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, the second silicon nitride layer being more silicon-rich than the first silicon nitride layer.

40. 40. The method of any of claims 35 to 39, wherein the first spacer passivation layer comprises a silicon-rich silicon nitride layer that is richer in silicon than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

41. 41. The method of any of claims 35 to 40, wherein the first spacer passivation layer directly contacts all three sidewalls of the first through third silicon nitride layers.

42. 42. The method of any of claims 34 to 41, further comprising forming a gate contact in the opening, wherein the first spacer passivation layer is between the multi-layer passivation structure and the gate contact.

43. 43. The method of any of claims 34 to 42, wherein an outer surface of the first spacer passivation layer opposite the multi-layer passivation structure has a concave profile.

44. 13. The high electron mobility transistor of claim 1, wherein the spacer passivation layer includes a fourth silicon nitride layer and a fifth silicon nitride layer between the fourth silicon nitride layer and the multi-layer passivation structure.

45. 45. The high electron mobility transistor of claim 44, wherein the fourth silicon nitride layer and the fifth silicon nitride layer are each more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

46. 45. The high electron mobility transistor of claim 44, wherein the fifth silicon nitride layer is an L-shaped layer directly contacting a sidewall of the multi-layer passivation structure.

47. 17. The high electron mobility transistor of claim 16, wherein the spacer passivation layer comprises a fourth silicon nitride layer and a fifth silicon nitride layer between the fourth silicon nitride layer and the multi-layer passivation structure.

48. 48. The high electron mobility transistor of claim 47, wherein the fourth silicon nitride layer and the fifth silicon nitride layer are each more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.

49. 49. The high electron mobility transistor of claim 48, wherein the fifth silicon nitride layer is an L-shaped layer directly contacting a sidewall of the multi-layer passivation structure.

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