Wafer bonding process with reduced overlay distortion

Abstract

An embodiment of a method includes determining an upper vacuum condition, a lower vacuum condition, a bond gap distance, and a striker pressure condition based on measurements of residual strain from previously bonded wafers. The method includes applying an upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a backside of the upper wafer, the upper wafer having a front side opposite the backside. The method includes applying a lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a backside of the lower wafer, the lower wafer having a front side opposite the backside. The method includes positioning the front side of the upper wafer over the front side of the lower wafer to create a bond gap distance between the upper and lower wafers. The method also includes using a striker pressure condition to press the backside of the upper wafer with a striker to bond the front side of the upper wafer and the front side of the lower wafer together.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a wafer bonding process with reduced overlay distortion. [Background technology]

[0002] In integrated circuit (IC) production, precise alignment and bonding of multiple layers is crucial to ensure the functionality and performance of the final device. Overlay distortion, also known as misregistration, refers to the misplacement or misalignment of patterns and features between different layers during the wafer bonding process. Overlay distortion can lead to various problems, such as reduced device yield, degraded electrical performance, and increased fabrication costs.

[0003] Existing wafer bonding techniques, such as direct wafer bonding, thermocompression bonding, and adhesive bonding, are used to achieve strong bonds between wafers. However, these methods often suffer from overlay distortion due to the inherent mechanical and thermal stresses generated during the bonding process. These stresses can cause the bonded wafers to warp, bend, or tilt, leading to pattern and feature misalignment, known as overlay distortion. Summary of the Invention [Means for solving the problem]

[0004] According to a preferred embodiment of the present invention, a method includes determining upper vacuum conditions, lower vacuum conditions, a bond gap distance, and a striker pressure condition based on measurements of residual strain from previously bonded wafers. The method includes applying an upper vacuum condition to an upper wafer using an upper wafer holder, the upper vacuum condition being applied to a backside of the upper wafer, the upper wafer having a front side opposite the backside. The method includes applying a lower vacuum condition to a lower wafer using a lower wafer holder, the lower vacuum condition being applied to a backside of the lower wafer, the lower wafer having a front side opposite the backside. The method includes positioning the front side of the upper wafer over the front side of the lower wafer to create a bond gap distance between the upper and lower wafers. The method also includes using a striker pressure condition to press the backside of the upper wafer with a striker to bond the front side of the upper wafer and the front side of the lower wafer together.

[0005] A wafer bonding method for reducing overlay distortion includes forming a first plurality of bonded wafers using a plurality of process recipes, where the forming includes, for each respective one of the first plurality of bonded wafers, bonding the first wafer to a second wafer by pressing a backside of the first wafer with a striker, where each of the first plurality of bonded wafers is formed using a different one of the plurality of process recipes. The method includes measuring the overlay distortion for each of the first plurality of bonded wafers and, based thereon, determining a residual overlay distortion for each of the first plurality of bonded wafers. The method includes selecting one of the first plurality of bonded wafers having a lower value of residual overlay distortion. The method includes determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers. The method includes forming a second plurality of bonded wafers using the target process recipe.

[0006] An adaptive wafer bonding method for reducing overlay distortion includes forming a plurality of bonded wafers by performing cycles of bonding, each cycle including receiving a set of wafers to be bonded, the wafer set including a first wafer and a second wafer. Each cycle includes measuring the overlay distortion of a previously bonded wafer and, based thereon, determining a residual overlay distortion of the previously bonded wafer. Each cycle includes determining a process recipe based on the previous residual overlay distortion. Each cycle includes aligning the first wafer with the second wafer and positioning them so that they are separated by a bonding gap distance. Each cycle includes pressing the backside of the first wafer with a striker to bond the first wafer and the second wafer together to form a bonded wafer.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure, as claimed.

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1A] 1A-1C are schematic diagrams of cross-sectional views of the direct bonding method showing the initial alignment and separation distance of the top and bottom wafers to be bonded. [Figure 1B] FIG. 1C is a schematic diagram of a cross-sectional view of the direct bonding method showing the striker beginning to move the top wafer to be bonded towards the bottom wafer. [Figure 1C] FIG. 1 is a schematic diagram of a cross-sectional view of a direct bonding method showing a striker bringing the top and bottom wafers into direct contact and propagating the bonding front across the surfaces of the wafers. [Figure 1D] FIG. 1 is a schematic diagram of a cross-sectional view of the direct bonding method showing the combined wafers after pre-bonding processing at the room temperature step of the conventional direct bonding method. [Figure 2A] FIG. 1 is a schematic diagram of two wafers that have been patterned to allow overlay distortion to be measured by a scanner once the wafers are bonded. [Figure 2B] FIG. 1 is a schematic diagram of two wafers bonded using a direct bonding method with substantially no overlay distortion. [Figure 2C] FIG. 1 is a schematic diagram of two wafers bonded using a direct bonding method, where the overlap distortion present is a result of rotation of one of the wafers. [Figure 2D] FIG. 1 is a schematic diagram of two wafers bonded using a direct bonding method, where the overlay distortion present is the result of translational movement of one of the wafers. [Figure 2E] FIG. 1 is a schematic diagram of two wafers bonded using a direct bonding method, where the overlapping distortion present is the result of expansion of one of the wafers. [Figure 2F] FIG. 1 is a schematic diagram of two wafers bonded using a direct bonding method, where the overlap distortion present is the result of a combination of rotation, translation, and expansion of one wafer. [Figure 3A] FIG. 1 is a schematic diagram of a wafer holder that is a vacuum chuck with all of the chuck vacuum zones activated at the edge of the wafer in one embodiment. [Figure 3B] FIG. 1 is a schematic diagram of a wafer holder that is a vacuum chuck with only half of the edge vacuum zone activated in one embodiment. [Figure 4] 1 is a flowchart of a wafer bonding method for reducing overlay distortion, according to an embodiment. [Figure 5] 1 is a flow chart of a modified direct bonding method. [Figure 6] 1 is a flowchart of an adaptive wafer bonding method for reducing overlay distortion, according to an embodiment. [Figure 7] FIG. 1 is a system diagram of one embodiment of a wafer processing tool that implements the wafer bonding method of the present disclosure. [Figure 8] 1 shows a flow chart illustrating a method for direct wafer bonding. [Figure 9] 1 shows a flowchart illustrating a method for determining a target process recipe for direct wafer bonding to reduce residual overlay distortion. [Figure 10] 1 shows a flowchart illustrating a method for adaptively determining a target process recipe for direct wafer bonding. DETAILED DESCRIPTION OF THE INVENTION

[0010] Wafer bonding methods are used in a variety of semiconductor processing applications to manufacture semiconductor devices. Some examples of semiconductor processing applications that use wafer bonding methods include the fabrication of integrated circuits (ICs), the fabrication of microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS), and the stacking of many processing layers (3D integration) in microelectronics. There are many different wafer bonding methods, including direct bonding (also called fusion bonding), thermocompression bonding, and adhesive bonding.

[0011] Wafer-to-wafer bonding quality depends on the uniformity and integrity of the bond and maintaining wafer alignment across the wafer bonding interface. Overlay distortion, also known as misregistration, refers to the misplacement or misalignment of patterns and features between different surface layers during the wafer bonding process. Overlay distortion can lead to various problems, such as reduced device yield, degraded electrical performance, and increased fabrication costs. The minimum achievable overlay distortion generally depends on the fabrication hardware.

[0012] This disclosure describes a wafer bonding method. In various embodiments, the wafer bonding method generates an optimized direct bonding recipe for a direct bonding method. The direct bonding recipe minimizes overlay distortion by identifying and adapting bonding parameters. By systematically varying the bonding parameters of a best-known recipe, the wafer bonding method refines (or adjusts) the best-known recipe to generate a new wafer bonding process that minimizes wafer overlay distortion. As a result, overlay distortion is reduced, and semiconductor manufacturers do not need to purchase expensive new wafer processing tools to achieve similar results. Another result of reducing overlay distortion in bonded wafers is an increase in the yield of fabricated semiconductor devices.

[0013] This disclosure begins with a description of a wafer bonding process called direct bonding, followed by the bonding steps of the direct bonding process in FIGS. 1A-1D. Different examples of linear overlay distortion that can occur by bonding wafer pairs with a direct bonding method are shown using FIGS. 2A-2F. An exemplary wafer holder with various configurable chuck vacuum zones is then described using FIGS. 3A-3B. A flow chart of a linear calibration and adaptive version of the wafer bonding method is described using FIGS. 4 and 6. One embodiment of a wafer processing tool using direct bonding is described using FIG. 7.

[0014] Direct bonding (also called fusion bonding) is a wafer bonding method in which two surfaces of wafers are directly contacted and bonded without the use of any adhesive or any other intermediate layer. Direct bonding between two wafers is the result of chemical bonding between the two surfaces of the wafers. The chemical bond formed can be the result of van der Waals or covalent bonding. The direct bonding method includes the steps of wafer pre-processing, pre-bonding which involves aligning and positioning the wafers with each other, bonding, and annealing. For good bonding, the wafer surfaces must be sufficiently clean, flat, and smooth. Nevertheless, bonding defects can occur when wafers are bonded, which can cause device failures in later processing steps. Overlay distortion is one type of bonding defect.

[0015] 1A-1D show cross-sectional views of wafers 50 during a pre-bonding process. Wafer 50 includes an upper wafer 104 and a lower wafer 106 to be bonded together. As shown in FIGS. 1A-1D, wafer 50 is placed in a wafer bonding tool, which includes an upper wafer holder 102, a lower wafer holder 108, a gap 110 separating upper wafer 104 and lower wafer 106, a striker 100, and a bonding gap distance d (which initially separates upper wafer 104 from lower wafer 106 in FIG. 1A). Upper wafer 104 is held to upper wafer holder 102 by a pressure differential created by applying a vacuum between upper wafer 104 and upper wafer holder 102. Similarly, lower wafer 106 is held to lower wafer holder 108 by vacuum.

[0016] FIG. 1A shows the initial configuration of wafer 50 after loading, aligning and positioning top wafer 104 and bottom wafer 106 such that wafer 50 is separated by a bond gap distance d.

[0017] FIG. 1B shows the beginning of the process where the striker 100 is used to bring the top wafer 104 into direct contact with the bottom wafer 106 .

[0018] Once the wafers are properly aligned and separated by the bonding gap distance d, the striker 100 is applied to bring the wafers into direct contact. During this process, the upper wafer 104 is not fully released by the upper wafer holder 102, causing the upper wafer 104 to bow. A gap 110 begins to form between the upper wafer 104 and the lower wafer 106. In one embodiment, the gap 110 separating the wafers 50 may be air, or in a different embodiment, an inert gas such as argon or nitrogen. In one embodiment, the gap 110 separating the two wafers 50 may contain residual cleaning solution remaining from a pre-processing step. In one embodiment, the striker 100 is integrated with the lower wafer holder 108, and bonding is initiated by pressing the lower wafer 106 toward the upper wafer 104.

[0019] Following the process of pushing the upper wafer 104 with the striker 100, the upper wafer 104 comes into direct contact with the lower wafer 106 over a smaller area, as shown in FIG. 1C. After the upper wafer 104 contacts the lower wafer 106, a bonding front propagates across the surfaces of the upper wafer 104 and the lower wafer 106, starting from the contact area. As the bonding front propagates, the upper wafer 104 is released from the upper wafer holder 102 such that the entire surface of the upper wafer 104 contacts the entire surface of the lower wafer 106. Additionally, as the direct bonding front propagates across the surfaces, the gap 110 separating the wafers is pushed out from between the two wafers.

[0020] The bond formed between the top wafer 104 and the bottom wafer 106 is based on intermolecular interactions that may be the result of van der Waals forces, hydrogen bonding, or strong covalent bonds.

[0021] FIG. 1D shows the upper wafer 104 and the lower wafer 106 being bonded together to form a bonded wafer. The striker 100 brings the upper wafer 104 and the lower wafer 106 into contact, and the bond front propagates across their surfaces, so that the upper and lower wafers are no longer separated by a medium and form a bonded wafer. Typically, after forming the bonded wafers, the bonded wafers are exposed to high temperatures in an annealing process to help strengthen the bond between the two wafers. In some embodiments, only surface forces can hold the wafers together until annealing. After annealing, the direct bonding process is complete, and any overlay strain resulting from bonding the two wafers can no longer be relieved.

[0022] Overlay distortions arise from direct bonding methods in various ways, and they can be classified as either due to linear distortion or due to nonlinear distortion (called residual). Linear distortions can be classified into three distinct categories: translational distortion, rotational distortion, or dilational distortion. Linear distortions are generally easier to prevent and account for, unlike nonlinear distortions, which can be a significant portion of the distortion. Embodiments of the present application describe various techniques for reducing overlay distortions, especially those resulting from residual distortions.

[0023] Typically, the same best known recipe is used for all wafers, and therefore any wafer overlay distortion resulting from the direct bonding method remains unrelaxed and propagates to all wafers bonded using that recipe. By improving the direct bonding recipe, the wafer overlay distortion is reduced and the new recipe can be used for all future direct bonds performed by a particular wafer bonding tool.

[0024] Overlay distortion can be measured using a scanner to scan the patterned wafer. The scanner determines the overlay distortion by generating a distortion map using measurements of the deviations of the patterned wafer. An example of linear overlay distortion and what the overlay distortion looks like is shown in Figures 2A-2F.

[0025] 2A-2F show two patterned wafers and the various different types of linear overlay distortion that can occur after bonding.

[0026] Figure 2A is a schematic diagram of two wafers patterned to allow overlay distortion to be measured by a scanner once the wafers are bonded using a direct bonding method. The wafers in Figure 2A are not bonded. Figure 2A shows a first wafer 201 patterned with a left cross 202a and a right cross 202b, and a second wafer 203 patterned with a left square 204a and a right square 204b. Once the first wafer 201 and second wafer 203 are bonded together, the alignment of the patterns (202a-b and 204a-b) can be used to measure overlay distortion.

[0027] Figure 2B shows an exemplary bonded wafer with no overlay distortion. First wafer 201 is bonded to second wafer 203, with left cross 202a perfectly aligned with left square 204a and right cross 202b perfectly aligned with right square 204b. Figure 2B is an ideal scenario in which there are no observable overlay distortions in the bonded wafers.

[0028] 2C illustrates the case of rotational distortion between bonded wafers, which is a linear overlay distortion. Rotational distortion is a result of misalignment between the top and bottom chucks in a direct bonding tool and variations in wafer handling between the top and bottom wafers. In this embodiment, the centers of the first wafer 201 and the second wafer 203 are aligned, and there is a rotation that causes the left cross 202a to be misaligned with the left square 204a and the right cross 202b to be misaligned with the left square 204b. These factors cause the scanner to determine that the overlay distortion is the result of rotational distortion.

[0029] 2D illustrates the case of translational distortion between bonded wafers, which is a linear overlay distortion. Translational distortion is a result of differences in alignment between the upper and lower chucks in a direct bonding tool and variations in wafer handling between the upper and lower wafers. In this embodiment, the centers of the first wafer 201 and the second wafer 203 are not aligned. The distance from the center of the left cross 202a to the center of the left square 204a is also equidistant from the center of the right cross 202b to the center of the right square 204b. These factors cause the scanner to determine that the overlay distortion is the result of translational distortion.

[0030] FIG. 2E illustrates the case of expansion distortion between bonded wafers, which is a linear overlay distortion. The expansion distortion is the result of the wafers contracting or expanding during the direct bonding process. Additional expansion distortion can occur because each wafer has a different coefficient of thermal expansion (CTE), which causes the wafers to expand at different rates during the annealing process. In this embodiment, the centers of the first wafer 201 and the second wafer 203 are aligned. The outer edges of the two wafers are not aligned. The distance from the center of the left cross 202a to the center of the left square 204a is also equidistant from the center of the right cross 202b to the center of the right square 204b, but each is equidistant toward the center of the wafer. These factors cause the scanner to determine that the overlay distortion is the result of expansion distortion.

[0031] Figure 2F shows the case where all linear forms of overlap distortion are present. The resulting bonded wafer in Figure 2F is a combination of rotational, translational, and dilational distortions. The second wafer 203 is dilated, as evidenced by the misalignment of the outer edges of the two wafers. The second wafer 203 is translated, as evidenced by the misalignment of the centers of the wafers. The second wafer 203 is rotated, as evidenced by the left square 204a being approximately the same height as the left cross 202a, while the right square 204b is below the right cross 202b.

[0032] Overlay distortions present in bonded wafers that are not accounted for by the linear overlay distortions shown in Figures 2A-2F are nonlinear overlay distortions. Nonlinear overlay distortions are also referred to as residuals. The wafer bonding method of the present disclosure reduces the residuals of direct bonding methods. Residual reduction is achieved by identifying and modifying specific bonding parameters in the direct bonding recipe.

[0033] FIGS. 3A-3B illustrate a vacuum chuck that can be used as the upper and lower wafer holders in one embodiment. The vacuum chuck holds the wafer by using a vacuum to pump air out of a cavity located behind the vacuum chuck, allowing the air pressure to hold the wafer in place. The cavities in the vacuum chuck are called vacuum zones, such as the upper wafer holder vacuum zone, and different zones can be configured to be active or inactive. FIGS. 3A-3B illustrate two of the bonding parameters that can be varied to minimize residuals in the direct bonding method. In one embodiment, the vacuum zones shown in FIGS. 3A-3B are only one possible zone configuration. In one embodiment, the vacuum zone configuration can include multiple rings of vacuum from the center to the edge of the vacuum chuck (FIG. 3B shows only two), and these rings can be further subdivided (e.g., the subdivided outer ring shown in FIG. 3B) depending on how fine the vacuum control is desired.

[0034] Referring to FIG. 3A, the vacuum chuck 301 can be either the lower wafer holder 108 or the upper wafer holder 102 of FIG. 1. One of the variable bonding parameters in the direct bonding method embodiment is the configuration of the vacuum zones of the vacuum chuck. The vacuum zones can be activated or deactivated. When a vacuum zone is activated, a vacuum is applied between the wafer and the chuck to attract the wafer to the chuck. One or both of the wafers, i.e., the upper wafer holder 102 and the lower wafer holder 108, can include configurable vacuum zones. FIG. 3A shows all of the vacuum zones at the edge of the vacuum chuck 301 in an activated state 300, which is referred to as the full-edge configuration.

[0035] Referring to FIG. 3B, vacuum chuck 301 can be either lower wafer holder 108 or upper wafer holder 102 of FIG. 1. In FIG. 3B, only half of the vacuum zones are in an activated state 300, while the other vacuum zones are in an inactivated state 303. This use case may be referred to as an edge-diagonal configuration. The same vacuum chuck can be operated in a full-edge configuration or an edge-diagonal configuration. In various embodiments, the percentage of the inactivated zone may be used as a bonding parameter. In FIG. 3B, this percentage is approximately 50%, but in other embodiments, this percentage may be designed to vary from 0% to 80%, as an example.

[0036] FIG. 4 is a flowchart of an adjusted wafer bonding method for reducing overlay distortion, according to one embodiment of the present application.

[0037] The method begins in box 402 where two wafers are bonded using a baseline recipe for a direct bonding method for bonding two wafers. In one embodiment, the bonding method used in box 402 is the wafer bonding method described in more detail using the flowchart in FIG.

[0038] 5 is a flowchart of the initial direct bonding method, which may represent all of the steps occurring in box 402 of FIG.

[0039] In box 502, wafers are pretreated to clean, planarize, smooth, and activate their surfaces. Wafer pretreatment can be performed to improve the expected bond strength between two wafers intended to be bonded. The wafers are planarized and smoothed to increase the expected bonding surface area and ensure that there are no large gaps between the two wafers where contaminants can become trapped. Once the wafers are sufficiently smooth and flat, they begin to bond immediately upon making atomic contact. The wafers can be cleaned to ensure that the two wafers are free of impurities that could cause particle, organic, or ionic contamination. Cleaning can be achieved by various processes, such as plasma treatment, UV / ozone cleaning, or wet chemical cleaning procedures. Surface activation can adjust the surface energy and friction along the bonding interface and alter strain during the bonding process. The activation process (or surface activation) is a separate step that involves bombarding the wafer surfaces with plasma to modify the surfaces. This modification creates active sites that terminate with dangling bonds. Active sites are where bonding occurs, and increasing the number of bonding sites improves the bonding energy. The amount and uniformity of bonding sites also affect the propagation speed and subsequent strain.

[0040] After the wafer is pre-processed to produce a pre-processed wafer (cleaned, planarized, smoothed, and surface activated), the direct bonding method proceeds to box 504. In box 504, three of the variable bonding parameters are configured according to the bonding recipe to be used to bond the wafers. The three bonding parameters configured in box 504 include chuck vacuum pressure, upper chuck vacuum zone, and lower chuck vacuum zone.

[0041] Chuck vacuum pressure is the strength of the vacuum used by the vacuum chuck to hold the preprocessed wafer. The upper chuck vacuum zone and the lower chuck vacuum zone are variable vacuum cavities of the vacuum chuck that can be configured to be either active or inactive. The configuration in which the chuck vacuum zones are active corresponds to the amount of surface area of ​​the preprocessed wafer that is under vacuum. For example, the chuck vacuum zone configuration shown in FIG. 3B (i.e., the edge-diagonal configuration) corresponds to approximately 50% of the surface area of ​​the edge of the preprocessed wafer being under vacuum.

[0042] After setting the vacuum chuck bonding parameters, the direct bonding method continues in box 506. In box 506, the preprocessed wafers (preprocessed upper wafer and preprocessed lower wafer) are placed in wafer holders within a processing chamber of a wafer processing tool. In one embodiment, the preprocessed upper wafer is placed in the upper wafer holder, which is a vacuum chuck, such as the vacuum chuck shown in FIGS. 3A-3B. In one embodiment, the preprocessed lower wafer is placed in the lower wafer holder, which is a vacuum chuck, such as the vacuum chuck shown in FIGS. 3A-3B. The preprocessed upper wafer is positioned such that the side to be bonded to the preprocessed lower wafer faces downward toward the preprocessed lower wafer. In other words, the backside of the preprocessed upper wafer is the side that contacts the upper wafer holder (upper vacuum chuck). The preprocessed lower wafer is positioned such that the side to be bonded to the preprocessed upper wafer faces upward toward the preprocessed upper wafer. In other words, the backside of the pre-processed lower wafer is the side that contacts the lower wafer holder (lower vacuum chuck).

[0043] After placing the preprocessed wafers in their corresponding wafer holders and configuring the chuck vacuum pressure, upper chuck vacuum zone, and lower chuck vacuum zone, the direct bonding method continues to box 508. In box 508, another bonding parameter is configured according to the bonding recipe being used in the direct bonding method. The bonding parameter configured in box 508 is the bond gap distance, which is the separation distance between the preprocessed upper wafer and the preprocessed lower wafer. The bond gap distance is shown in FIG. 1A as distance d. Once the bond gap distance d is configured, the preprocessed wafer is moved to the separation distance specified by the bonding recipe.

[0044] Once the preprocessed wafers have been moved to a separation distance close to the bond gap distance specified by the bonding recipe in box 508, the direct bonding method proceeds to box 510. In box 510, the two preprocessed wafers are aligned to sub-micron accuracy using alignment measurements performed by an optical device, such as an infrared scanner. This may be achieved by moving the chucks relative to each other until an alignment sensing algorithm determines that the two preprocessed wafers are aligned within sub-micron accuracy. This alignment process is a step related to reducing linear overlay distortion. If the two preprocessed wafers are not properly aligned before bonding, linear overlay distortion will be the most significant contributor to the resulting overlay distortion in the bonded wafers.

[0045] After the preprocessed wafers are aligned in box 510, the direct bonding method can proceed to box 512. In box 512, another variable bonding parameter, namely, striker pressure, is configured according to the bonding recipe being used. The striker pressure is the pressure that the striker will apply to form direct (atomic) contact between the top preprocessed wafer and the bottom preprocessed wafer. Once the striker pressure is configured, the striker advances to make direct contact at a single point between the top preprocessed wafer and the bottom preprocessed wafer. In one embodiment, the striker presses downward from behind the center of the preprocessed top wafer, pushing the center of the preprocessed top wafer down into direct contact with the preprocessed bottom wafer. In one embodiment, the striker presses downward from behind the edge of the preprocessed top wafer, pushing the edge of the preprocessed top wafer down into direct contact with the edge of the preprocessed bottom wafer. In other embodiments, the preprocessed bottom wafer is pressed upward by the striker onto the preprocessed top wafer.

[0046] Starting the bonding process can be referred to as initiation. Once the wafers are in direct contact, a bond front propagates across the contact surfaces of the two wafers. In box 513, as the vacuum zone propagates across the surfaces, it is reduced / released in line with the bond front, bonding the two wafers together. The bond front is a wave that pushes any medium that may be present between the two wafers out from between them, allowing a bond to form across the entire contact surface between the two wafers. Direct bonding between the surfaces of the pre-treated wafers is based on intermolecular interactions, including van der Waals forces, hydrogen bonding, and strong covalent bonds.

[0047] Once the wafers have undergone initiation and the bond front has sufficiently propagated across the entire contact surface between the two wafers, the direct bonding method proceeds to box 514. In box 514, the bonded wafers are annealed to strengthen the bond formed between the top and bottom wafers. The annealing is accomplished by exposing the bonded wafers to a high-temperature bake (e.g., several hundred degrees Celsius). Exposing the bonded wafers to a high-temperature anneal introduces thermal energy into the system, which not only causes more hydrogen bonds to form, but also increases the contact surface area, promoting the diffusion of trapped hydrogen molecules along the interface, and interfacial voids may reduce in size or disappear entirely. This may also lead to hydrogen bond condensation, covalent bond formation, and an increase in the contact surface area between the wafers, promoting the diffusion of trapped species into the bulk material. All of these increase the bond strength between the now-annealed wafers. In some embodiments where copper electrical contacts are present at the bond interface, a metallurgical bond may form during the annealing step, forming an electrical connection across the bond interface.

[0048] After annealing in box 514, an annealed wafer is produced, which can be inspected to determine any overlay distortion present. In one embodiment, the overlay distortion is measured using various techniques (e.g., infrared scanning) after the annealing process of the direct bonding method. In other embodiments, the overlay distortion is measured before annealing the bonded wafers, which allows for inspection of the overlay distortion resulting from the room temperature bonding step of the direct bonding method. Note that the wafer bonding method of the present disclosure is applicable regardless of whether the overlay distortion is measured before or after annealing the bonded wafers.

[0049] The direct bonding method of FIG. 4 can utilize an optimized (residual minimized) direct bonding recipe (or target process recipe) determined by using the wafer bonding method described by the subsequent steps of the flowchart of FIG. 5.

[0050] Referring again to FIG. 4 , after bonding two wafers to create a bonded wafer in box 402, the method proceeds to box 404. In box 404, overlay distortions of the bonded wafers are measured to determine residuals for the bonded wafers. Determining residuals for the bonded wafers involves inspecting the bonded wafers using a measurement device. As previously mentioned, residuals are overlay distortions resulting from nonlinear distortions. When linear distortions are accounted for by the measurement device, residual distortions are assumed to be the result of nonlinear origins, quantified, and labeled residuals. Residuals are typically quoted as a certain number of standard deviations from alignment. For example, a bonded wafer is measured and found to have residuals for a particular direct bonding recipe with a 3-standard deviation of X of 41.72 nm and a 3-standard deviation of Y of 55.16 nm. In this example, the residuals mean that 99.73% of the bonded wafers produced using the corresponding direct bonding recipe are within 41.72 nm in X and 55.16 nm in Y of no nonlinear distortion (or perfectly aligned bonded wafers).

[0051] Once the residuals for the bonded wafers produced using the first best known recipe have been determined in box 404, the wafer bonding method proceeds to box 406. In box 406, a new set of wafers is bonded using a new direct bonding recipe. The new direct bonding recipe is the same as the best known recipe except for a single bonding parameter that is changed. For example, instead of using a bond gap distance of 60 μm, the new recipe uses a bond gap distance of 40 μm. The determined residuals and bonding parameters for the best known recipe are stored for use by the optimization algorithm.

[0052] Bonding parameters that can be varied in the disclosed wafer bonding method include bond gap distance, striker pressure (which can be varied over time), chuck vacuum pressure, upper chuck vacuum zone, lower chuck vacuum zone, and timing (adjustment) of the release of the chuck vacuum zone, which corresponds to the movement of the bond front during bonding of the two wafers. The bond gap distance is the separation distance from the lower wafer to the upper wafer before the wafers are pressed together using the striker. Configurable values ​​for the bond gap distance typically range from 5 μm to 1000 μm. The striker pressure is the pressure used by the striker to press the upper wafer into the lower wafer (or vice versa) at a single point to initiate the bond front that bonds the two wafers together. Configurable values ​​for the striker pressure typically range from 0 kPa to 100 kPa, and the striker pressure can also be varied over time (taking on different values ​​over time). In an exemplary embodiment, the value of the striker pressure can be reduced after initial contact. Chuck vacuum pressure is the vacuum pressure that holds the wafer to be bonded to the vacuum chuck. Chuck vacuum pressure is the difference from atmospheric pressure; therefore, the configurable values ​​for chuck vacuum pressure typically vary from 0 kPa to -100 kPa. The upper and lower chuck vacuum zones correspond to whether or not the configuration of vacuum cavities behind the vacuum chuck is activated. As mentioned above, there can be different rings of chuck vacuum zones (not just the outer rings) subdivided from the center to the edge of the vacuum chuck, all of which are configurable in some embodiments. Different configurations of vacuum chuck zones are referred to as full edge, edge-diagonal only, or full, or additional configurations incorporating different settings for various rings of chuck vacuum zones (not just the outer rings). In the full edge configuration, all of the vacuum cavities at the edge of the vacuum chuck are activated, which corresponds to 100% edge coverage (as shown in FIG. 3A). In the edge diagonal only configuration, only 30-50% of the vacuum cavities at the edge of the vacuum chuck are activated (this is shown in Figure 3B).The full configuration corresponds to all vacuum cavities of the vacuum chuck being activated, which corresponds to 100% coverage of the entire surface area (not just the edge) of a wafer loaded into the vacuum chuck. The timing of the release of the chuck vacuum zones during the bonding process is also configurable, which corresponds to releasing the vacuum zones as the bond front propagates across the surface of the wafer.

[0053] After the new bonded wafer is created using the new bonding recipe with the single modified bonding parameter in box 406, the wafer bonding method proceeds to box 408. In box 408, the residuals of the new bonded wafer created in box 406 are measured. Determining the residuals may involve the same methods as described in box 404 and will not be repeated here for brevity. The determined residuals and bonding parameters of the new bonding recipe are stored for use by the optimization algorithm.

[0054] Once the residuals for the new bonded wafers have been determined, the wafer bonding method proceeds to box 410, where there are two possible outcomes. In box 410, the wafer bonding method checks whether a set of bonded wafers has been produced using the new recipe, each with a change in one of the bonding parameters. There are two possibilities in box 410: "Yes" or "No."

[0055] If bonded wafers have not been produced using a recipe in which a single bonding parameter of the bonding parameters has been changed for all bonding parameters (i.e., "No"), the wafer bonding method returns to box 406 to produce a new bonded wafer using a new direct bonding recipe in which a single bonding parameter of the best known method that was not changed by the previous recipe has been changed. After producing the new bonded wafer, the adjustable wafer bonding method proceeds to box 408, where residuals are determined for the new bonded wafer and stored with the bonding parameters for use by the optimization algorithm. The wafer bonding method then proceeds to box 410, where a check is made again.

[0056] If bonded wafers have been generated using a recipe in which a single bonding parameter among the bonding parameters has been changed (i.e., "Yes"), the wafer bonding method proceeds to box 412. In box 412, an optimization algorithm is employed to determine which change in the bonding parameters minimizes the residuals using the residuals of the previous recipe and the bonding parameters corresponding to the stored residuals. In other words, the bonding parameters can be configured to minimize the residuals. Configuring the bonding parameters can include setting minimum and maximum values ​​for each bonding parameter. In one embodiment, the bond gap distance d is designed to be between 30 μm and 75 μm. In one embodiment, the bond gap distance d is designed to be between 50 μm and 75 μm. In one embodiment, the bond gap distance d is designed to be between 30 μm and 50 μm. In one embodiment, the bond gap distance d is designed to be less than 50 μm. In one embodiment, the upper vacuum conditions are designed to include a vacuum surface area on the backside of the upper wafer of less than 50%, for example, as low as 0.5% in one embodiment, and a vacuum level of 0 kPa to -100 kPa. In one embodiment, the upper vacuum conditions are designed to include a vacuum surface area on the backside of the upper wafer of 30% to 50%. In one embodiment, the lower vacuum conditions are designed to be less than -25 kPa. In one embodiment, the striker pressure condition is designed to be 10 kPa to 25 kPa. In one embodiment, the lower vacuum conditions are designed to include a second vacuum surface area on the backside of the lower wafer of greater than 80% and a vacuum level on the lower wafer of 0 kPa to -100 kPa. In various embodiments, the ratio of the actuated zone to the non-actuated zone can be used as a bonding parameter. In FIG. 3B, this ratio is approximately 50%, but in other embodiments, this ratio can be designed to vary from 0% to 100% or 20% to 80%, for example.

[0057] The optimization algorithm can be a linear programming algorithm, a genetic algorithm, a random forest algorithm, a regression algorithm, or other technique. Once the optimization algorithm determines the set of bonding parameters that minimizes the residuals in the bonded wafers, the set of bonding parameters is returned as the target (tuned or calibrated) direct bonding recipe.

[0058] After determining the adjusted direct bonding recipe in box 412, the wafer bonding method proceeds to box 414, where the target direct bonding recipe can be used by a wafer processing tool to produce future bonded wafers with minimized residuals. Note that the wafer bonding method is applicable to any wafer processing tool that bonds wafers using a striker-based direct bonding method. As a result, the wafer bonding method can optimize a bonding recipe used in an existing wafer processing tool to minimize residuals in the bonded wafers.

[0059] The example wafer bonding method of FIG. 4 can be described as a linearly calibrated, adjusted wafer bonding method, in which an adjusted wafer bonding recipe is determined, which is then used for future wafer fabrication. In other words, the direct bonding recipe of the wafer processing tool is calibrated to minimize residuals. In one embodiment, the wafer bonding method can be adaptively calibrated, in which the direct bonding recipe of the wafer processing tool is calibrated and improved each time a bonded wafer is fabricated. The adaptively adjusted wafer bonding method is shown in FIG. 6.

[0060] 6 is a flowchart of an adaptively adjusted wafer bonding method for reducing overlay distortion. The adaptively adjusted wafer bonding method starts with a preprocessed wafer pair (top wafer 104 and bottom wafer 106). The preprocessed wafers are placed inside a wafer processing tool 606, which will first bond the preprocessed top wafer 602 and the preprocessed bottom wafer 106 together using a direct bonding method (such as the direct bonding method shown in FIG. 5) using the best known direct bonding recipe.

[0061] Wafer processing tool 606 produces bonded wafers 608. Bonded wafers 608 are then scanned using scanner 610 to measure overlay distortion. Scanner 610 can be any type of scanner capable of measuring overlay distortion, such as an infrared scanner. This can be accomplished by using scanner 610 to generate a distortion map that can be used by an optimization algorithm.

[0062] After the bonded wafer 608 is scanned with scanner 610, residuals are determined using the measured overlay distortions from scanner 610. In box 612, the residuals are determined and then used to refine the wafer bonding recipe to minimize the residuals (box 614).

[0063] An improved wafer bonding recipe is determined using an optimization algorithm, which may be a linear programming algorithm, a genetic algorithm, a random forest algorithm, a regression algorithm, or other technique. In box 614, the improved (or adjusted) wafer bonding recipe is determined and then communicated to the wafer processing tool 606 to be used as the direct bonding recipe for the next bonded wafer produced using the direct bonding method.

[0064] Returning now to the wafer processing tool 606, the wafer processing tool 606 uses the wafer bonding recipe to create a new bonded wafer 608. The new bonded wafer 608 is then scanned by a scanner 610 to determine the bonded wafer residuals at 612, and an optimization algorithm will again refine the direct wafer bonding recipe at 614. Thus, the wafer bonding method shown in FIG. 6 is an adaptively adjusted wafer bonding method that generates an adjusted wafer bonding recipe for each new bonded wafer or group of wafers created.

[0065] A system diagram of a wafer processing tool 606 that can be used to implement either the linear calibration or adaptively adjusted wafer bonding methods of FIGS. 4 and 6 is shown in FIG.

[0066] 7 is a system diagram of a wafer processing tool 606 in which the adjustable wafer bonding method of the present disclosure can be implemented to bond pre-processed wafers. The wafer processing tool 606 includes a process chamber 700 having a striker 100, an upper wafer holder 102, an upper wafer holder vacuum zone 706, a lower wafer holder 108, and a lower wafer holder vacuum zone 708. The process chamber 700 is connected to a processor 712 and a memory 714.

[0067] The process chamber 700 is where the direct bonding method is used to bond a set of pre-processed wafers. The process chamber 700 provides a controlled environment, including temperature, atmospheric pressure, gas inlets and outlets, etc. In one embodiment, the process chamber 700 contains all of the elements necessary to perform the bonding of the pre-processed wafers, including the striker 100, the upper wafer holder 102 and upper wafer holder vacuum zone 706, and the lower wafer holder 108 and lower wafer holder vacuum zone 708.

[0068] Striker 100 is a tool used to establish physical contact between two preprocessed wafers by applying a configurable amount of pressure, referred to as striker pressure. In one embodiment, striker 100 is placed within upper wafer holder 102 and pressed down through upper wafer holder 102, applying pressure to the preprocessed upper wafer and forcing it down into direct contact with the preprocessed lower wafer. In one embodiment, striker 100 is placed within lower wafer holder 108 and pressed upward through lower wafer holder 108, applying pressure to the preprocessed lower wafer and forcing it up into direct contact with the preprocessed upper wafer.

[0069] The upper wafer holder 102 is a device for holding a wafer during the bonding process of the wafer-processing tool 606. In one embodiment, the upper wafer holder 102 may include a chuck, such as the vacuum chuck discussed in FIGS. 3A-3B. The vacuum chuck holds the wafer by using a vacuum to pump air out of a cavity located behind the vacuum chuck, allowing the air pressure to hold the wafer in place. The cavities in the vacuum chuck are referred to as vacuum zones, such as the upper wafer holder vacuum zone 706, and different zones may be configured to be activated or deactivated. In one embodiment, the upper wafer vacuum zone may be configured with all zones turned on, for example, as in FIG. 3A. In another embodiment, the upper wafer vacuum zone 710 may be configured with only half of the edge chuck vacuum zones activated and the other half deactivated, as in FIG. 3B.

[0070] The lower wafer holder 108 is a device for holding a wafer during the bonding process of the wafer-processing tool 606. In one embodiment, the lower wafer holder 108 can be a vacuum chuck. A vacuum chuck holds a wafer by using a vacuum to pump air out of a cavity located behind the vacuum chuck, allowing the air pressure to hold the wafer in place. The cavities in the vacuum chuck are called vacuum zones, such as the lower wafer holder vacuum zone 708, and different zones can be configured to be activated or deactivated. In one embodiment, the lower wafer vacuum zone can be configured with all zones turned on, for example, as in FIG. 3A. In another embodiment, the lower wafer holder vacuum zone 708 can be configured with only half of the chuck vacuum zones activated and the other half deactivated, as in FIG. 3B.

[0071] The processor 712 may be any device capable of executing instructions stored in memory 714 to bond wafers in the wafer-processing tool 606. The processor 712 is capable of performing the wafer bonding method of the present disclosure to adjust the wafer bonding recipe used by the wafer-processing tool 606. The processor 712 provides the processing conditions (bonding parameters) of the wafer bonding recipe to the processing chamber 700. The processor 712 also implements an optimization algorithm to adjust the wafer bonding recipe to minimize the residuals by using the residuals and bonding parameters of the set of recipes stored in memory 714. The processor 712 may be a single processor with multiple cores or may be multiple processors including the cores of a distributed computing system.

[0072] The memory 714 may be any device capable of storing instructions executed by the processor 712 and storing overlay distortion measurements (such as determined residuals and bonding parameters used in a particular direct bonding recipe) used in an optimization algorithm to determine an adjusted direct bonding recipe. The memory 714 may also store adjusted wafer bonding method instructions executed by the processor 712. The memory 714 may also be used to store distortion maps generated by the scanner. The memory 714 may include both non-volatile and volatile memory. Some of the instructions may be stored in different portions of the memory, which may be stored in different systems.

[0073] By implementing the wafer bonding method of the present disclosure in a wafer processing tool 606 (as shown in FIG. 7), a tailored wafer bonding recipe is determined that minimizes the residuals. By minimizing the residual overlay distortion, semiconductor manufacturers can increase device yield without increasing fabrication costs.

[0074] FIG. 8 shows a flow chart illustrating an embodiment of the present disclosure.

[0075] In one embodiment, the method includes determining upper vacuum conditions, lower vacuum conditions, a bond gap distance, and a striker pressure condition based on measurements of residual strain from previously bonded wafers (box 802). The method further includes applying upper vacuum conditions to the upper wafer using an upper wafer holder, the upper vacuum condition being applied to a backside of the upper wafer, and the upper wafer having a front side opposite the backside (box 804). The method further includes applying lower vacuum conditions to the lower wafer using a lower wafer holder, the lower vacuum condition being applied to a backside of the lower wafer, and the lower wafer having a front side opposite the backside (box 806). The method further includes positioning the front side of the upper wafer over the front side of the lower wafer to create a bond gap distance between the upper and lower wafers (box 808). The method also further includes using striker pressure conditions to press the backside of the upper wafer with a striker to bond the front side of the upper wafer and the front side of the lower wafer together (box 810).

[0076] The various boxes described above may be implemented as further described using Figures 4 and 5. For example, in one embodiment, box 810 may be implemented as box 402 in Figure 4. As another example, in one embodiment, box 808 may be implemented as box 508 in Figure 5.

[0077] FIG. 9 shows a flow chart illustrating an embodiment of the present disclosure.

[0078] In one embodiment, the method includes forming a first plurality of bonded wafers using a plurality of process recipes (box 902). The forming includes, for each one of the first plurality of bonded wafers, bonding the first wafer to a second wafer by pressing a backside of the first wafer with a striker, wherein each of the first plurality of bonded wafers is formed using a different one of the plurality of process recipes (box 904). The method further includes measuring an overlay distortion for each of the first plurality of bonded wafers and, based thereon, determining a residual overlay distortion for each of the first plurality of bonded wafers (box 906). The method further includes selecting one of the first plurality of bonded wafers having a lower value of residual overlay distortion (box 908). The method further includes determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers (box 910). The method further includes forming a second plurality of bonded wafers using the target process recipe (box 912).

[0079] The various boxes described above may be implemented as further described using Figure 4. For example, in one embodiment, box 904 may be implemented as box 406 in Figure 4.

[0080] FIG. 10 shows a flow chart illustrating an embodiment of the present disclosure.

[0081] In one embodiment, the method includes forming a plurality of bonded wafers by performing cycles of bonding (box 1002). Each cycle includes receiving a set of wafers to be bonded, the wafer set including a first wafer and a second wafer (box 1004). Each cycle further includes measuring an overlay distortion of a previously bonded wafer and, based thereon, determining a residual overlay distortion of the previously bonded wafer (box 1006). Each cycle further includes determining a process recipe based on the previous residual overlay distortion (box 1008). Each cycle further includes aligning a first wafer with a second wafer and positioning them so that they are separated by a bonding gap distance (box 1010). Each cycle further includes pressing a striker against the backside of the first wafer to bond the first wafer and the second wafer together to form a bonded wafer (box 1012).

[0082] The various boxes described above may be implemented as further described using Figure 6. For example, in one embodiment, box 1008 may be implemented as box 614 in Figure 6.

[0083] Illustrative embodiments of the present invention are now described below, although other embodiments may be understood from the entire specification and claims of this application.

[0084] Example 1. A method includes determining top vacuum conditions, bottom vacuum conditions, a bond gap distance, and a striker pressure condition based on measurements of residual strain from previously bonded wafers. The method includes applying top vacuum conditions to a top wafer using an top wafer holder, the top vacuum condition being applied to a backside of the top wafer, and the top wafer having a front side opposite the backside. The method includes applying bottom vacuum conditions to a bottom wafer using a bottom wafer holder, the bottom vacuum condition being applied to a backside of the bottom wafer, and the bottom wafer having a front side opposite the backside. The method includes positioning the front side of the top wafer over the front side of the bottom wafer to create a bond gap distance between the top and bottom wafers. The method also includes using a striker pressure condition to press the backside of the top wafer with a striker to bond the front side of the top wafer and the front side of the bottom wafer together.

[0085] Example 2. The wafer bonding method of Example 1, wherein applying the upper vacuum condition includes applying a vacuum to a first vacuum surface area at a first vacuum level, the first vacuum surface area being 0.1% to 5% of the total area of ​​the backside of the upper wafer, and the first vacuum level being 0 kPa to -100 kPa. The wafer bonding method of Example 1, wherein applying the lower vacuum condition includes applying a vacuum to a second vacuum surface area at a second vacuum level, the second vacuum surface area being 80% to 100% of the total area of ​​the backside of the lower wafer, and the second vacuum level being 0 kPa to -100 kPa. The wafer bonding method of Example 1, wherein the striker pressure condition is 10 kPa to 25 kPa. The wafer bonding method of Example 1, wherein the bonding gap distance is 30 μm to 75 μm.

[0086] Example 3. The wafer bonding method according to one of Examples 1 or 2, wherein the bonding gap distance is between 50 μm and 75 μm, or the bonding gap distance is between 30 μm and 50 μm, or the bonding gap distance is less than 50 μm.

[0087] Example 4. The wafer bonding method according to one of Examples 1-3, wherein the bottom vacuum condition is less than -25 kPa.

[0088] Example 5. A wafer bonding method according to one of Examples 1-4, wherein the top vacuum condition comprises a first vacuum surface area that is less than 50% of the total area of ​​the backside of the top wafer.

[0089] Example 6. The wafer bonding method of one of Examples 1-5, further comprising an annealing process to strengthen the bonding of the upper and lower wafers, the annealing process comprising exposing the bonded upper and lower wafers to a temperature greater than 100°C.

[0090] Example 7. A method includes forming a first plurality of bonded wafers using a plurality of process recipes, where the forming includes, for each one of the first plurality of bonded wafers, bonding the first wafer to a second wafer by pressing a backside of the first wafer with a striker, where each of the first plurality of bonded wafers is formed using a different one of the plurality of process recipes. The method includes measuring an overlay distortion for each of the first plurality of bonded wafers and, based thereon, determining a residual overlay distortion for each of the first plurality of bonded wafers. The method includes selecting one of the first plurality of bonded wafers having a lower value of residual overlay distortion. The method includes determining a target process recipe associated with forming the selected one of the first plurality of bonded wafers. The method includes forming a second plurality of bonded wafers using the target process recipe.

[0091] Example 8. The method of example 7, wherein each one of the plurality of process recipes differs from another one of the plurality of process recipes in only one bonding parameter.

[0092] Example 9. The method of Example 7 or 8, further comprising applying a first vacuum condition to a first wafer using an upper wafer holder, the first vacuum condition being applied to a backside of the first wafer, and the first wafer having a front side opposite the backside. The method further comprises applying a second vacuum condition to a second wafer using a second wafer holder, the second vacuum condition being applied to a backside of the second wafer, and the second wafer having a front side opposite the backside. The method further comprises disposing the front side of the second wafer over the front side of the second wafer to create a bonding gap distance between the first wafer and the second wafer, and the pressing is performed at a striker pressure condition to bond the first wafer to the second wafer.

[0093] Example 10. The method of one of Examples 7-9, wherein each of the plurality of process recipes includes a first vacuum condition, a second vacuum condition, a bond gap distance, and a striker pressure condition.

[0094] Example 11. The method of one of Examples 7-10, wherein applying the first vacuum condition includes having a plurality of chuck vacuum zones each having a vacuum level and activating a subset of the chuck vacuum zones around the first wafer during formation.

[0095] Example 12. The method of any one of Examples 7-11, wherein applying the first vacuum condition includes having a plurality of chuck vacuum zones, and the vacuum levels of adjacent ones of the chuck vacuum zones are different during formation.

[0096] Example 13. The method of any one of Examples 7-12, including receiving a target process recipe at a process controller and activating a plurality of chuck vacuum zones in the first wafer holder and the second wafer holder based on the target process recipe.

[0097] Example 14. The method of any one of Examples 7-13, including receiving a target process recipe at a process controller and modifying a striker pressure condition of the striker based on the target process recipe.

[0098] Example 15. The method of any one of Examples 7-14 for tuned wafer bonding, further comprising annealing the bonded wafers, wherein the measurement of overlay distortion is performed after annealing.

[0099] Example 16. A method includes forming a plurality of bonded wafers by performing cycles of bonding, each cycle including receiving a set of wafers to be bonded, the wafer set including a first wafer and a second wafer. Each cycle includes measuring an overlay distortion of a previously bonded wafer and, based thereon, determining a residual overlay distortion of the previously bonded wafer. Each cycle includes determining a process recipe based on the previous residual overlay distortion. Each cycle includes aligning a first wafer with a second wafer and positioning them so that they are separated by a bonding gap distance. Each cycle includes pressing a striker against the backside of the first wafer to bond the first wafer and the second wafer together to form a bonded wafer.

[0100] Example 17. The method of example 16, wherein the pressing includes pressing a central portion of the first wafer.

[0101] Example 18. The method of example 16 or 17, wherein the pressing includes pressing a peripheral region of the first wafer.

[0102] Example 19. The method of any one of Examples 16-18, wherein measuring includes scanning the bonded wafers with an infrared scanner and generating a distortion map.

[0103] Example 20. The method of any one of Examples 16-19, wherein determining the process recipe includes having a distortion model of the bonded wafers, generating a residual distortion map from the distortion map, and selecting a new process recipe to minimize the residual distortion based on the distortion model, the process recipe, and the residual distortion map, wherein the process recipe includes a value for the bonding gap distance and a pressure at which the striker presses the first wafer.

[0104] Example 21. The method of any one of Examples 16-20, further comprising applying a first vacuum condition to a first wafer using a first wafer holder, the first vacuum condition being applied to a backside of the first wafer, and the first wafer having a front side opposite the backside. The method further comprises applying a second vacuum condition to a second wafer using a second wafer holder, the second vacuum condition being applied to a backside of the second wafer, and the second wafer having a front side opposite the backside, and the process recipe comprises the first vacuum condition and the second vacuum condition.

[0105] Example 22. The method of any one of Examples 16-21, wherein each cycle further comprises annealing the bonded wafers.

[0106] Example 23. The method of any one of Examples 16-22, wherein the annealing is performed at a temperature greater than 150°C.

[0107] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this specification. It is therefore intended that the appended claims cover any such modifications or embodiments.

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