3D Memory Cells, Array Architectures and Processes

Abstract

Various 3D memory cell, array architectures and processes are disclosed. In embodiments, a memory cell structure is provided formed by a process that includes depositing multiple alternating semiconductor and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers through the bit line holes using an isotropic doping process, depositing a conductive material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing a gate material on the gate dielectric layer.

Description

[Technical Field]

[0001] Priority claims This application is a continuation-in-part (CIP) of U.S. patent application Ser. No. 17 / 937,432, filed Sep. 30, 2022, entitled "3D Memory Cells and Array Architectures."

[0002] This application is a U.S. provisional patent application, serial number 63 / 398,807, filed August 17, 2022, entitled "Memory Cell and Array Architectures and Operation Conditions," U.S. provisional patent application, serial number 63 / 406,255, filed September 14, 2022, entitled "3D Cell and Array Structures," U.S. provisional patent application, serial number 63 / 413,493, filed October 5, 2022, entitled "3D Cell and Array Structures," U.S. provisional patent application, serial number 63 / 418,698, filed October 24, 2022, entitled "3D Cell and Array Structures," U.S. provisional patent application, serial number 63 / 445,670, filed February 14, 2023, entitled "3D Cell and Array 119(e) to U.S. Provisional Patent Application No. 63 / 445,672, filed February 14, 2023, entitled "3D Cell and Array Structures," U.S. Provisional Patent Application No. 63 / 449,938, filed March 3, 2023, entitled "Novel 3D DRAM Cell, Array and Technology," U.S. Provisional Patent Application No. 63 / 458,059, filed April 7, 2023, entitled "3D Cell and Array Structures and Processes," and U.S. Provisional Patent Application No. 63 / 460,289, filed April 18, 2023, entitled "3D Cell and Array Structures and Processes," all of which are incorporated herein by reference in their entireties.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS Application No. 17 / 937,432 is a U.S. provisional patent application, filed August 17, 2022, serial number 63 / 398,807, entitled "Memory Cell and Array Architectures and Operation Conditions," U.S. provisional patent application, filed January 1, 2022, serial number 63 / 295,874, entitled "Alpha-RAM (a-RAM) or Alpha-DRAM (a-DRAM) Technology," U.S. provisional patent application, filed December 18, 2021, serial number 63 / 291,380, entitled "3D DRAM-replacement Technologies," U.S. provisional patent application, filed October 12, 2021, serial number 63 / 254,841, entitled "3D DRAM-replacement Technologies," and U.S. provisional patent application, filed October 1, 2021, serial number 63 / 251,583, entitled "3D DRAM-replacement Technologies." This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. provisional patent application No. 10 / 109,599, filed on Dec. 1, 2003, entitled "DRAM-Replacement Technologies," all of which are incorporated herein by reference in their entireties.

[0004] This application is related to the following co-pending application, having attorney docket number SIONS.PT9.CIP1, filed May 2, 2023, and entitled "3D MEMORY CELLS AND ARRAY ARCHITECTURES."

[0005] Exemplary embodiments of the present invention relate generally to the field of memories, and more particularly to memory cells, array structures and related processes. [Background technology]

[0006] With the increasing complexity and density of electronic circuits, memory size, complexity, and cost have become important considerations. One approach to increasing memory capacity is to use a three-dimensional (3D) array structure. 3D array structures are currently being used successfully in NAND flash memory. However, cost-effective 3D array structures have not been realized for dynamic random access memory (DRAM) due to its special one-transistor-one-capacitor (1T1C) cell structure. Summary of the Invention

[0007] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. In one embodiment, a novel 3D array structure is disclosed that implements DRAM using floating body cells. The array structure is formed using a deep trench process similar to that used for 3D NAND flash memory, enabling ultra-high density DRAM. In one embodiment, a 3D NOR type memory cell and array structure is provided. The disclosed memory cell and array structure are applicable to many technologies. For example, the innovative memory cell and array structure are applicable to dynamic random access memory (DRAM), floating body cell (FBC) memory, NOR type flash memory, and thyristors.

[0008] In an exemplary embodiment, a memory cell structure is provided that includes a first semiconductor material, a floating body semiconductor material having an inner surface surrounding and connecting to the first semiconductor material, and a second semiconductor material having an inner surface surrounding and connecting to the floating body semiconductor material, the memory cell structure further including a first dielectric layer connected to a top surface of the floating body material, a second dielectric layer connected to a bottom surface of the floating body material, a front gate connected to the first dielectric layer, and a back gate connected to the second dielectric layer.

[0009] In an exemplary embodiment, a three-dimensional (3D) memory array is provided that includes a plurality of memory cells separated by a dielectric layer to form a stack of memory cells. Each memory cell in the stack of memory cells includes a bit line formed from one of a first semiconductor material and a first conductor material, a floating body semiconductor material having an inner surface surrounding and connecting to the bit line, a source line formed from one of a second semiconductor material and a second conductor material having an inner surface surrounding and connecting to the floating body semiconductor material, and a word line formed from a third conductor material that is coupled to the floating body semiconductor through the dielectric layer to form a gate of the memory cell. Furthermore, the bit lines of the stack of memory cells are connected to form a vertical bit line.

[0010] In an exemplary embodiment, a memory cell structure is provided formed by a process that includes depositing multiple alternating semiconductor and sacrificial layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, forming floating bodies in the semiconductor layers through the bit line holes using an isotropic doping process, depositing a conductive material to fill the bit line holes, removing the sacrificial layers, depositing a gate dielectric layer between the semiconductor layers, and depositing a gate material on the gate dielectric layer.

[0011] Additional features and benefits of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below.

[0012] Exemplary embodiments of the present invention will be better understood from the detailed description given below and from the accompanying drawings of various embodiments of the present invention, which should not be construed as limiting the invention to the specific embodiments, but are for illustration and understanding only. [Brief explanation of the drawings]

[0013] [Figure 1A] 1 illustrates an embodiment of a cell structure for a three-dimensional (3D) NOR-type array constructed in accordance with the present invention. [Figure 1B] 1B illustrates an embodiment of the internal cell structure of the cell shown in FIG. 1A. [Figure 1C] 1 illustrates another embodiment of a cell structure constructed in accordance with the present invention. [Figure 1D] 1D shows the cell structure of FIG. 1C with portions of the cell removed. [Figure 1E] 1 illustrates another embodiment of a cell structure constructed in accordance with the present invention. [Figure 1F] 1C shows the internal cell structure of the cell shown in FIG. 1E with portions of the cell removed. [Figure 1G] 1 illustrates another embodiment of a cell structure constructed in accordance with the present invention. [Figure 1H] 1C shows the internal cell structure of the cell shown in FIG. 1G with portions of the cell removed. [Figure 1I] 1 illustrates another embodiment of a cell structure constructed in accordance with the present invention. [Figure 1J] 1A shows the internal cell structure of the cell shown in FIG. 1I with portions of the cell removed. [Figure 1K] 10 shows another embodiment of a cell structure constructed using junctionless thin film transistors according to the present invention. [Figure 1L] 1C illustrates an embodiment of a cross-sectional view of the cell structure shown in FIG. 1K along cross-section indicator AA′. [Figure 1M] 10 shows another embodiment of a cell structure using a junctionless thin film transistor according to the present invention. [Figure 1N] 1C shows a cross-sectional view of the cell structure shown in FIG. 1M along cross-section indicator AA′. [Figure 1O] 10 shows another embodiment of a cell structure using a junctionless thin film transistor according to the present invention. [Figure 1P] 1A shows a cross-sectional view of the cell structure shown in FIG. 1O along cross-section indicator AA′. [Figure 1Q] 1 illustrates an exemplary embodiment of a three-dimensional (3D) NOR memory cell structure using a floating body cell (FBC) configuration according to the present invention. [Figure 1R]1Q shows the cell structure shown in FIG. 1Q with the front gate and gate dielectric layer removed. [Figure 1S] 1 shows a cell formed using a PMOS transistor. [Figure 1T] 1A illustrates an embodiment of an array structure based on the cell structure shown in FIG. 1Q. [Figure 1U] 10 shows another embodiment of an array structure according to the present invention. [Figure 1V] 1A shows an equivalent circuit diagram of the array structure shown in FIG. 1T. [Figure 1W] 1A shows another embodiment of an equivalent circuit diagram of the array structure shown in FIG. 1T. [Figure 2A] 10 illustrates another embodiment of a cell structure for a 3D NOR flash memory constructed according to the present invention. [Figure 2B] 2B shows the internal cell structure of the cell shown in FIG. 2A with portions of the cell removed. [Figure 2C] 10 illustrates another embodiment of a cell structure for a 3D non-volatile random access memory constructed in accordance with the present invention. [Figure 2D] 2D shows the internal cell structure of the embodiment shown in FIG. 2C with portions of the cell removed. [Figure 3A] 1 illustrates an embodiment of a 3D array structure constructed in accordance with the present invention. [Figure 3B] 1 illustrates an embodiment of a 3D array structure constructed in accordance with the present invention. [Figure 3C] 1 illustrates an embodiment of a 3D array structure constructed in accordance with the present invention. [Figure 4A] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4B] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4C] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4D]1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4E] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4F] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4G] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4H] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 4I] 1B illustrates an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention. [Figure 5A] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1E according to the present invention. [Figure 5B] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1E according to the present invention. [Figure 5C] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1E according to the present invention. [Figure 6A] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 6B] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 6C] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 6D] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 6E]1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 6F] 1A and 1B illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention. [Figure 7A] 1A-1C illustrate an embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1I according to the present invention. [Figure 7B] 1A-1C illustrate an embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1I according to the present invention. [Figure 7C] 1A-1C illustrate an embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1I according to the present invention. [Figure 7D] 1A-1C illustrate an embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1I according to the present invention. [Figure 8A] 1C illustrates another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G according to the present invention. [Figure 8B] 1C illustrates another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G according to the present invention. [Figure 8C] 1C illustrates another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G according to the present invention. [Figure 8D] 1C illustrates another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G according to the present invention. [Figure 8E] 1C illustrates another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G according to the present invention. [Figure 9A] 1E-1F show another embodiment of the simple process steps for forming the cell structure shown in FIGS. 1E-1F according to the present invention. [Figure 9B] 1E-1F show another embodiment of the simple process steps for forming the cell structure shown in FIGS. 1E-1F according to the present invention. [Figure 9C] 1E-1F show another embodiment of the simple process steps for forming the cell structure shown in FIGS. 1E-1F according to the present invention. [Figure 10A] 1A illustrates another embodiment of the simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention. [Figure 10B] 1A illustrates another embodiment of the simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention. [Figure 10C] 1A illustrates another embodiment of the simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention. [Figure 10D] 1A illustrates another embodiment of the simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention. [Figure 10E] 1A illustrates another embodiment of the simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention. [Figure 11A] 1C illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1M according to the present invention. [Figure 11B] 1C illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1M according to the present invention. [Figure 11C] 1C illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1M according to the present invention. [Figure 11D] 1C illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1M according to the present invention. [Figure 12A] 1A illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1O according to the present invention. [Figure 12B] 1A illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1O according to the present invention. [Figure 12C] 1A illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1O according to the present invention. [Figure 12D] 1A illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1O according to the present invention. [Figure 12E] 1A illustrates another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1O according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] Those skilled in the art will realize that the following detailed description is for purposes of illustration only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to those skilled in the art having the benefit of this disclosure. Reference will now be made in detail to examples of illustrative embodiments of the present invention as illustrated in the accompanying drawings. The same reference designations or characters are used throughout the drawings and the following detailed description to refer to the same or similar parts.

[0015] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. For example, 3D NOR type cells, array structures, and processes are disclosed. Various embodiments of the present invention are applicable to many technologies. For example, aspects of the present invention are applicable to dynamic random access memory (DRAM) using floating body cells (FBC), NOR flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), and memory elements known as "synapses" in in-memory computing or neural networks for artificial intelligence (AI) applications. Furthermore, embodiments of the present invention are applicable to other memory applications not listed here.

[0016] FIG. 1A illustrates an embodiment of a cell structure for a three-dimensional (3D) NOR-type array constructed in accordance with the present invention. The cell structure illustrated in FIG. 1A includes semiconductor layers forming vertical bit lines (BIT LINES: BL) 101 made of silicon or polysilicon, floating bodies (FLOATING BODY: BL) 102 made of silicon or polysilicon, and horizontal source lines (SOURCE LINES: SL) 103 made of silicon or polysilicon. The cell also includes a front gate (FRONT GATE) 104a, a back gate (BACK GATE) 104b, a first gate dielectric layer (FIRST DIELECTRIC LAYER: ...

[0017] The cells can be formed as either NMOS or PMOS transistors. For NMOS cell embodiments, the bit line 101 and source line 103 have N+ type doping and the floating body 102 has P- type doping. For PMOS cell embodiments, the bit line 101 and source line 103 have P+ type doping and the floating body 102 has N- type doping.

[0018] 1B shows an embodiment of the internal cell structure of the cell shown in FIG. 1A, with the front gate 104a, gate dielectric layer 105a, and a portion of BL 101 removed. While the embodiment shows the bit lines 101 and floating bodies 102 as being circular in shape, in other embodiments, the bit lines 101 and floating bodies 102 may have any suitable shape, such as square, rectangular, triangular, hexagonal, etc. These variations are within the scope of the embodiments.

[0019] Depending on the cell type and technology, the gate dielectric layers 105a and 105b can be formed of a variety of different materials and structures. For example, in one embodiment, the cell may be formed as a floating body cell for DRAM applications. For this embodiment, the gate dielectric layers 105a and 105b are thin gate oxide layers or layers of high-k (K) material such as hafnium oxide (HfO). In other embodiments, the gate dielectric layers 105a and 105b are formed of other suitable materials to form NOR flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), and others, as shown in FIGS. 2A-D.

[0020] 1C shows another embodiment of a cell structure constructed in accordance with the present invention. This embodiment is similar to the embodiment of FIG. 1A, except that a metal vertical bit line 101 is formed with a metal core in the center of a semiconductor layer 109 to reduce bit line resistance.

[0021] FIG. 1D shows the cell structure of FIG. 1C with the front gate 104a and gate dielectric layer 105a as well as parts of the metal BL 101 and semiconductor layer 109 removed.

[0022] FIG. 1E illustrates another embodiment of a cell structure constructed in accordance with the present invention. This embodiment is similar to the embodiment illustrated in FIGS. 1C-1D, except that the drain region 107 is formed around the sides of the metal bit line 101 as shown. In this embodiment, the drain region 107 is formed of silicon or polysilicon with a heavy doping opposite to the doping of the floating body 102. For example, "opposite doping" means that P-type (positive) doping is the opposite of N-type (negative) doping. For example, if the floating body 102 has P-type doping, the drain region 107 has N-type doping, which is the opposite doping. If the floating body 102 has N-type doping, the drain region 107 has P-type doping, which is the opposite doping. The terms "heavily doped" and "lightly doped" are relative terms describing the amount of doping. When a semiconductor is doped with an excess of electrons or holes, it is called a heavily doped semiconductor, designated N+ or P+, respectively. When a semiconductor is doped with a small amount of electrons or holes, it is called a lightly doped semiconductor, designated N- or P-, respectively. As shown in Figure 1E, the vertical bit line holes are filled with metal to form metal bit lines 101 to reduce bit line resistance.

[0023] FIG. 1F shows the internal cell structure of the cell shown in FIG. 1E with the front gate 104a, gate dielectric layer 105a and portions of the metal bit line 101 removed.

[0024] 1G shows another embodiment of a cell structure constructed in accordance with the present invention. This embodiment is similar to the embodiment shown in FIGS. 1C-1D, except that the source line 103 is formed of a conductive material, such as metal, to reduce source line resistance. A source region 108, comprising a semiconductor material, such as silicon or polysilicon, is formed between the metal source line 103 and the floating body 102. The source region 108 has a heavy doping that is opposite to the doping of the floating body 102.

[0025] FIG. 1H shows the internal cell structure of the cell shown in FIG. 1G with the front gate 104a and gate dielectric layer 105a as well as parts of the metal BL 101 and semiconductor layer 109 removed.

[0026] FIG. 1I shows another embodiment of a cell structure constructed in accordance with the present invention. This embodiment is similar to FIGS. 1A-B, except that the bit line 101 and source line 103 are formed of metal. The floating body 102 is formed of a semiconductor material, such as silicon or polysilicon. In one embodiment, the floating body 102 has a high N+ or P+ doping concentration. This constitutes a junctionless cell transistor. In another embodiment, the floating body 102 has a low N- or P- doping concentration. This constitutes a Schottky junction cell transistor.

[0027] FIG. 1J shows the internal cell structure of the cell shown in FIG. 1I with the front gate 104a, gate dielectric layer 105a and part of BL 101 removed.

[0028] FIG. 1K illustrates another embodiment of a cell structure constructed using junctionless thin-film transistors according to the present invention. This embodiment is similar to the embodiment illustrated in FIGS. 1A-1B, except that a semiconductor layer 115, comprising silicon, polysilicon, germanium (Ge), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material, surrounds the BL 101 and an insulator 116, comprised of an oxide or nitride. In one embodiment, the semiconductor layer 115 has a heavy N-type or P-type doping that forms the channel of the cell transistor. In one embodiment, the bit line 101 and the source line 103 are formed of a conductive material, such as metal or heavily doped polysilicon. FIG. 1K also illustrates a cross-section indicator AA'.

[0029] FIG. 1L shows an embodiment of a cross-sectional view of the cell structure shown in FIG. 1K along cross-section indicator AA' shown in FIG. 1K.

[0030] FIG. 1M shows another embodiment of a cell structure using a junctionless thin film transistor according to the present invention. This embodiment is similar to the embodiment shown in FIGS. 1A-B, except for the semiconductor region 109. The semiconductor region 109 is formed of a different material than the floating body 102. For example, if the floating body 102 is formed of silicon or polysilicon, the semiconductor region 109 may be formed of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material. This configuration forms a heterostructure junction between the two materials, forming a quantum well within the semiconductor region 109 to store charges, such as holes. This increases the data retention time of the cell.

[0031] FIG. 1N shows a cross-sectional view of the cell structure shown in FIG. 1M along cross-section indicator AA' shown in FIG. 1M.

[0032] FIG. 1O illustrates another embodiment of a cell structure using a junctionless thin film transistor according to the present invention. This embodiment is similar to the embodiment illustrated in FIGS. 1M-N, except that the semiconductor region 109 is formed with a different shape. The semiconductor region 109 is formed of a different material than the floating body 102. For example, if the floating body 102 is formed of silicon or polysilicon, the semiconductor region 109 may be formed of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material. This forms a heterostructure junction between the two materials, forming a quantum well within the semiconductor region 109 to store charges, such as holes. This increases the data retention time of the cell.

[0033] FIG. 1P shows a cross-sectional view of the cell structure shown in FIG. 1O along cross-section indicator AA' shown in FIG. 1O.

[0034] FIG. 1Q illustrates an exemplary embodiment of a three-dimensional (3D) NOR memory cell structure using a floating body cell (FBC) configuration according to the present invention. For example, a 3D NOR array can include multiple layers of floating body arrays to increase memory capacity. A floating body cell is essentially a transistor with a floating body. The floating body stores charges, such as electrons or holes, to represent data. The cell structure includes a control gate, a drain, a source, and a floating body. In a 3D memory array, the control gate, drain, and source of a cell are connected to a word line (WL), a bit line (BL), and a source line (SL), respectively.

[0035] In the cell structure shown in FIG. 1Q, N+ silicon or polysilicon forms the bit line (BL) 101, and P- floating body 102 is used for charge storage. N+ silicon or polysilicon forms the source line (SL) 103. The cell can be configured as a dual-gate transistor, as shown in FIG. 1Q, or a single-gate transistor, as shown in FIG. 1R. For the dual-gate transistor shown in FIG. 1Q, the cell structure includes two control gates, referred to as the front gate (FG) 104a and the back gate (BG) 104b, respectively. Both the front gate 104a and the back gate 104b are coupled to the floating body 102 through gate dielectric layers 105a and 105b, respectively. The gate dielectric layer is an insulating layer between the gate and body of the transistor. When appropriate voltages are applied to the front gate 104a or back gate 104b, a front gate channel (FGC) 1014 or back gate channel (BGC) 1012 is formed in the plane of the floating body 102 beneath the gate dielectric layers 105a and 105b, providing conduction between the bit line 101 and the source line 103. In an embodiment, the front gate 104a and the back gate 104b are connected to different word lines (WL).

[0036] 1Q, the P-floating body 102 has multiple surfaces. An internal side surface 1002 surrounds and connects to the BL101. An external side surface 1004 connects to the source line 103. A top surface 1008 connects to the dielectric layer 105a, and a bottom surface 1006 connects to the dielectric layer 105b. Thus, in one embodiment, a memory cell structure is provided that includes a first semiconductor material BL101, a floating body semiconductor material 102 having an internal side surface 1002 surrounding and connecting to the first semiconductor material BL101, and a second semiconductor material SL103 having an internal side surface 1010 surrounding and connecting to the floating body semiconductor material 102. The memory cell structure also includes a first dielectric layer 105a connected to the top surface 1008 of the floating body material 102, a second dielectric layer 105b connected to the bottom surface 1006 of the floating body material 102, a front gate 104a connected to the first dielectric layer 105a, and a back gate 104b connected to the second dielectric layer 105b. In various embodiments, minor modifications can be made to the disclosed structures, such as adding a lightly doped drain (LDD), halo implementation, pocket implementation, or channel implementation, all of which are within the scope of the present invention.

[0037] 1R shows the cell structure shown in FIG. 1Q with portions of the front gate 104a, gate dielectric layer 105a, and bit line 101 removed. The P-floating body 102 forms a donut shape as shown. While this embodiment shows the bit line 101 and floating body 102 as being circular in shape, it should be apparent that they may have any desired shape, such as square, rectangular, triangular, hexagonal, etc. These variations are within the scope of the present invention.

[0038] In one embodiment, the cell structure includes only one single gate, as shown in Figure 1R. The floating body 102 is coupled to only one gate 104b as shown. An embodiment of a 3D array structure using this embodiment of the cell structure is shown in Figure 1T.

[0039] The embodiment shown in Figure 1Q uses NMOS transistors as cells. In another embodiment shown in Figure 1S, the cells are constructed using PMOS transistors. The bit line 101, floating body 102, and source line 103 are formed of P+, N-, and P+ materials, respectively.

[0040] Figure 1T shows an embodiment of an array structure based on the cell structure shown in Figure 1Q. The array structure comprises vertical bit lines (BL) 101a-101c and floating bodies (FB) 102a-102e. The array structure also comprises source lines (SL) 103a-103e and word lines (WL) 104a-104d. The array structure also includes a dielectric layer (DIELECTRIC) 105 comprising a gate oxide or a high-k material such as HfOx.

[0041] In an embodiment, a three-dimensional (3D) memory array includes multiple memory cells separated by a dielectric layer to form a stack of memory cells. For example, FIG. 1T shows a 3D array with three stacks of memory cells, with specific "memory cells" identified. Each memory cell in the stack of memory cells includes a bit line 101 formed from one of a first semiconductor material and a first conductor material, a floating body semiconductor material 102 having an inner surface surrounding and connecting to the bit line, a source line 103 formed from one of a second semiconductor material and a second conductor material having an inner surface surrounding and connecting to the floating body semiconductor material 102, and a word line 104 formed from a third conductor material that is coupled to the floating body semiconductor 102 through a dielectric layer 105 to form the gate of the memory cell. Furthermore, the bit lines of the stack of memory cells are connected to form a vertical bit line (e.g., 101a).

[0042] Figure 1U shows another embodiment of an array structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 1T, except that the cells are single-gate transistors. Also shown in Figure 1U are insulating layers 106a and 106b formed from a material such as oxide.

[0043] FIG. 1V shows an equivalent circuit diagram for the array structure shown in FIG. 1T. For example, the equivalent circuit shows transistors 301a-h configured by the array structure shown in FIG. 1T. Referring again to the array structure in FIG. 1T, word line structures 104a-104d are connected to word lines WL0-WL3. Floating body structures 102a-102e are floating bodies FB0-FB4. Source line structures 103a-103e are connected to source lines SL0-SL4, and bit line structure 101a is a vertical bit line (BL). In this embodiment, each floating body (e.g., FB0-FB4) is coupled to two word lines. This array requires special bias conditions for read and write operations to avoid two cells being selected simultaneously.

[0044] FIG. 1W shows another embodiment of an equivalent circuit diagram for the array structure shown in FIG. 1T. This embodiment is similar to the embodiment shown in FIG. 1V, except that odd word lines WL1, WL3, etc. are connected to ground. This turns off transistors 301c, 301d, 301g, and 301h. In this embodiment, each floating body is coupled to only one word line. However, the storage capacity of this embodiment is reduced by a factor of two compared to the embodiment shown in FIG. 1V.

[0045] FIG. 2A illustrates another embodiment of a cell structure for a 3D NOR flash memory constructed in accordance with the present invention. This embodiment is similar to the embodiment illustrated in FIGS. 1A-1B, except that gate dielectric layers 105a and 105b are replaced with charge trapping layers 160a and 160b comprising oxide-nitride-oxide (ONO) layers. In one embodiment, charge trapping layer 160b comprises tunnel oxide layer 161a, which is thin enough to allow electrons to tunnel when a high electric field is applied, thereby changing the threshold voltage of the cell, which represents stored data. Nitride layer 161b traps electrons for data storage. Blocking oxide 161c is thick enough to prevent electrons from tunneling through gates 104a and 104b. In another embodiment, blocking oxide 161c comprises a tunnel oxide layer, and tunnel oxide layer 161a comprises a blocking oxide layer. In this embodiment, during programming, electrons are injected into nitride layer 161b from the selected one of gates 104a or 104b.

[0046] FIG. 2B shows the internal cell structure of the cell shown in FIG. 2A with the front gate 104a, charge trapping layer 160a and part of BL 101 removed.

[0047] While the ONO layers 161a-c shown in FIG. 2B are used as an example of the charge trapping layers 160a and 160b, in other embodiments, the charge trapping layers 160a and 160b comprise any suitable number of oxide and nitride layers. For example, in other embodiments, the charge trapping layers 160a and 160b comprise oxide-nitride-oxide-nitride-oxide (ONONO) layers. In other embodiments, the charge trapping layers 160a and 160b consist of only one oxide and one nitride (ON) layer. These variations are within the scope of the embodiments.

[0048] In various embodiments, charge trapping layers 160a and 160b are also utilized in other cell embodiments shown in Figures 1A-L to replace gate dielectric layers 105a and 105b to construct different types of NOR flash memory cells.

[0049] 2C illustrates another embodiment of a cell structure for a 3D nonvolatile random access memory constructed in accordance with the present invention. This embodiment is similar to the embodiment illustrated in FIGS. 1A-1B, except that gate dielectric layers 105a and 105b are replaced with nonvolatile memory gate dielectric layers 170a and 170b. In one embodiment, nonvolatile memory gate dielectric layers 170a and 170b are comprised of multiple layers, such as layers 171a and 171b.

[0050] FIG. 2D shows the internal cell structure of the embodiment shown in FIG. 2C with the front gate 104a, non-volatile memory gate dielectric layer 170a and a portion of BL101 removed.

[0051] In one embodiment constituting a ferroelectric random access memory (FRAM), nonvolatile memory gate dielectric layer 170b comprises ferroelectric layer 171a, such as orthorhombic phase lead zirconate titanate (PZT) or hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO2). Layer 171b comprises a dielectric layer, such as hafnium oxide (HfO2). When a high voltage is applied to gates 104a and 104b, the generated electric field changes the polarity of the ferroelectric material in ferroelectric layer 171a, changing the threshold voltage of the cell, representing stored data.

[0052] In another embodiment forming a resistive random access memory (RRAM), the non-volatile memory gate dielectric layers 170a and 170b comprise a tunable resistance change layer 171a, such as hafnium oxide (HfOx), titanium oxide (TiOx), or tantalum oxide (TaOx), and a dielectric layer 171b, such as silicon dioxide (SiO2). In another embodiment forming a phase change memory (PCM), the non-volatile memory gate dielectric layers 170a and 170b are formed of multiple layers, including at least one phase change layer 171a, such as a germanium antimony tellurium alloy or chalcogenide glass, Ge2Sb2Te5 (GST), and a heater layer 171b, such as tungsten (W), titanium (Ti), or polysilicon.

[0053] In another embodiment forming a magnetoresistive random access memory (MRAM), the nonvolatile memory gate dielectric layers 170a and 170b comprise multiple layers including ferromagnetic materials 171a and 171b, such as iron-nickel (NiFe) or iron-cobalt (CoFe) alloys, and a tunnel-barrier layer, such as hafnium oxide (HfO), formed between layers 171a and 171b. The materials for the nonvolatile memory gate dielectric layers 170a and 170b described above are only some examples, and any other suitable materials can be used for the nonvolatile memory gate dielectric layers 170a and 170b within the scope of the embodiments.

[0054] The non-volatile memory gate dielectric layers 170a and 170b shown in this embodiment can be used in all other cell embodiments shown in FIGS. 1A-L to replace gate dielectric layers 105a and 105b to construct various types of non-volatile random access memory cells.

[0055] 3A-C illustrate an embodiment of a 3D array structure constructed in accordance with the present invention. FIG. 3A illustrates the construction using the cell structure shown in FIGS. 1C-D. However, in other embodiments, the 3D array structure may be constructed using any of the other cell structures shown in FIGS. 1A-2D. The 3D array comprises multiple layers of cells stacked vertically. The cells are connected to vertical bit lines, such as vertical bit lines 101a-101d. The 3D array also comprises multiple word line layers 104a-104h, which are connected to the gates of the cells. The 3D array also comprises multiple source line layers 103a-103h. Each intersection of one of the vertical bit lines 101a-101d and one of the source lines 103a-103h constitutes a cell, such as cell 120.

[0056] FIG. 3B illustrates an embodiment of bit line connections for the 3D array structure shown in FIG. 3A constructed in accordance with the present invention. Vertical bit lines 101a-101d are connected to horizontal bit lines 130a-130d through select gates, such as select gate 135a, and contacts, such as contact 137a. Horizontal bit lines 130a-130d are formed of a conductive material, such as metal or heavily doped polysilicon. Select gates, such as select gate 135a, are composed of vertical channel transistors. Select gate lines 136a-136d are connected to the control gates of vertical channel select gates, such as select gate 135a.

[0057] The word line layers 104a-104h and source line layers 103a-103h are connected to a word line detector (not shown) and a source line voltage generator (not shown), respectively, by forming sacrificial structures for the word lines and source lines at the edges of the array as structured in conventional 3D NAND flash memories.

[0058] 3C shows another embodiment of a 3D array structure according to the present invention. The array is divided into multiple stacks by vertical slits 112a and 112b. Each stack is connected to a different word line, such as 104a-104h, so that vertical bit lines, such as 101a-101c, can be connected to horizontal bit lines 130a-130d without the vertical select gates, such as 135a, shown in FIG. 3B.

[0059] The 3D array structure can be used in various 3D_NOR memory applications, such as dynamic random access memory (DRAM) using floating body cells (FBC), NOR flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM).

[0060] Furthermore, the 3D array structure is applicable to in-memory computing and 3D neural network arrays for artificial intelligence (AI) applications. For these applications, the vertical bit lines 101a-101d, word line layers 104a-104h, and source line layers 103a-103h are connected to input neuron circuits and output neuron circuits. In addition to these applications, the novel 3D cell and array structures constructed in accordance with the present invention are suitable for use in any other applications.

[0061] 4A-I illustrate an embodiment of a simple process step for forming a 3D array comprising the cell structure shown in FIG. 1A according to the present invention.

[0062] 4A shows how multiple semiconductor layers 103a-103g and multiple sacrificial layers 110a-110f are alternately deposited to form a stack. In one embodiment, the semiconductor layers 103a-103g comprise silicon or polysilicon layers. The sacrificial layers 110a-110f comprise oxide or nitride layers.

[0063] In one embodiment, semiconductor layers 103a-103g are formed of amorphous silicon using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process.

[0064] In one embodiment, after deposition, an annealing process is applied to convert the amorphous silicon to polycrystalline silicon (polysilicon), hi one embodiment, the annealing process utilizes low temperature rapid thermal annealing, such as 700° C. for 4 minutes, or any other suitable annealing process.

[0065] The semiconductor layers 103a-103g are doped during deposition using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition process.

[0066] In another embodiment, the semiconductor layers 103a-103g are formed using a polysilicon deposition process, such as pyrolysis of silane (SiH4) at 580-650° C. This process forms a polysilicon layer on the surface of the sacrificial layers 110a-110f and releases hydrogen (H2).

[0067] In other embodiments, the semiconductor layers 103a-103g are formed by forming single crystal silicon (monosilicon) on the surfaces of the sacrificial layers 110a-110f using a silicon epitaxial growth process, which may require longer processing times because the silicon layers are grown layer by layer.

[0068] The sacrificial layers 110a-110f are formed using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process.

[0069] FIG. 4B shows how a plurality of vertical bit line holes (or openings), such as bit line holes 111a-111c, are formed by using a photolithography process to define a pattern, and then using an anisotropic etching process, such as a deep trench process or a dry etching process, to etch through the plurality of semiconductor layers 103a-103g and sacrificial layers 110a-110f to form vertical bit line holes 111a-111c.

[0070] 4C shows how floating bodies such as floating bodies 102a-102c are formed by using impact plasma doping (PLAD) or plasma immersion ion implantation (PIII), gas-phase doping, or any other suitable doping process. For NMOS cells, diborane and hydrogen (BH / H) plasma is used to implant boron ions into N-type semiconductor layers 103a-103g through vertical bit line holes 111a-111c to reverse the doping and form P-floating bodies 102a-102c. For PMOS cells, phosphine (PH) or arsine (AsH) plasma is used to implant phosphorus or arsenic ions into P-type semiconductor layers 103a-103g to reverse the doping and form N-floating bodies 102a-102c.

[0071] FIG. 4D shows how vertical bit line holes, such as bit line holes 111a-111c shown in FIG. 4C, are filled with heavily doped polysilicon to form vertical bit lines, such as vertical bit lines 101a-101c. The semiconductor is deposited using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process. The semiconductor of bit lines, such as bit lines 101a-101c, is doped with the same heavy doping as semiconductor layers 103a-103g using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH) or arsine (AsH), is added during the bit line deposition. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the bitline deposition.

[0072] 4E-F illustrate embodiments of process steps used to form the cell structure shown in FIG. 1C. After the process steps shown in FIG. 4C are performed, the process steps shown in FIG. 4E are performed, in which semiconductor layers 107a-107c, such as polysilicon or silicon, are formed on the sidewalls of the vertical bit line holes 111a-111c using a deposition process described with reference to FIG. 4A, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process, or by using an epitaxial growth process to form a monocrystalline silicon layer. The semiconductor layers 107a-107c are doped with the same heavy doping as the semiconductor layers 103a-103g using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition of the semiconductor layer 107. For a PMOS cell, a P-type dopant, such as diborane (B2H6), is added during the deposition of the semiconductor layer 107.

[0073] 4F shows how vertical bit line holes 111a-111c are filled with a refractory metal, such as tungsten (W), to form vertical bit lines, such as vertical bit lines 101a-101c. Tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH). The metal bit lines 101a-101c reduce bit line resistance.

[0074] Prior to depositing metal into the vertical bit line holes 111a-111c, an adhesion layer (not shown), such as a titanium and titanium nitride (Ti / TiN) layer, may be formed on the surface of the semiconductor layers 107a-107c. The adhesion layer helps prevent delamination of the metal bit lines 101a-101c from the semiconductor layers 107a-107c, improving reliability. The TiN and Ti layers are formed using chemical vapor deposition (CVD) and ion metal plasma (IMP) physical vapor deposition (PVD) processes, respectively. In various embodiments, adhesion layers, such as the adhesion layer added to the semiconductor layer 107, are optional and can be omitted if desired.

[0075] FIG. 4G shows how the sacrificial layers 110a-110f can be selectively removed using an isotropic etching process, such as wet etching. If the sacrificial layers 110a-110f are oxide layers (SiO), they can be etched using buffered hydrofluoric acid (HF), ammonium hydroxide (NHF), or a mixture of hydrofluoric acid (HF) and nitric acid (HNO). If the sacrificial layers 110a-110f are nitride layers (SiN), they can be etched using concentrated hot orthophosphoric acid (HPO) at a temperature of 150-180°C.

[0076] 4H shows how gate dielectric layers 105a-105f, such as gate oxide (SiO) layers or layers of high-k material such as hafnium oxide (HfO), zirconium oxide (ZrO), or titanium oxide (TiO), are formed on the sidewall surfaces of the spaces previously occupied by the sacrificial layers 110a-110f. The gate dielectric layers 105a-105f are formed by growing a silicon oxide (SiO) layer on the surfaces of the semiconductor layers 103a-103g and vertical bit lines such as 101a-101c using thermal or dry oxidation, or by depositing a thin film of gate dielectric material on the surfaces of the spaces using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process.

[0077] FIG. 4I shows how the space previously occupied by the sacrificial layers 110a-110f is filled with a metal material, such as tungsten (W), tantalum (Ta), titanium (Ti), or niobium (Nb) for NMOS cells or ruthenium (Ru) for PMOS cells, or a composite of metal nitrides, such as WN, TaN, and TiN, or heavily doped polysilicon, to form the metal word lines (or gates) 104a-104f of the cell transistors. The metal word lines 104a-104f are formed using a deposition process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process. As a result, an array with floating-body cell structures, as shown in FIG. 1C, is formed.

[0078] 5A-C illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1E according to the present invention.

[0079] Figure 5A shows the array structure formed after the process steps shown in Figures 4A-C, and the reader is referred to Figures 4A-C for a detailed description of forming the array structure shown in Figure 5A.

[0080] 5B shows how drain regions such as 107a-107c are formed using plasma doping (PLAD) or gate phase doping, or any other suitable doping process that dopes floating bodies such as 102a-102c with a heavy opposite-type dopant. This doping process is performed through vertical bit line holes such as bit line holes 111a-111c. For NMOS cells, phosphine (PH) or arsine (AsH) plasma is used to implant phosphorus or arsenic ions into P-type floating bodies such as 102a-102c to reverse the doping and form N+ drain regions such as 107a-107c. For PMOS cells, diborane and hydrogen (BH / H) plasma is used to implant boron ions into N-type floating bodies such as 102a-102c to reverse the doping and form P+ drain regions such as 107a-107c.

[0081] After the process steps described with reference to Figure 5B are performed, the process steps shown in Figures 4F-I are performed to form the array structure shown in Figure 5C. The reader is referred to Figures 4F-I for a detailed description of these process steps. As a result, an array is formed with the floating body cell structure shown in Figure 1E.

[0082] 6A-F illustrate an embodiment of a simple process step for forming an array using the cell structure shown in FIG. 1I according to the present invention.

[0083] Figure 6A shows the array structure formed after the process steps shown and described with reference to Figures 4A-B. The reader may refer to Figures 4A-B for a detailed description of the process steps for forming the array structure shown in Figure 6A. In this embodiment, the source line (SL) layers 103a-103g are formed from a refractory metal such as tungsten (W). The tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH).

[0084] 6B shows how an isotropic etching process, such as a wet etch, is performed through vertical bit line holes, such as 111a-111c, to selectively etch sacrificial layers 110a-110f to form recesses, such as recesses 114a-114c. The dimensions of recesses 114a-114c are controlled by the etch rate and etch time of the etching solution. If first sacrificial layers 110a-110f are formed of silicon dioxide (SiO2), they can be etched using buffered hydrofluoric acid (HF) with ammonium hydroxide (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0085] FIG. 6C illustrates how recesses, such as recesses 114a-114c, and vertical bit line holes, such as vertical bit line holes 111a-111c, are filled with semiconductor material 116, such as polysilicon or silicon. In one embodiment, the polysilicon is formed using a polysilicon deposition process that comprises the silicon epitaxial growth process described with reference to FIG. 4A. The reader may refer to FIG. 4A for a detailed description of the polysilicon deposition process. The semiconductor material 116 is doped using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH) or arsine (AsH), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (BH), is added during the deposition process.

[0086] 6D illustrates how an anisotropic etching process, such as dry etching, is performed using the sacrificial layers 110a-110f as a hard mask to selectively etch away the semiconductor material 116 and reform vertical bit line holes, such as vertical bit line holes 111a-111c. Because this etching process is self-aligned, a high yield can be achieved. After the vertical bit line holes, such as vertical bit line holes 111a-111c, are reformed, the semiconductor material 116 in the recesses (e.g., recesses 114a-114c) become floating bodies, such as floating bodies 102a-102c, of the cell transistors.

[0087] 6E shows how vertical bit line holes such as 111a-111c are filled with a refractory metal such as tungsten (W) to form vertical metal bit lines such as metal bit lines 101a-101c. Tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH).

[0088] After filling the vertical bit line holes 111 to form the metal bit lines 101, the process steps shown and described with reference to Figures 4G-I are performed to form the array structure shown in Figure 6F. For example, the sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, and metal word lines 104 are formed. The reader is referred to Figures 4G-I for a detailed description of these process steps. In this embodiment, the vertical bit lines, such as metal bit lines 101a-101c, and the source line layers 103a-103g are formed of metal. As a result, an array with floating body cell structures is formed as shown in Figure 1I.

[0089] 7A-D illustrate an embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1I according to the present invention.

[0090] FIG. 7A shows the array structure configured after performing the process steps shown in FIGS. 4A-D. The reader is referred to FIGS. 4A-D for a detailed description of these process steps. In this embodiment, layers 113a-113g are formed of a second sacrificial material, such as an oxide or a nitride. The second sacrificial layers 113a-113g and the first sacrificial layers 110a-110f are configured to have different etch selectivities. For example, in one embodiment, the first sacrificial layers 110a-110f are formed of an oxide, and the second sacrificial layers 103a-103g are formed of a nitride.

[0091] 7B shows how the second sacrificial layers 113a-113g can be selectively removed by using an isotropic etching process, such as wet etching. If the second sacrificial layers 113a-113g are made of silicon dioxide (SiO2), they can be etched using buffered hydrofluoric acid (HF) with ammonium hydroxide (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0092] 7C shows how a refractory metal such as tungsten (W) is deposited to fill the space previously occupied by the second sacrificial layers 113a-113g to form the metal source line layers 103a-103g. Tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH).

[0093] After the metal deposition process described above, the process steps shown and described with reference to Figures 4G-I are performed to form the array structure shown in Figure 7D. For example, the sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word lines 104 are formed. The reader is referred to Figures 4G-I for a detailed description of these process steps. As a result, an array is formed with the floating body cell structures shown in Figure 1I.

[0094] 8A-E illustrate another embodiment of a simple process step for forming an array comprising the cell structure shown in FIG. 1G in accordance with the present invention.

[0095] FIG. 8A illustrates the array structure formed after performing the process steps illustrated in FIGS. 4A-F. The reader may refer to FIGS. 4A-F for a detailed description of the process steps for forming this array structure. In this embodiment, layers 113a-113g are formed of a second sacrificial material, such as an oxide or a nitride. The second sacrificial layers 113a-113g and the first sacrificial layers 110a-110f are configured to have different etch selectivities. For example, in one embodiment, the first sacrificial layers 110a-110f are formed of an oxide, and the second sacrificial layers 103a-103g are formed of a nitride.

[0096] 8B shows how the second sacrificial layers 113a-113g can be selectively removed by using an isotropic etching process, such as wet etching. If the second sacrificial layers 113a-113g are made of silicon dioxide (SiO2), they can be etched using buffered hydrofluoric acid (HF) with ammonium hydroxide (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0097] FIG. 8C shows how source regions such as 108a-108c are formed by reversing the doping type of floating bodies such as 102a-102c using a plasma doping (PLAD) or gate phase doping process or any other suitable doping process with a heavy dopant of the opposite type.

[0098] 8D shows how a refractory metal such as tungsten (W) is deposited to fill the space previously occupied by the second sacrificial layers 113a-113g to form the metal source line layers 103a-103g. Tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH).

[0099] After depositing the metal as described above, the process steps illustrated in Figures 4G-I are performed to form the array structure shown in Figure 8F. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, and metal word lines 104 are formed. The reader is referred to Figures 4G-I for a detailed description of these process steps. The result is an array with floating body cell structures as shown in Figure 1G.

[0100] Figures 9A-C illustrate an alternative embodiment for forming source regions such as 108a-108c for an array having the cell structure shown in Figure 1G. After the process steps shown and described with reference to Figure 8B are performed, the process steps shown in Figure 9A are performed.

[0101] 9A shows how semiconductor layers 108a-g, such as polysilicon or silicon, are formed on the sidewall surfaces of the spaces previously occupied by second sacrificial layers 113a-g. Each semiconductor layer 108 forms a source region, such as source regions 108a(1)-108a(3), on the sidewall of a floating body, such as floating bodies 102a-c.

[0102] In one embodiment, the semiconductor layer 108 is formed by a polysilicon deposition process or a silicon epitaxial growth process, such as that described with reference to FIG. 4A. The semiconductor layer 108 is doped using an in-situ doping process. For an NMOS cell, an N-type dopant, such as phosphine (PH) or arsine (AsH), is added during the deposition process. For a PMOS cell, a P-type dopant, such as diborane (BH), is added during the deposition process.

[0103] FIG. 9B illustrates how a refractory metal, such as tungsten (W), is deposited to fill the spaces previously occupied by the second sacrificial layers 113a-113g to form metal source line layers 103a-103g. Tungsten is deposited using any suitable deposition process, such as a chemical vapor deposition (CVD) reaction of tungsten hexafluoride (WF), hydrogen (H), and silane (SiH). After the metal is deposited, the process steps shown and described with reference to FIGS. 4G-I are performed to form the array structure shown in FIG. 9C. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, and metal word lines 104 are formed. The reader is referred to FIGS. 4G-I for a detailed description of these process steps.

[0104] 10A-E illustrate another embodiment of simple process steps performed to form an array comprising the cell structure shown in FIG. 1K in accordance with the present invention.

[0105] Figure 10A shows the array structure constructed after performing the process steps shown in Figures 6A-B, and the reader is referred to Figures 6A-B for a detailed description of the process steps performed to form this array structure.

[0106] Figure 10B shows how a semiconductor layer 115, such as silicon, polysilicon, silicon germanium (SiGe), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material, is formed on the surfaces of the recesses 114, such as recesses 114a-114c, and the sidewalls of the vertical bit line holes, such as 111a-111c, by using an epitaxial or deposition process such as that described with reference to Figure 4A. The reader is referred to Figure 4A for a detailed description of these processes.

[0107] FIG. 10C shows that after the semiconductor layer 115 is formed, an insulator material 116, such as an oxide or nitride, is deposited to fill the recesses, such as recesses 114a-114c, and the vertical bit line holes 111a-111c.

[0108] 10D shows how an anisotropic etching process, such as dry etching, is performed using the sacrificial layers 110a-110f and the semiconductor layer 115 as a hard mask to selectively etch the semiconductor material 116 inside the vertical bit line holes, such as bit line holes 111a-111c. Because this etching process is self-aligned, the process achieves a high yield.

[0109] After the etching process described above, the vertical bit line holes, such as bit line holes 111a-111c, are filled with a conductive material, such as metal or polysilicon, by using a deposition process to form vertical bit lines, such as bit lines 101a-101c. The process steps shown and described with reference to FIGS. 4G-I are then performed to form the array structure shown in FIG. 10E. For example, first sacrificial layer 110 is removed, gate dielectric layer 105 is deposited, and metal word lines 104 are formed. The reader is referred to FIGS. 4G-I for a detailed description of these process steps. As a result, an array with floating body cell structures, as shown in FIG. 1K, is formed.

[0110] 11A-D illustrate another embodiment of a simple process step designed to form an array comprising the cell structure shown in FIG. 1M in accordance with the present invention.

[0111] Figure 11A shows the resulting array structure after performing the process steps shown in Figures 6A-B, and the reader is referred to Figures 6A-B for a detailed description of the process steps performed to form this array structure.

[0112] Figure 11B shows how a first semiconductor layer 118, such as silicon or polysilicon, is formed on the surfaces of the sidewalls of recesses, such as recesses 114a-114c, and vertical bit line holes, such as bit line holes 111a-111c, by using the silicon epitaxial process or polysilicon deposition process described with reference to Figure 4A. The reader is referred to Figure 4A for a detailed description of these processes.

[0113] After first semiconductor layer 118 is formed, a second semiconductor material 119 is deposited to fill the recesses, such as recesses 114a-114c, and vertical bit line holes, such as bit line holes 111a-111c. In one embodiment, second semiconductor material 119 is different from first semiconductor layer 118. For example, in one embodiment, first semiconductor layer 118 is formed of silicon or polysilicon, and second semiconductor material 119 is made of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material.

[0114] 11C shows how an anisotropic etching process, such as dry etching, is performed using the sacrificial layers 110a-110f as a hard mask to selectively etch the semiconductor layer 118 and second semiconductor material 119 inside the vertical bit line holes, such as bit line holes 111a-111c. This etching process is self-aligned and therefore achieves high yields. After the vertical bit line holes, such as bit line holes 111a-111c, are formed, the semiconductor layers 118a-118c become the individual floating bodies of each cell, and the second semiconductor material 119a-119c become second semiconductor regions for charge storage.

[0115] After the etching process described above, the process steps shown in Figures 4E-I are performed to form the array structure shown in Figure 11D. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, metal word lines 104 are formed, a semiconductor layer 107 is deposited, and vertical bit lines 101 are formed. The reader is referred to Figures 4E-I for a detailed description of these process steps. As a result, the array shown in Figure 11D is formed with the floating body cell structure shown in Figure 1M.

[0116] 12A-E illustrate another embodiment of a simple process sequence designed to form an array comprising the cell structure shown in FIG. 1O in accordance with the present invention.

[0117] Figure 12A shows the resulting array structure after performing the process steps shown in Figures 4A-C, and the reader is referred to Figures 4A-C for a detailed description of the process steps used to form this array structure.

[0118] FIG. 12B illustrates how an isotropic etching process, such as a wet etch, is performed through vertical bit line holes, such as bit line holes 111a-111c, to selectively etch floating bodies, such as floating bodies 102a-102c, to form recesses, such as recesses 114a-114c. In another embodiment, floating body 102 is formed after recess 114 is formed. In this embodiment, after the process steps illustrated in FIG. 4B are performed, an isotropic etching process, such as a wet etch, is performed through vertical bit line holes, such as bit line holes 111a-111c, to selectively etch semiconductor layers 103a-103c to form recesses, such as recesses 114a-114c. Next, an isotropic doping process, such as plasma doping or vapor phase doping, is performed to dope semiconductor layers 103a-103g with dopants opposite to those of semiconductor layers 103a-103g, to form floating bodies, such as floating bodies 102a-102c, as shown in FIG. 12B.

[0119] 12C illustrates how a semiconductor material 109, such as semiconductors 109a-c, different from the material of the floating body 102 is deposited by filling the vertical bit line holes 111 and recesses 114 using an appropriate deposition process. For example, in one embodiment, if the floating body 102 is formed of silicon or polysilicon, the semiconductor material 109 is formed of silicon germanium (SiGe) or silicon carbide (SiC).

[0120] FIG. 12D shows how an anisotropic etching process, such as a dry etch, is performed using the sacrificial layers 110a-110f as a hard mask to selectively etch away the semiconductor material 109 and reshape the vertical bit line holes 111. This etching process is self-aligned and therefore achieves a high yield. After the vertical bit line holes 111 are reshaped, the remaining semiconductor material in the recesses becomes semiconductor regions 109 (e.g., regions 109a-109c) that form quantum wells that store charge, such as by storing holes, as described with reference to FIG. 1O.

[0121] Figure 12E shows the resulting array structure after the process steps described with reference to Figures 4E-I have been performed. The reader is referred to Figures 4E-I for a detailed description of these process steps. For example, first sacrificial layer 110 is removed, gate dielectric layer 105 is deposited, metal word lines 104 are formed, semiconductor layer 107 is deposited, and vertical bit lines 101 are formed. As a result, the array shown in Figure 12E is formed with the floating body cell structures shown in Figure 1O.

[0122] While exemplary embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that, based on the teachings herein, changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. Therefore, the following claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. 1. A memory cell structure comprising: depositing a plurality of alternating semiconductor layers and sacrificial layers to form a stack; forming vertical bit line holes through the stack using a deep trench process; forming a floating body in the semiconductor layer through the bit line hole using an isotropic doping process; depositing a conductive material to fill the bit line holes; removing the sacrificial layer; depositing a gate dielectric layer between said semiconductor layers; depositing a gate material over the gate dielectric layer; A memory cell structure formed by the process.

2. 10. The memory cell structure of claim 1, wherein the isotropic doping process comprises one of plasma doping (PLAD), gas phase doping, bombardment plasma doping, or plasma immersion ion implantation (PIII).

3. 2. The memory cell structure of claim 1, wherein said floating body is formed to have a doping type opposite that of said semiconductor layer.

4. The memory cell structure of claim 1 , wherein the conductive material comprises one of a metallic material or a polysilicon material.

5. 10. The memory cell structure of claim 1, further comprising the act of depositing a semiconductor layer before depositing said conductive material to fill said bit line holes.

6. 10. The memory cell structure of claim 1, further comprising the operation of forming a drain region in the floating body through the bit line hole using an isotropic doping process before depositing the conductive material to fill the bit line hole.

7. 1. A memory cell structure comprising: depositing a plurality of alternating conductive and sacrificial layers to form a stack; forming vertical bit line holes through the stack using a deep trench process; forming a recess in the conductor layer through the bit line hole using an isotropic etching process; depositing a semiconductor to fill the bit line hole and recess to form a floating body; removing the semiconductor within the bit line hole to reform the bit line hole; depositing a conductor to fill the bit line hole; removing the sacrificial layer; depositing a gate dielectric layer between said semiconductor layers; depositing a gate material over the gate dielectric layer; A memory cell structure formed by the process.

8. The memory cell structure of claim 7 , wherein the isotropic etching process comprises a wet etching process.

9. The memory cell structure of claim 7 , wherein the conductor is one of a metal or polysilicon.

10. 8. The memory cell structure of claim 7, further comprising the act of depositing a semiconductor layer in the bit line holes before depositing the conductor to fill the bit line holes.

11. 8. The memory cell structure of claim 7, further comprising the act of forming a drain region in the floating body through the bit line hole using an isotropic doping process before depositing the conductor to fill the bit line hole.

12. 1. A memory cell structure comprising: a plurality of semiconductor layers and sacrificial layers alternately deposited to form a stack; a vertical bit line hole formed through the stack; a floating body in the semiconductor layer formed through the bit line hole using an isotropic doping process; a conductive material deposited to fill the bit line holes; a gate dielectric layer formed between the semiconductor layers, deposited after the sacrificial layer is removed; a gate material deposited on the gate dielectric layer; A memory cell structure comprising:

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