New transistor devices

Abstract

A vertical transistor is described having collector and emitter regions of a first type semiconductor, a base region including sub-regions of a second type semiconductor, and a channel of the first type extending between the collector and emitter regions, the channel extending through the sub-regions such that the channel is surrounded on all sides by the sub-regions along its entire length.

Description

[Background technology]

[0001] WO 2022 / 123261 describes a lateral bipolar junction transistor having a channel type interconnecting the collector and emitter that is the same semiconductor type as the emitter and collector. As a result of the channel characteristics, the transistor device exhibits several favorable electrical properties over conventional lateral bipolar junction transistors (BJTs), including superior current gain.

[0002] In the PNP variant described, a lightly doped P channel is fabricated by counterdoping an N-type well. Because the channel depth needs to be very shallow, it is located substantially at the surface of the wafer, where the doping can be most precisely controlled. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been devised with the aim of producing a vertical equivalent of the lateral transistor disclosed in WO2022 / 123261. [Means for solving the problem]

[0004] According to a first aspect of the present invention, there is provided a transistor device having a collector region provided by a first region of a semiconductor of a first type, a collector terminal associated with the collector region, an emitter region provided by a second region of a semiconductor of the first type, an emitter terminal associated with the emitter region, a base region provided by a third region of a semiconductor between and interfacing with both the collector region and the emitter region, and a base terminal associated with the base region, wherein the base region includes a sub-region of a semiconductor of the second type and a channel of a semiconductor of the first type, and the base terminal contacts the sub-region, the sub-region interfacing with the channel. a first diode junction formed by a first gate electrode and an emitter region and interfacing with both the emitter region and the collector region to form a further diode junction; a channel interfacing with and interconnecting the collector region and the emitter region, the channel having a net doping concentration lower than the net doping concentrations of the emitter and collector regions; the channel extending a distance from the first diode junction, the collector region and the emitter region being spaced apart by 1.5 microns or less; and the subregion surrounding the channel such that the interface between the subregion and the channel typically extends continuously around the channel for substantially the entire length of the channel.

[0005] As described in detail in WO 2022 / 123261 (the entire contents of which are incorporated by reference), the presence of a channel in what is otherwise a substantially conventional BJT semiconductor structure allows unipolar conduction between the collector and emitter terminals. This improves the gain characteristics of the transistor compared to BJT transistors of conventional structure. This is believed to be because the channel forms a conduction path between the emitter and collector regions without crossing a diode junction, thus providing a relatively low resistance.

[0006] The structure of this transistor allows for unique operation in several modes.

[0007] For example, the device may be configured to operate under a first condition, i.e., when a voltage (V ce ) and implemented in a circuit with the base terminal floating or shorted to the emitter terminal, the current between the collector and emitter terminals may be at least primarily due to unipolar conduction.

[0008] When the device is implemented in a circuit under a second condition, i.e., when the voltage across the emitter and collector terminals is below the first threshold voltage and the base terminal is either floating or shorted to the emitter terminal, a depletion region sufficient to pinch the channel forms around the first diode junction, causing substantially no current to flow between the collector and emitter terminals of the device.

[0009] The device operates under a third condition, i.e., when a voltage is applied between the emitter and collector terminals and a voltage (V) is applied between the emitter and base terminals that causes a current to flow to the base terminal. be ) is implemented in a circuit under such conditions, the current between the collector and emitter terminals may be at least primarily due to bipolar conduction.

[0010] V ce The value of the threshold voltage depends on the width of the channel and the length of the channel extending between the emitter and collector regions, and usually also on the separation between the emitter and collector regions.

[0011] The presence of the channel allows the transistor to be switched on, i.e., a minimum current flows through the collector terminal at a value of |Vbe| that is lower than the forward bias voltage |(Vft)| of the base-emitter diode junction. While on in this state, no current flows through the base terminal. The advantages of this technology are explained in detail in WO2022 / 123261.

[0012] Thus, the device may be implemented in a circuit adapted to selectively switch Vbe between |Vbe1| and |Vbe2|, where |Vbe1| is selected to be less than |Vft| to provide unipolar conduction, and |Vbe2| is selected to be greater than or equal to |Vft| to provide bipolar conduction.

[0013] Switching between conduction modes that include virtually exclusively unipolar and bipolar conduction has two advantages over operating in unipolar conduction mode alone: ​​overshoot is minimized and known voltage limits are enforced.

[0014] When the current between the collector and emitter switches between two Vbe voltages due to unipolar conduction only, inrush charge to / from the base of the transistor can cause the voltage to overshoot when switching to the larger |Vbe|. This causes a delay as the overshooting Vbe returns to the larger |Vbe| as charge is discharged from / backcharged into the base. This has the effect of limiting the maximum switching frequency, as as the switching frequency is increased the circuit attempts to switch while the larger |Vbe| is still overshooting. This problem occurs in MOSFETs and JFETs, where the current between the gate and drain terminals is only unipolar.

[0015] In contrast, when switching to a voltage Vbe where |Vbe| > |Vft|, such that the current between collector and emitter is partially due to bipolar conduction, the forward-biased base-emitter junction causes a rapid increase in base current as Vbe increases beyond Vft. This has the effect of clamping the larger |Vbe|, minimizing overshoot and increasing the maximum possible switching frequency.

[0016] In other words, when operating in fully unipolar mode like a JFET, it can pull its base voltage (the gate voltage for a JFET) from rail to rail. However, in bipolar mode, when |Vbe| > |Vft|, a base current occurs that prevents it from pulling to the rails, limiting the Vbe voltage. This means that the voltage swing is at most one rail to Vbe2. The smaller the voltage swing, the faster the switching speed.

[0017] The appropriate width of the channel, i.e., the dimension orthogonal to both the first diode junction and the direction of current flow through the channel, is determined by the value of Vce at which the transistor is designed to operate and / or the doping concentration of the channel.

[0018] For example, for a transistor adapted to operate within a nominal voltage range of 0 V to |5 V|, a channel width of less than 0.50 μm, preferably 0.2 μm or less, may be suitable. This range is larger than that specified in WO 2022 / 123261. This is because the first diode junction surrounds the channel on all sides, causing the depletion region to extend radially inward from all sides toward the channel.

[0019] However, at a given operating voltage, the maximum channel width allowed to turn the transistor off is significantly smaller than for a JFET designed to operate at a comparable operating voltage.

[0020] The width of the subregions extending laterally to one or both sides from the first diode junction may be at least five times the width of the channel, and in some embodiments, the width of the subregions may be at least 20 times the width of the channel.

[0021] The net doping concentration of the channel may be less than or equal to (e.g., between 0.01 and 0.1 times) the net doping concentration of the sub-regions. This ensures that the depletion region of the first diode junction is preferentially formed in the channel compared to in the sub-regions. For example, if the channel is composed of a P-type semiconductor material and the sub-regions are composed of an N-type semiconductor material, the net doping concentration of P-type dopants in the channel may be between 0.01 and 0.1 times the net concentration of N-type dopants in the sub-regions.

[0022] To provide good conduction properties within the sub-regions, the sub-regions may have a net doping concentration of from 1e16 per cm3 to 5e17 per cm3, inclusive.

[0023] Because good bipolar conduction characteristics also depend on a relatively small separation between the collector and emitter regions, the spacing between the collector and emitter regions may be 1.5 microns or less, preferably 0.6 microns or less. In one embodiment, the spacing may be 0.3 microns. Typically, the spacing between the collector and emitter regions is equal to the length of the channel, and therefore may also be 1.5 microns or less.

[0024] The ratio of channel width to the separation between the collector and emitter regions, expressed as a fraction, can be 2 / 3 or less.

[0025] The channel may be provided by a semiconductor layer of the first type having a lower net doping concentration than the first region of the semiconductor of the first type and located over the first region of the first type. The semiconductor layer is preferably an epitaxial layer because its thickness, and therefore the channel length, can be more closely controlled compared to using an implantation and diffusion process.

[0026] The subregion of the second type semiconductor can extend completely through the semiconductor layer of the first type. The subregion can define a hole, typically located at the center of the subregion, to provide or define a core of the semiconductor layer that provides the channel. The first region of the first type semiconductor can be provided, at least in part, by a polysilicon layer immediately above the semiconductor layer of the first type.

[0027] A common application of transistor devices is logic circuits in which multiple similar transistors are integrally formed on a single semiconductor die. In such cases, it may be advantageous for two or more transistors to share a common emitter region and emitter terminal. Thus, the transistor device may comprise multiple transistors, where a second region of a first type of semiconductor provides a common emitter region for the multiple transistors, the transistor device also comprising multiple subregions of the second type extending through the semiconductor layer, each subregion being laterally spaced apart from the other subregions around the periphery of the semiconductor layer, and multiple first regions of the first type of semiconductor, each directly overlying one of the multiple subregions.

[0028] The emitter, collector, and base terminals can be on the same side of the substrate, or the emitter terminal can be on a first side of the substrate and the collector and base terminals can be on an opposite second side of the substrate.

[0029] The semiconductor may be a silicon semiconductor.

[0030] The invention will now be described by way of example with reference to the following figures: [Brief explanation of the drawings]

[0031] [Figure 1A] 1 is a plan view of a first modified semiconductor layer structure providing a vertical bipolar junction transistor. FIG. [Figure 1B] A side cross-sectional view through the vertical plane QQ. [Figure 2A]FIG. 1 is a plan view of a second modified semiconductor layer structure providing a vertical bipolar junction transistor. [Figure 2B] 1 is a side cross-sectional view through a vertical plane RR of the second modified semiconductor layer structure. [Figure 3] FIG. 10 is a cross-sectional side view of a second modified semiconductor layer structure adapted to fabricate multiple integrated vertical bipolar junction transistors sharing a common emitter terminal. [Figure 4] 4 is a graph showing how the operating characteristics of the transistor devices of FIGS. 1 to 3 change with changes in Vbe and Vce. DETAILED DESCRIPTION OF THE INVENTION

[0032] 1A and 1B, a semiconductor structure is shown that implements a vertical transistor device. This transistor device is devised as an improvement over, and in some aspects operates in a similar manner to, the conventional bipolar junction transistor (BJT) device. For this reason, the terminals of this device use the BJT nomenclature.

[0033] The device is of the PNP type in this example and is not to scale, and is made up of silicon semiconductor material doped to provide a collector region 1, an emitter region 2, and a base region 3. The base region 3 is located between the collector region 1 and the emitter region 2.

[0034] Both the collector region 1 and the emitter region 2 are P-type semiconductors, and as is conventional, the emitter region 2 may be more heavily doped than the collector region 1. For example, the net doping concentration of the collector region 1 is 1×10 18 cm -3 or more, and the net doping concentration of the emitter region 2 is 2×10 18 cm -3or more. Alternatively, they may instead have substantially the same net doping concentration. Collector terminal C (see FIG. 1A) is connected to collector region 1, emitter terminal E to emitter region 2, and base terminal B to base region 3.

[0035] Unlike a conventional BJT, the base region 3 of the transistor device is composed of two different types of semiconductor regions: a first region of N-type material (hereinafter referred to as N-type base region 3A) and a second region of P-type material (hereinafter referred to as channel 3B).

[0036] The base terminal B connects to the base region 3 through an N-type region 3A, which directly interfaces with the channel 3B, forming a PN junction 4. The N-type base region 3A also directly interfaces with both the collector region 1 and the emitter region 2, providing respective PN junctions 5 and 6.

[0037] Channel 3B extends between collector region 1 and emitter region 2 and has a direct interface with both collector region 1 and emitter region 2. Channel 3B has a very weak net doping concentration compared to collector region 1 and emitter region 2. For example, the net doping concentration of channel 3B is 5×10 16 cm -3 It may be the following:

[0038] Additionally, the channel 3B has a lateral width, i.e., the dimension extending perpendicularly from the NP junction 4 with the N-type base region 3A, that is significantly smaller than that of a conventional junction field effect transistor (JFET). In one embodiment, the lateral width may be 0.2 microns.

[0039] The net concentration of N dopants in the N-type base region 3A may be about 1e17 / cm3.

[0040] The separation between the collector and emitter regions, which corresponds to the length of channel 3B, may be 1.5 microns or less, preferably 0.8 microns or less, and in one embodiment it is about 0.3 microns.

[0041] Semiconductor structures that implement the above-mentioned features are described below.

[0042] Provided on the P-type substrate 100 providing the emitter region 1 is a 5×10 16 cm -3 A relatively lightly doped P-type layer 101 having a net doping concentration of:

[0043] A square annular N-type region 102 providing base sub-region 3A extends completely through P-type layer 101 and partially into substrate 100. N-type region 102 defines a centrally located opening that extends completely through N-type region 102 between the upper and lower sides of the P-type layer to define portion 101A of P-type layer 101 providing channel 3B that is isolated from the remainder of P-type layer 101.

[0044] N-type region 102 may take forms other than a square annulus, such as an annulus, a rectangular annulus, or an irregular annulus. The opening need not be located directly in the center of N-type region 102, but preferably is located entirely within perimeter 102A of N-type region 102 to ensure isolation of channel 3B from the rest of P-type layer 101.

[0045] As shown in FIG. 1A, P-type layer 101 typically extends laterally around all sides of N-type region 102.

[0046] A first oxide layer 104 overlies P-type layer 101A. Formed through first oxide layer 104 is a first window 105. P-type region 106, provided in part by a polysilicon layer 107 formed through window 105 over P-type layer 101 and in part by converted portion 106A of epitaxial layer 101, lies in direct overlying contact with portion 101A and N-type region 102, defining interface 5. Portion 107A of the polysilicon layer extends over first oxide layer 104 to provide a conductive track for interconnecting the collector terminal to circuitry.

[0047] A second oxide layer 108 is provided over the first oxide layer 104 and polysilicon layer 107, isolating the polysilicon layer 107 from the patterned metal layer 110. A second window 111 through the first oxide layer 104 and the second oxide layer 108 allows the metal layer 110 to directly contact the N-type region 102 to provide a base contact B. In this example, the junction between the metal layer 110 and the N-type region 102 provides a Schottky diode.

[0048] A further metal layer 112 is provided on the opposite side of the substrate 100, opposite the side on which the P-type layer 101 is located, to provide an emitter contact E. Although not shown in Figure 1B, the portion of the substrate 100 adjacent to the metal layer 112 is more heavily doped to provide a good ohmic contact.

[0049] An example of a manufacturing process is now described: A P-type layer 101 is epitaxially grown on a P-type substrate 100. The thickness X of the epitaxy layer is selected to define the desired channel length and hence the separation between the collector and emitter regions.

[0050] Thereafter, using a mask defining a square annular pattern, a first implantation and diffusion process is performed to convert a region of P-type layer 101A and a portion of substrate 100 directly below it to form a square annular N-type region 102, defining channel 3B and diode junctions 4 and 6.

[0051] A first oxide layer 104 is deposited on the P-type layer 101. A first mask and etch process is used to form a first window 105. A pattern of polysilicon is then deposited over the window 105 and the first oxide layer 104, providing a polysilicon layer 107. Using a second mask, the polysilicon material is doped with P dopants and diffused downward to form portion 106A and the collector-base diode junction 5 in the epitaxial layer 101. The implantation of the P dopants is followed by a short anneal, e.g., for 10 seconds, to restore the crystalline structure of the polysilicon and silicon wafer.

[0052] A second oxide layer 108 is deposited over the first oxide layer 104 and the polysilicon layer including the P-type region 106. A second mask and etch process is used to form a second window 111 through the first oxide layer 104 and the second oxide layer 108. A metal layer 110 is deposited over the second oxide layer 108 including the second window 111 to form a Schottky junction with the base region 102, and conductive tracks are formed over the second oxide layer 108 to interconnect the base to circuitry.

[0053] Additionally, the backside of the substrate is metallized to form a layer 112 that provides the emitter terminal E.

[0054] 2A and 2B show an alternative embodiment in which the emitter terminal E is provided on the same side of the substrate 100 as the emitter and collector terminals.

[0055] Metal contact 112 on the second side of the semiconductor die is omitted, and instead a metal region 113 formed through third window 114 through first oxide layer 104 and second oxide layer 108 is provided, directly interfacing with P+ region 115 that extends through P-type layer 101 and into P substrate 100 to provide the emitter contact. A portion of metal region 113A extends over the oxide layer to provide a trace for connecting the emitter to circuitry. P+ region 115 is laterally spaced from base region 102, separated by portion 101B of P-type layer 101.

[0056] P+ region 115 may be formed through an additional implantation and diffusion step using an additional mask. Metal region 113 may be deposited using the same processing steps used to deposit metal layer 110.

[0057] The P-type layer 101 is preferably formed using epitaxy because the layer thickness can be controlled very precisely, however, in principle it could also be formed by doping the substrate with N dopants, provided that precise and sufficient control of the doping is possible.

[0058] The emitter region of either embodiment may be common to multiple integrated transistor devices. Figure 3 shows an implementation of two transistors based on the semiconductor structure of Figures 2A and 2B.

[0059] Using the fabrication methods described above, a plurality of separate annular N-type regions 102X, 102Y are formed laterally spaced apart across the P-type layer 101. Separate channels 101AX, 101AY are provided through each, and separate collector regions 106X, 106Y are formed over each. The substrate 100 and P+ region 115 provide a common emitter for both transistors.

[0060] It will be appreciated that the embodiment of Figures 1A and 1B may be similarly modified to provide multiple separate vertical transistors that share a common emitter region.

[0061] In any of the above-described embodiments, the substrate 101 may be provided by a semiconductor wafer and / or a further epitaxial layer.

[0062] In a variation on any of the above examples, N-type base region 102 may include an N+ subregion having a higher N-type net doping concentration, e.g., about 1e18 / cm3 or 1e19 / cm3, directly interfacing with metal layer 110. This variation may be preferred if an ohmic contact to base region 3 is desired instead of a Schottky diode. In this case, metal layer 110 may be substituted with a polysilicon layer.

[0063] In a variant, substrate 100 is used as the collector region and P-type region 106 is used as the emitter, but this arrangement is less preferred if it is desired to have multiple transistors share a common emitter.

[0064] N-type subregion 3A does not have to extend completely through epitaxial layer 101. This may be necessary if epitaxial layer 101 is thicker than the desired spacing between the emitter and collector. This may degrade transistor performance, but may be acceptable if a very small base width is desired.

[0065] It will be appreciated that various of the above-described devices may alternatively be implemented as NPN devices having N-type channel, emitter and collector regions, and P-type base sub-regions.

[0066] Operation Mode Referring to FIG. 4, the operating characteristics or modes of operation of a device described in connection with any of FIGS. 1-3 vary depending on the voltage between the collector and emitter terminals (Vce) and the voltage between the base and emitter terminals (Vbe).

[0067] PNP devices, such as those shown in Figure 1, typically operate with a negative Vce, regardless of the operating mode. This means that the voltage applied to the collector will be more negative than the voltage applied to the emitter, and Vbe will be either positive or negative, with a negative base-emitter junction forward threshold voltage, Vft. All currents through the base terminal will be negative (in other words, current is pulled through the base terminal). In contrast, NPN devices typically operate with a positive Vce, have a positive Vft, and all currents through the base will be positive (in other words, current is pushed into the device through the base).

[0068] Five modes of operation are shown: K, J, L, M, and N. When the device is off and no current is flowing through any of the terminals, the device is operating in region K. When the device is on, the device can operate in one of modes J, L, M, and N.

[0069] When the device is on (i.e., current flows between the collector and emitter) and there is no or negligible current through the base terminal (i.e., Ib = 0 A), excluding momentary switching currents due to capacitive effects, the device is operating in region L or M. When the device is on (i.e., current between the collector and emitter is non-zero) and there is current through the base terminal (i.e., Ib < 0 A), the device is operating in region J or N.

[0070] Operation when |Vce|<|Vt| When the transistor device 1 operates at |Vce| which is smaller than |Vt|, the transistor device 1 functions as a normally-off device. That is, when Vbe is zero, no current flows between the emitter 2 and the collector 3 (the device is off (operating in the (K) region)).

[0071] Increasing |Vbe| so that the base-emitter diode junction 5B is forward biased (i.e., for a PNP transistor, Vbe becomes more negative than -Vft, and for an NPN transistor, Vbe becomes more positive than Vft) causes the device to switch on and operate in the on-majority bipolar region J, where current is drawn through the base terminal and most of the current between the collector and emitter results from bipolar conduction.

[0072] Alternatively, if |Vbe| is increased in the opposite direction so that the base-emitter diode junction 5B becomes more reverse biased (i.e., for a PNP transistor, Vbe becomes more positive, and for an NPN transistor, Vbe becomes more negative), the device remains off (operating in region (K)).

[0073] When |Vce| is greater than |Vt'| but less than |Vt|, the device behaves similarly to when |Vce| is less than |Vt'|, except when |Vbe| approaches |Vft| but is less than |Vft|, the device enters the on-majority unipolar operation region L, where the device is on and the current through the base terminal is zero, resulting in most of the current flow between the collector and emitter being unipolar.

[0074] When |Vbe| becomes larger than |Vft|, this enters the transition region N where the unipolar conduction current is maximum, and the bipolar conduction current increases until it becomes larger than the unipolar conduction current, and the device operates in the on-majority bipolar conduction region J.

[0075] Advantageously, the normally-off device can be switched on and operated in the L region at a lower Vbe than existing BJTs, advantageously below the forward voltage (Vft) of the base-emitter diode junction. When operating in the L region, the device has significantly higher current gain, but a lower maximum collector current magnitude than when operating in the J region at the same Vce. Because the Vbe is significantly lower, the device has significantly higher current gain when operating in the L region than existing BJTs, and because the current through the base terminal is essentially zero, the gain approaches infinity.

[0076] Operation when |Vce|>|Vt| When transistor device 1 operates at a threshold voltage |Vce| that is greater than |Vt|, transistor device 1 functions as a always-on device, i.e., when Vbe is zero, more than a small amount of current flows between the emitter and collector, for example, because the base terminal is floating or connected to the emitter.

[0077] When |Vce| is greater than |Vt| and |Vbe| is at or near zero, the transistor operates in the on-majority unipolar region M, where the current through the base terminal is zero and most of the current between the collector and emitter results from unipolar conduction.

[0078] When |Vbe| becomes greater than Vft and the base-emitter diode junction 5B becomes forward biased (i.e., for a PNP transistor, Vbe becomes more negative than -Vft, and for an NPN transistor, Vbe becomes more positive than Vft), the device operates in transition region N, where unipolar conduction is greatest and bipolar conduction is increasing. As |Vbe| increases further, the fraction of Ice that can result in bipolar conduction becomes greater than the fraction of Ice that results in unipolar conduction current, and operation becomes on-majority bipolar (region J).

[0079] The magnitude of Vbe required to operate in the J region increases as the magnitude of Vce increases.

[0080] Alternatively, increasing |Vbe| in the reverse direction so that the base-emitter diode junction 5B becomes more reverse biased (i.e., for a PNP transistor, Vbe becomes more positively biased, and for an NPN transistor, Vbe becomes more negatively biased) will switch the device off (operate in region K).

[0081] Between the off region K and the on-majority unipolar regions L and M is the transition region O, where device behavior is unpredictable or difficult to control. For example, if the collector current in the off region K is less than 1 nA and the collector current in the on regions L and M is approximately 1 μA or greater, the collector current in the transition region O will be approximately 10 nA to 100 nA.

[0082] Device 1 has collector region 2 and emitter region 3 separated by a distance X (see Figure 1) that defines the length of channel 4B. The values ​​of Vt and Vt' are related to the separation X between the emitter and collector regions. As the value of X increases, the magnitudes of |Vt| and |Vt'| increase. The maximum value of X is typically 1.5 microns to ensure that the device has good bipolar conduction characteristics when operating in the J region.

[0083] The nominal operating voltage range of a circuit defines the range of Vce values ​​that may be applied to the transistors within it. For a typical logic circuit in which this device is expected to be commonly employed, the nominal operating voltage range may be between 0V and |5V|.

Claims

1. 1. A transistor device comprising: a collector region provided by a first region of a first type semiconductor, a collector terminal associated with said collector region; an emitter region provided by a second region of the first type semiconductor, an emitter terminal associated with the emitter region; a base region provided by a third region of semiconductor located between the collector region and the emitter region and having an interface with both the collector region and the emitter region, a base terminal associated with the base region; and The base region is a subregion of a second type semiconductor; a channel of the first type semiconductor; Including, the base terminal contacts the sub-region; the subregion has an interface with the channel to provide a first diode junction and an interface with both the emitter region and the collector region to form respective second and third diode junctions; the channel has an interface with the collector region and the emitter region and is interconnected therewith; the channel has a net doping concentration lower than the net doping concentrations of the emitter region and the collector region, the channel extending a distance from the first diode junction; a separation of 1.5 microns or less between the collector region and the emitter region; the subregion surrounds the channel such that the interface between the subregion and the channel extends continuously around the channel; Transistor device.

2. a layer of a first type semiconductor having a net doping concentration lower than the first region of a first type semiconductor and located on the second region of the first type semiconductor; the subregion of the second type semiconductor extends completely through the semiconductor layer, the subregion comprising a through hole providing a core of the semiconductor layer for providing the channel; the first region of the first type semiconductor is at least partially provided by a polysilicon layer directly overlying the first type semiconductor layer; The transistor device of claim 1 .

3. 3. The transistor device of claim 2, comprising a plurality of transistors, wherein the second region of semiconductor of the first type provides a common emitter region for the plurality of transistors, a plurality of subregions of the second type extending through the semiconductor layer, each subregion being laterally spaced apart from other subregions around the periphery of the semiconductor layer, and a plurality of first regions of semiconductor of the first type, each of the plurality of first regions positioned so as to directly overlie one of the plurality of subregions.

4. 2. A method for manufacturing a transistor according to claim 1, comprising: (i) providing a substrate of a first semiconductor type and providing the emitter region or the collector region of the transistor; (ii) forming a first layer of the first semiconductor type on the substrate, the first layer having a lower net doping concentration than the substrate; (iii) forming a third region of the second semiconductor type extending through the first layer, interfacing with the substrate, surrounding and isolating a portion of the first layer from the remainder of the first layer, and providing the channel; (iv) forming a region of the first semiconductor type overlying the third region having a direct interface with both the third region and the channel; A method comprising:

5. The method of claim 4 , comprising forming the first layer on the substrate using epitaxy.

6. 6. The method of claim 4, further comprising depositing a polysilicon layer on the first layer and performing a mask and doping process to form the first semiconductor type region.

7. 7. The method of claim 4, 5, or 6, comprising forming the third region using a mask and doping process.

8. 8. The method of claim 6, further comprising: depositing a first oxide layer on the first layer; forming a first window through the first oxide layer directly overlying the third region and the channel; and depositing the polysilicon layer on the first layer through the first window.

9. 9. The method of claim 8, comprising depositing a second oxide layer overlying the polysilicon layer and the first oxide layer, forming a second window through the first oxide layer and the second oxide layer directly overlying the third region, and depositing a metal or semiconductor material onto the third region through the second window to form a base contact.

10. 10. A method according to any preceding claim, wherein the first layer is provided on a first side of the substrate and the emitter terminal is formed on an opposite second side of the substrate.

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