Semiconductor device termination structure and method for fabricating a semiconductor device termination structure

Abstract

In one example, the semiconductor device (10) includes an active trench region (22A) and intersecting trench regions (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A), and the intersecting trench regions (22C, 22CA, 22CB) include intersecting shield electrodes (21C, 21C'). The connecting trench regions (22B, 22B', 22BA) connect the active trench region (21A) to the intersecting trench regions (22C, 22CA, 22CB). The connecting trench regions (22B, 22B', 22BA) include intersecting shield electrodes (21B, 21B'). Linking shield electrodes (21B, 21B') and crossing shield electrodes (21C, 21C') are provided adjacent to the termination mesa regions (16B, 16B', 16B"). One or more of the linking shield electrodes (21B, 21B') or crossing shield electrodes (21C, 21C') are thinner than the active shield electrode (21A). Thinner shield electrodes reduce depletion in the termination mesa regions, improving, among other things, breakdown voltage performance.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority from U.S. Provisional Application No. 63 / 375,073, filed September 9, 2022, which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE INVENTION The present disclosure relates generally to electronic devices, and more particularly to semiconductor device termination structures and methods of forming semiconductor devices having termination structures, such as shielded gate trench MOSFET devices. [Background technology]

[0003] As the size of semiconductor devices, such as shielded gate trench metal oxide field effect transistor (MOSFET) devices, decreases, it becomes difficult to integrate additional shield contact structures within the MOSFET cell topography to achieve reduced shield electrode resistance without adversely affecting other MOSFET characteristics. Low shield resistance is desirable to provide MOSFETs with low gate bounce, excellent unclamped inductive switching (UIS) performance, and higher operating efficiency. For proper device function, structures and methods are desired that facilitate reduced shield resistance without adversely affecting the device's breakdown voltage. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a partial top view of an exemplary cell topography of a semiconductor device according to the present description. [Figure 2] 2A-2C show partial cross-sectional views of the semiconductor device of FIG. 1, the semiconductor device of FIG. 4, the semiconductor device of FIG. 5, and the semiconductor device of FIG. 7A taken along reference line 2'-2', in accordance with the present description. [Figure 3]3A and 3B show partial cross-sectional views of the semiconductor device of FIG. 1 and the semiconductor device of FIG. 4 taken along reference line 3'-3' according to the present description. [Figure 4] 1 illustrates a partial top view of an example cell topography of a semiconductor device according to the present description. [Figure 5] 1 illustrates a partial top view of an example cell topography of a semiconductor device according to the present description. [Figure 6A] 6 shows an enlarged partial top view of portion 6A' referred to in FIG. 1 according to the present description. [Figure 6B] 6B shows an enlarged partial top view of portion 6B' referred to in FIG. 4 according to the present description. [Figure 6C] 6 shows an enlarged partial top view of portion 6C' referred to in FIG. 5 according to the present description. [Figure 7A] 1 illustrates a partial top view of an example cell topography of a semiconductor device according to the present description. [Figure 7B] 7B' is a partial cross-sectional view of the semiconductor device of FIG. 7A taken along reference line 7B'-7B'. [Figure 8A] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8B] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8C] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8D] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8E] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8F] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8G] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8H] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8I]1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8J] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8K] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8L] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8M] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 8N] 1A-1D show partial cross-sectional views of a semiconductor device according to the present description at various stages of fabrication; [Figure 9A] 9A'-9A' show partial cross-sectional views of the semiconductor device of FIG. 1 and the semiconductor device of FIG. 7A, according to the present description. [Figure 9B] 9B'-9B' show partial cross-sectional views of the semiconductor device of FIG. 4, the semiconductor device of FIG. 5, and the semiconductor device of FIG. 7A, according to the present description.

[0005] The following description provides various examples of semiconductor devices and methods for fabricating semiconductor devices. Such examples are non-limiting, and the scope of the appended claims is not limited to the disclosed examples. In the following description, the terms "example" and "for example" are non-limiting.

[0006] For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, the same reference numbers in different figures refer to the same elements, and descriptions and details of well-known steps and components have been omitted for simplicity of description.

[0007] For clarity of the drawings, certain regions of the device structures, such as doped regions, dielectric regions, or trench regions, may be shown as having generally straight edges and precisely angled corners, however, those skilled in the art will understand that due to the diffusion and activation of dopants or layer formation, the edges of such regions may not be generally straight and the corners may not be precisely angled.

[0008] Although semiconductor devices are described herein as having particular N-type conductivity regions and particular P-type conductivity regions, those skilled in the art will understand that the conductivity types can be reversed and that any necessary polarity reversals of voltages, transistor types and / or current directions, etc., are possible in accordance with this description.

[0009] Additionally, the terminology used herein is for the purpose of describing examples only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0010] As used herein, a "current-carrying electrode" means an element of a device that allows current to flow through the device, e.g., the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and a "control electrode" means an element of a device that controls current flow through the device, e.g., the gate of a MOS transistor or the base of a bipolar transistor.

[0011] The term "major surface" when used with respect to a semiconductor region, wafer, or substrate means a surface of the semiconductor region, wafer, or substrate that forms an interface with another material, e.g., a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. A major surface may have a topography that varies in the x, y, and z directions.

[0012] The terms "comprises," "comprising," "includes," "including," "has," "have," and / or "having," as used herein, are open-ended terms that specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0013] The term "or" means any one or more of the items in the list joined by "or." As an example, "x or y" means any element of the 3-element set {(x), (y), (x,y)}. As another example, "x, y, or z" means any element of the 7-element set {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0014] Terms such as "first," "second," and the like may be used herein to describe various members, elements, regions, layers, and / or sections, but these members, elements, regions, layers, and / or sections are not intended to be limited by these terms. These terms are used only to distinguish one member, element, region, layer, and / or section from another. Thus, for example, a first member, first element, first region, first layer, and / or first section described below could be referred to as a second member, second element, second region, second layer, and / or second section without departing from the teachings of the present disclosure.

[0015] Those skilled in the art will recognize that the terms "during," "while," and "when," as used herein with respect to circuit operation, are not precise terms meaning that an action occurs immediately based on an initiating action, but rather that there may be some small, reasonable delay, e.g., a propagation delay between responses initiated by the initiating action. Furthermore, the term "while" means that a particular action occurs within at least a portion of the duration of the initiating action.

[0016] The use of the words "about," "approximately," or "substantially" means that the value of an element is expected to be close to a stated value or location. However, as is well known in the art, there are usually small variations that prevent the value or location from being exactly as stated.

[0017] Unless otherwise specified, as used herein, the terms "over" or "on" include an orientation, arrangement, or relationship in which the specified elements may be in direct or indirect physical contact.

[0018] Unless otherwise specified, as used herein, the term "overlapping" includes an orientation, arrangement, or relationship in which the specified elements are at least partially or completely coincident or aligned in the same or different planes.

[0019] It will be further understood that the examples shown and described below as suitable may have other elements not specifically disclosed herein and / or may be practiced in the absence of any element not specifically disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0020] Insulated gate field effect transistors (IGFETs), such as metal-oxide semiconductor field effect transistors (MOSFETs), have been used in many power switching applications, such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control upon application of an appropriate gate voltage. As an example, in an N-type enhancement-mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., channel region) forms in the P-type body region in response to the application of a positive gate voltage above its characteristic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region, allowing majority carrier conduction between these regions.

[0021] There is a class of MOSFET devices called trench MOSFET devices. In trench MOSFET devices, the gate electrode is formed in a trench that extends downward (e.g., vertically downward) from a major surface of a semiconductor material such as silicon. Additionally, a shield electrode may be formed below the gate electrode in the trench and insulated by one or more dielectrics. Current flow in trench MOSFET devices is primarily vertical (e.g., in an N-type conductivity doped drift region), resulting in device cells being more densely packed.

[0022] A device cell may include, for example, a trench containing a gate electrode and an adjacent mesa containing the drain, source, body, and channel regions of the device. An exemplary trench MOSFET device may include an array of hundreds or thousands of device cells (each including a trench and an adjacent mesa). The device cells may be referred to herein as trench-mesa cells because each device cell geometrically includes a trench structure and a mesa structure (or two half mesas).

[0023] Packing several device cells together increases the current carrying capability and reduces the on-resistance of the device. In addition, in trench MOSFET devices that include a shield electrode, the shield electrode may require low shield resistance to provide, among other things, low gate bounce, excellent unclamped inductive switching performance, and higher efficiency in applications. However, as next-generation trench MOSFETs target cell pitches of less than 1 micron (e.g., about 0.65 μm) and mesa widths of about half the target cell pitch (e.g., about 0.32 μm), such feature size reduction results in increased shield resistance.

[0024] One approach to reducing shield resistance is to provide multiple shield electrode contacts along the length of the trench between the two gate feeds. One drawback of this approach is that it requires a cut in the gate feed layer, thus making it impossible to efficiently add shield contacts between the two gate feeds. Another approach to address this issue is to include a cross-trench region oriented perpendicular to the active trench region with both the gate feed and shield feed layers, with the gate feed pass-through trench within the shield contact area of ​​the cell. However, in some MOSFET devices, such as medium-voltage MOSFET devices (e.g., voltages from about 30 to about 80 volts), the cross-trench region can reduce the breakdown voltage (BV), resulting from, for example, charge imbalance and a three-dimensional depletion region. DSS ) may cause performance degradation.

[0025] This BV DSS Solutions to address the performance issues are described herein. The present disclosure describes structures and cell topographies that address, among other things, the charge imbalance and three-dimensional depletion region issues associated with crossing trenches in power MOSFET devices.

[0026] In one example, a semiconductor device includes a region of semiconductor material. A first active trench region extends inward into the region of semiconductor material and includes an active shield electrode in the first active trench region separated from the region of semiconductor material by an active shield electrode dielectric. A second active trench region extends inward into the region of semiconductor material and is laterally spaced apart from and parallel to the first active trench region and includes an active shield electrode in the second active trench region separated from the region of semiconductor material by an active shield electrode dielectric. An intersection trench region extends inward into the region of semiconductor material and is perpendicular to the first and second active trench regions. A first connecting trench region connects the first active trench region to the intersection trench region. The first connecting trench region includes a connecting shield electrode in the first connecting trench region separated from the region of semiconductor material by a connecting shield electrode dielectric. A second connecting trench region connects the second active trench region to the intersection trench region, and the second connecting trench region includes a connecting shield electrode in the second connecting trench region separated from the region of semiconductor material by a connecting shield electrode dielectric, the active shield electrode having a first thickness in the first cross-sectional view, and the connecting shield electrode having a second thickness in the first cross-sectional view, the second thickness being less than the first thickness.

[0027] In one example, a semiconductor device includes a top surface and a region of semiconductor material having a first conductivity type. A first active trench region including an active shield electrode within the region of semiconductor material and separated from the region of semiconductor material by an active shield electrode dielectric. A cross trench region within the region of semiconductor material, perpendicular to the first active trench region, and including a cross shield electrode separated from the region of semiconductor material by a cross shield electrode dielectric. A first connecting trench region within the region of semiconductor material including a connecting shield electrode connecting the first active trench region to the cross trench region and separated from the region of semiconductor material by a connecting shield electrode dielectric. The active shield electrode has a first thickness in a first cross-sectional view, the connecting shield electrode has a second thickness in the first cross-sectional view, and the cross shield electrode has a third thickness in a second cross-sectional view, wherein one or more of the second thickness or the third thickness is less than the first thickness.

[0028] In one example, a method for manufacturing a semiconductor device includes providing a region of semiconductor material. The method includes providing a first active trench region extending inward into the region of semiconductor material, the first active trench region including an active shield electrode in the first active trench region separated from the region of semiconductor material by an active shield electrode dielectric. The method also includes providing a second active trench region extending inward into the region of semiconductor material, laterally spaced from and parallel to the first active trench region, the second active trench region including an active shield electrode separated from the region of semiconductor material by the active shield electrode dielectric. The method also includes providing an intersection trench region extending inward into the region of semiconductor material and perpendicular to the first and second active trench regions. The method also includes providing a first connecting trench region connecting the first active trench region to the intersection trench region and including a connecting shield electrode separated from the region of semiconductor material by the connecting shield electrode dielectric. The method includes providing a second coupling trench region that couples the second active trench region to the intersection trench region and includes a coupling shield electrode in the second coupling trench region that is separated from the region of semiconductor material by a coupling shield electrode dielectric, the active shield electrode having a first thickness in a first cross-sectional view, and the coupling shield electrode having a second thickness in the first cross-sectional view, the second thickness being less than the first thickness.

[0029] This disclosure also includes other examples, which may be found in the drawings, claims, or description of this disclosure.

[0030] FIG. 1 illustrates a partial top view of a cell topography 100 of a semiconductor device 10 according to the present description. FIG. 2 illustrates a partial cross-sectional view of the semiconductor device 10 along reference line 2'-2' of FIG. 1 , including an active trench region 22A that bounds the active mesa region 16A, and FIG. 3 illustrates a partial cross-sectional view of the semiconductor device 10 along reference line 3'-3' of FIG. 1 , including a connecting trench region 22B that bounds the termination mesa region 16B. FIG. 9A illustrates a partial cross-sectional view of the semiconductor device 10 along reference line 9A'-9A' of FIG. 1 , including an intersection trench region 22CA. The cell topography 100 may also be referred to as a device layout or cell layout, and the semiconductor device 10 may also be referred to as a semiconductor component, an electronic device structure, or an electronic component. In some examples, the cell topography 100 is suitable for medium-voltage devices, such as 30-80 volt MOSFET devices. However, the structures and methods described herein are relevant to structures that use charge-balanced structures or where three-dimensional depletion regions are an issue.

[0031] According to this description, the semiconductor device 10 has a plurality of shield contact trenches 210 each having a breakdown voltage (BV DSS ) while maintaining a low conductivity. Although semiconductor device 10 is shown as an N-channel MOSFET device, it is understood that the described structures and methods may be used with other types of semiconductor devices, such as insulated gate bipolar transistor (IGBT) devices. In another example, semiconductor device 10 may be a P-channel MOSFET device by reversing the conductivity types of the various regions described below.

[0032] Cell topography 100 is shown as a half cell; a full cell can be provided by replicating the half cell shown and rotating it, for example, 180 degrees, relative to reference line 101, with the upper portion adjacent the lower portion along reference line 101. As known to those skilled in the art, cell topography 100 is replicated multiple times as part of a photolithographic reticle or mask set to provide the desired cell density in semiconductor device 10.

[0033] In this example, cell topography 100 includes active trench region 22A, connecting trench region 22B, and intersection trench region 22CA. Active trench region 22A is configured for the active region of semiconductor device 10, and connecting trench region 22B and intersection trench region 22CA are configured as part of the termination structure of semiconductor device 10. In some examples, intersection trench region 22CA is approximately perpendicular to active trench region 22A, and connecting trench region 22B connects active trench region 22A to intersection trench region 22CA. In this example, active trench region 22A has active trench region width 220A, connecting trench region 22B has connecting trench region width 220B, and intersection trench region 22CA has intersection trench region width 220CA. In this example, connecting trench region width 220B is smaller than active trench region width 220A and intersection trench region width 220CA. Active trench region 22A1 is an example of a first active region, active trench region 22A2 is an example of a second active trench region, connecting trench region 22B1 is an example of a first connecting trench region, and connecting trench region 22B2 is an example of a second connecting trench region. Second active trench region 22A2 is laterally spaced from and parallel to first active trench region 22A1. Connecting trench region 22B3 is an example of a third connecting trench region that connects shield contact trench 210 to intersection trench region 22CA. Connecting trench region 22B4 is an example of a connecting trench region that connects gate contact trench 218 to intersection trench region 22CA.

[0034] In the cell topography 100, the semiconductor device 10 is provided with a termination mesa region 16B that is disposed between adjacent connecting trench regions 22B (e.g., between the first connecting trench region 22B1 and the second connecting trench region 22B2) and abuts an intersection trench region 22CA that extends perpendicular to the connecting trench regions 22B. In addition, the semiconductor device 10 includes an active mesa region 16A that is disposed between adjacent active trench regions 22A (e.g., between the first active trench region 22A1 and the second active trench region 22A2). In this example, the termination mesa region 16B has a termination mesa width 16BB, and the active mesa region 16A has an active mesa region width 16AA. In this example, the active mesa region width 16AA is smaller than the termination mesa width 16BB. In some examples, the semiconductor device 10 includes a doped region 17 in a portion of the termination mesa region 16B. Doped region 17 is configured to control charge balance within termination mesa region 16B and can be either P-type or N-type conductivity.

[0035] The cell topography 100 includes a shield contact trench 210 and a gate contact trench 280. The multiple shield contact trenches 210 may also be referred to as multiple shield trenches, and the multiple gate contact trenches 280 may also be referred to as multiple gate trenches. In this example, the connection trench region 22B also connects the shield contact trench 210 and the gate contact trench 280 to the intersection trench region 22CA. The cell topography 100 also includes a body contact region 36 disposed between the active trench region 22A and the connection trench region 22B. The body contact region 36 is spaced apart from the active trench region 22A, the connection trench region 22B, and the intersection trench region 22CA.

[0036] Referring now to FIGS. 2, 3, and 9A, in some examples, semiconductor device 10 includes region 11 of semiconductor material, which may also be referred to as a body of semiconductor material, a semiconductor workpiece, a semiconductor region, or semiconductor material. As shown in FIGS. 2 and 3, in some examples, region 11 of semiconductor material may include substrate 12, such as an N-type silicon substrate, and semiconductor region 14 adjacent to substrate 12. Substrate 12 may also be referred to as a semiconductor substrate or starting substrate, and semiconductor region 14 may also be referred to as a semiconductor layer or extended drain region. In some examples, substrate 12 has a resistivity in the range of about 0.0005 ohm-cm to about 0.005 ohm-cm. By way of example, substrate 12 may be doped with phosphorus, arsenic, or antimony. In the illustrated example, substrate 12 provides a drain region, drain contact, or first current-carrying contact for semiconductor device 10. Region 11 of semiconductor material includes a major surface 18 and a major surface 19 opposite major surface 18. Major surface 18 may also be referred to as the top surface or upper side, and major surface 19 may also be referred to as the back surface or lower side.

[0037] In some examples, semiconductor region 14 can be formed using semiconductor epitaxial growth techniques. Alternatively, semiconductor region 14 can be formed using semiconductor doping and diffusion techniques. In an example suitable for a 50 volt device, semiconductor region 14 has N-type conductivity and a dopant concentration of approximately 1.0×10 16 atoms / cm 3 ~Approx. 5.0×10 17 atoms / cm 3 and may have a thickness of about 3 microns to about 5 microns. The dopant concentration and thickness of semiconductor region 14 are determined based on the desired drain-source breakdown voltage (BV) of semiconductor device 10. DSS ) rating. In some examples, semiconductor region 14 may include a graded dopant profile. In other examples, the conductivity type of substrate 12 may be opposite to that of semiconductor region 14, for example, to form an IGBT semiconductor device.

[0038] As shown in FIG. 2 , active trench regions 22A extend inward from major surface 18 into region 11 of semiconductor material and are separated from one another by active mesa regions 16A having active mesa width 16AA. Active trench regions 22A include active region shield electrodes 21A in central and lower portions of active trench regions 22A, with active region shield electrodes 21A separated from region 11 of semiconductor material by active shield dielectric 24A. In some examples, active shield electrodes 21A include a stepped shape in cross section, as shown in FIG. 2 . In other examples, active shield electrodes 21A may include other shapes, including, but not limited to, sloped, linear, or non-stepped shapes. Active trench regions 22A also include an active gate electrode 28A at the top of active trench regions 22A, with active gate electrode 28A separated from active shield electrode 21A by inter-electrode dielectric 27. Active gate electrode 28A is laterally separated from region 11 of semiconductor material by gate dielectric 26. The active shield electrode 21A has an active shield electrode thickness 216A, which may also be referred to as an active shield electrode height. In some examples, the active mesa region 16A is located between the first active trench region 22A1 and the second active trench region 22A2.

[0039] Referring briefly to FIG. 9A , intersecting trench region 22CA extends inward from major surface 18 into region 11 of semiconductor material. Intersecting trench region 22CA includes intersecting shield electrodes 21C in a central and lower portion of the intersecting trench region, with intersecting shield electrodes 21C separated from region 11 of semiconductor material by intersecting shield dielectric 24C. Intersecting trench region 22CA also includes intersecting gate electrodes 28C separated from intersecting shield electrodes 21C by inter-electrode dielectric 27. Intersecting gate electrodes 28C are laterally separated from region 11 of semiconductor material by gate dielectric 26. Intersecting shield electrodes 21C have intersecting shield electrode thickness 216C, which may also be referred to as intersecting shield electrode height. In this example, active shield electrode 21A and intersecting shield electrode 21C may be similar, including being similar in size and shape. In some examples, active shield electrode thickness 216A and intersecting shield electrode thickness 216C are substantially equal. Active shield electrode thickness 216A is an example of a first thickness, and cross shield electrode thickness 216C is an example of a third thickness.

[0040] In some examples, active shield electrode thickness 216A ranges from about 0.8 microns to about 10 microns. In some examples, connecting shield electrode thickness 216B ranges from about 0.5 microns to about 5 microns. In some examples, cross shield electrode thickness 216C ranges from about 0.5 microns to about 10 microns.

[0041] Referring now to FIG. 3 , the linking trench regions 22B extend inward from the major surface 18 into the region 11 of semiconductor material and are separated from each other by the termination mesa region 16B having a termination mesa width 16BB. That is, the termination mesa region 16B is located between the first linking trench region 22B1 and the second linking trench region 22B2. As shown in FIG. 1 , the termination mesa region 16B abuts or is adjacent to the intersection trench region 22CA. The linking trench region 22B includes a linking shield electrode 21B in a central or intermediate portion of the linking trench region 22B and is separated from the region 11 of semiconductor material by a linking shield dielectric 24B. The linking trench region 22B also includes a linking gate electrode 28B at the top of the linking trench region 22B, the linking gate electrode 28B being separated from the linking shield electrode 21B by an inter-electrode dielectric 27. In some examples, the linking gate electrode 28B is laterally separated from the region 11 of semiconductor material by a gate dielectric 26. According to this description, the linking shield electrode 21B includes a linking shield electrode thickness 216B that is smaller than the active shield electrode thickness 216A. The linking shield electrode thickness 216B is an example of a second thickness. In this example, the linking shield electrode thickness 216B is also smaller than the crossing shield electrode thickness 216C. The linking shield electrode thickness 216B may also be referred to as the linking shield electrode height. According to this example, the linking shield electrode 21B is located within the central portion of the linking trench region 22B but not within the lower portion of the linking trench region 22B. In other words, the linking shield electrode 21B is not present in the lower portion of the linking trench region 22B.

[0042] It has been experimentally observed that when the intersection trench region 22CA intersects with the active trench region 22A without the connecting trench region 22B and the connecting shield electrode 21B, a three-dimensional depletion region is formed in the active trench region 22A away from the intersection trench region 22CA, compared to a two-dimensional depletion region. The three-dimensional depletion results in a lower BV in the termination mesa region 16B. DSSIn accordance with this example and description, connecting trench region 22B with a thinner or shorter connecting shield electrode 21B near its intersection with intersection trench region 22CA modifies the depletion region within termination mesa region 16B. In some instances, a thinner connecting shield electrode 21B reduces the depletion caused by a thicker shield electrode, which results in a higher BV DSS results.

[0043] In some examples, the active gate electrode 28A, the connecting gate electrode 28B, and the termination gate electrode 28C are connected together and may comprise the same material, such as a doped polycrystalline semiconductor material. In some examples, the active shield electrode 21A, the connecting shield electrode 21B, and the crossing shield electrode 21C are connected together and may comprise the same material, such as a doped polycrystalline semiconductor material. In some examples, the doped polycrystalline semiconductor material may be doped polysilicon. In some examples, an N-type conductivity dopant material may be used to dope the polysilicon. In some examples, a metal, silicide, or other conductor may be included as part of the active gate electrode 28A, the connecting gate electrode 28B, the crossing gate electrode 28C, the active shield electrode 21A, the connecting shield electrode 21B, or the crossing shield electrode 21C.

[0044] The active shield dielectric 24A, the linking shield dielectric 24B, and the cross shield dielectric 24C can be one or more dielectric or insulating materials. In some examples, the active shield dielectric 24A and the linking shield dielectric 24B can be thermal oxide layers of about 0.1 microns to about 1.5 microns. In some examples, the active shield dielectric 24A, the linking shield dielectric 24B, and the cross shield dielectric 24C can be multiple layers of similar or different materials, such as thermally deposited dielectric or insulating materials. The thickness of the shield dielectrics can be determined based on the required BV of the device. DSS Varies depending on BV DSS requires a thicker layer.

[0045] The gate dielectric 26 and the inter-electrode dielectric 27 may comprise oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 and the inter-electrode dielectric 27 may be silicon oxide. In some examples, the gate dielectric 26 may have a thickness of about 0.02 microns to about 0.1 microns, and the inter-electrode dielectric 27 may have a thickness greater than that of the gate dielectric 26. In some examples, the active shield dielectric 24A, the link shield dielectric 24B, or the cross shield dielectric 24C may have a thickness greater than that of the gate dielectric 26 and the inter-electrode dielectric 27.

[0046] As further shown in FIGS. 2, 3, and 9A, semiconductor device 10 includes a body region 31 extending inward from major surface 18 into region 11 of semiconductor material adjacent active trench region 22A (e.g., extending inward into semiconductor region 14). Body region 31 may also be referred to as a doped region or a base region. Body region 31 may have a conductivity type opposite that of semiconductor region 14. For example, when semiconductor region 14 comprises N-type conductivity, body region 31 comprises P-type conductivity. Body region 31 includes a dopant concentration suitable for forming an inversion layer that acts as channel region 45 of semiconductor device 10. In some examples, body region 31 may extend from major surface 18 to a depth of about 0.3 microns to about 1.5 microns. Body region 31 may be formed using doping techniques, such as ion implantation and annealing techniques. In some examples, body region 31 is a single, continuous, interconnected region. In other examples, the body region 31 may be multiple regions including isolated regions.

[0047] 2 and 3, the semiconductor device 10 may further include a doped region 33 in the body region 31 in the active mesa region 16A. In some examples, the doped region 33 may be optionally included in the body region 31 in the termination mesa region 16B. That is, in some examples, the doped region 33 is not included in the body region 31 in the termination mesa region 16B, such that the termination mesa region 16B does not have the doped region 33. The doped region 33 may also be referred to as a source region, a current carrying region, or a current conducting region. The doped region 33 comprises N-type conductivity when the body region 31 comprises P-type conductivity, and may be formed using, for example, a phosphorus or arsenic dopant source. In some examples, the doped region 33 may be formed in the body region 31 using an ion implantation doping process. The doped region 33 may extend from the major surface 18 to a depth of, for example, about 0.2 microns to about 0.5 microns.

[0048] 3 and 9A, in some examples, doped region 17 is included within termination mesa region 16B. In some examples, doped region 17 has the same conductivity type as semiconductor region 14 (e.g., N-type conductivity). In other examples, doped region 17 has the opposite conductivity type to semiconductor region 14 (e.g., P-type conductivity). In some examples, the peak dopant concentration of doped region 17 can be higher than the peak dopant concentration of semiconductor region 14. In some examples, the peak dopant concentration can be about 20 percent to about 150 percent higher than the peak dopant concentration of semiconductor region 14. In some examples, doped region 17 can be formed using an ion implantation process and an annealing process. In other examples, the arrangement and shape of doped region 17 can be different from those shown in FIGS. 3 and 9A. For example, doped region 17 can be larger or smaller and / or can be in different portions of termination mesa region 16B. In other examples, doped region 17 can include multiple, differentially doped portions. The dimensions and dopant concentration of doped region 17 are determined based on the desired BV for semiconductor device 10. DSSThis can be used in conjunction with other features of the present description, including a shorter connecting shield electrode 21B, to provide this feature.

[0049] In some examples, the semiconductor device 10 further includes an interlayer dielectric (ILD) 41 above the active gate electrode 28A, above the connecting gate electrode 28B, and above the crossover gate electrode 28C. In some examples, the interlayer dielectric 41 includes silicon oxide, such as doped or undoped deposited silicon oxide. In some examples, the interlayer dielectric 41 may include one layer of deposited silicon oxide doped with phosphorus or boron and phosphorus, and one layer of undoped oxide. In some examples, the interlayer dielectric 41 may have a thickness of about 0.25 microns to about 1.0 micron. In some examples, the interlayer dielectric 41 may be planarized to provide a more uniform surface topography, which improves manufacturability.

[0050] In some examples, the semiconductor device 10 further includes a body contact region 36 in the body region 31. The body contact region 36 may also be referred to as a doped region, an enhancement region, or a contact region. In some examples, the body contact region 36 may include P-type conductivity and be configured to provide a lower contact resistance to the body region 31. The body contact region 36 may be formed using ion implantation techniques (e.g., using boron) and annealing techniques.

[0051] In some examples, the semiconductor device 10 further includes a conductive region 43 configured to provide electrical contact to the doped region 33 and the body region 31 via the body contact region 36. The active gate electrode 28A, the connecting gate electrode 28B, and the crossing gate electrode 28C can be connected to one or more gate contact trenches 280, and the active shield electrode 21A, the connecting shield electrode 21B, and the crossing shield electrode 21C can be connected to one or more shield contact trenches 210. In some examples, the conductive region 43 includes a conductive plug or plug structure. In some examples, the conductive region 43 can include a conductive barrier structure or liner and a conductive fill material. In some examples, the barrier structure can include a metal / metal nitride structure, such as titanium / titanium nitride, or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure can further include a metal silicide structure. In some examples, the conductive fill material includes tungsten. In some examples, the conductive region 43 can be planarized to provide a more uniform surface topography.

[0052] In some examples, conductor 44 may be formed adjacent to major surface 18, and conductor 46 may be formed adjacent to major surface 19. Conductor 44 may also be referred to as a top metal or top conductor, and conductor 46 may also be referred to as a bottom conductor or backside metal. Conductors 44 and 46 may be configured to provide electrical connections between individual cells of semiconductor device 10 and the next level of assembly. In some examples, conductor 44 comprises titanium / titanium nitride / aluminum-copper or other related or equivalent materials known to those skilled in the art and is configured as a source electrode or terminal. In some examples, conductor 46 comprises a solderable metal structure, such as titanium-nickel-silver, chromium-nickel-gold, or other related or equivalent materials known to those skilled in the art and is configured as a drain electrode or terminal. In some examples, an additional passivation layer (not shown) may be formed adjacent to conductor 44. In some examples, active shield electrode 21A, linking shield electrode 21B, and cross shield electrode 21C may be connected to conductor 44 such that active shield electrode 21A, linking shield electrode 21B, and cross shield electrode 21C are configured to be at the same potential as doped region 33 when semiconductor device 10 is in use. In other examples, active shield electrode 21A, linking shield electrode 21B, or cross shield electrode may be configured to be partially independently biased or coupled to gate contact trench 280.

[0053] 6A shows an enlarged, partial top view of portion 6A' of cell topography 100 of FIG. 1. In some examples, body contact region 36 includes tip region 360 within termination mesa region 16B. Tip region 360 includes side 361, side 362 opposite side 361, and end 363 connecting side 361 to side 362. End 363 may also be referred to as the distal end or outermost end of body contact region 36 relative to active mesa region 16A. Side 361 may be an example of a first side, and side 362 may be an example of a second side.

[0054] Side 361 is laterally spaced a distance 361A from first connection trench region 22B1, side 362 is laterally spaced a distance 362A from second connection trench region 22B2, and end 363 is laterally spaced a distance 363A from intersection trench region 22CA. Body contact region 36 is laterally spaced a distance 36A from first active trench region 22A1 (which is also the distance between body contact region 36 and second active trench region 22A2). In this example, distances 361A, 362A, and 363A are greater than distance 36A. In this example, termination mesa region width 16BB of termination mesa region 16B is greater than active mesa region width 16AA of active mesa region width 16A. This results in a higher concentration of charge in the termination mesa region 16B in the tip region 360, making charge balancing in the semiconductor device 10 easier and reducing the BV DSS Further improve performance.

[0055] In one example, operation of semiconductor device 10 may proceed as follows: conductor 44 and shield electrodes 21A, 21B, and 21C are at a potential V S When operating at 10 V, gate electrodes 28A, 28B, and 28C are coupled to a control voltage V of 10 volts, which is greater than the conduction threshold of semiconductor device 10. G and the drain electrode (or output terminal) 46 receives a drain potential V less than 2.0 volts. D It works with V G and V S The value of I causes body region 31 to invert adjacent gate electrode 28 to form channel region 45, which electrically connects doped region 33 to semiconductor region 14 in active mesa region 16A. DS flows from conductor 46 and is delivered to conductor 44 through semiconductor region 14, channel region 45, and doped region 33. In some examples, I DS is approximately 10.0 amperes. To switch the semiconductor device 10 to the off state, a control voltage V G Such a control voltage clears the channel region 45 and causes I DSno longer flows through the semiconductor device 10. According to the present description, the configuration of the semiconductor device 10 described herein provides improved BV due to the structural attributes of the thinner or shorter connecting shield electrode 21B. DSS This achieves performance by reducing depletion in the termination mesa region and overcoming excess depletion adjacent to the intersection trench region. In addition, doped region 17 provides improved BV through charge balancing techniques. DSS Furthermore, the dimensions of the termination mesa region 16B support improved BV through charge balancing techniques. DSS Supports performance.

[0056] In another example, the length of the connecting trench region 22B is varied to change the BV DSS Performance can be further optimized. Additionally, doped regions 17 can be included to increase the drift region charge in the termination mesa region. BV DSS The dopant concentration of doped region 17 can be varied to optimize performance. Additionally, the lateral length of connection trench region 22B can be different from the lateral length of doped region 17. That is, some portions of connection trench region 22B adjacent to intersection trench region 22CA can have doped region 17, while other portions of connection trench region 22B adjacent to active trench region 22A can be free of doped region 17. These variations are discussed in detail in conjunction with the BV DSS These attributes can be used in any of the topographies described herein.

[0057] FIG. 4 shows a partial top view of a cell topography 200 of a semiconductor device 10 according to the present description. The cell topography 200 may also be referred to as a device layout or a cell layout. FIG. 2 shows a partial cross-sectional view of the semiconductor device 10 along reference line 2'-2' of the cell topography 200 of FIG. 4, including active trench regions 22A, and FIG. 3 shows a partial cross-sectional view of the semiconductor device 10 along reference line 3'-3' of the cell topography 200 of FIG. 4, including interconnect trench regions 22B. FIG. 9B shows a partial cross-sectional view of the semiconductor device 10 along reference line 9B'-9B' of the cell topography 200 of FIG. 4, including intersection trench regions 22CB. FIG. 6B shows an enlarged partial top view of portion 6B' of the cell topography 200. The cell topography 200 includes similar features to the cell topography 100, and these similar features will not be repeated here.

[0058] 4 and 9B, in this example, semiconductor device 10 includes intersection trench region 22CB having intersection trench region width 220CB. In some examples, intersection trench region width 220CB is smaller than active trench region width 220A. In some examples, intersection trench region width 220CB may be similar to linking trench region width 220B. At the reduced width, intersection trench region 22CB includes intersection shield electrode 21C' having intersection shield electrode thickness 216C' that is thinner than active shield electrode thickness 216A and may be similar to linking shield electrode thickness 216B. In some examples, intersection shield electrode thickness 216C' is equal to linking shield electrode thickness 216B. Intersection shield electrode thickness 216C' is an example of a third thickness, and linking shield electrode thickness 216C is an example of a second thickness.

[0059] According to the present description, the cross shield electrode 21C' is within the central portion of the cross trench region 22CB, but not within the lower portion of the cross trench region 22BC. That is, the lower portion of the cross trench region 22CB does not have the cross shield electrode 21C'. In this example, the linking shield electrode 21B and the cross shield electrode 21C' are shorter or thinner than the active shield electrode 21A. The cross shield electrode 21C' is separated from the region of the semiconductor material by a cross shield dielectric 24C' that is thicker than the cross shield dielectric 24C shown in FIG. 9A. According to the present description, the shorter cross shield electrode 21C' further reduces the effects of three-dimensional depletion, thereby reducing the BV of the semiconductor device 10. DSS Improve performance.

[0060] Referring to FIG. 6B , tip region 360′ in cell topography 200 can be longer than tip region 360 in cell topography 100. Like tip region 360, tip region 360′ includes side 361, side 362, and end 363. In some examples, distances 361A′, 362A′, and 363A′ can be similar to distances 361A, 362A, and 363A of tip region 360. In other examples, one or more of distances 361A′, 362A′, or 363A′ can be different from distances 361A, 362A, and 363A. In this example, distances 361A′, 362A′, and 363A′ are greater than distance 36A. In this example, termination mesa region width 16BB of termination mesa region 16B is greater than active mesa region width 16AA of active mesa region width 16A. This results in a higher concentration of charge in the termination mesa region 16B in the tip region 360', which further facilitates charge balancing of the semiconductor device 10 and reduces the BV DSS Further improve performance.

[0061] FIG. 5 shows a partial top view of a cell topography 300 of a semiconductor device 10 according to the present description. Cell topography 300 may also be referred to as a device layout or a cell layout. FIG. 2 shows a partial cross-sectional view of semiconductor device 10 along reference line 2'-2' of cell topography 300 of FIG. 5, including active trench region 22A, and FIG. 9B shows a partial cross-sectional view of semiconductor device 10 along reference line 9B'-9B' of cell topography 300 of FIG. 5, including intersection trench region 22CB. FIG. 6C shows an enlarged partial top view of portion 6C' of cell topography 300. Cell topography 300 includes similar features to cell topography 100 and cell topography 200, and these similar features will not be repeated here.

[0062] 5 and 9B, in this example, semiconductor device 10 includes a coupling trench region 22B' having a coupling trench region width 220B' and an intersection trench region 22CB having an intersection trench region width 220CB. In this example, coupling trench region width 220B' is greater than intersection trench region width 220CB. In some examples, coupling trench region width 220B' can be similar to active trench region width 220A such that coupling trench region 22B' has a coupling shield electrode similar to active shield electrode 21A. As shown in FIG. 9B, intersection trench region 22CB includes an intersection shield electrode 21C' that is thinner or shorter than active shield electrode 21A and the coupling shield electrode. According to this description, the shorter intersection shield electrode 21C' reduces the effects of three-dimensional depletion, thereby reducing the BV of semiconductor device 10. DSS The connection trench region 22B1′ may be an example of a first connection trench region, and the connection trench region 22B2′ may be an example of a second connection trench region. In some examples, the termination mesa region 16B′ is smaller than the termination mesa 16B of the cell topography 100 and the cell topography 200.

[0063] 6C, tip region 360'' in cell topography 300 includes side 361, side 362, and end 363. In this example, side 361 is laterally spaced a distance 361A'' from first connecting trench region 22B1', side 362 is laterally spaced a distance 362A'' from second connecting trench region 22B2', and end 363 is laterally spaced a distance 363A'' from intersection trench region 22CB. In this example, termination mesa region width 16BB' of termination mesa region 16B' is similar to active mesa region width 16AA of active mesa region 16A, and therefore the charge in termination mesa region 16BB' is similar to the charge in active mesa region 16A. In this example, shorter intersecting shield electrode 21C' and doped region 17 are used to provide a BV DSS Improve performance.

[0064] FIG. 7A shows a partial top view of a cell topography 400 of a semiconductor device 10 according to the present description. The cell topography 400 may also be referred to as a device layout or a cell layout. FIG. 2 shows a partial cross-sectional view of the semiconductor device 10 along reference line 2'-2' of the cell topography 400 of FIG. 7A, including active trench region 22A; FIG. 7B shows a partial cross-sectional view of the semiconductor device 10 along reference line 7B'-7B' of the cell topography 400 of FIG. 7A, including interconnecting trench region 21BA; FIG. 9A shows a partial cross-sectional view of the semiconductor device 10 along reference line 9A'-9A' of the cell topography 400 of FIG. 7A, including intersecting trench region 22CA; and FIG. 9B shows a partial cross-sectional view of the semiconductor device 10 along reference line 9B'-9B', including intersecting trench region 22CB. Cell topography 400 includes similar features to cell topography 100, cell topography 200, and cell topography 300, and these similar features will not be repeated here.

[0065] In this example, semiconductor device 10 includes intersection trench region 22C, which includes one or more intersection trench regions 22CA and one or more intersection trench regions 22CB. In some examples, intersection trench region 22CA can be referred to as a first portion of intersection trench region 22C, and intersection trench region 22CB can be referred to as a second portion of intersection trench region 22C. Intersection trench region 22CA has intersection trench region width 220CA, and intersection trench region 22CB has intersection trench region width 220CB that is smaller than intersection trench region width 220CA. Intersection trench region width 220CA is an example of a first width, and intersection trench region width 220CB is an example of a second width that is smaller than the first width.

[0066] In this example, intersecting trench region 22CA includes intersecting shield electrode 21A (FIG. 9A), and intersecting trench region 22CB includes intersecting shield electrode 21C' (FIG. 9B) that is thinner or shorter than intersecting shield electrode 21C. Intersecting shield electrode 21C is an example of a first intersecting shield electrode having a third thickness, and intersecting shield electrode 21C' is an example of a second intersecting shield electrode having a fourth thickness that is smaller than the third thickness. In this example, intersecting shield electrode 21C may be similar to active shield electrode 21A.

[0067] In this example, semiconductor device 10 includes connection trench region 22BA having connection trench region width 220BA. Connection trench region width 220BA is greater than intersection trench region width 220CB but less than intersection trench region width 220CA. In this example, connection trench region width 220BA is less than active trench region width 220A. In this example, connection trench region width 220BA is greater than connection trench region width 220B in cell topography 100 but less than connection trench region width 220B' in cell topography 300.

[0068] 7A and 7B, the linking trench region 22BA includes a linking shield electrode 21B' having a linking shield electrode thickness 216B'. The linking shield electrode thickness 216B' may also be referred to as the linking shield electrode height. In this example, the linking shield electrode thickness 216B' is greater than the cross shield electrode thickness 216C' (FIG. 9B) but less than the cross shield electrode thickness 216C (FIG. 9A). In this example, the linking shield electrode thickness 216B' is less than the active shield electrode thickness 216A. In this example, the linking shield electrode 21B' is separated from the region 11 of semiconductor material by a linking shield dielectric 24B'. The linking shield electrode 21B' is in a central portion of the linking trench region 22BA and includes a lower surface 2100B that extends partially into the lower portion of the linking trench region 22BA. According to this description, the connecting shield electrode 21B′ and the crossing shield electrode 21C′ are shorter shield electrodes compared to the active shield electrode 21A, which helps to reduce the effect of three-dimensional depletion, thereby reducing the BV DSS Improve performance.

[0069] In this example, the portions of the semiconductor device 10 in the cell topography 400 include a termination mesa region 16B″ having a termination mesa region width 16B″ that is greater than the active mesa region width 16A. In those portions of the semiconductor device 10 having this configuration, the termination mesa region 16B″ contains a higher charge concentration compared to the active mesa region 16A, and together with the shorter connecting shield electrode 21B′, the BV DSS Improve performance.

[0070] In this example, other portions of semiconductor device 10 in cell topography 400 include termination mesa region 16B' having termination mesa region width 16BB' similar to active mesa region width 16A, and therefore have similar charge concentrations. In these portions of semiconductor device 10 having this configuration, shorter connecting shield electrode 21B' and shorter crossing shield electrode 21C' are connected to BV DSS Improve performance.

[0071] Cell topography 400 is comprised of doped regions 17A and 17B within termination mesa regions 16B" and 16B', respectively. In some examples, doped regions 17A and 17B have different peak dopant concentrations, which provides design flexibility for controlling charge balance in the different termination mesa regions 16B' and 16B" of semiconductor device 10. This allows for the BV DSS Further improve performance.

[0072] 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8I, 8J, 8K, 8L, 8M, and 8N illustrate partial cross-sectional views of semiconductor device 10 at various stages of fabrication according to the present description. 8A, 8C, 8E, 8G, 8I, 8K, and 8M illustrate portions of semiconductor device 10 corresponding to active trench regions, such as one of active trench regions 22A. 8B, 8D, 8F, 8H, 8J, 8L, and 8N illustrate portions of semiconductor device 10 corresponding to link trench regions, such as one of link trench regions 22B. It will be understood that similar fabrication steps (e.g., steps illustrated in FIGS. 8A, 8C, 8E, 8G, 8I, 8K, and 8M) can be used to provide link trench region 22B′ of FIG. 5 . Similar steps can be used for connecting trench region 22BA of Figure 7A, e.g., with trenches having widths between those shown in Figures 8A and 8B. It will be further understood that the steps shown in Figures 8A, 8C, 8E, 8G, 81, 8K, and 8M can be used to provide crossed shield electrodes 21C shown in Figure 9A, and the steps shown in Figures 8B, 8D, 8F, 8H, 8J, 8L, and 8N can be used to provide crossed shield electrodes 21C' shown in Figure 9B.

[0073] 8A and 8B show cross-sectional views of semiconductor device 10 at early stages of fabrication. In some examples, region 11 of semiconductor material is provided with major surface 18. A masking material (not shown) may be provided on major surface 18 and patterned to provide openings for active trenches 221A, in which active trench regions 22A will be formed, and for connecting trenches 221B, in which connecting trench regions 22B will be formed. After the openings are provided, segments of region 11 of semiconductor material may be removed to provide active trenches 221A and connecting trenches 221B extending inward from major surface 18 into region 11 of semiconductor material. In this example, connecting trenches 221B have a smaller width than active trenches 221A. In some examples, active trenches 221A may have a width in the range of about 0.2 microns to about 1.5 microns, and connecting trenches 221B may have a width that is about 50% to 80% of the width of active trenches 221A. In some examples, the width of the connection trench 221B is selected using a target thickness of the shield dielectric so that the shield electrode in the connection trench region is in the central portion of the connection trench region and not in the lower portion of the connection trench region.

[0074] In some examples, the active trenches 221A and the connecting trenches 221B can be etched using plasma etching techniques with fluorocarbon or fluorinated chemistries (e.g., SF / O) or other chemistries or removal techniques known to those skilled in the art. In some examples, the active trenches 221A and the connecting trenches 221B can be formed using a multi-step etching process.

[0075] In some examples, doped regions 17, 17A, and 17B may be provided in region 11 of semiconductor material in the termination region of semiconductor device 10 prior to the formation of active trench 221A and connecting trench 221B. In some examples, ion implantation and annealing techniques may be used to provide doped regions 17, 17A, and 17B. In other examples, doped regions 17, 17A, and 17B may be provided in a later manufacturing step.

[0076] Next, a dielectric 241 is provided adjacent to the major surface 18, the dielectric 241 including a dielectric portion 241A adjacent to the surface of the active trench 221A and a dielectric portion 241B adjacent to the surface of the connecting trench 221B. In some examples, the dielectric 241 includes one or more dielectric materials, such as one or more oxides, one or more nitrides, combinations thereof, or other insulating materials known to those skilled in the art. The dielectric 241 can be provided using thermal oxidation, chemical vapor deposition (CVD) techniques, plasma enhanced CVD (PECVD) techniques, low pressure CVD (LPCVD) techniques, or other techniques known to those skilled in the art. In some examples, the dielectric 241 includes a thermal oxide and has a thickness ranging from about 0.05 microns to about 0.8 microns.

[0077] 8C and 8D show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, an etch-back material 51 or other planarizing material is provided over dielectric portions 241A in active trenches 221A and over dielectric portions 241B in connecting trenches 221B. In some examples, etch-back material 51 includes an organic material such as photoresist. In this example, etch-back material 51 is provided in lower portions of active trenches 221A and connecting trenches 221B.

[0078] 8E and 8F show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, portions of dielectric portion 241A and portions of dielectric portion 241B are removed to a position proximate etch-back material 51. In some examples, dry etching techniques can be used to remove the upper portions of dielectric portions 241A and 241B. In other examples, wet etching techniques can be used to remove the upper portions of dielectric portions 241A and 241B. After the upper portions of dielectric portions 241A and 241B are removed, etch-back material 51 can be removed. This step also removes dielectric 241 adjacent to major surface 18. In other examples, only portions of dielectric 241 are removed, leaving portions of dielectric 241 along upper portions of active trenches 221A and connecting trenches 221B and along major surface 18.

[0079] 8G and 8H show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, a dielectric 242 is provided adjacent major surface 18, including a dielectric portion 242A adjacent the top surface of active trench 221A and a dielectric portion 242B adjacent the top surface of connecting trench 221B. In some examples, dielectric 242 comprises a deposited dielectric having a thickness that fills the lower portion of connecting trench 221B but leaves the central and lower portions of active trench 221A unfilled. The central portion of connecting trench 221B remains unfilled by dielectric portion 242B. In some examples, dielectric 242 comprises a deposited oxide and can have a thickness ranging from about 0.05 microns to about 1.0 micron.

[0080] 8I and 8J show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, a conductive material is provided adjacent major surface 18 and within active trenches 221A and connecting trenches 221B. In some examples, the conductive material may include a crystalline material, a conductor, or a combination thereof. In some examples, the conductive material may be doped polysilicon. In some examples, the doped polysilicon may be doped with an N-type conductivity dopant, such as phosphorus or arsenic. In a subsequent step, the conductive material may be planarized to provide structures 212A and 212B shown in FIGS. 8I and 8J. In some examples, chemical mechanical planarization (CMP) techniques may be used for the planarization step. When the conductive material for structures 212A and 212B includes a crystalline semiconductor material, the conductive material may be heat-treated before or after planarization to anneal, activate, and / or diffuse any dopant material present in the doped crystalline semiconductor material.

[0081] 8K and 8L show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, structure 212A can be recessed into active trench 221A to form active shield electrode 21A, and structure 212B can be recessed into connecting trench 221B to form connecting shield electrode 21B. In some examples, when active shield electrode 21A and connecting shield electrode 21B comprise doped polysilicon, dry etching using fluorine- or chlorine-based chemistry can be used for the recessing step. According to the present description, connecting shield electrode 21B is located in the central portion of connecting trench 221B but not in the lower portion of connecting trench 221B. That is, the connecting shield electrode 21B is absent in the lower portion of connecting trench 221B. Active shield electrode 21B includes portion 211A located in the central portion of active trench 221A and portion 211B located in the lower portion of active trench 221A.

[0082] 8M and 8N show partial cross-sectional views of semiconductor device 10 after additional processing. In some examples, exposed portions of dielectric 242 (including a portion of dielectric portion 242A and a portion of dielectric portion 242B) can be removed. In other examples, portions of dielectric 242 can be left in place or thinned to a preselected thickness to become part of gate dielectric 26. In some examples, dielectrics can be formed in active trench 221A adjacent to active shield electrode 21A and in connecting trench 221B adjacent to connecting shield electrode 21B to provide gate dielectric 26 and inter-electrode dielectric 27, respectively. Gate dielectric 26 and inter-electrode dielectric 27 can be oxide, nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric material, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, gate dielectric 26 and inter-electrode dielectric 27 can be oxide. In some examples, gate dielectric 26 can have a thickness of about 0.02 microns to about 0.1 microns, and inter-electrode dielectric 27 can have a thickness greater than the thickness of gate dielectric 26. In some examples, dielectric portions 241A and 242A provide active shield dielectric 24A that separates active shield electrode 21A from region 11 of semiconductor material, and dielectric portions 241B and 242B provide linking shield dielectric 24B that separates linking shield electrode 21B from region 11 of semiconductor material. In some examples, active shield dielectric 24A and linking shield dielectric 24B can have thicknesses greater than gate dielectric 26 and inter-electrode dielectric 27. Active shield electrode 21A has active shield electrode thickness 216A, and linking shield electrode 21B has linking shield electrode thickness 216B that is less than active shield electrode thickness 216A. That is, linking shield electrode 21B is thinner or shorter than active shield electrode 21A. The active shield electrode 21A and the connecting shield electrode 21B are connected together, for example, to the shield contact trench 210 of the cell topography 100 shown in FIG.

[0083] Further processing provides a semiconductor device 10 including an active gate electrode 28A and a linking gate electrode 28B that can be coupled together and coupled to a gate contact trench 280 via, for example, the intersecting gate electrode 28C of the cell topography 100 shown in FIG. 1 . In some examples, the active gate electrode 28A and the linking gate electrode 28B can comprise a crystalline semiconductor material, a conductive material, or a combination thereof. In some examples, the active gate electrode 28A and the linking gate electrode 28B can be doped polysilicon. In some examples, the polysilicon can be doped with an N-type dopant, such as phosphorus or arsenic. In some examples, the active gate electrode 28A and the linking gate electrode 28B can be recessed below the major surface 18 of the region 11 of semiconductor material. In some examples, the active gate electrode 28A and the linking gate electrode 28B can be recessed below the major surface 18 by about 0.15 microns to about 0.25 microns. The top surfaces of the active gate electrode 28A and the linking gate electrode 28B can be substantially flat or can have a convex or concave shape in cross section.

[0084] Body region 31 may be formed extending from major surface 18 adjacent active trench 221A and connecting trench 221B. In this example, body region 31 comprises P-type conductivity and may be formed using, for example, a boron dopant source. Body region 31 has a dopant concentration suitable for forming an inversion layer that acts as channel region 45 (shown, for example, in FIG. 2) of semiconductor device 10. Body region 31 may extend from major surface 18 to a depth of, for example, about 0.3 microns to about 1.0 microns. It is understood that body region 31 may be formed earlier in fabrication, for example, before active trench 221A and connecting trench 221B are formed. Body region 31 may be formed using doping techniques such as ion implantation and annealing.

[0085] Doped region 33 may be formed within, at, or adjacent to body region 31 and may extend from major surface 18 to a depth of, for example, about 0.2 microns to about 0.4 microns. In this example, doped region 33 has N-type conductivity and may be formed using, for example, a phosphorus or arsenic dopant source. In some examples, an ion implantation doping process may be used to form doped region 33 within body region 31 using a masking layer. The masking layer may then be removed, and the implanted dopant may be annealed. As previously mentioned, doped region 33 is optionally provided adjacent to connecting trench region 22B, as represented by the dashed line in FIG. 8N.

[0086] An interlayer dielectric 41 can be formed adjacent major surface 18. In some examples, interlayer dielectric 41 comprises one or more dielectric or insulating layers. In some examples, interlayer dielectric 41 includes silicon oxide, such as doped or undoped deposited silicon oxide. In other examples, interlayer dielectric 41 comprises one layer of deposited silicon oxide doped with phosphorus or boron and phosphorus, and one layer of undoped oxide. Interlayer dielectric 41 can have a thickness of about 0.3 microns to about 1.0 microns and can be planarized to provide a more uniform surface topography, which improves manufacturability.

[0087] A masking layer (not shown) may then be formed adjacent to major surface 18, and openings may be formed to create contact trenches 422 that provide contact to doped region 33 and provide openings for forming body contact regions 36. In some examples, a recess etch may be used to remove portions of doped region 33. The recess etch step may expose portions of body region 31 below doped region 33. The masking layer may then be removed. Body contact regions 36 may be formed in body region 31, and may be configured to provide a lower contact resistance to body region 31. Ion implantation techniques (e.g., using boron) and annealing techniques may be used to form body contact regions 36.

[0088] Additional processing can be used to provide a conductive region 43 within the contact trench 422, configured to provide electrical contact to the doped region 33 and the body region 31 via the body contact region 36, as shown in FIGS. 2 and 3 , for example. In some examples, the conductive region 43 can be a conductive plug or plug structure. In some examples, the conductive region 43 can include a conductive barrier structure or liner and a conductive fill material. The barrier structure can include a metal / metal nitride structure, such as titanium / titanium nitride, or other related or equivalent materials known to those skilled in the art. The barrier structure can further include a metal silicide structure. In some examples, the conductive fill material includes tungsten. In some examples, the conductive region 43 can be planarized to provide a more uniform surface topography. Further processing can be used to provide the conductors 44 and 46, as described above.

[0089] As previously described, similar processes can be used to provide the intersection trench region 22CA shown in FIG. 9A and the intersection trench region 22CB shown in FIG. 9B. In some examples, the intersection trench region 22CA comprises a cross shield dielectric 24C including dielectric portions 241C and 242C, which may be similar to the dielectric portions 241A and 242A. In some examples, the intersection trench region 22CB comprises a cross shield dielectric 24C' including dielectric portions 241C' and 242C', which may be similar to the dielectric portions 241B and 242B. The cross shield dielectric 24C separates the cross shield electrode 21C from the region 11 of semiconductor material. The cross shield dielectric 24C' separates the cross shield electrode 21C' from the region 11 of semiconductor material. The cross shield electrode 21C comprises a portion 211C in a central portion of the intersection trench region 22CA and a portion 211D in a lower portion of the intersection trench region 22CA. Portions 211C and 211D may be similar to portions 211A and 211B of active shield electrode 21A described above. Intersecting shield electrode 21C' is within the central portion of intersection trench region 22CB, but is not in the lower portion of intersection trench region 22CB. That is, there is no intersecting shield electrode 21C' in the lower portion of intersection trench region 22CB.

[0090] In some examples, the active shield electrode 21A, the connecting shield electrode 21B, and the intersecting shield electrodes 21C / 21C' are connected together and coupled to the shield contact trench 210. In some examples, the active gate electrode 28A, the connecting gate electrode 28B, and the intersecting gate electrodes 28C / 28C' are connected together and coupled to the gate contact trench 280. In some examples, the body region 31 adjacent to the intersecting trench region 22CA / 22CB is free of the doped region 33 and the body contact region 36, as shown in, for example, FIGS. 9A and 9B .

[0091] In summary, improved BV DSSA semiconductor device and associated method have been described that have performance. The semiconductor device includes an active trench region, an intersection trench region, and a connecting trench region that connects the active trench region to the intersection trench region. In some examples, the intersection trench region or the connecting trench region includes a shield electrode that is shorter than the shield electrode of the active region. The shorter shield electrode reduces the effects of three-dimensional depletion proximate the intersection trench region, thereby reducing the BV. DSS In some instances, it provides charge balance control in the termination mesa region to improve BV DSS To further improve performance, a termination mesa region having a width greater than the active mesa region is provided. In some examples, charge balance control is further provided to reduce the BV DSS To further improve performance, one or more doped regions are provided in the termination region. The present structure and method support the use of multiple shield electrode contact trenches, which reduces shield resistance. Reduced shield resistance provides a semiconductor device with low gate bounce, excellent UIS performance, and higher efficiency.

[0092] It will be understood that the different examples described herein can be combined with any of the other examples described herein to obtain different implementations.

[0093] While the subject matter of the present disclosure has been described using certain representative examples, the foregoing drawings and description thereof merely depict typical examples of the subject matter and should not be considered as limiting its scope. It is apparent that many alternatives and modifications will be apparent to those skilled in the art. For example, the conductivity types of various regions can be reversed.

[0094] As the claims reflect below, inventive aspects may lie in fewer than all features of a single example disclosed above. Therefore, the claims expressed below are expressly incorporated into this Detailed Description of the Drawings, with each claim standing alone as a separate example of this disclosure. Furthermore, some examples described herein may include some features, but not others, included in other examples, and as will be understood by those skilled in the art, a combination of features from different examples is intended to be within the scope of this disclosure and to form different examples.

Claims

1. a region of semiconductor material (11); a first active trench region (22A, 22A1) extending inwardly into said region of semiconductor material, said first active trench region including an active shield electrode (21A) separated from said region of semiconductor material by an active shield electrode dielectric (24A); a second active trench region (22A, 22A2) extending inwardly into said region of semiconductor material and laterally spaced from and parallel to said first active trench region, said second active trench region including said active shield electrode (22A) separated from said region of semiconductor material by said active shield electrode dielectric (24A); an intersecting trench region (22C, 22CA, 22CB) extending inwardly into said region of semiconductor material and perpendicular to said first active trench region and said second active trench region; a first connecting trench region (22B, 22B', 22BA, 22B1) connecting the first active trench region to the intersection trench region, the first connecting trench region (22B, 22B', 22BA, 22B1) including a connecting shield electrode (21B, 21B') within the first connecting trench region separated from the region of semiconductor material by a connecting shield electrode dielectric (24B, 24B'); a second coupling trench region (22B, 22B', 22BA, 22B2) coupling the second active trench region to the intersection trench region, the second coupling trench region (22B, 22B', 22BA, 22B2) including the coupling shield electrode (21B, 21B') within the second coupling trench region separated from the region of semiconductor material by the coupling shield electrode dielectric (24B, 24B'); the active shield electrode has a first thickness (216A) in a first cross-sectional view; the linking shield electrode has a second thickness (216B, 216B′) in the first cross-sectional view, The second thickness is less than the first thickness.

2. the intersecting trench regions (22C, 22CA, 22CB) include intersecting shield electrodes (21C, 21C') in a lower portion of the intersecting trench regions that are separated from the regions of semiconductor material by intersecting shield electrode dielectrics (24C, 24C'); The semiconductor device of claim 1 , wherein the cross shield electrodes have a third thickness (216C, 216C′).

3. The semiconductor device of claim 2, wherein the third thickness (216C') is equal to the second thickness (216B).

4. The semiconductor device of claim 2 , wherein the third thickness (216C) is equal to the first thickness (216A).

5. The intersection trench region (22C) is a first portion (22CA) having a first width (220CA) in a top view; a second portion (22CB) connected to the first portion and having a second width (220CB) in the top view; a first intersecting shield electrode (21C) in a lower portion of the first portion of the intersecting trench region, the first intersecting shield electrode being separated from the region of semiconductor material by a first intersecting shield electrode dielectric (24C); a second intersecting shield electrode (21C') at a lower portion of the second portion of the intersecting trench region, the second intersecting shield electrode (21C') being separated from the region of semiconductor material by a second intersecting shield electrode dielectric (24C'); the first cross-shield electrode has a third thickness (216C) in a second cross-sectional view; the second cross-shield electrode has a fourth thickness (216C') in the second cross-sectional view; the second width is smaller than the first width; The semiconductor device of claim 1 , wherein the fourth thickness is less than the third thickness.

6. The semiconductor device of claim 5 , wherein the fourth thickness is equal to the second thickness.

7. The semiconductor device of claim 5 , wherein the third thickness is equal to the first thickness.

8. an active mesa region (16A) located between the first active trench region and the second active trench region and having an active mesa region width (16AA); a termination mesa region (16B, 16B″) located between the first connection trench region and the second connection trench region and bordering the intersection trench region; a base region (31) within the active mesa region and the termination mesa region; a body contact region (36) in the base region, the body contact region (36) including a tip region (360, 360') in the termination mesa region; 2. The semiconductor device of claim 1, wherein said termination mesa region has a termination mesa region width (16BB, 16BB") greater than said active mesa region width (16AA).

9. a shield contact trench (210); a gate contact trench (218); a third connecting trench region (22B, 22B3) connecting the shield contact trench to the intersection trench region, the third connecting trench region (22B, 22B3) including the connecting shield electrode (21B, 21B') within the third connecting trench region separated from the region of semiconductor material by the connecting shield electrode dielectric (24B); 2. The semiconductor device of claim 1, further comprising: a fourth coupling trench region (22B, 22B4) coupling the gate contact trench to the intersection trench region, the fourth coupling trench region (22B, 22B4) including the coupling shield electrode (21B, 21B′) within the fourth coupling trench region separated from the region of semiconductor material by the coupling shield electrode dielectric (24B).

10. a region (11) of semiconductor material having a top surface (18) and a first conductivity type; a first active trench region (22A, 22A1) within said region of semiconductor material and including an active shield electrode (21A) separated from said region of semiconductor material by an active shield electrode dielectric (24A); an intersecting trench region (22C, 22CA, 22CB) within said region of semiconductor material and perpendicular to said first active trench region, said intersecting shield electrodes (21C, 21C') separated from said region of semiconductor material by an intersecting shield electrode dielectric (24C, 24C'); a first linking trench region (22B, 22B', 22BA) within said region of semiconductor material, linking said first active trench region to said intersection trench region and including a linking shield electrode (21B, 21B') separated from said region of semiconductor material by a linking shield electrode dielectric (24B, 24B'); the active shield electrode has a first thickness (216A) in a first cross-sectional view; the linking shield electrode has a second thickness (216B, 216B′) in the first cross-sectional view, the cross shield electrodes have a third thickness (216C, 216C') in a second cross-sectional view; A semiconductor device (10), wherein one or more of the second thickness or the third thickness is less than the first thickness.

11. a second active trench region (22A, 22A2) within said region of semiconductor material, laterally spaced from and parallel to said first active trench region, said second active trench region including said active shield electrode (21A) separated from said region of semiconductor material by said active shield electrode dielectric (24A); an active mesa region (16A) located between the first active trench region and the second active trench region and having an active mesa region width (16AA); a second linking trench region (22B, 22B2) within said region of semiconductor material, linking said second active trench region to said intersection trench region and including said linking shield electrode (21B, 21B') separated from said region of semiconductor material by said linking shield electrode dielectric (24B, 24B'); a termination mesa region (16B, 16B') located between the first and second connection trench regions and bordering the intersection trench region; a base region (31) having a second conductivity type opposite to the first conductivity type within the active mesa region and the termination mesa region; 11. The semiconductor device of claim 10, further comprising: a doped region (17, 17A, 17B) in the termination mesa region below the base region between the first and second connecting trench regions.

12. the region of semiconductor material includes a substrate (12) and a semiconductor region (14) over the substrate; the doped region has the first conductivity type; the doped region has a first peak dopant concentration; the semiconductor region has a second peak dopant concentration; The semiconductor device of claim 11 , wherein the first peak dopant concentration is greater than the second peak dopant concentration.

13. The semiconductor device of claim 11 , wherein the doped region has the second conductivity type.

14. The semiconductor device of claim 10, wherein the second thickness (216B, 216B') is less than the first thickness (216A).

15. The semiconductor device of claim 10, wherein the third thickness (216C') is less than the first thickness (216A).

16. The semiconductor device of claim 10, wherein the second thickness (216B, 216B') and the third thickness (216C') are less than the first thickness (216A).

17. 1. A method for manufacturing a semiconductor device, comprising: providing a region (11) of semiconductor material; providing a first active trench region (22A, 22A1) extending inwardly into the region of semiconductor material, the first active trench region (22A, 22A1) including an active shield electrode (21A) in the first active trench region separated from the region of semiconductor material by an active shield electrode dielectric (24A); providing a second active trench region (22A, 22A2) extending inwardly into the region of semiconductor material and laterally spaced from and parallel to the first active trench region, the second active trench region (22A, 22A2) including the active shield electrode (21A) in the second active trench region separated from the region of semiconductor material by the active shield electrode dielectric (24A); providing an intersection trench region (22C, 22CA, 22CB) extending inwardly into said region of semiconductor material and perpendicular to said first active trench region and said second active trench region; providing a first linking trench region (22B, 22B', 22BA, 22B1) linking the first active trench region to the intersection trench region and including a linking shield electrode (21B, 21B') separated from the region of semiconductor material by a linking shield electrode dielectric (24B, 24B'); providing a second connection trench region (22B, 22B', 22BA, 22B2) connecting the second active trench region to the intersection trench region, the second connection trench region (22B, 22B', 22BA, 22B2) including the connection shield electrode (21B, 21B') in the second connection trench region separated from the region of semiconductor material by the connection shield electrode dielectric (24B, 24B'); the active shield electrode has a first thickness (216A) in a first cross-sectional view; the linking shield electrode has a second thickness (216B, 216B′) in the first cross-sectional view, The method of manufacturing a semiconductor device, wherein the second thickness is less than the first thickness.

18. Providing the intersection trench region comprises: providing an intersecting shield electrode dielectric (24C, 24C') in said intersecting trench region; providing intersecting shield electrodes (21C, 21C') in the intersecting trench regions; the crossed shield electrode dielectric separates the crossed shield electrodes from the region of semiconductor material; The method of claim 17, wherein the crossed shield electrodes have a third thickness (216C, 216C').

19. 20. The method of claim 18, wherein providing the crossed shield electrodes comprises providing the third thickness (216C') equal to the second thickness (216B).

20. 20. The method of claim 18, wherein providing the crossed shield electrodes comprises providing the third thickness (216C) equal to the first thickness (216A).

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