Transition control in bias supply devices

Abstract

A bias supply apparatus and bias control method are disclosed. One method includes applying an asymmetric periodic voltage waveform and providing a corresponding current waveform at an output node to a feedback node, receiving a signal to change from a current state of the asymmetric periodic voltage waveform to a next state of the asymmetric periodic voltage waveform, and adjusting at least a portion of the asymmetric periodic voltage waveform during the transition from the current state to the next state while simultaneously adjusting a fundamental frequency of the asymmetric periodic voltage waveform to settle to the next state.

Description

[Technical Field]

[0001] The present invention relates generally to power supplies, and more particularly to power supplies for applying voltages for plasma processing. [Background technology]

[0002] Many types of semiconductor devices are fabricated using plasma-based etching techniques. If it is a conductor to be etched, a negative voltage relative to ground is applied to the conductive substrate, creating a substantially uniform negative voltage across the surface of the substrate conductor, which can attract positively charged ions toward the conductor, resulting in positive ions striking the conductor having substantially the same energy.

[0003] However, if the substrate is a dielectric, a constant voltage is ineffective for imposing a voltage across the surface of the substrate. However, an alternating current (AC) voltage (e.g., a high-frequency AC or a time-varying periodic voltage waveform) can be applied to a conductive plate (or chuck) by a bias supply, and the AC field induces a voltage on the surface of the substrate. During the negative portion of the applied waveform, the surface of the substrate is negatively charged, which causes ions to be attracted toward the negatively charged surface during the negative portion of the periodic cycle. Then, when the ions collide with the surface of the substrate, the impact removes material from the surface of the substrate (resulting in etching).

[0004] During operation of the bias supply, the bias supply undergoes a state change, such as from an off state to an on state. In addition, the periodic waveform can be changed consistently with the state change, resulting in a different ion energy distribution function (IEDF). For example, directionality, feature profile, and selectivity to mask and stop layers can be controlled by changing the state of the bias supply and adjusting the IEDF.

[0005] In recent years, advanced plasma processing systems have transitioned to the use of pulsed plasma for several reasons. In one instance, pulsing is used to reduce the average energy imparted to the wafer. For example, to achieve a desired etch rate or etched feature depth, high power, such as bias power of 10 kilowatts or more, may be used. Unfortunately, continuous application of such high power can damage the wafer or process hardware, so pulsing of source supplies is used to reduce the average power delivered by reducing the duty cycle. In another instance, pulsing is used to control the electron temperature in the plasma. The operating state of a bias supply may be synchronized with the pulsing of the source supply, such that the bias supply undergoes state changes that are synchronized with the state changes of the source supply. Summary of the Invention [Means for solving the problem]

[0006] One aspect can be characterized as a bias supply including an output node, a feedback node, and a switch network and at least one power supply coupled to the output node and the feedback node. The switch network and the at least one power supply are configured in combination to apply an asymmetric periodic voltage waveform and provide a corresponding current waveform at the output node to the feedback node. The bias supply also includes a measurement component configured to receive and sample voltage and current signals indicative of the periodic voltage waveform. A controller is configured to control the switch network and the at least one power supply, the controller including a transition control module configured to receive a signal to change from a current state to a next state, adjust a voltage of the at least one power supply during a transition from the current state to the next state, and simultaneously control a switching frequency of the switch network, adjust a fundamental frequency of the asymmetric periodic voltage waveform, and settle to the next state after the defined transition.

[0007] Yet another aspect may be characterized as a method of applying a periodic voltage, the method including applying an asymmetric periodic voltage waveform and providing a corresponding current waveform at an output node to a feedback node, receiving a signal to change from a present state of the asymmetric periodic voltage waveform to a next state of the asymmetric periodic voltage waveform, and adjusting at least one of first, second, and third portions of the asymmetric periodic voltage waveform during a transition from the present state to the next state while simultaneously adjusting a fundamental frequency of the asymmetric periodic voltage waveform to settle at the next state, wherein the fundamental frequency during the transition is different from the fundamental frequency during either the present or next state. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram depicting an exemplary plasma processing environment in which the bias supply apparatus disclosed herein may be utilized.

[0009] [Figure 2] FIG. 2 is a schematic diagram depicting an exemplary bias supply apparatus.

[0010] [Figure 3] FIG. 3 is a schematic side electrical representation of a plasma processing chamber.

[0011] [Figure 4] FIG. 4 depicts graphs and timing diagrams illustrating aspects of a bias supply arrangement comprising two switches.

[0012] [Figure 5] FIG. 5 depicts graphs and timing diagrams illustrating aspects of a bias supply arrangement with a single switch.

[0013] [Figure 6] FIG. 6 is a block diagram depicting the sampling, readback, and control aspects of the bias supply.

[0014] [Figure 7] FIG. 7 is a schematic diagram depicting the inductance that affects the voltage applied to the plasma chamber relative to the bias supply.

[0015] [Figure 8A] FIG. 8A is a graph depicting the effect of the inductance depicted in FIG.

[0016] [Figure 8B] FIG. 8B is a graph depicting the results of a method for compensating for the inductance depicted in FIG. 7 and mitigating the effect depicted in FIG.

[0017] [Figure 9A] FIG. 9A depicts an example of an asymmetric periodic voltage waveform.

[0018] [Figure 9B] FIG. 9B depicts an example of an output current associated with the asymmetric periodic voltage waveform depicted in FIG. 9A.

[0019] [Figure 9C] FIG. 9C depicts the wafer voltage reconstructed from the voltage waveform of FIG. 9A and the current waveform of FIG. 9B according to the methods disclosed herein.

[0020] [Figure 10] FIG. 10 is a schematic diagram depicting an example of a bias supply with two power supplies.

[0021] [Figure 11] FIG. 11 is a block diagram depicting a control system for a bias supply with two power supplies, such as the bias supply depicted in FIG.

[0022] [Figure 12]FIG. 12 includes graphs depicting examples of asymmetric periodic voltage waveforms and corresponding sheath and wafer voltages consistent with a mode of operating the bias supply of FIG. 10 using the control system of FIG.

[0023] [Figure 13] FIG. 13 includes graphs depicting examples of asymmetric periodic voltage waveforms and corresponding sheath and wafer voltages consistent with another mode of operating the bias supply of FIG. 10 using the control system of FIG.

[0024] [Figure 14A] FIG. 14A is a schematic diagram illustrating an example of the switch network depicted in FIG. 10 with two active switches.

[0025] [Figure 14B] FIG. 14B is a schematic diagram depicting another example of the switch network depicted in FIG. 10 with one active switch.

[0026] [Figure 15] FIG. 15 is a schematic diagram depicting yet another example of a bias supply with a single power supply.

[0027] [Figure 16] FIG. 16 is a block diagram depicting a control system for a bias supply with a single power supply, such as the bias supply depicted in FIG.

[0028] [Figure 17] FIG. 17 includes graphs depicting example operational aspects of the bias supply depicted in FIG. 15 when controlled by the control system of FIG.

[0029] [Figure 18A] FIG. 18A is a schematic diagram depicting an example of the switch network depicted in FIG. 15 with a single active switch.

[0030] [Figure 18B] FIG. 18B is a schematic diagram depicting another example of the switch network depicted in FIG. 15 comprising a bidirectional switch.

[0031] [Figure 18C] FIG. 18C is a schematic diagram depicting yet another example of the switch network depicted in FIG. 15 comprising a single active switch.

[0032] [Figure 19] FIG. 19 depicts graphs and timing diagrams illustrating aspects of a bias supply comprising the switch network depicted in FIG. 18C.

[0033] [Figure 20] FIG. 20 is a diagram depicting graphs representing an exemplary RF pulse of the source generator, several states of the bias supply, and the corresponding substrate voltage.

[0034] [Figure 21] FIG. 21 is a flow chart depicting a method for controlling a bias supply.

[0035] [Figure 22] FIG. 22 depicts several waveforms resulting from controlling the bias supply across a state change without using transition control.

[0036] [Figure 23] FIG. 23 depicts several waveforms resulting from controlling the bias supply across a state change using transition control.

[0037] [Figure 24-1] 24A, 24B, 24C, 24D, and 24E depict examples of inductor currents and voltages for various transition types. [Figure 24-2]24A, 24B, 24C, 24D, and 24E depict examples of inductor currents and voltages for various transition types.

[0038] [Figure 25] FIG. 25 is a flow chart depicting another method that may be considered for controlling the bias supply.

[0039] [Figure 26] FIG. 26 is a flow diagram depicting an exemplary method for performing the transition control of FIG.

[0040] [Figure 27] FIG. 27 is another flow diagram depicting an exemplary method for performing the transition control of FIG.

[0041] [Figure 28] FIG. 28 is a flow diagram depicting yet another exemplary method for performing the transition control of FIG.

[0042] [Figure 29] FIG. 29 is a flow diagram depicting yet another exemplary method for performing the transition control of FIG.

[0043] [Figure 30] FIG. 30 is a flowchart depicting a method for performing transition control using a lookup table.

[0044] [Figure 31] FIG. 31 is an exemplary lookup table that may be used in connection with the method described with reference to FIG. 30 and other methods.

[0045] [Figure 32] FIG. 32 is a flow chart depicting a method that can be considered using a step voltage.

[0046] [Figure 33]FIG. 33 is a flow diagram depicting an exemplary method for performing the transition control of FIG.

[0047] [Figure 34] FIG. 34 is a flow diagram depicting another exemplary method for performing the transition control of FIG.

[0048] [Figure 35] FIG. 35 is a diagram depicting components that may be utilized to implement the control aspects disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0049] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0050] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, segments, or portions of code, which comprise one or more executable instructions for implementing the specified logical function(s). The instructions may be executable by a processor or may be used to program a field programmable gate array. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a special-purpose hardware-based system that performs the specified function(s) or operation(s), or a combination of special-purpose hardware and computer instructions.

[0051] For purposes of this disclosure, source generators or excitation supplies are those whose energy is primarily directed to generating and sustaining the plasma, while "bias supplies" are those whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma.

[0052] Applicant has found that when a bias supply undergoes a state change, the periodic voltage and / or current waveform output by the bias supply may have undesirable oscillations, which may result in undesired and / or unintended IEDF. Additionally, the oscillations may result in a slower than desired settling time for the bias supply. An aspect of the present disclosure is control of the fundamental frequency of the periodic voltage waveform applied by the bias supply to mitigate these undesirable oscillations during transitions between one operating state of the bias supply and another operating state of the bias supply. Applicant has also found that specific control of the fundamental frequency may result in a faster change from one state of the periodic voltage waveform to another state of the periodic voltage waveform. The state change undergone by the bias supply may or may not be in the context of a pulsed plasma. And, the transition control may simply be between an off state and an on state of the bias supply, or the transition control (relative to the fundamental frequency) may occur during an ongoing bias during a state change to result in a particular recipe being applied to a workpiece (also referred to herein as a substrate).

[0053] Control aspects of bias supply devices that can be used to apply a periodic voltage function to a substrate support within a plasma processing chamber are also described herein. Referring initially to FIG. 1 , an exemplary plasma processing environment (e.g., a deposition or etching system) is shown in which a bias supply device can be utilized. The plasma processing environment can include many pieces of equipment directly and indirectly coupled to a plasma processing chamber 101, including a volume containing a plasma 102 and a workpiece 103 (e.g., a wafer) and an electrode 104 (which can be embedded within the substrate support). The equipment can include vacuum handling and gas delivery equipment (not shown), one or more bias supply devices 108, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 can be a high-frequency RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents what may be implemented using an inductively coupled plasma (ICP) source, a dual capacitively coupled plasma source (CCP) with a secondary upper electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or other independently operated source of plasma energy.

[0054] In variations of the system depicted in Figure 1, the source generator 112 and source matching network 113 may be replaced by or augmented with a remote plasma source. Other variations of the system may include only a single bias supply 108. It should be appreciated that many other variations of the plasma processing environment depicted in Figure 1 may be utilized. By way of example, and not limitation, U.S. Patent No. 10,707,055, issued July 7, 2020, and U.S. Patent No. 10,811,227, issued October 20, 2020 (both of which are incorporated by reference in their entirety), disclose various types of system designs.

[0055] While the following disclosure generally refers to plasma-based wafer processing, it should also be recognized that implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can also be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure also applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to affect surface changes, sub-surface changes, deposition, or removal by physical or chemical means.

[0056] 2, an exemplary bias supply 208 that may be utilized to implement the bias supply 108 described with reference to FIG. 1 is shown. The bias supply 208 generally represents many variations of the bias supplies described further herein for applying a periodic voltage function. Accordingly, reference to the bias supply 208 generally refers to any of the bias supplies described further herein. As shown, the bias supply 208 includes an output 210 (also referred to as an output node 210), a feedback node 212, a switch network 220, an inductance 214 coupled between the output node 210 and the feedback node 212, and a first power supply 216 (also referred to herein as V supply Optional second power supply 218 (also referred to herein as V rail Also shown is a bias supply 208. Generally, the bias supply 208 functions to apply an asymmetric periodic voltage function between an output node 210 and a feedback node 212. Current delivered to the load through the output node 210 is returned to the bias supply 208 through the feedback node 212, which may be common with the load.

[0057] FIG. 2 also depicts example electrical parameters associated with the bias supply 208, including the inductor voltage V b Including V bis the voltage across the inductance 214, which may be measured as the voltage between the output node 210 and the negative node 226 of the first power supply 216. In addition, the inductance current I b may be measured along the current path that includes the inductance 214 and the first power supply 216. Yet another electrical parameter that may be measured is the output current I, which may be measured along the current path between the switch network and the output node 210, as shown. out In addition, the output voltage V out is another electrical parameter that can be measured and utilized as described herein. out may be, for example, the voltage across the output node 210 and the feedback node 212. As described herein, the feedback node 212 may be grounded or may comprise another non-zero voltage in some variations of the bias supply 208. It should be appreciated that other electrical parameters of the bias supply 208 may also be monitored and / or measured, depending on the particular design of the bias supply 208.

[0058] As shown, the bias supply 208 may include a controller that controls the electrical parameters (e.g., I b , V b , I out , and V out), the first power supply 216, the second power supply 218, and the switch network 220. The controller 230 may reside within the housing 224 of the bias supply 208, or alternatively, may reside outside the housing 222 of the bias supply 208. When implemented outside the housing 222 of the power supply 208, the controller 230 may be implemented as part of a centralized controller that controls several pieces of processing equipment, such as, for example, but not limited to, the bias supply 208, the source generator 112, the source matching network 113, other bias supplies 108, mass flow controllers, and other components. The controller 230 may be distributed between the bias supply 208 and control-related components external to the bias supply 208. It is also envisioned that the controller 230 may be implemented within the housing of another piece of equipment, such as the source generator 112, or that the controller 230 may be implemented as a distributed controller resident in several pieces of equipment.

[0059] As shown, controller 230 includes a bias control portion 232 and a transition control module 234. While the depiction of bias control portion 232 and transition control module 234 is logical for purposes of describing functional aspects of controller 230, it should be appreciated that bias control portion 232 and transition control module 234 may be realized by a common hardware structure. For example, bias control portion 232 and transition control module 234 may share one or more common processors and / or field programmable gate arrays (FPGAs). As one skilled in the art would understand, processor-executable instructions and / or instructions for programming an FPGA may be utilized to effect the control methods described further herein.

[0060] Generally, bias control portion 232 is configured to control switch network 220, first power supply 216, and second power supply 218 (when a second power supply is utilized) to effect desired aspects of the periodic voltage waveform (as described further herein) applied to output node 210 and feedback node 212. Transition control module 234 generally operates in conjunction with bias control portion 232 to modify the operation of bias control portion 232 during transitions between control states such that the fundamental frequency of the asymmetric voltage waveform is different during the transition from both the pre-transition state and the post-transition state, as described further herein. Adjusting the fundamental frequency during a transition can be useful to mitigate undesirable effects and / or achieve a desired effect, as described further herein.

[0061] Variations of the switch network 220 (and variations with or without the second power supply 218) are also disclosed herein, but first it is useful to understand the plasma load aspect.

[0062] 3, a schematic diagram is shown that electrically depicts aspects of an exemplary plasma load within a plasma processing chamber 101. As shown, the plasma processing chamber 101 has a chuck capacitance C ch (including the capacitance of the chuck and workpiece 103), and the chuck capacitance C ch is the sheath voltage V at the input 310 (also referred to as input node 310) to the plasma processing chamber 101 and the surface of the workpiece 103 (also referred to as wafer substrate 103). s As a result, the sheath voltage V s References to are also referred to herein as the voltage at the surface of the wafer or substrate. In addition, a feedback node 312 (which may be a connection to ground) is depicted. The plasma 102 in the processing chamber is coupled to the sheath capacitance C s, a diode, and a current source. The diode represents the nonlinear diode-like nature of the plasma sheath, which results in rectification of the applied AC field, such that a direct current (DC) voltage drop appears between the workpiece 103 and the plasma 102.

[0063] 4 and 5, timing diagrams associated with implementations of bias supply 208 are shown, each having two switches and one switch. In each of FIGS. 4 and 5, an asymmetric periodic voltage waveform is shown, providing a corresponding current waveform. As depicted, bias supply 208 disclosed herein generates an asymmetric periodic voltage waveform V between output node 210 and feedback node 212. o (times t0-t4). As shown, the asymmetric periodic voltage waveform V o has a first portion (times t0-t2), the first portion starts from a first negative voltage and changes to a positive peak voltage during the first portion (at time t1), the asymmetric periodic voltage changes from the first portion to a third voltage level (at time t3) during a second portion (times t2-t3), and the asymmetric periodic voltage waveform has a third portion (times t3-t4), the third portion including a voltage ramp between the third voltage level and a fourth negative voltage level (at time t4).

[0064] As shown in Figures 4 and 5, the asymmetric periodic voltage waveform has a voltage step V between times t2 and t3. step Equipped with V step is the ion at any energy level -E ion Then, during the third portion of the asymmetric periodic voltage waveform, the sheath voltage at t4 corresponds to E ion +ΔE ion At time t, the potential can become more negative, so that ions at the energy level reset (between times t0 and t3) and t ramp (between times t3 and t4) is also shown in Figures 4 and 5. As shown, t resetincludes the time that includes both the first and second portions of the asymmetric periodic voltage waveform, and t ramp includes a third part. Examples of the compensation currents referred to in FIG. 2 are also shown in FIGS. 4 and 5. The compensation current I comp can be provided throughout the application of an asymmetric periodic voltage function, and I out is the voltage during the third part of the asymmetric periodic voltage waveform (t ramp Between comp The negative voltage peak V may or may not be equal to pk- 4 and 5, which identifies the endpoint for the third portion of the asymmetric periodic voltage function. As further explained herein, the negative voltage peak, V pk- can be used as a control parameter. For example, the negative voltage peak V pk- A threshold value for may trigger the closure of S1 (as shown in FIG. 4) or a single switch controlled with reference to FIG.

[0065] As discussed further herein, the fundamental period (t0-t4) of the asymmetric periodic voltage waveform can be adjusted to adjust the ion energy spread. As shown in Figures 4 and 5, a complete current cycle occurs between times t0 and t3 during the first and second portions of the asymmetric periodic voltage waveform. The time between complete current cycles is then the time t between t3 and t4. ramp Aspects of the present disclosure include: out and adjust the ion current I ion Another aspect of the present disclosure addresses the problem of how to adjust the level and distribution of ion energy within a plasma chamber.

[0066] 4, in a variation of the bias supply 208 with two switches, the first portion of the asymmetric periodic voltage waveform may transition to the second portion of the asymmetric periodic voltage waveform (during time t1-t2), and as shown in FIG. 5, in a variation of the bias supply 208 with one switch, t1 may equal t2, and the first portion of the asymmetric periodic voltage waveform may end at the positive peak voltage level (from which the second portion may begin).

[0067] Further details of both the single switch and two-switch bias supply arrangements are disclosed further herein, but FIGS. 4 and 5 provide a basis for the variant control methodologies and various structural variations disclosed further herein.

[0068] The switching sequence of the first switch S1 and the second switch S2, the current I provided to the output node 210 of the bias supply 208, out , the voltage V at the output node 210 of the bias supply 208 out , sheath voltage V s (also shown in FIG. 3), and the corresponding ion energy distribution function (IEDF), depicted as ion flux versus ion energy, is shown in FIG.

[0069] As shown in FIG. 4, the first switch S1 and the second switch S2 are connected to each other to supply the output current I out can be controlled to complete a full current cycle between times t0 and t3. During the start of the current cycle at t0, the output current I out But Level-I o From t1, the current is controlled to reach a positive peak current value, and then the current is controlled to reach a positive peak current value, -I o Then, at t2, the output current I out But at t3, -I o before decreasing back to -I oThe current is controlled to increase in the opposite direction (opposite the positive peak current value) from -I to a peak value. More specifically, during the positive portion of the current cycle (when the first switch S1 is closed and the second switch S2 is open), the current increases to a peak positive value and then decreases to -I o During the negative portion of the complete current cycle (time t2-t3), the current increases to a negative peak value and then decreases to -I o decreases to.

[0070] As shown in FIG. 4, the first switch S1 and the second switch S2 can be controlled with an adjustable dead time, which is a time t1-t2 (after switch S1 is opened from a closed position and before switch S2 is closed).

[0071] As depicted in FIG. 4, controlling the dead time is reset allows for control of t reset t ramp Adjusting the ratio to t adjusts the average power. reset Controlling allows the fundamental switching frequency to be controlled (eg, to remain below a level that affects the plasma density within the plasma processing chamber 101).

[0072] Another aspect of control that can be achieved using the bias supply 208 disclosed herein is ion current compensation. More specifically, the length of the dead time, t ramp The length of t and / or the period (t-t) of the periodic voltage function can be controlled to control the level of ionic current compensation. ramp , Dead Time, and / or Level I o is the ion current I ion I o =I ion -(C ch +C str 1) × slope, and I comp =I ion -(C ch +C str 0+C str1) × slope (the slope is the output voltage V out , which is the slope of the curve (if desired).

[0073] As shown in Figure 4, overcompensating the ion current increases the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp time frame) becomes increasingly negative. And there is a distribution of ion energies due to the range of sheath voltage between times t3 and t4. However, the ion current is proportional to the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp It should be appreciated that the time period may be undercompensated so that the time period is not too negative.

[0074] Sheath voltage V s is substantially constant between times t3 and t4. out It is also possible to adjust the slope of the beam, which results in a very narrow distribution of ion energies.

[0075] Dead time and t ramp By adjusting both the frequency of the periodic voltage waveform and the dead time, t ramp , and the frequency of the periodic voltage waveform can be varied. ramp It is also envisioned that the length of the slit may be shortened while shortening or lengthening the slit.

[0076] 5, waveforms depicting the electrical aspects of the bias supply 208 and plasma processing chamber 101 when the switch network 220 is implemented with a single switch are shown. As shown in FIG. 5, the switch network generates an output current I out But -I o From the peak value, -I o Return to the peak value in the opposite direction, -I oIt should be appreciated that the peak value of the current in the first half of the current cycle may be different from the peak value of the current in the second half of the current cycle.

[0077] 6, a block diagram depicting general aspects of measurement, readback, and control is shown. Shown are bias supply 208, measurement component 620, and digital control 622. Generally, measurement component 620 receives and samples a signal indicative of a power-related parameter value and provides a digital representation of the power-related parameter value to digital control 622. For example, the power-related parameter may be the current provided to output node 210 and the voltage V between output node 210 and feedback node 212. out Although not required, the feedback node may be a ground connection.

[0078] The measurement component 620 may receive and sample signals from one or more bias supply signal lines 624. The bias supply signal lines 624 may include the I comp The current signal line 626 may carry a signal indicative of bias supply parameters such as voltage, temperature, and other parameters. The current signal line 626 may carry an output current I from the current converter, which is provided to the output node 210. o , and voltage line 628 may provide an analog signal indicative of the voltage V at the output of the bias supply. out An analog signal indicative of the power-related signal (I o and V out In response to receiving the asymmetric periodic voltage waveform V, the measurement component 620 samples and digitizes the power-related signal. For example, the measurement component 620 may receive the asymmetric periodic voltage waveform V out , output current I out , and / or I comp It may provide a complete digital representation of

[0079] An aspect of many variations of the measurement component 620 is that the complete voltage and current waveforms are captured, which provides improved visibility of the bias supply output and also enables improved control aspects as further disclosed herein.

[0080] Although not required, metrology component 620 may be implemented in part by a field programmable gate array, and the digital controller may be implemented by one or more processors executing code stored in a non-transitory medium (to provide the functionality of digital controller 622). However, other combinations of hardware, software, and firmware may be used to implement metrology component 620 and digital controller 622.

[0081] As shown, the asymmetric periodic voltage waveform V out , output current I out , and / or I comp The digital representation of V may be provided to a data reporting component 631, which may be a user interface (e.g., a touch screen display). out : Output current I out and / or I comp The digital representation of V is provided to a data processing module, which processes the asymmetric periodic voltage waveform V out : Output current I out and / or I comp The digital representation of is further processed to obtain the sheath voltage V s , and E ion , V step , ΔE ion , the output voltage slope (e.g., the slope of the third portion of the asymmetric periodic voltage waveform), and / or the slope deviation coefficient K s The parameter may provide one or more readbacks of one or more other parameter values, such as:

[0082] Slope deviation coefficient K s can be calculated as follows:

number

[0083] Or alternatively, the slope deviation coefficient may be calculated to satisfy the following equation:

number

[0084] Slope deviation coefficient K s is the ion current I ion Compensation current I comp provides a convenient representation of the level of s When is equal to zero, the compensation current provides full compensation, and K s >0, then I comp overcompensates the ion current, and K s <0, the compensation current I comp is the ion current I comp Compensate for any shortfall.

[0085] As shown, readback values ​​(e.g., depicted as Readback1 and Readback2) may also be used as part of the feedback control. As shown, a first comparator 638 may calculate the difference between a first setpoint, Setpoint1, and a first readback value, Readback1, to generate a first error signal, Error1. And a second comparator 640 may calculate the difference between a second setpoint, Setpoint2, and a second readback value, Readback2, to generate a second error signal, Error2. As shown, the error signals (Error1 and Error2) are fed to one or more compensators 632, which may provide control signals (Ctrl_knob1 and Ctrl_knob2) to the bias supply 208, as described further herein.

[0086] A timing parameter estimator 634 is also shown within the digital control section 622, which derives the output waveform Vout and the output current I out and generate a pulse width control signal. According to one aspect, timing parameter estimator 634 detects when there is zero current through the bias supply switches to reduce switching related losses. Timing parameter estimator 634 determines when t reset (shown in Figures 4 and 5) can also be determined, and t reset The values ​​for t are reported via the data reporting component 631. reset The values ​​for may be provided to the data processing module 630. The timing parameter estimator 634 may also be configured (e.g., using firmware, hardware, and / or a programmed FPGA) to perform the transition control methods discussed herein.

[0087] The digital controller 622 also includes a gate drive signal generator 636 configured to provide gate drive signals to the switches (S1, S2) of the bias supply 208 in response to a pulse width control signal 637 from the timing parameter estimator 634 and / or in response to a control signal 639 output by the one or more compensators 632. While many types of switches are controlled by electrical gate drive signals, it is also contemplated that optical control signals may be used. For example, the gate drive signal generator 636 may provide an optical signal.

[0088] Another aspect of the capabilities of the data processing module 630 is its ability to compensate for inductance between the output 210 of the bias supply 208 and the input 310 to the plasma chamber. Referring to FIG. 7 , a lumped element inductance 740 (also referred to as stray inductance 740) is shown, which represents the inductive element between the output 210 of the bias supply 208 and the input 310 to the plasma chamber. In many implementations, the digital representation of the asymmetric periodic voltage waveform (output by the measurement component 620) can be adjusted, for example, by the data processing module 630 to compensate for the stray inductance 740 (to obtain an adjusted digital representation of the asymmetric periodic voltage waveform). By compensating for the inductance 740, the V at the input 310 to the plasma chamber can be adjusted. step can be calculated, wafer voltage values ​​can be calculated, and ion energy values ​​E ion can be calculated.

[0089] As shown in FIG. 8A, due to inductance 740, the actual applied voltage V out1 is the voltage V applied at the output node 210 of the bias supply 208 out As a result, the data processing module 630 can calculate the voltage V actually applied to the plasma processing chamber 101. out1 may be configured to estimate:

number

[0090] As shown in Figure 8B, the estimated voltage V out1closely matches the actual voltage at the chamber input 310.

[0091] In addition, E ion can be calculated more accurately by taking into account the inductance:

number

[0092] The wafer voltage may also be more accurately reconstructed by compensating for the inductance 740. Referring to Figures 9A and 9B, examples of the output voltages and currents associated with the operation of the bias supply 208 are shown. Figure 9C shows measurements of the actual wafer voltage compared to a reconstructed wafer voltage reconstructed using the data from Figures 9A and 9B.

[0093] For example, the reconstructed wafer voltage V w can be determined as follows:

number

[0094] 9C also shows how close the actual measured wafer voltage is to the reconstructed wafer voltage. Note that in some implementations, a complete reconstruction of the wafer waveform can be obtained by capturing the entire current and voltage waveform (as described with reference to FIG. 6).

[0095] 10 and 11, examples of bias supply 208 (comprising two power supplies) and corresponding control systems are shown, respectively. More specifically, FIG. 10 illustrates a bias supply in FIG. 10 that includes a first power supply (V supply ) 216 and a second power supply (V rail supply11 is an example of a bias supply 208 comprising a first power supply 218 and a second power supply 218, and FIG. 11 is a block diagram depicting example control aspects that may be utilized in connection with a two-feed configuration such as that depicted in FIG. 10. Switch network 220 may comprise a variety of different topologies including one or two switches, and as shown, switch network 220 couples to bias supply 208 at node 1050 (coupled to the positive output of second power supply 218), at node 212 (coupled to the negative output of second power supply 218), and at output node 210.

[0096] As shown in FIG. 11, the control system includes two control "knobs": supply and V rail This approach allows for the compensation current I comp (to control the width of the ion energy distribution), and V rail 11, the first power supply 216 (V supply ) and the voltage of the second power supply (V rail ) can be controlled based on the general relationship:

number

[0097] In this control approach, the first setpoint is the ion energy setpoint, E ion_set and the second set value is the ion energy spread (also called distribution), ΔE ion_set (E ion_set and ΔE ion_set 4), and the data processing module 630 processes the I received from the measurement component 620. out and V out Based on the digital representation of E ion and ΔE ion As shown, the first comparator 638 may calculate a first set value Eion_set and E ion The second comparator 640 may generate a first error signal, Error 1, based on the difference between the calculated value of ΔE ion_set and ΔE ion A second error signal, Error2, may be generated based on the difference between the calculated values ​​of

[0098] Alternatively, the first set point (to set the ion energy value) is V step The first setpoint may be a setpoint, and the second setpoint (for setting the ion energy spread) may be a slope setpoint (for setting the slope of the third portion (the time between t3 and t4) of the asymmetric periodic voltage waveform), or the second setpoint may be a slope deviation coefficient setpoint (for setting the slope deviation coefficient K s The data processing module 630 may process the I received from the measurement component 620. out and V out Based on the digital representation of V step , and the slope or slope deviation coefficient K s In this alternative, the first comparator 638 may calculate a first set value (e.g., V step setting value) and V step The second comparator 640 may generate a first error signal, Error 1, based on the difference between a second set value (either a slope set value or a slope deviation factor set value) and the calculated value of slope or slope deviation factor K s A second error signal, Error2, may be generated based on the difference between the calculated values ​​of

[0099] As shown, the control system may include two compensators associated with the two control loops: a first compensator 1132A and a second compensator 1132B. The first compensator 1132A receives a first error signal, Error1, and generates a signal V for controlling the first power supply 216. supply_set The second compensator 1132B receives the second error signal, Error2, and generates a signal V for controlling the second power supply 218. rail_setIn some variations, the gate drive signal generator 636 may be configured with a fixed switching time for the first switch of the bias supply 208 (and the second switch in a two-switch bias supply). In other variations, the timing parameter estimator 634 may provide a pulse width signal such that the gate drive signal generator 636 closes the switch of the bias supply 208 to provide zero current switching. Each of the compensators 1132A, 1132B may be realized by a proportional-integral-derivative (PID) controller, and in some variations, the bandwidth of the first compensator 1132A is set to be different from the bandwidth of the second compensator 1132B, which allows the two control loops associated with each of the compensators 1132A, 1132B to be decoupled. For example, the sampling rate of each control loop may be set to a different rate to result in different bandwidths. As another option, a single control loop associated with MIMO compensator 632 can be used with multiple inputs (generally shown as Error 1 and Error 2 in FIG. 6) and multiple outputs, as generalized in FIG. 6, where Ctrl_knob1 and Ctrl_knob2 in FIG. 6 are V supply_set and V rail_set It could be.

[0100] Also shown in Figure 11 is a transition control module 1134 that may be used to implement the transition control module 234 depicted in Figure 2. The transition control module 1134 controls the transition frequency control signal f during transitions between various steady states (using methodologies disclosed further herein). sw.set0and controls the fundamental frequency of the asymmetric periodic voltage waveform. As shown, a transition mode signal 1136 (e.g., from bias control portion 232) triggers a transition switch 1138 (e.g., in response to a state change) to change a nominal frequency control position 1140, e.g., between steady-state control (using a pulse width or dead-time signal from a timing parameter estimator) and transition control (using transition control module 1134). It should be appreciated that transition control module 1134 and transition switch 1138 may be realized as control logic that may be implemented by, for example, but not limited to, hardware, a field programmable gate array, and / or firmware.

[0101] 12 and 13, examples of how the first power supply 216 and the second power supply 218 may be controlled are shown. More specifically, in the graph shown in FIG. 12, the second power supply 218 (V rail ) is fixed at −2,000 V, and three examples of asymmetric periodic voltage waveforms are depicted when the first power supply 216 is set to 4,500 V, 5,000 V, and 5,500 V. Three wafer voltage V(w) waveforms corresponding to the three asymmetric periodic voltage waveforms are also shown.

[0102] 13, three example graphs are shown, with the voltage of the first power supply 216 set to 5,500 V and the voltage of the second power supply 218 set to 300 V, −200 V, and −700 V. Three wafer voltage V(w) waveforms corresponding to the three asymmetric periodic voltage waveforms are also shown. While FIGS. 12 and 13 are provided merely as examples of the ability to provide desired ion energy values ​​and ion energy distributions using the first power supply 216 and the second power supply 218, it should be recognized that in many variations, both the first power supply 216 and the second power supply 218 are variable power supplies that can be adjusted and controlled using the control system depicted in FIG.

[0103] 14A and 14B, examples of switch networks that may be used in connection with the two-supply configuration of FIG. 10 are shown. Referring first to FIG. 14A, switch network 1420A is a two-switch network coupling bias supply 208 at node 1050, feedback node 212, and output node 210. Node 1460 is also shown for reference within the switch network. As depicted, switch network 1420A includes a first switch S1 disposed in series with a first diode D1 between node 1050 and node 1460. The cathode of diode D1 is coupled to node 1460, and the anode of diode D1 is coupled to switch S1. Switch network 1420A also includes a second switch S2 (disposed in series with a second diode D2) between feedback node 212 and node 1460. The anode of diode D2 is coupled to node 1460, and the cathode of diode D2 is coupled to switch S2. Additionally, inductor L1 is positioned between node 1460 and output node 210.

[0104] In operation, the switches (S1 and S2) generate the asymmetric periodic waveform V depicted in FIG. 4, as described with reference to FIG. out and the output current I out It should be appreciated that because switch S1 and diode D1 are arranged in series, the order of switch S1 and diode D1 may be interchanged. Similarly, because switch S2 and diode D2 are arranged in series, the order of switch S2 and diode D2 may be interchanged.

[0105] In many implementations, the switches disclosed herein are realized by field-effect switches such as metal-oxide-semiconductor field-effect transistors (MOSFETs), and in some implementations, the switches are realized by silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) or gallium nitride metal-oxide-semiconductor field-effect transistors (GaN MOSFETs). As another example, the switches may be realized by insulated-gate bipolar transistors (IGBTs). In these implementations, the gate drive signal generator 636 may comprise an electrical driver known in the art configured to apply an electrical drive signal to the switch in response to signals from the timing parameter estimator 634 and / or one or more compensators 632. It is also contemplated that the drive signal may be transmitted via an optical line to convey an optical switching signal. The switch may switch in response to an optical signal and / or an optical signal converted to an electrical drive signal.

[0106] It should be appreciated that each of the switches depicted herein generally represents one or more switches that can be closed and opened to respectively connect and disconnect current paths. For example, each of the switches can be realized by multiple switches arranged in series (for improved voltage capability), by multiple switches arranged in parallel (for improved current capability), or by multiple switches arranged in a series-parallel combination (for improved voltage and / or current capability). In these variations, those skilled in the art will recognize that each switch can be driven synchronously by a corresponding drive signal.

[0107] It should also be appreciated that any of the diodes depicted herein may be implemented with multiple diodes. For example, any diode may be implemented with multiple series-connected diodes (to improve voltage capability), multiple diodes arranged in parallel (to improve current capability), or may consist of multiple diodes arranged in a series-parallel combination (for improved voltage and / or current capability).

[0108] 2 and 10 is shown. As shown, switch network 1420B includes a first current path (for current iS1) between node 1050 and output node 210. The first current path includes a series combination of switch S1, diode D1, and inductor L1. In addition, switch network 1420B includes a second current path (for current iD2) (between output node 210 and feedback node 212), which includes a second diode D2 and an inductive element L2.

[0109] In operation, switch S1 in switch network 1420B, as shown in FIG. 5, generates an asymmetric periodic waveform V out and the output current I out It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between node 1050 and output node 210) may be swapped (because switch S1, diode D1, and inductor L1 are arranged in series).

[0110] 15 and 16, a schematic (depicting the bias supply 208 with the first power supply 216 as a single power supply) and a block diagram are shown, which respectively depict a control system for the bias supply 208. As shown, the control system for the single supply configuration is such that the second compensator 1632B controls the frequency setpoint signal f sw.set117. The control system is similar to the control system for the two-supply configuration (described with reference to FIG. 11), except that the first power supply 216 provides a voltage to control the frequency of switching of the bias supply 208. As shown in FIG. 17, the switching frequency is related to the voltage applied by the first power supply 216 to achieve the desired ion energy value E ion and the desired ion energy distribution ΔE ion can be used to provide

[0111] 18A , a schematic diagram is shown depicting a switch network 1820A, which is an example of a switch network 220 including two switches: a first switch S1 and a second switch S2. In the variation depicted in FIG. 18A , a series combination of a first switch S1 and a first diode D1 is disposed between the feedback node 212 of the bias supply 208 and a node 1862. In addition, a series combination of a second switch S2 and a second diode D2 is disposed between the node 1862 of the bias supply 208 and the feedback node 212. As shown in FIG. 18A , the first diode D1 is disposed between the first switch S1 and the node 1862, with its anode coupled to the first switch S1 and its cathode coupled to the node 1862. A second diode D2 is disposed between the second switch S2 and the node 1862, with its cathode coupled to the second switch S2 and its anode coupled to the node 1862. In this arrangement, the cathode of the first diode D1 is coupled to the anode of the second diode D2 at the node 1862.

[0112] In operation, the first diode D1 is conductive when the first switch S1 is closed, and the second diode D2 is conductive when the second switch D2 is closed. The first switch S1 and the second switch S2 provide an asymmetric periodic voltage waveform V out and the output current I out(shown in FIG. 4). Although not depicted, it should be appreciated that the positions of the first switch S1 and the first diode D1 may be interchanged. Similarly, the positions of the second switch S2 and the second diode D2 may be interchanged.

[0113] 18B, a schematic diagram is shown depicting switch network 1820B, another example of switch network 220, including bidirectional switch S1. As shown, a first inductor L1 is coupled between node 1870 and output node 210. Switch S1 is coupled between node 1870 and feedback node 212. A diode D1 is coupled in parallel with switch S1 between node 1870 and feedback node 212. In operation, switch S1 is opened and closed, generating an asymmetric periodic voltage function V 1 shown in FIG. 5, as shown in FIG. out and the output current I out For example, application of an asymmetric periodic voltage waveform closes switch S1, causing -I o From the peak value, -I o The output current I out After switch S1 is opened, the current increases in the opposite direction to a peak value, -I o To reduce losses, the timing parameter estimator 634 optionally calculates the output current I out I o It detects when the output current I out I o , a signal may be provided to the gate drive signal generator 636 to cause switch S1 to open.

[0114] 18C , a schematic diagram depicting a switch network 1820C is shown, which is another example of the switch network 220 including a single switch S1. As shown, the switch network 1820C includes a first current path (for current iS1) between the feedback node 212 and a node 1872. The first current path includes a series combination of the switch S1, a diode D1, and an inductor L1. In addition, the switch network 1820C includes a second current path (for current iD2) (between the node 1872 and the feedback node 212), which includes a second diode D2 and an inductive element L2. As shown, the cathode of the diode D2 is coupled to the feedback node 212, and a third inductor L3 is positioned between the node 1872 and the output node 210.

[0115] In operation, switch S1 in switch network 1820C generates an asymmetric periodic voltage waveform V between output node 210 and feedback node 212 from time t0 to time t4, as shown in FIG. out The sheath voltage V corresponding to the asymmetric periodic voltage can be s 19. As shown, the asymmetric periodic voltage waveform V out is the sheath voltage V s and the sheath voltage V s is generally negative to attract ions to impact the surface of the workpiece, allowing etching of the workpiece 103.

[0116] When switch S1 is closed at time t0, a current path (comprising switch S1, diode D1, and inductor L1) connects feedback node 212 to node 1872, and unidirectional current iS1 begins to increase from zero current at time t0, causing an asymmetric periodic voltage V applied at output node 210 to increase. outThe voltage (with respect to feedback node 212) begins to move (over the first portion 1951 of the periodic voltage waveform) from a first negative voltage 1952 to a positive peak voltage 1956. As shown, current iS1 increases to a peak value and then decreases to zero at time t1 when switch S1 is opened. As shown, iD2 increases in a ramp-down manner while switch S1 is closed, such that current iD2 is non-zero when switch S1 is opened at time t1.

[0117] As depicted, current iS1 through the first current path drops to zero, and when switch S1 is opened, the asymmetric periodic voltage drops from a positive peak voltage 1956. After switch S1 is opened (during the second portion 1953 of the asymmetric waveform), unidirectional current iD2 increases to a peak through the second current path (through the second diode D2) and then drops to zero current flow at time t1-t3. As shown, the increase and drop in unidirectional current iD2 occurs while the asymmetric periodic voltage changes from the positive peak voltage 1956 to a third negative voltage level 1958 (during the second portion 1953). As depicted, during times t0-t3, the first portion 1951 of the asymmetric periodic voltage increases due to the sheath voltage V s approaches a positive voltage, causing positive charges (which accumulate on the surface of the workpiece while it is held at a negative voltage) to be repelled, and the second portion 1953 of the asymmetric periodic voltage generates a sheath voltage V s is the desired negative voltage (or range of voltages) to achieve an ion flux that achieves the desired ion energy value 1960.

[0118] As depicted, the unidirectional current iD2 rises and then falls back to the zero current level, followed by the asymmetric periodic voltage V out becomes more negative (as a negative voltage ramp) during the third portion 1961 until switch S1 is closed again at time t4. As depicted, the compensation current I comp may be provided during the cycles of the asymmetric periodic voltage to compensate for the ion current in the plasma chamber 101. For example, a compensation current Icomp If not, the sheath voltage V s may gradually change and become more positive during the fourth portion of the asymmetric periodic voltage, which may produce a wider distribution of ion energies, which may be undesirable. However, in some variations, the compensation current I comp can be intentionally set to over- or under-compensate the ion current in the plasma chamber 101, producing a wider distribution of ion energies. In the mode of operation depicted in FIG. 19, the compensation current I comp is the asymmetric periodic voltage V o During the third portion of the s to provide.

[0119] It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between feedback node 212 and node 1872) (since switch S1, diode D1, and inductor L1 are arranged in series) can be changed. Additionally, the order in which L2 and D2 are arranged can be swapped.

[0120] To maintain a narrow ion energy distribution (IED) width, the switching frequency is increased at higher ion currents and lower ion energies. Note that changing the switching frequency also affects the ion energy (eV) level, requiring adjustment of the first power supply 216 to maintain constant ion energy. The multiple-input multiple-output (MIMO) control system shown in Figure 6 can still be implemented in this system configuration, with the control variables being:

number

number

[0121] Voltage level signal V rail_set In contrast to the second compensator 1132B (described with reference to FIG. 11) which produces a frequency control signal f in response to the second error signal error2, FIG. 16 shows a second compensator 1132B which produces a frequency control signal f sw.set1 As shown, the gate drive signal generator 636 includes a second compensator 1632B that produces f during steady state operation within the various states that the bias supply 108 may operate under. sw.set1 16 also depicts a transition control module 1634 that may be used to implement the transition control module 234 depicted in FIG. 2. The transition control module 1634 generates a transition frequency control signal f sw.set0 and configured to control (using methodologies disclosed further herein) the fundamental frequency of the asymmetric periodic voltage waveform during transitions between various steady states. As shown, a transition mode signal 1636 (e.g., from bias control portion 232) triggers a transition switch 1638 (e.g., in response to a state change) to change between steady state control (using second compensator 1632B) and transition control (using transition control module 1634). It should be appreciated that transition control module 1634 and transition switch 1638 may be realized as control logic, which may be implemented, for example, without limitation, by hardware, a field programmable gate array, and / or firmware.

[0122] 6, 11, and 16, block diagrams are shown depicting aspects of the sampling, readback, and control methods for bias supply 208. Aspects of these methods are illustrated in FIG. 6, 11, and 16, where an asymmetric periodic voltage waveform V out(at output node 210 to feedback node 212) and the corresponding output current waveform I out The method includes providing a digital representation of the asymmetric periodic voltage waveform and the corresponding current waveform. Voltage and current signals indicative of the periodic voltage waveform and the corresponding current waveform are received and sampled (e.g., by measurement component 620) to provide digital representations of the asymmetric periodic voltage waveform and the corresponding current waveform. The digital representations of the asymmetric periodic voltage waveform and the corresponding current waveform are processed (e.g., by data processing module 630) to produce a first readback value indicative of the ion energy and a second readback value indicative of the ion energy distribution. Depending on the implementation, as described above, the data processing module 630 may provide parameter values ​​utilized in one or more control loops to control desired attributes of, for example, but not limited to, the asymmetric periodic voltage waveform, the output current, the ion energy, and the ion energy distribution.

[0123] Referring now to FIG. 20, examples of an RF source envelope (which may be output from the source generator 112), an exemplary bias supply waveform (which may be output by the bias supply device 108), and an exemplary substrate voltage (which may be generated at the surface of the workpiece 103) are shown.

[0124] In some plasma processing recipes, it is desirable to provide a pulse waveform with multiple states (or power levels), as illustrated in FIG. 20 . For example, a recipe may include several pulse cycles (PCs) and several states per pulse cycle. As shown, the RF power output by the source generator 112 may vary during each state according to a target power level for each state. In this example, two pulse cycles are shown, with each pulse cycle including three different states. As shown, the bias supply 108 may output multiple cycles of a periodic voltage waveform during each state, and the voltage level of the periodic voltage waveform may vary from state to state. In FIG. 20 , the cycles of the periodic voltage waveform are depicted, but the cycles of the source generator are not. This is because the frequency of the periodic voltage waveform (typically) is several hundred kilohertz, whereas the frequency of the source generator 112 may be megahertz (e.g., 13.56 MHz). As a result, the waveform of the source generator 112 is not shown in FIG. 20; instead, the envelopes corresponding to different power levels are shown.

[0125] 20 merely depicts an example of a state change, and it should be appreciated that a variety of different power states can be applied according to a variety of different pulse cycles. For example, although the output of bias supply 108 is shown to change as source generator 112 changes state, it is entirely possible for the power level output by source generator 112 to remain the same while the output of bias supply 108 changes according to different states.

[0126] Applicant has determined that during a transition from one state to another (e.g., when the setting of the bias supply 108 changes), the inductor current I b and the output voltage V out It has been found that there can be undesirable transient overshoot and / or oscillations in both the chuck and the inductance 214. The transient dynamic aspects are related to the inductance 214 and the total capacitance (chuck capacitance C ch , sheath capacitance C s , and stray capacitance (C stray0+C stray The output voltage overshoot results from a resonance at the output node 210 between the inductor current I (through the inductance 214) and the b Transient aspects can occur in the context of multi-level pulsing (as shown in FIG. 20) or during any single event state change.

[0127] For example, referring briefly to Figures 22 and 23, graphs are shown depicting three exemplary operating states: an off state (before approximately 2 microseconds), a second state (State 2), and a third state (State 3). The depicted states and transition controls (described with reference to Figure 23) are merely exemplary, and other state combinations and transition controls are fully contemplated. Figure 22 depicts the operation of bias supply 108 without transition control, while Figure 23 depicts an example of transition control that may be used when bias supply 108 changes state. As shown, Figures 22 and 23 depict the pulse width modulated (PWM) signal and the current I through inductance 214. b and the voltage V at the output node 210 out and the sheath voltage V between the plasma 102 and the surface of the workpiece 103. s It depicts the following.

[0128] As shown in FIG. 22, without transition control, after the first state change from the off state to the second state (at about 2 microseconds), the inductance current I b , output voltage V out , and the sheath voltage V s There is a transient oscillation at the workpiece 103 surface, which lasts for more than 60 microseconds. Because the sheath voltage affects the energy of ions striking the surface of the workpiece 103 (i.e., the sheath voltage affects the ion energy distribution), the transient overshoot and oscillation can adversely affect the processing of the workpiece 103.

[0129] Applicant has discovered that varying the fundamental frequency of the asymmetric periodic voltage waveform during the transition between one state and another can reduce the output voltage Vout Consistent with embodiments disclosed herein, frequency switching can be used to adjust the fundamental frequency of the asymmetric periodic voltage waveform. For example, a lower fundamental frequency (e.g., a lower switching frequency f sw ) results in a lower voltage across the inductance 214, which is proportional to the current I b To enable transition control, the transition control module 234 and the transition control module 1623 depicted in FIG. b and V out to mitigate unwanted vibrations (at out the desired response time to achieve the desired voltage at step The method is configured to adjust the fundamental frequency of the asymmetric periodic voltage waveform to provide a desired time to achieve the desired period.

[0130] The PWM signal can be a voltage pulse (rising above 0.9 volts) that is used to close the switches described herein. It is also envisioned that PWM optical pulses can be utilized to control optically activated switches, and the period of the pulses (the time it takes for a cycle of the PWM signal to repeat) can be modulated to vary the switching frequency. While the particular PWM signal depicted in FIG. 22 corresponds to a gate drive signal for a single switch embodiment (e.g., described with reference to FIGS. 5 and 19), it should be appreciated that the fundamental period of a switching cycle in a two-switch embodiment (e.g., shown in FIG. 4) can be varied (e.g., the time between t0 and t4 can be varied in the timing diagram depicted in FIG. 4). As shown in FIG. 22 (and previously described with reference to FIGS. 16 and 17), the fundamental frequency of the asymmetric periodic voltage waveform can be adjusted to match the desired ion energy value E ion and the desired ion energy distribution ΔE ionIt should also be recognized that the fundamental frequency of the asymmetric periodic voltage waveform may be varied between the steady-state portions of different states to achieve this. However, varying the fundamental frequency of the asymmetric periodic voltage waveform from steady-state operation to steady-state operation differs from transition control in that the fundamental frequency during the transition is neither the fundamental frequency of the current state nor the fundamental frequency of the next state.

[0131] 21, which is a flowchart depicting a transition control method that may be considered in connection with embodiments disclosed herein. As shown, an asymmetric periodic voltage waveform is applied and a corresponding current waveform is provided (block 2102), and when a signal is received to change from a current (i.e., present) state of the asymmetric periodic voltage waveform to a next state of the asymmetric periodic voltage waveform (block 2104), at least one of the first, second, and third portions of the asymmetric periodic voltage waveform is adjusted (e.g., adjusted by a first power supply (V supply At the same time, an adjustment is made to the fundamental frequency of the asymmetric periodic voltage waveform to settle into the next state (block 2106). As discussed above, the fundamental frequency during the transition is different from the fundamental frequency during either the current or next state.

[0132] An example of the transition control method and its benefits is shown in Figure 23. The steady state settings that produce the waveforms in Figure 23 are the same as the steady state settings that produce the waveforms in Figure 22. However, the inductance current I (through inductance 214) in Figure 23 is b , voltage V out , and the sheath voltage V s are very different under transition control. It should be appreciated that Figure 23 is only an example of the types of events that may be experienced by the bias supply, and that the transition control in block 2106 is applicable to any single event state change, such as the bias supply 108 changing from an off state to an on state.

[0133] For example, the inductance current I occurs after the first state change (without transition control) and lasts for 60 microseconds. b , output voltage Vout , and the sheath voltage V s In contrast to the substantial transient oscillations in b , output voltage V out , and the sheath voltage V s is fully settled by about 40 microseconds with much smaller fluctuations during oscillation. As shown in FIG. 23, the signal indicating a change of state occurs at about 2 microseconds, after which the voltage V applied by the second power supply supply begins to change, but in contrast to the control approach depicted in FIG. 22 (which begins applying the steady-state fundamental frequency of the asymmetric periodic voltage waveform immediately after the state change signal), in FIG. 23 three PWM signals are applied at longer fundamental frequencies (longer than the steady-state fundamental frequency for the second state) from about 2 microseconds to about 12 microseconds, and then four PWM signals are applied at faster fundamental frequencies (faster than the steady-state fundamental frequency for the second state) from about 12 microseconds to about 19 microseconds before the asymmetric periodic voltage waveform is applied at the steady-state fundamental frequency at about 19 microseconds.

[0134] FIG. 23 illustrates another advantage of transition control: step This also illustrates the ability to arrive at a voltage more quickly. More specifically, at approximately 73 microseconds, when a state change signal is received that triggers a second state change, a lower fundamental frequency (lower than the steady state fundamental frequency for the third state) is utilized two cycles to bring a lower voltage across inductance 214, which in turn brings a lower level of current I b (during the first 10 microseconds after the second state change) and a lower output voltage V out (for the same time frame depicted in FIG. 22). More specifically, when a signal is received that triggers a second state change at approximately 73 microseconds, without transition control, V out The asymmetric periodic voltage waveform at V step However, with transition control, V step The desired level of is achieved at approximately 92 microseconds.

[0135] From the operator's perspective (e.g., when the operator is running a recipe), state changes can be considered (and controlled) in terms of ion energy (and / or ion energy distribution), but the ion energy is determined by the substrate voltage (which can be characterized in terms of sheath voltage), and the substrate voltage (also referred to as wafer voltage) is determined by the asymmetric periodic voltage waveform. Therefore, state changes can also be viewed in terms of changes to the asymmetric periodic voltage waveform. For example, V (shown in FIGS. 4 and 5) step A change to V can be used to effect a state change in ion energy, step can be adjusted by adjusting the second portion of the asymmetric periodic voltage waveform (t2 to t3 in FIG. 4). Then, as described with reference to FIG. 12, the first power supply 216 (herein referred to as V supply (also referred to as a "variable voltage") may be used to vary the first, second, and third portions of the asymmetric periodic voltage waveform.

[0136] The adjustment of the fundamental frequency of the asymmetric periodic voltage waveform (at block 2106) may be performed to settle to a next state after a predefined transition time using a predefined transition type, where the transition time and / or transition type may be established in a lookup table as discussed further herein.

[0137] Referring to FIGS. 24A-24B, the current I through the inductance 214 b and the corresponding voltage across the inductance V b Examples of the linear current ramp trajectory and the inductance voltage V are shown, which can be achieved by varying from the fundamental frequency of the asymmetric periodic voltage waveform during the transition from one state to another. b Figure 24B depicts the corresponding flat trajectory for the inductance voltage V bFIG. 24C depicts an exponential decay current curve and corresponding trajectory of the inductance voltage V. b The inductance current I to produce a decreasing lamp voltage for b FIG. 24D shows the inductance current I b Overshoot trajectory and inductance voltage V for b 24E depicts the corresponding trajectory for the inductance current I b Undershoot waveform and corresponding inductance voltage V for b Depicts the following.

[0138] Referring now to FIG. 25, a variation of the method described with reference to FIG. 21 is shown, in which the inductance current I b or the inductor voltage V b is related to the transition type and time, V out As shown, the bias supply 108 performs bias control for the current state (block 2500) until the next state is requested (block 2502), at which point the inductance current I b The latest value of the inductance current I is saved (block 2504). b If is not available for both states (block 2506), bias control for the next state is performed (block 2518).

[0139] However, the inductance current I b If I is available for both states (block 2506), a variable I1 is set equal to the most recent value for the inductance current of the current state, and another variable I2 is set equal to the last saved value for the inductance current of the next state (block 2508). Then, a transition type (e.g., any of the transition types depicted in Figures 24A-24E) is loaded along with the time for the transition (block 2510), and the desired inductance current Ib or the inductance voltage V b is calculated (block 2512) and used to determine the fundamental frequency of the asymmetric voltage waveform, and a transition control is performed (block 2514) until the transition time expires (block 2516), at which point the steady state bias control for the next state is used to control the bias supply 108 (block 2518). The transition control in block 2514 may be performed according to different methods, including, but not limited to, a bang-bang control method (e.g., as described with reference to FIGS. 26 and 27), a proportional-integral-derivative (PID) compensator method (e.g., as described with reference to FIGS. 27 and 28), and a look-up table method (e.g., as described with reference to FIG. 30).

[0140] Referring to FIG. 26, for example, current sensing is used (at block 2514) to measure the inductance current I b A method for performing transition control according to a bang-bang method for obtaining the inductance current I b The desired trajectory for b_ref is calculated (block 2600) to yield the average inductance current I b_ave is obtained (block 2602). As shown, the average inductance current I b_ave is acquired during a time window set by the PWM reset signal 2605. As shown, the reference current value I b_ref and the average inductance current I b_aveA difference value 2603 representing the difference between the maximum period and the actual PWM signal 2608 is obtained (block 2604), and then a minimum PWM period check is performed (block 2606) to generate a PWM reset signal 2605 using the difference value 2603 and feedback 2607 of the actual PWM signal 2608. The PWM reset signal 2605 is used to generate a PWM signal 2608 with a maximum period timeout (block 2611). The PWM signal 2608 is then used by a switcher driver 2610 to provide switching signals to one or more switches for adjusting the fundamental frequency of the asymmetric periodic voltage waveform.

[0141] Referring now to FIG. 27, (at block 2514) the inductor voltage V b Another method is presented for performing transition control according to the bang-bang method using sensing of the inductance voltage V b The desired trajectory of the reference voltage V b_ref is calculated (block 2700) to yield the average inductance voltage V b_ave is obtained (block 2702). b The trajectory of the is based on a predefined shape, or I b can be obtained based on the orbit, V b =L b di b / dt. As shown, the average inductance voltage V b_ave is taken during a time window set by the PWM reset signal 2705 (the average in 2702 is reset at the start of each PWM cycle). b The sensing to obtain V b =V out -V s (V s This can be done directly or indirectly using a reference voltage value V b_ref and the average inductance voltage V b_aveA difference value 2703 between is obtained (block 2704), and then a minimum PWM period check is performed (block 2706) to generate a PWM reset signal 2705 using the difference value 2703 and feedback 2707 of the actual PWM signal 2708. The PWM reset signal 2705 is used to generate a PWM signal 2708 with a maximum period timeout (block 2711). The PWM signal 2708 is then used by a switcher driver 2710 to provide switching signals to one or more switches for adjusting the fundamental frequency of the asymmetric periodic voltage waveform.

[0142] 28 and 29, additional methods for performing transient control (at block 2514) according to proportional-integral-derivative (PID) compensator methods are shown, including integrator-only, proportional-only, PI, and PID. Unlike traditional PID controllers with fixed sampling rates, the PID compensation methods described with reference to FIGS. 28 and 29 execute every PWM cycle, and the cycle period varies. In these methods, the compensator coefficients can be constant or a function of the PWM cycle.

[0143] In the method depicted in Figure 28, the inductance current I b The desired trajectory for is calculated and the reference current value I b_ref (block 2800) and the average inductance current I b_ave is obtained (block 2802). The average inductance current I b_ave is acquired during a time window set by the PWM signal 2807. As shown, the reference current value I b_ref and the average inductance current I b_ave I show the difference between b An error value is obtained (block 2804) and then the PID compensation with minimum and maximum limits is applied to I bThe PID compensation is performed using the error value and the sample ready signal 2803 (block 2806). As shown, PID compensation with minimum and maximum limits may yield a PWM period value or dead time value, which may be used to generate a PWM signal (block 2810). The dead time value may be used in the context of a two-switch embodiment such as shown in FIG. 4. The PWM period value may be used in connection with one-switch and two-switch embodiments and is depicted in FIGS. 4 and 5 as a fundamental period. The PWM signal 2807 is used by the switcher driver 2610 to provide switching signals to one or more switches for adjusting the fundamental frequency of the asymmetric periodic voltage waveform.

[0144] Referring to Figure 29, the inductance voltage V b The desired trajectory for the reference voltage value V b_ref is obtained (block 2900) to produce an average V b_ave is obtained (block 2902). The average inductance voltage V b_ave is acquired during a time window set by the PWM signal 2907. As shown, the reference voltage value V b_ref and average voltage and current V b_ave V indicates the difference between b An error value is obtained (block 2904), and then the PID compensation with minimum and maximum limits is applied to V b The error value and sample ready signal 2903 are used (block 2906). As shown, PID compensation with minimum and maximum limits may yield a PWM period value or dead time value, which may be used to generate a PWM signal (block 2910). The dead time value may be used in the context of a two-switch embodiment such as shown in FIG. 4. The PWM period value may be used in connection with one-switch and two-switch embodiments and is depicted in FIGS. 4 and 5 as a fundamental period. The PWM signal 2907 is used by the switcher driver 2610 to provide switching signals to one or more switches for adjusting the fundamental frequency of the asymmetric periodic voltage waveform.

[0145] 30, a flowchart is shown depicting a method for performing transition control (at block 2514) according to a lookup table approach. As shown, the bias supply 108 may perform bias control for a current state (block 3002) until a next state is requested (block 3004), when a new state is requested (at block 3004), a pre-programmed transition is performed (block 3006), and when the transition is complete, bias control for the next state is performed (block 3008). The pre-programmed transition may be performed utilizing a lookup table, which generally provides data that can be used to set the fundamental frequency in association with the amount of cycles for each fundamental frequency setting.

[0146] For example, Figure 31 shows an exemplary lookup table that may be used to define pre-programmed transitions for one or more state changes. Generally, the lookup table may define the transitions in terms of waveform timing parameters (related to the fundamental period of the asymmetric voltage waveform) and number of cycles. Examples of waveform timing parameters include, but are not limited to, t ramp and t reset (t ramp and t reset 4 and 5), a PWM period (depicted as a fundamental period in FIGS. 4 and 5), and a dead time (depicted and described with reference to FIG. 4). As shown in FIG. 31, a PWM period is utilized as an example waveform timing parameter, and for each PWM period value, there is a corresponding number of PWM cycles. More specifically, during a transition from State 0 to State 1, a PWM period of T01 is used for N_01 PWM cycles, a PWM period of T02 is used for N_02 PWM cycles, and any number of waveform timing values ​​(each having a corresponding number of PWM cycles) up to T_0M may be used.

[0147] Referring now to FIG. 32, a flow chart is shown depicting a method that is a variation of the method described with reference to FIG. 21, in which state transition control is performed by V step or V pk- Based on V step and V pk- 4 and 5. As shown, the bias supply 108 performs bias control for the current state (block 3200) until the next state is requested (block 3202), at which point V step and V pk- The latest value of V is saved (block 3204). As shown, the next state is the new V step (Block 3206), the variable V1 is V (current state) step and variable V2 is set to the last saved value for V (in the next state). step The next state is set to the latest value for V (block 3208), and then the transition type and time are loaded (block 3212). step If V1 contains V (current state), step V is set to the latest value for V step The new value for V is set (block 3210), and then the transition type and time are loaded (block 3212). step or V pk- Any desired values ​​for are calculated (block 3214) before executing transition control (block 3216) until the transition time expires (block 3218). Once the transition time expires, bias control for the next state is then executed (block 3220).

[0148] 33, a flowchart illustrating an example of a method for performing transition control (at block 3216) according to the bang-bang method is shown. pk- The desired trajectory for the reference V is calculated. pk- Produce a value (block 3300), V outA measurement of is taken (block 3302). As shown, the reference V pk- Value and V out A difference value 3303 indicating the difference between V and V is obtained (block 3304), and then a minimum PWM period check is performed (block 3306), and the difference value 3303 and feedback 3307 of the actual PWM signal 3308 are used to generate a PWM reset signal 3305. The PWM reset signal 3305 is used to generate a PWM signal 3308 with a maximum period timeout (block 3310). The PWM signal 3308 is then used by the switcher driver 2610 to provide switching signals to one or more switches for adjusting the fundamental frequency of the asymmetric periodic voltage waveform. V pk- The trajectory calculation may involve obtaining a predefined shape, or V step Based on the orbit, V pk- ≒V step (1.5 to 2Kc), where:

number

[0149] 34, a flow diagram of another example of a method for performing transient control (at block 3216) according to a PID compensator method is shown. As shown, V step Orbit calculations are performed and the reference V step Produce a value (block 3400), V step V out A calculation is performed to obtain from V step V out The calculation to obtain from the reference V is performed during the time window set by the PWM signal 3407. As shown, step Value and V step Show the difference between the calculated values ​​for V step An error value is obtained (block 3404), and then the PID compensation with minimum and maximum limits is applied to V stepThe PID compensation is performed using the error value and the sample ready signal 3403 (block 3406). As shown, PID compensation with minimum and maximum limits may yield a PWM period value or dead time value 3405, which may be used to generate a PWM signal (block 3410). The dead time value may be used in the context of a two-switch embodiment such as shown in FIG. 4. The PWM period value may be used in connection with one-switch and two-switch embodiments, with the PWM period being depicted in FIGS. 4 and 5 as the fundamental period. The PWM signal 3407 is used by the switcher driver 2610 to provide switching signals to one or more switches to adjust the fundamental frequency of the asymmetric periodic voltage waveform.

[0150] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0151] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0152] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0153] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

[0154] Many embodiments and methods described herein may be implemented using a processor in conjunction with processor-executable instructions and a field-programmable gate array (programmed by hardware description language instructions). Non-volatile memory may be encoded with instructions executable by the processor and / or readable by the field-programmable gate array, e.g., to program the field-programmable gate array. In some embodiments, the FPGA is used for high-speed processing and control, including switching control, measurement, pulsing, and multi-level operation, while the processor is utilized for other, slower processing. Referring to FIG. 35, for example, a block diagram is shown depicting the physical components of a controller that may be utilized to implement the control aspects disclosed herein.

[0155] As shown, in this embodiment, display 1312 and non-volatile memory 1320 are coupled to bus 1322, which is also coupled to random access memory (“RAM”) 1324, processing portion (including N processing components) 1326, field programmable gate array (FPGA) 1327, and transceiver component 1328, which includes N transceivers. While the components depicted in FIG. 20 represent physical components, FIG. 20 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 20 may be realized by a general structure or distributed among additional physical components. Furthermore, it is envisioned that other existing and yet-to-be-developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG. 20.

[0156] The display 1312 generally operates to provide a user interface for a user, and in some implementations, the display is realized by a touch screen display. Generally, the non-volatile memory 1320 is a non-transitory memory that functions to store (e.g., persistently store) data and processor-executable code (including executable code associated with steps that effectuate the methods described herein). In some embodiments, for example, the non-volatile memory 1320 includes boot loader code, operating system code, file system code, and non-transitory processor-executable code to facilitate execution of methods of biasing a substrate using the bias supply apparatus 208 described herein. The non-volatile memory 1320 is executable by the processor and / or readable by the field programmable gate array, e.g., may be encoded with instructions that program the field programmable gate array, such that the instructions (when executed by the processing portion 1326 or provided by the FPGA 1327) cause the bias supply apparatus 108 to perform the methods disclosed herein. Those skilled in the art will also appreciate that FPGA 1327 may also include non-transitory media integrated with the FPGA.

[0157] In many implementations, non-volatile memory 1320 is realized by flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from non-volatile memory 1320, executable code in non-volatile memory is typically loaded into RAM 1324 and executed by one or more of the N processing components in processing portion 1326.

[0158] The N processing components, in association with RAM 1324, generally operate to execute instructions stored in non-volatile memory 1320 to enable performance of the algorithms and functions disclosed herein. While several algorithms are disclosed herein, it should be appreciated that some of these algorithms are not represented in flowcharts. Processor-executable code for effecting the methods described herein may be persistently stored in non-volatile memory 1320 and executed by the N processing components in association with RAM 1324. As one skilled in the art would understand, processing portion 1326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing component or a combination of hardware and software processing components (e.g., an FPGA or FPGAs including digital logic processing portions).

[0159] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1320 and accessed (e.g., during boot-up) to configure the field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0160] The input component 1330 may be a power-related signal (e.g., an output current I) obtained (e.g., by a current transformer, a VI sensor, a current transformer, and / or a voltage sensor) at the output node 210 and / or the feedback node 212 of the disclosed bias supply 208. out and voltage V out The input component 1330 may receive a signal indicative of the inductor current I b and the inductor voltage V b A signal indicating

[0161] Although not required, in some implementations, the FPGA 1327 samples the power-related signals and calculates the output current I out and the output voltage V out, and may provide a digital representation of the bias supply 108 and the source generator 112. In some embodiments, the processing component 1326 (in conjunction with processor-executable instructions stored in the non-volatile memory 1320) is used to realize the data processing modules, comparators, and compensators disclosed herein. However, the FPGA 1327 may also be used to implement these functions. Additionally, the input component 1330 may receive phase information and / or synchronization signals between the bias supply 108 and the source generator 112 that indicate one or more aspects of the environment within the plasma processing chamber 101 and / or synchronized control between the source generator and the single-switch bias supply. Signals received at the input component 1330 may include, for example, synchronization signals, power control signals for various generator and power supply units, or control signals from a user interface. Those skilled in the art will readily understand that any of a variety of types of sensors, such as, but not limited to, directional couplers and voltage-current (VI) sensors, can be used to sample power parameters such as voltage and current, and that signals indicative of the power parameters can be generated in the analog domain and converted to the digital domain.

[0162] The output components generally operate to provide one or more analog or digital signals to provide gate drive signals for opening and closing switches. The output components may also control the power supplies described herein.

[0163] The depicted transceiver component 1328 includes N transceiver chains that can be used to communicate with external devices over wireless or wired networks, each of which can represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0164] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining all software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied thereon.

[0165] As used herein, the recitation of "at least one of A, B, and C" or "at least one of A, B, or C" is intended to mean "any of A, B, or C or any combination of A, B, and C." The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bias supply device for applying a periodic voltage, wherein the bias supply device is A switch network and at least one power supply device, wherein the switch network and at least one power supply device are configured together to apply a periodic voltage waveform at a first node, Controller and Equipped with, The aforementioned controller, Receiving a signal to change from the current state to the next state, During the transition from the current state to the next state, the switching frequency of the switch network is adjusted so that it settles into the next state after the transition. A bias supply device configured to perform the following actions.

2. The bias supply device according to claim 1, wherein the controller comprises a lookup table for accessing waveform timing parameter values ​​and a corresponding number of pulse width modulation cycles for each timing parameter value.

3. The bias supply device according to claim 1, wherein the controller comprises a feedback control loop for adjusting the frequency of the periodic voltage waveform during the transition.

4. The bias supply device according to claim 3, wherein the feedback control loop utilizes a bang-bang control scheme.

5. The bias supply device according to claim 3, wherein the feedback control loop utilizes a proportional-integral-derivative control scheme.

6. The bias supply device according to claim 1, wherein the controller is configured to adjust the switching frequency of the at least one power supply device and the switch network according to a transition type selected from the group consisting of a linear current ramp transition, an exponential decay current transition, a concave parabolic current transition, an intentional overshoot transition type, and an intentional undershoot transition type.

7. The bias supply device according to claim 1, wherein the controller is configured to adjust the frequency according to a predefined transition time using a predefined transition type.

8. A method for applying a periodic voltage, wherein the method is Applying a periodic voltage waveform, Receiving a signal to change the current state of the periodic voltage waveform to the next state of the periodic voltage waveform, During the transition from the current state to the next state, the frequency of the periodic voltage waveform is adjusted so that it settles into the next state after the transition. Methods that include...

9. The method according to claim 8, wherein the adjustment includes accessing a lookup table for accessing waveform timing parameter values ​​and the corresponding number of pulse width modulation cycles for each timing parameter value.

10. The method according to claim 8, wherein the adjustment includes utilizing a feedback control loop for adjusting the frequency.

11. The method according to claim 10, wherein the feedback control loop utilizes a bang-bang control scheme.

12. The method according to claim 10, wherein the feedback control loop utilizes a proportional-integral-derivative control scheme.

13. The method according to claim 8, wherein the adjustment includes adjusting the frequency according to a transition type selected from the group consisting of linear current ramp transitions, exponentially decaying current transitions, concave parabolic current transitions, intentional overshoot transition types, and intentional undershoot transition types.

14. The method according to claim 8, comprising adjusting the frequency according to a predefined transition time using a predefined transition type.

15. A non-transient medium encoded with instructions executable by a processor and / or instructions readable by a field-programmable gate array, wherein the instructions are The bias supply device is made to apply a periodic voltage waveform, Processing a signal to change the current state of the periodic voltage waveform to the next state of the periodic voltage waveform, During the transition from the current state to the next state, the bias supply device is instructed to adjust the frequency of the periodic voltage waveform so that it settles into the next state. Equipped with instructions for carrying out, A non-transient medium in which the frequency during the transition is different from any of the frequencies in the current state or the next state.

16. The non-transient medium according to claim 15, wherein the instruction includes an instruction for accessing a lookup table for accessing waveform timing parameter values ​​and a corresponding number of pulse width modulation cycles for each timing parameter value, and for adjusting the frequency.

17. The non-transient medium according to claim 15, wherein the instruction comprises an instruction for adjusting the frequency of the periodic voltage waveform during the transition using a feedback control loop.

18. The non-transient medium according to claim 17, wherein the feedback control loop utilizes a bang-bang control scheme.

19. The non-transient medium according to claim 17, wherein the feedback control loop utilizes a proportional-integral-derivative control scheme.

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