Capacitive Micromachined Ultrasonic Transducer Arrays on Printed Circuit Boards

Abstract

Capacitive micromachined ultrasonic transducers (CMUTs) can be fabricated on prefabricated, interconnected substrates such as printed circuit boards (PCBs). PCBs can be rigid or flexible. The substrate can also be ceramic. CMUTs can be polymer- or silicon-based. Arrays of CMUTs can also be fabricated, consisting of multiple CMUT elements, each consisting of an individual CMUT cell. CMUT elements on a substrate such as a PCB are electrically connected to electrical interconnects (vias), allowing selective control of individual elements. CMUTs can be fabricated by depositing, patterning, and etching away various materials on the substrate, with the solvents used for etching being selected to be chemically compatible with the substrate and other materials deposited on it.

Description

[Technical Field]

[0001] This application relates generally to capacitive micromachined ultrasound transducer arrays, and more particularly to methods for manufacturing transducer arrays using pre-fabricated interconnected substrates such as printed circuit boards (PCBs). [Background technology]

[0002] Ultrasound systems have used piezoelectric materials in their transducers since the 1930s. Materials such as piezoelectric crystals (e.g., quartz), ceramics (e.g., lead zirconate titanate [PZT]), and polymers (e.g., polyvinylidene fluoride [PVDF]) are known transducer materials.[1] Although piezoelectric transducer technology is mature, it has many drawbacks, including technical challenges in manufacturing large two-dimensional arrays due to difficulties in interconnection and integration at the die level.[1]

[0003] Acoustic impedance (the speed of sound in a material multiplied by its density, measured in Rayls) is a measure of the resistance a system offers to an applied acoustic pressure. It is an important quantity in piezoelectric-based ultrasound systems because it determines the amount of acoustic power that is effectively transferred to the target material being imaged. An "acoustic matching layer" is an essential structure in piezoelectric-based systems to reduce the impedance mismatch between the impedance of the piezoelectric crystal and the lower or higher impedance of the target material (e.g., tissue or metal). These matching layers are typically made of high-density rubber combined with a liquid gel and are placed between the crystal and the target material.

[0004] Capacitive micromachined ultrasonic transducers (CMUTs) are an alternative technology to current piezoelectric-based transducers [1]. CMUTs are essentially parallel-plate capacitors with a bottom electrode fixed to a substrate and a membrane suspended over a cavity and sealed along its edges. Metal electrodes are patterned on the suspended membrane. CMUTs emit ultrasound when an AC signal superimposed on a DC voltage is applied between these electrodes. Ultrasound can be detected by measuring the change in the device's capacitance when a DC voltage is applied in the presence of incoming ultrasound. CMUTs are most often fabricated from silicon-based materials on silicon substrates. However, acoustic mismatches still exist with CMUTs because silicon has a higher acoustic impedance than soft tissue and a lower acoustic impedance than metals or composites.

[0005] U.S. Patent Nos. 10,509,013, 10,564,132, and 10,598,632, all of which are incorporated herein by reference, describe the microfabrication of ultrasonic transducers using polymer membranes. These polymer-based CMUTs (poly-CMUTs) can, at least in some cases, operate at lower operating voltages than piezoelectric or silicon-based CMUTs.

[0006] U.S. Patent Nos. 10,509,013, 10,564,132, and 10,598,632 collectively describe two methods for micromachining CMUTs: surface micromachining and wafer bonding. In surface micromachining, the cavity beneath the membrane is formed by depositing or growing a sacrificial layer on a carrier substrate. After membrane deposition, the sacrificial layer is removed with an etchant specifically selected to dissolve the sacrificial material through the etching channels without damaging the membrane material. In wafer bonding, the membrane and cavity are defined on separate wafers, which are then bonded together under vacuum conditions. Because no etching channels are required, the manufacturing process is simplified and high fill factors can be achieved.

[0007] Silicon nitride and polysilicon are the most common materials for fabricating CMUT films, and chromium and aluminum are typically used to pattern electrodes on these films. These materials are chosen primarily for their mechanical properties, allowing the films to be as thin as possible to minimize the effective gap between the bottom and top (or "hot") electrodes. Reducing the effective gap between the electrodes increases the electric field, improving impedance matching with the electronic components driving the CMUT. Once the desired operating frequency and maximum bias voltage are identified, it is preferable to design the CMUT film as thick as possible, given that the bandwidth of the CMUT film increases linearly with thickness.

[0008] Through-silicon vias (TSVs) are vertical electrical interconnects that pass through a silicon wafer or chip, connecting different layers of a circuit. TSVs are used to achieve higher performance, smaller form factors, and greater integration in semiconductor devices. TSVs offer several advantages, including reduced signal propagation delay, increased bandwidth, and the ability to compactly connect multiple chip layers. The main limitation of TSVs is that they only allow communication between opposing surfaces (front and back) of a substrate through a vertical conductive channel.

[0009] Printed circuit boards (PCBs) can facilitate routing on various layers through the use of vias and multi-layer construction. Through-hole vias penetrate the entire thickness of the PCB, connecting all layers. They are commonly used for components and traces that require a strong connection. Blind and buried vias connect only specific layers of the PCB. Blind vias connect an outer layer to one or more inner layers, while buried vias connect two or more inner layers. Both types of vias allow for more complex routing without affecting the outer layers. Today's PCBs often consist of multiple layers of copper traces separated by insulating material in the form of the PCB's substrate. The inner layers are sandwiched between the outer layers. Each layer can be used for routing, power layers, or ground layers.

[0010] PCBs can be manufactured using materials such as FR-4 (fiberglass reinforced epoxy), high Tg materials for high temperatures, flexible materials like polyimide and polyester, rigid-flex materials that combine stiffness and flexibility, metal core materials for improved heat dissipation, ceramic materials for high temperature stability, RF / microwave materials for high frequency applications, and specialty materials for specific performance requirements like Teflont™ (PTFE). The choice depends on factors such as the application, thermal management, operating frequency, and desired electrical and mechanical properties.

[0011] Low-temperature co-fired ceramic (LTCC) is a ceramic electronic component technology used to manufacture ceramic PCBs or PCBAs (i.e., PCB assemblies with all components on the PCB). LTCC evolved from HTCC (high-temperature co-fired ceramic) technology in 1982 and is a multilayer, low-temperature ceramic PCB manufacturing technology. HTCC is a ceramic primarily composed of alumina (Al2O3) and aluminum nitride (AlN). LTCC is a ceramic made by mixing glass with alumina and is commonly referred to as "glass ceramic." HTCC substrates are cured at temperatures above 1500°C. Because of the high curing temperature, tungsten (W) and molybdenum (Mo) are used for circuit electrodes due to their high melting points. For LTCC substrates, the curing temperature can be reduced to 900°C by mixing glass with the alumina ceramic. This allows the use of silver or copper, which have low electrical conductivity, for wiring.

[0012] PCBs made with FR-4 utilize a composite of fiberglass and epoxy, offering adequate electrical insulation and mechanical strength for standard electronic components. FR-4 is versatile and cost-effective for general-purpose electronic components and can be manufactured in numerous manufacturing facilities around the world. In contrast, PCBs made with LTCC involve laminating ceramic tapes with embedded conductors, resulting in excellent electrical properties, high thermal stability, and suitability for high-frequency and high-temperature applications, making them ideal for RF modules, microwave devices, and sensors in demanding environments. Summary of the Invention

[0013] According to an aspect of the present disclosure, a method for fabricating a capacitive micromachined ultrasonic transducer includes removing a layer from a top surface of a substrate, wherein at least one pair of electrical interconnects extends through at least a portion of the substrate and is exposed on the top surface; depositing a first conductive material on the top surface after the removal, wherein the first conductive material covers the pair of electrical interconnects; patterning the first conductive material to form contact areas for a bottom electrode and a top electrode, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects and the contact area for the top electrode is electrically connected to the other of the pair of electrical interconnects; and after patterning, depositing a sacrificial material on the bottom electrode. patterning the sacrificial material to form a sacrificial membrane area connected to at least one sacrificial etching channel; depositing a first polymer or silicon layer over the substrate, the bottom electrode, the contact area, and the sacrificial material after patterning the sacrificial material; patterning the first polymer or silicon layer to form at least one via leading to the at least one sacrificial etching channel; depositing a second conductive material on the first polymer or silicon layer and over the contact area for the top electrode; patterning the second conductive material to avoid electrical connection with the bottom electrode; and etching away the sacrificial membrane area using the at least one via.

[0014] A first polymer layer may be deposited over the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material has been patterned, and the method may further include depositing a second polymer layer over the second conductive material and the sacrificial membrane area, and patterning the second polymer layer so as not to block the at least one via. Alternatively, a silicon layer may be deposited over the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material has been patterned.

[0015] The substrate may comprise a printed circuit board, which may be flexible.

[0016] The substrate may comprise a ceramic.

[0017] Layer removal may be performed mechanically, for example, layer removal may include polishing or grinding the top surface of the substrate.

[0018] The layer removal may be performed chemically, for example, the layer removal may include etching the top surface of the substrate.

[0019] Before removing the layer, pads of conductive material may each be electrically coupled to a pair of electrical interconnects on the top surface, and removing the layer may include removing the pads and a portion of the substrate.

[0020] After removal, the top surface may have a surface roughness of 50 nanometers or less.

[0021] The first conductive material may comprise a layer of gold between two layers of chromium.

[0022] The first conductive material may have a thickness of about 100 nm.

[0023] The thickness of the sacrificial material may be about 200 nm.

[0024] Depositing the sacrificial material may include depositing a layer of lift-off resist and then depositing a layer of positive photoresist.

[0025] Patterning the sacrificial material can be performed by wet etching using an aqueous solution containing tetramethylammonium hydroxide.

[0026] The first polymer layer may have a thickness of about 700 nm.

[0027] Depositing the second conductive material may include depositing a layer of titanium and then depositing a layer of gold.

[0028] The method may further include encapsulating the transducer with an encapsulating material.

[0029] The bottom surface of the substrate may include pads of conductive material each electrically coupled to a pair of electrical interconnects, and the method further includes covering the pads on the bottom surface before encapsulating the transducer to prevent the pads from being covered by the encapsulating material.

[0030] The method may further include, after the top surface layer is removed and before depositing the first conductive material, depositing a planarizing layer over the top surface, and patterning the planarizing layer to leave exposed electrical interconnects on the top surface.

[0031] The thickness of the planarization layer may be about 1 μm.

[0032] The planarization layer may include SU-8 photoresist.

[0033] The planarization layer may have a roughness of 50 nanometers or less.

[0034] Prior to removing the layer from the top surface of the substrate, the method further includes depositing a substrate conductive material on the surface of the substrate and patterning the substrate conductive material to form a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode, wherein the substrate conductive area for the bottom electrode is electrically connected to one of a pair of electrical interconnects and the other of the substrate conductive area is electrically connected to the other of the pair of electrical interconnects; and depositing a planarization layer over the substrate and the substrate conductive areas, wherein the substrate conductive area and the contract area for the bottom electrode are electrically connected to the same electrical interconnect and the substrate conductive area and the contract area for the top electrode are electrically connected to the same electrical interconnect, and the layer removed from the top surface of the substrate includes the planarization layer over the substrate conductive material.

[0035] The planarization layer may include an epoxy resin.

[0036] The planarization layer may have a thickness equal to or greater than the thickness of the substrate conductive material.

[0037] The method may further include degassing the planarizing layer after depositing the planarizing layer and before removing the layer from the top surface of the substrate.

[0038] The planarization layer may include a solder mask layer of a printed circuit board.

[0039] The layer removed from the top surface of the substrate can include an upper substrate layer adhered to the substrate. Between the substrate and the upper substrate layer can be a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode, with the substrate conductive area for the bottom electrode electrically connected to one of a pair of electrical interconnects and the other of the substrate conductive areas electrically connected to the other of the pair of electrical interconnects. The substrate conductive area and contract area for the bottom electrode can be electrically connected to the same electrical interconnect, and the substrate conductive area and contract area for the top electrode can be electrically connected to the same electrical interconnect.

[0040] The electrical interconnects may extend non-linearly through the substrate.

[0041] The capacitive micromachined ultrasonic transducer can be one of an array of capacitive micromachined ultrasonic transducers simultaneously fabricated by the method.

[0042] According to another aspect of the present disclosure, there is provided a capacitive micromachined ultrasonic transducer assembly comprising: a printed circuit board (PCB) having at least one pair of electrical interconnects extending through at least a portion of the PCB and exposed on a top surface of the PCB; and a capacitive micromachined ultrasonic transducer cell on the PCB, the capacitive micromachined ultrasonic transducer cell comprising: a bottom electrode electrically connected to one of the pair of electrical interconnects on the top surface; a top electrode electrically connected to the other of the pair of electrical interconnects on the top surface; a polymer or silicon layer between the top electrode and the bottom electrode; and a sealed cavity between the polymer or silicon layer and the bottom electrode.

[0043] The PCB may be flexible. Alternatively, the PCB may comprise ceramic.

[0044] The bottom electrode may be directly on the PCB, or alternatively, the bottom electrode may be on a planarization layer.

[0045] The bottom electrode may be on a planarization layer, which may include a solder mask.

[0046] The bottom electrode may be flush with some of the layers of the PCB.

[0047] The bottom electrode may be flush with a portion of the planarization layer.

[0048] The bottom electrode may be flush with the bottom portion of the polymer or silicon layer.

[0049] The capacitive micromachined ultrasonic transducer cell may be one of an array of capacitive micromachined ultrasonic transducer cells, and the array may include capacitive micromachined ultrasonic transducer elements corresponding to distinct groups selected from the plurality of capacitive micromachined ultrasonic transducer cells, and the capacitive micromachined ultrasonic transducer elements may each be electrically connected to an electrical interconnect.

[0050] The polymer layer may be between the top and bottom electrodes, or the silicon layer may be between the top and bottom electrodes.

[0051] The electrical interconnects may extend non-linearly through the substrate.

[0052] According to another aspect of the present disclosure, an apparatus is provided that includes a printed circuit board having exposed interconnects and a polymer-based capacitive micromachined ultrasonic structure having connections located on the exposed interconnects of the printed circuit board.

[0053] The printed circuit board may have a roughness of less than 1 micrometer.

[0054] The polymer-based capacitive micromachined ultrasonic structure can be a transducer.

[0055] The polymer-based capacitive micromachined ultrasonic structure can be a sensor.

[0056] The polymer-based capacitive micromachined ultrasonic structure can be a receiver.

[0057] The printed circuit board may include a layer of polishable material.

[0058] The layer of polishable material can be polished to achieve a roughness of less than 1 micrometer.

[0059] According to another aspect of the present disclosure, there is provided a method including: obtaining a printed circuit board having a bottom electrode on a surface thereof, the bottom electrode positioned such that the bottom electrode is electrically coupled to a first via in the printed circuit board; depositing a sacrificial layer on the bottom electrode; depositing a first polymer layer on the sacrificial layer; depositing a top electrode on the first polymer layer such that the top electrode is electrically coupled to a second via in the printed circuit board; depositing a second polymer layer on the top electrode; removing the sacrificial layer to provide a cavity; and encapsulating the bottom electrode, the first polymer layer, the top electrode, the second polymer material, and the cavity in an encapsulation material on the printed circuit board. The selection of materials for the printed circuit board may be based on factors such as the intended application, budget, performance requirements, and manufacturing process. Example materials include FR-4 (Flame Retardant 4), high Tg (glass transition temperature) materials, flexible materials (e.g., polyimide and polyester), Rigiflex Technology Inc. rigid-flex materials, metal core materials (MCPCB), ceramic materials, and low dielectric constant RF / microwave materials.

[0060] Obtaining a printed circuit board having a bottom electrode thereon can include depositing the bottom electrode onto the printed circuit board.

[0061] The method may further include polishing the printed circuit board before depositing the bottom electrode.

[0062] Printed circuit boards can be polished to a roughness of less than 1 micrometer.

[0063] The method may further include depositing a planarization layer between the printed circuit board and the bottom electrode.

[0064] The method may further include depositing a planarization layer over the bottom electrode.

[0065] The method may further include polishing the planarization layer to obtain a polished surface of the bottom electrode before depositing the sacrificial layer.

[0066] Obtaining a printed circuit board having a bottom electrode on a surface thereof may include patterning the bottom electrode on an inner layer of the printed circuit board, and the method may further include grinding and polishing the printed circuit board to obtain a polished surface of the bottom electrode before depositing the sacrificial layer.

[0067] According to another aspect of the present disclosure, there is provided a device manufactured according to the above method.

[0068] According to another aspect of the present disclosure, an apparatus is provided, comprising: a printed circuit board including a polished surface and a pair of vias extending through the polished surface; and a polymer-based capacitive micromachined ultrasonic structure disposed on the polished surface and including a top electrode and a bottom electrode, the top electrode being electrically coupled to one of the vias and the bottom electrode being electrically coupled to another one of the vias.

[0069] According to another aspect of the present disclosure, there is provided a device comprising: a printed circuit board fabricated using low-temperature co-fired ceramic (LTCC) or high-temperature co-fired ceramic (HTCC) technology, the printed circuit board having a polished surface and a pair of vias extending through the polished surface; and a silicon-based capacitive micromachined ultrasonic structure disposed on the polished surface, the silicon-based capacitive micromachined ultrasonic structure having a top electrode and a bottom electrode, the top electrode being electrically coupled to one of the vias and the bottom electrode being electrically coupled to another of the vias. LTCC and HTCC technologies enable the fabrication of silicon-based CMUTs because their processing temperatures (above 900°C) are compatible with standard deposition methods for silicon, polysilicon, silicon dioxide, and silicon nitride layers.

[0070] Additional features and advantages of the present disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0071] [Figure 1A-1B] 2A and 2B are top and cross-sectional views, respectively, of a substrate with pre-fabricated conductive vias according to a first embodiment. [Figure 2A-2B] 1C and 1D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 1A and 1B after the substrate has been mechanically polished to remove the annular ring and leave a planarized surface. [Figure 3A-3B] 2C and 2D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 2A and 2B after a first conductive layer has been deposited and patterned to form the bottom electrode of a poly-CMUT cell. [Figure 4A-4B] 3A and 3B are top and cross-sectional views, respectively, of the substrate shown in Figures 3A and 3B after deposition and patterning of a sacrificial layer, which will become the cavity for the poly-CMUT cell. [Figure 5A-5B] 4C and 4D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 4A and 4B after depositing and patterning a first polymer layer. [Figures 6A-6B] 5C and 5D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 5A and 5B after depositing and patterning a second conductive layer. [Figures 7A-7B] 6A and 6B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 6A and 6B after depositing and patterning a second polymer layer, with via holes on the first polymer layer remaining open to allow etching of the sacrificial layer. [Figure 8A-8B] 7A and 7B are top and cross-sectional views, respectively, of the substrate shown in Figures 7A and 7B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with an air-filled cavity. [Figure 9A-9B] 8C are top and cross-sectional views, respectively, of the substrates shown in FIGS. 8A and 8B after the assembly has been sealed with a sealing material deposited in a low-pressure chamber. [Figures 10A-10B] 10A and 10B are top and cross-sectional views, respectively, of a substrate with pre-fabricated conductive vias according to a second embodiment. [Figures 11A-11B]10A and 10B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 10A and 10B after the substrate has been mechanically polished to remove the annular ring and leave a planarized surface. [Figures 12A-12B] 11A and 11B are top and cross-sectional views, respectively, of the substrate shown in Figures 11A and 11B after depositing and patterning a planarization layer, leaving areas on the substrate leading to the vias open for subsequent processing. [Figures 13A-13B] 12C and 12D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 12A and 12B after a first conductive layer has been deposited and patterned to form the bottom electrode of a poly-CMUT cell. [Figures 14A-14B] 13A and 13B are top and cross-sectional views, respectively, of the substrate shown in Figures 13A and 13B after deposition and patterning of a sacrificial layer, which will become the cavity for the poly-CMUT cell. [Figures 15A-15B] 14C and 14D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 14A and 14B after depositing and patterning a first polymer layer. [Figures 16A-16B] 15A and 15B are top and cross-sectional views, respectively, of the substrate shown in Figures 15A and 15B after depositing and patterning a second conductive layer, such that an electrical connection exists between one of the via holes in the substrate and this second conductive layer. [Figures 17A-17B] 16A and 16B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 16A and 16B after a second polymer layer has been deposited and patterned, with the via holes on the first polymer layer remaining open to allow etching of the sacrificial layer. [Figures 18A-18B] 17A and 17B are top and cross-sectional views, respectively, of the substrate shown in Figures 17A and 17B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with an air-filled cavity. [Figures 19A-19B] 18A and 18B are top and cross-sectional views, respectively, of the substrates shown in FIGS. 18A and 18B after the assembly has been sealed with a sealing material deposited in a low-pressure chamber. [Figures 20A-20B]10A and 10B are top and cross-sectional views, respectively, of a substrate having pre-fabricated conductive vias and a central patterned conductive region according to a third embodiment. [Figures 21A-21B] 20A and 20B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 20A and 20B after depositing and patterning a planarizing layer. [Figures 22A-22B] 21A and 21B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 21A and 21B after the substrate has been mechanically polished to remove a portion of the planarization layer. [Figures 23A-23B] 22C and 22D are top and cross-sectional views, respectively, of the substrate shown in FIGS. 22A and 22B after depositing and patterning a sacrificial layer. [Figures 24A-24B] 23A and 23B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 23A and 23B after depositing and patterning a first polymer layer. [Figures 25A-25B] 24A and 24B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 24A and 24B after depositing and patterning a second conductive layer. [Figures 26A-26B] 25A and 25B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 25A and 25B after a second polymer layer has been deposited and patterned, with the via holes on the first polymer layer remaining open to allow etching of the sacrificial layer. [Figures 27A-27B] 26A and 26B are top and cross-sectional views, respectively, of the substrate shown in Figures 26A and 26B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with an air-filled cavity. [Figures 28A-28B] 27A and 27B are top and cross-sectional views, respectively, of the substrates shown in FIGS. 27A and 27B after the assembly has been sealed with a sealing material deposited in a low-pressure chamber. [Figures 29A-29B] 10A and 10B are top and cross-sectional views, respectively, of a substrate having multiple layers and pre-fabricated conductive vias according to a fourth embodiment. [Figure 30A-30B] 29A and 29B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 29A and 29B after the substrate has been mechanically polished to remove portions of the substrate layer and expose conductive areas. [Figure 31A-31B] 30A and 30B are top and cross-sectional views, respectively, of the substrate shown in Figures 30A and 30B after deposition and patterning of a sacrificial layer, which will become the cavity for the poly-CMUT cell. [Figure 32A-32B] 31A and 31B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 31A and 31B after depositing and patterning a first polymer layer. [Figure 33A-33B] 32A and 32B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 32A and 32B after depositing and patterning a second conductive layer. [Figure 34A-34B] 33A and 33B are top and cross-sectional views, respectively, of the substrate shown in FIGS. 33A and 33B after a second polymer layer has been deposited and patterned, with the via holes on the first polymer layer remaining open to allow etching of the sacrificial layer. [Figure 35A-35B] 34A and 34B are top and cross-sectional views, respectively, of the substrate shown in Figures 34A and 34B after the sacrificial layer has been etched in a solvent. The remaining structure is a CMUT with an air-filled cavity. [Figure 36A-36B] 35A and 35B are top and cross-sectional views, respectively, of the substrates shown in FIGS. 35A and 35B after the assembly has been sealed with a sealing material deposited in a low-pressure chamber. [Figure 37A-37B] 10A and 10B are top and cross-sectional views, respectively, of a silicon-based CMUT fabricated on a printed circuit board according to a fifth embodiment, the material of which can withstand the processing conditions (above 400° C.) of the deposition of the silicon, polysilicon, silicon dioxide, and silicon nitride layers. [Figure 38A-38B] 2A-2C are diagrams illustrating the front and back sides, respectively, of a circular-shaped substrate having a plurality of conductive vias, according to an exemplary embodiment. [Figure 39A-39B] 38A and 38B are top isometric and top plan views, respectively, of an exemplary poly-CMUT linear array fabricated from the substrate of FIG. 38A and FIG. 38B. [Figure 40A-40B] 39A and 39B are bottom isometric and bottom plan views, respectively, of the poly-CMUT linear array of FIGS. 39A and 39B. [Figure 41] FIG. 39C is a cross-sectional view of the Poly CMUT linear array of FIGS. 39A and 39B. [Figure 42A-42B] 1A-1C illustrate top and bottom isometric views, respectively, of an example poly-CMUT matrix array fabricated in accordance with an example embodiment. [Figure 43A] 42A and 42B are top views of the Poly-CMUT matrix array of Figures 42A and 42B. The Poly-CMUTs were fabricated on a polished surface with buried vias. [Figure 43B] 43A Detail A showing multiple Poly-CMUT elements in a matrix array, with via holes not visible. [Figure 44A] FIG. 42C is a bottom view of the poly-CMUT matrix array of FIGS. 42A and 42B. [Figure 44B] FIG. 44B is a view of Detail A of FIG. 44A showing multiple conductive vias and annular rings. [Figure 45A] 45A and 45B are bottom views of a Poly-CMUT linear array fabricated in accordance with an example embodiment. Figure 45A shows an electrical contact assembly attached to the backside of the array with multiple electrical tracks. [Figure 45B] 45B illustrates Detail A shown in Figure 45A. An optional electronic component (or circuit including an electronic component, such as a bias tee) is mounted between the via and the electrical contact assembly. [Figure 46A] FIG. 45B is a top view of the Poly-CMUT linear array of FIG. 45A showing multiple Poly-CMUT elements. [Figure 46B] 46B is a cross-sectional view A-A' of FIG. 46A showing multiple buried areas. On the top section are poly-CMUT elements. [Figure 46C] FIG. 46B is a bottom view of the poly-CMUT linear array of FIG. 46A showing multiple contact areas. [Figure 46D] FIG. 46B shows detail B of FIG. 46B, showing several layers of a substrate with embedded electronic components. [Figure 47]1 illustrates an exploded view of a Poly-CMUT transducer assembly fabricated in accordance with an example embodiment, with an acoustic lens mounted above a Poly-CMUT linear array and a contact assembly mounted on the backside. [Figures 48A-48B-48C] 1A-1C are cross-sectional views of linear arrays of Poly-CMUTs fabricated in accordance with example embodiments, with different thicknesses and their relative bending states along at least one axis, where thinner substrates result in less curvature. [Figure 49A-49B] 1 is a photograph of a substrate having a circular shape and a plurality of conductive vias. [Figure 50A] 50A shows detail B shown in FIG. 49B. In FIG. 50A, multiple contact areas are visible to which a conventional electrical header can be attached. [Figure 50B] 50B shows detail C shown in FIG. 50A, where the individual annular rings and even the conductive vias are visible. [Figure 51] 51 shows Detail A of Figure 49A. In Figure 51, several via holes that will connect to the top electrodes of the Poly-CMUT elements are visible. [Figure 52A-52B] 49A and 49B show measurements of the surface roughness of the substrate of FIG. 49A and FIG. 49B before and after polishing the substrate. [Figure 53A] 49A and 49B show a circular substrate with several Poly-CMUT arrays fabricated thereon, according to an example embodiment. [Figure 53B] FIG. 53B shows some of the poly-CMUT arrays of FIG. 53A after the substrate has been diced to mechanically separate the arrays in the substrate. [Figure 54A] 1 shows a linear Poly-CMUT array fabricated in accordance with an example embodiment, with a contact assembly soldered to the bottom of the array. [Figure 54B] The Poly-CMUT array of Figure 54A mounted on a test circuit board, which can be used to independently control the Poly-CMUT elements. [Figure 55A]54C shows the time domain response obtained from the poly-CMUT array of FIG. 54B operating in water. The CMUT transducers have short pulse characteristics. [Figure 55B] FIG. 55B shows the frequency domain response of FIG. 55A using a Fast Fourier Transform (FFT). [Figure 56A] FIG. 10 shows a computer design of a substrate PCB having a circular shape and a plurality of conductive vias shown in an inset. [Figure 56B] FIG. 56B is a back view of the substrate of FIG. 56A showing a plurality of contact pads electrically coupled to conductive vias in the substrate. [Figure 57A] FIG. 56B is a front view of a physical substrate PCB having a circular shape and multiple conductive vias fabricated according to the design of FIG. 56A. A protective solder mask layer acts as a planarizing layer. [Figure 57B] FIG. 57B is a front view of the substrate of FIG. 57A after polishing away the conductive layer and the planarizing layer. [Figure 58A] 57C is a photograph of the polished substrate of FIG. 57B taken using a microscope, showing that the polished surface has a mirror finish. [Figure 58B] FIG. 58B is an enlarged view of the polished substrate of FIG. 58A showing the polished conductive material and the polished planarization layer. [Figure 59A] 57C is a photograph of a stylus surface roughness meter for measuring the surface roughness of the substrate of FIG. 57B. [Figure 59B] FIG. 59B shows a profilometer measurement along the longitudinal axis of the substrate of FIG. 59A to measure the curvature or "bow" of the substrate. [Figure 59C] FIG. 59C shows a profilometer measurement along the longitudinal axis of the substrate of FIG. 59B to measure the surface roughness of the polished conductive material and planarization layer. [Figure 60A] FIG. 1 illustrates surface profilometer measurements along the X and Y axes of a standard 100 mm prime grade silicon wafer with an oxide layer to measure the curvature or "bow" of the substrate. [Figure 60B]59B shows a surface profilometer measurement along the X and Y axes of the substrate of FIG. 59A to measure the curvature or "warp" of the substrate. FIG. [Figure 61A] FIG. 1 shows a short measurement of a surface profilometer along the X-axis of the central area of ​​a standard 100 mm prime grade silicon wafer with an oxide layer to measure the surface roughness of the substrate. [Figure 61B] FIG. 59B shows a short measurement of a surface profilometer along the X-axis of the central region of the substrate of FIG. 59A to measure the surface roughness of the substrate. [Figure 62A] FIG. 59B shows a short measurement of the surface profilometer along the X-axis of the planarization layer area of ​​FIG. 59A to measure the surface roughness. [Figure 62B] 62B shows a shorter measurement (compared to FIG. 62A) of a surface profilometer along the X-axis of the central region of the substrate of FIG. 59A to measure the surface roughness of the substrate. FIG. [Figure 63] 1 is a table of expected ringing effects for FR4 substrates. The expected ringing correlates with the thickness of the substrate. [Figure 64A-64B] 1 is a cross-sectional view of an ultrasonic assembly including a poly-CMUT fabricated in accordance with an example embodiment. [Figures 65A-65B-65C] 1 illustrates a probe assembly fabricated in accordance with an example embodiment, with a flexible Poly-CMUT array at the bottom, which flexes inward in response to pressure within the interior chamber of the probe assembly. [Figures 66A-66B-66C] 1 illustrates a probe assembly fabricated in accordance with an example embodiment with a flexible Poly-CMUT array at the bottom, where the Poly-CMUT array is deflected inward by a deflection mechanism. [Figure 67] 1A-1C illustrate a poly-CMUT linear array fabricated in accordance with an example embodiment, including two planar inductors embedded in a substrate. DETAILED DESCRIPTION OF THE INVENTION

[0072] As used herein: a. "Annular ring" is the area of ​​the copper pad surrounding a drilled and completed via. There is enough conductive material (e.g., copper) around the entire perimeter of this via to form a strong connection between the conductive trace and the via in a multilayer PCB. Therefore, the main purpose of the annular ring is to establish a good connection between the via and the conductive trace that leads to it. In some cases, a via can be formed without the need for an annular ring, or the annular ring may be small enough to be comparable to the diameter of the via. The annular ring is a specific example of a conductive pad that is electrically connected to a via. b. A CMUT "array" is a group of CMUT elements (e.g., 128 elements) arranged side by side in a one-dimensional (1-D) configuration (a "1-D array" or "linear array"), multiple linear arrays arranged side by side (a "1.5-D array"), or a two-dimensional array of CMUT elements (a "2-D array", also known as a "matrix array") that communicate with each other in both dimensions of the array. All of these types of arrays can communicate with a user interface (when connected or activated) by either wired communication or wireless signals. c. "CMUT" means a capacitive micromachined ultrasonic transducer, and includes poly-CMUTs and silicon-based CMUTs unless the context indicates otherwise. d. A CMUT "cell" is a single CMUT transducer with a single movable membrane. e. A CMUT "element" is a group of CMUT cells (typically 100-300 cells). A CMUT element is typically the smallest collection of CMUTs connected to a single electrically coupled electrical connection (i.e., activating a signal along the single electrical connection correspondingly activates all of the CMUT cells that make up the CMUT element). f. "Embedding" an electrode within a polymer layer means completely covering the electrode with polymer except for any electrical connections made to the electrode, which connections are made prior to completely embedding the electrode within the polymer layer. g. "Patterning" a material means selectively removing that material either directly (e.g., if it is photosensitive) or using a masking layer (e.g., in the case of LOR™ compositions). h. The term "polymer-based capacitive micromachined ultrasonic transducer" ("poly-CMUT" or "polyCMUT") refers to a layered ultrasonic device in which a polymer membrane containing a buried upper electrode is suspended over a cavity. An example of a poly-CMUT is found in U.S. Pat. No. 10,598,362 to Gerardo, Rohling, and Cretu. This structure, combined with the formation of a sufficiently thin CMUT cavity, allows the CMUT to reach the MHz operating range without requiring unacceptably high operating voltages. "Poly-CMUT" elements can be formed by the methods disclosed in U.S. Pat. No. 10,598,362 to Cretu et al. or U.S. Pat. No. 7,673,375 to Chang et al. The poly-CMUT is fabricated using the LOR™ lift-off resist composition, which contains cyclopentanone, PGME, a polyaliphatic imide copolymer, and a proprietary dye (less than 2 percent by total volume), and a surfactant; and the light-transmitting polymer-based photoresist material "SU-8," which contains a bisphenol A novolac™ epoxy dissolved in an organic solvent and up to 10 percent by weight of a triarylsulfonium / hexafluoroantimonate salt. The LOR™ composition, as well as the SU-8 photoresist and corresponding SU-8 developer, are available from Kayaku Advanced Materials, Westborough, Massachusetts. i. "Substrate" refers to the underlying material or layer upon which the poly-CMUT device is fabricated. Substrates can include a wide range of metallic materials (e.g., aluminum), non-metallic materials (e.g., ceramics, composites), semiconductors (e.g., silicon), and even polymer-based materials such as polyimide, Kapton™, Plexiglas, or Lexan™. Substrates can also include optically transparent or semi-transparent materials such as glass or indium tin oxide (ITO). Substrates can be rigid, semi-rigid, or flexible. Substrates can also include combinations of the above options, such as a piece of glass coated with a layer of indium tin oxide or a piece of polyimide coated with a metal layer. Substrates in the form of PCBs can be rigid, semi-rigid, moderately flexible (i.e., bendable only to a certain radius of curvature), or fully flexible (i.e., bendable until opposite portions of the PCB touch each other and cannot bend any further). Fully flexible printed circuit boards in particular can be manufactured using, for example, polyimide as the substrate. j. In a substrate such as a PCB, a "via" refers to an electrical interconnection that extends through at least a portion of the substrate. For example, a via can be a conductive path created by filling a hole or opening with a conductive material. This via hole can connect two or more surfaces of a multilayer substrate (e.g., a PCB). Vias are typically formed mechanically (by drilling or laser ablation) or chemically (by selectively etching the substrate using an abrasive). These holes can then be electroplated to create the conductive path for forming the via. A common material for electroplating is copper (Cu) in some embodiments. When creating hollow vias (i.e., holes for vias that are not completely filled with conductive material), the filler can be a conductive or non-conductive epoxy. This is done to avoid contamination of the material and to prevent particle accumulation in the hole. Vias can be plugged vias, capped vias, through-hole vias, blind vias, buried vias, staggered vias, or microvias. Vias may follow non-linear paths through the substrate (i.e., vias need not be direct vertical connections between the top and bottom layers of the substrate). For example, inner layers of a substrate may be interconnected using conductive traces to facilitate deviation from linear vias that extend linearly between the top and bottom layers of the substrate. k. "X-ray mammography" means the practice of breast cancer screening using X-ray imaging of a patient's breasts. Young women, in particular, have a high rate of dense breast tissue. During X-ray imaging, dense breast tissue absorbs X-rays somewhat similarly to potential tumor tissue, making it difficult to distinguish between dense breast tissue and potential tumor tissue. Poly-CMUT arrays are useful in connection with X-ray mammography.

[0073] For quick reference, the following table lists the identifiers used in this document. [Explanation of symbols]

[0074] 10 Assembly 11 Circuit Board 12 Top surface 13 Bottom 14 Upper board layer 15 Lower board layer 21 Beer 22 Annular Ring 23 Substrate conductive material 24 Substrate conductive area for bottom electrode 25 Substrate conductive area for top electrode 26 Substrate conductive contact area 27 Substrate Conductive Track 30 Polished substrate 31 Polished vias 32 Polished Annular Ring 33 Polished substrate conductive material 34 Bottom electrode 35 Polished conductive area for top electrode 36 Polished upper substrate layer 40 Planarization layer 41 Planarization layer via hole 50 Polished planarization layer 100 boards 101 First conductive material 102 Bottom electrode 103 Contact area for top electrode 105 Sacrificial Materials 106 Sacrificial Etching Channel 107 Sacrificial membrane area 110 first polymer layer 111 First polymer via hole 115 Second conductive material 116 Top electrode area 117 Top Electrode Interconnect 120 Second polymer layer 121 Second polymer membrane area 125 Air Area 130 Encapsulating materials 131 Vacuum Area 140 Silicon-based materials 141 Via holes in silicon-based materials 201 PolyCMUT element 202 Poly CMUT linear array 203 Poly CMUT matrix array 204 PolyCMUT array A group of 205 polyCMUT arrays 210 wafer substrate 211 Wafer substrate front 212 Backside of wafer substrate 221 Electrical Interconnection Track 230 Electrical Contact Assembly 231 Electrical contact assembly connection 232 Electrical contact mating connection part 233 Electrical Test Circuit Board 234 Electrical Interface Board 240 Acoustic Lens 241 Electronic Components 242 Planar Inductor 250 Transducer Assembly 251 Probe Assembly 252 Probe Case 260 Passage 261 Inner Chamber 262 Deflection Mechanism 263 Deflected Distance 270 Ultrasound 271 Unfocused Ultrasound Beam 272 Focused Ultrasound Beam 273 focus 280 Wireless Signal

[0075] In this context, at least some embodiments focus on specific customization of Poly-CMUT technology for clinical purposes and non-destructive testing of physical structures.

[0076] Some diagrams of various embodiments are as follows: 1A-9B relate to a manufacturing procedure for a Poly-CMUT according to a first embodiment, in which a PCB with existing via holes is ground and polished to obtain a surface roughness on the order of a few nanometers or less. 10A-19B show a manufacturing procedure for a Poly-CMUT according to a second embodiment, in which a PCB with existing via holes is ground and polished to obtain a surface roughness on the order of tens or hundreds of nanometers. A planarization layer is then deposited to reduce the surface roughness to a few nanometers or less. This can be achieved, for example, by spin-coating a layer of polymer on top. 20A-28B show a fabrication procedure for a Poly-CMUT according to a third embodiment, in which a PCB with existing via holes and an existing bottom electrode is covered with a planarization layer. The substrate is then ground and polished to a surface roughness on the order of tens or hundreds of nanometers, exposing the polished surface of the bottom electrode. 29A-36B illustrate a fabrication procedure for a Poly-CMUT according to a fourth embodiment, involving a multilayer PCB with three or more layers and pre-existing via holes accessible from the bottom. The bottom electrode of the depicted Poly-CMUT is patterned into one of the inner layers and surrounded by a subsequent layer of the same core material. The substrate is then ground and polished to a surface roughness on the order of tens or hundreds of nanometers, exposing the polished surface of the bottom electrode. Because the core material surrounds and encapsulates the bottom electrode, no additional planarization layer is required. 37A and 37B relate to a manufacturing procedure for a silicon-based CMUT according to a fifth embodiment, in which the silicon-based CMUT is manufactured on a ceramic substrate.

[0077] In a first embodiment illustrated in FIGS. 1A (top view) and 1B (cross-sectional view taken along line X-X′ in FIG. 1A ), assembly 10 comprises substrate 11 having exposed top and bottom surfaces 12 and 13, respectively, and vias 21 fabricated in substrate 11. Bottom surface 13 may, in some embodiments, have additional layers (not shown), including a protective layer for the conductive vias or for protecting substrate 11. Vias 21 and annular ring 22 are also exposed. Diameter D2 of annular ring 22 extends beyond diameter D1 of via 21. In these figures, via 21 is shown completely filled for illustrative purposes. The surface roughness of the top surface is a result of the manufacturing process for via 21 and the type of material used for substrate 11. The thickness TC of substrate conductive material 23 used for annular ring 22 is determined from the expected current flow in conductive material 23; the thicker the layer, the greater the current that can flow through the conductive tracks. The thickness T1 of substrate 11 is determined from manufacturing specifications.

[0078] 2A (top view) and 2B (cross-sectional view along line X-X' in FIG. 2A), a portion of top surface 12 of assembly 10 is removed by mechanical means (e.g., a grinder or polisher) or chemical means (e.g., a solvent that etches both substrate 11 and the conductive material used for via 21 and annular ring 22). The thickness of material removed is equal to or greater than the thickness TC of annular ring 22. The initial thickness T1 of substrate 11 is reduced to a thickness T2 after the material is removed. The result is an assembly 10 having a polished substrate 30 and polished via 31 with a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism.

[0079] 3A (top view) and 3B (cross-sectional view along line X-X′ in FIG. 3A ), a first conductive material 101 is deposited over the polished substrate 30 and polished via 31. The first conductive material 101 can be patterned using lithography techniques, such as lift-off or etching of a blanket layer of conductive material. In some embodiments, the first conductive material 101 is a layer of chromium, followed by a layer of gold, followed by another layer of chromium. In some embodiments, the first conductive material 101 can be deposited using a physical vapor deposition system, such as an electron beam metal evaporator. A typical thickness of the first conductive material 101 is tens of nanometers (typically 100 nm) in some embodiments. The first conductive material 101 is patterned into geometric shapes, here to form contact areas 103 for the bottom electrode 102 and the top electrode. The bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101, but they are not electrically connected, and there are areas where the polished substrate 30 is still exposed. The bottom electrode 102 provides the bottom electrode in the Poly-CMUT cell. The contact area 103 for the top electrode provides the electrical connection for the top electrode in the Poly-CMUT cell.

[0080] 4A (top view) and 4B (cross-sectional view taken along line X-X′ in FIG. 4A ), a sacrificial material 105 is deposited over the assembly 10, the polished overlying portion of the substrate 30, and the first conductive material 101. The sacrificial material 105 can be patterned using lithographic techniques, such as lifting off or etching a blanket layer of the sacrificial material. In some embodiments, the sacrificial material 105 is deposited over a layer of LOR™ lift-off resist, followed by a layer of positive photoresist, and then patterned by wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). This layer of sacrificial material 105 can be deposited directly onto flat or curved surfaces with highly controllable thickness using spin coating or spray coating. For example, the sacrificial material 105 can be deposited using lithographic coating techniques (e.g., a spin coater). The typical thickness of this sacrificial material 105 ranges from tens of nanometers to hundreds of nanometers in some embodiments (typically 200 nm), and even micrometers in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form sacrificial etch channels 106 that contact sacrificial membrane areas 107. These sacrificial membrane areas 107 will become the cavities in the poly-CMUT cell. Only the sacrificial membrane areas 107 are visible in the X-X' cross section of FIG. 4B.

[0081] As shown in FIG. 5A (top view) and FIG. 5B (cross-sectional view along line X-X′ in FIG. 5A ), a first polymer layer 110 is deposited over the assembly 10, the polished overlying portion of the substrate 30, the first conductive material 101, and the sacrificial material 105. This first polymer layer 110 can be, but is not limited to, a UV-sensitive material such as SU-8 photoresist. The first polymer layer 110 can be directly patterned using a UV exposure system, followed by wet etching, for example, with an SU-8 developer. The first polymer layer 110 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. In some embodiments, the first polymer layer 110 can be deposited using a lithographic coating technique, for example, a spin coater. A typical thickness of the first polymer layer 110 ranges from tens of nanometers to several micrometers, but is not limited to this. In at least some embodiments, this is 700 nm. The thickness of this first polymer layer 110 is tailored to the specific design of the ultrasound transducer and to withstand normal operating voltages. The first polymer layer 110 is patterned (geometrically) to form a uniform layer with several first polymer via holes 111. The bottom portion of the first polymer layer 110 between the bottom electrode 102 and the contact area 103 for the top electrode is flush with the bottom electrode 102 and the contact area 103 for the top electrode. The first polymer via holes 111 directly contact portions of the sacrificial etching channels 106 from the outside. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent, allowing the sacrificial membrane areas 107 to become cavities in the poly-CMUT cell. The sacrificial membrane areas 107 and the sacrificial etching channels 106 are indicated by dashed lines in FIG. 5A. The first polymer layer 110 covers the unconnected areas of the polished substrate 30 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[0082] In Figures 6A (top view) and 6B (cross-sectional view taken along line X-X' in Figure 6A), a second conductive material 115 is deposited over assembly 10, overlying portions of first polymer layer 110, and portions of contact area 103 for the top electrode. In some embodiments, second conductive material 115 can be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of conductive material. Second conductive material 115, in at least some embodiments, comprises a layer of titanium covered by a layer of gold. In some embodiments, this second conductive material 115 is deposited using a physical vapor deposition system, such as a sputtering system, for conformal coverage. A typical thickness of this second conductive material 115 is tens of nanometers (e.g., including up to 100 nm) in some embodiments. Second conductive material 115 is patterned (in a geometric shape) to form top electrode area 116 and top electrode interconnect 117. The second conductive material 115 is patterned in a manner that avoids any overlap with the first polymer via hole 111 and any electrical contact with the bottom electrode 102. Generally, the second conductive material 115 is patterned to avoid creating a short between the bottom and top electrodes of the poly-CMUT cell. The second conductive material 115 is patterned in a manner that maintains electrical contact with the contact area 103 for the top electrode. Thus, an electrical connection is made between the second conductive material 115 and only one of the vias 21, which is the right-hand via 21 in FIG. 6B. The top electrode interconnect 117 is used to make an electrical connection with an adjacent poly-CMUT cell (not shown) and to enable fabrication of the poly-CMUT device 201. There is at least one connection point between the top electrode interconnect 117 and the contact area 103 for the top electrode. The second conductive layer 115 becomes the bottom electrode in the poly-CMUT cell.

[0083] 7A (top view) and 7B (cross-sectional view taken along line X-X′ in FIG. 7A ), a second polymer layer 120 is deposited over the assembly 10, the covered portion of the first polymer layer 110, and the second conductive material 115. This second polymer layer 120, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be directly patterned using a UV exposure system, followed by wet etching, for example, using an SU-8 developer. This second polymer layer 120 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This second polymer layer 120, in some embodiments, can be deposited using lithographic coating techniques (e.g., spin coating). A typical thickness of this second polymer layer 120, in some embodiments, ranges from hundreds of nanometers to tens of micrometers (typically 5 μm). The thickness of this second polymer layer 120 is tailored to the specific design of the ultrasound transducer to withstand normal operating voltages. The second polymer layer 120 is patterned (geometrically) to form a second polymer membrane area 121 that avoids sealing or blocking the first polymer via hole 111. This second polymer layer 120 can also uniformly cover the entire assembly 10, except for the area where the first polymer via hole 111 is located (not shown in Figures 7A or 7B). One purpose of this second polymer layer 120 is to increase the overall membrane thickness of the poly-CMUT cell and enable operation at relatively high frequencies, e.g., 1 MHz to 10 MHz. The sacrificial membrane area 107 and the sacrificial etch channel 106 are indicated by dashed lines in Figure 7A.

[0084] In Figures 8A (top view) and 8B (cross-sectional view taken along line X-X' in Figure 8A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise (e.g., mechanically) removed. In some embodiments, the sacrificial material can be removed using a wet etch using a solvent or a dry etch using a gas. When using a wet etch, the assembly 10, in some embodiments, is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH). In this way, the sacrificial material 105 is dissolved without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved (etched), the assembly 10 is transferred into a container filled with isopropanol (IPA). The IPA then replaces the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO2) enters the chamber and replaces the IPA. The liquid CO2 is then converted to gaseous CO2 as the pressure in the chamber is gradually reduced to atmospheric pressure. When the assembly 10 is removed from the critical point dryer system, the areas where the sacrificial material 105 was located have been replaced with air areas 125. The air areas 125 allow for movement of the membrane of the poly-CMUT cell, but may not be suitable for operations involving water due to the presence of the first polymer via holes 111.

[0085] 9A (top view) and 9B (cross-sectional view taken along line X-X' in FIG. 9A ), encapsulation material 130 is uniformly coated over the entire assembly 10, covering polished substrate 30, first conductive material 101, first polymer layer 110, second conductive material 115, and portions of second polymer layer 120. In some embodiments, encapsulation material 130 may be Parylene C. In some embodiments, encapsulation material 130 may be deposited using a low-pressure chamber (e.g., vacuum). The encapsulation material 130 conformally coats the top surface 12 of assembly 10 and gradually builds up until it seals to the inner walls of sacrificial etching channels 106. The thickness of this encapsulation material 130 may be at least half the thickness of sacrificial material 105 to ensure adequate sealing of sacrificial etching channels 106. The bottom surface 13 of assembly 10 may be protected (e.g., using peelable tape) to prevent encapsulation material 130 from covering annular ring 22. The area where air area 125 was previously is now replaced with a vacuum area 131. Vacuum area 131 allows for movement of the membrane of the Poly-CMUT cell in applications involving liquids, such as biomedical ultrasound testing. Vacuum area 131 becomes a sealed cavity in the Poly-CMUT cell.

[0086] In another embodiment, as shown in FIGS. 10A (top view) and 10B (cross-sectional view taken along line X-X' in FIG. 10A ), assembly 10 is comprised of substrate 11 having exposed top surface 12, bottom surface 13, and via 21 fabricated in substrate 11. Bottom surface 13 may have additional layers (not shown), including a protective layer for conductive via 21 or for protection of substrate 10. Via 21 and annular ring 22 are exposed. Note that diameter D2 of annular ring 22 extends beyond diameter D1 of via 21. In this figure, via 21 is shown completely filled for illustrative purposes. The surface roughness of top surface 12 is determined by the manufacturing process for via 21 and the type of material used for substrate 11. The thickness TC of substrate conductive material 23 used for annular ring 22 is determined from manufacturing specifications. The thickness T1 of substrate 11 is determined from manufacturing specifications.

[0087] 11A (top view) and 11B (cross-sectional view taken along line X-X' in FIG. 11A ), a portion of top surface 12 of assembly 10 is removed by mechanical means (e.g., a grinder or polisher) or chemical means (e.g., a solvent that etches both substrate 11 and the conductive material used for vias 21 and annular ring 22). The thickness of material removed, at least in some embodiments, is equal to or greater than the thickness Tc of annular ring 22. The initial thickness T1 of substrate 11 is reduced to a thickness T2 after the material is removed. The result, at least in some embodiments, is an assembly 10 having a front surface with a polished substrate 30 and polished vias 31 with a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism.

[0088] 12A (top view) and 12B (cross-sectional view taken along line X-X′ in FIG. 12A ), a planarization layer 40 is deposited over the assembly 10, the polished substrate 30 covering the polished vias 31, and the polished vias 31. The planarization layer 40, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the planarization layer 40 can be directly patterned using a UV exposure system, followed by wet etching using, for example, an SU-8 developer. The planarization layer 40 can also be patterned using lithographic techniques, such as lifting off or etching a blanket layer of polymer. In some embodiments, the planarization layer 40 can be deposited using lithographic coating techniques (e.g., spin coating). Typical thicknesses of the planarization layer 40 range from tens of nanometers to several micrometers (typically 1 μm) in some embodiments. The thickness of the planarization layer 40 is selected based on the surface roughness of the polished substrate 30. The purpose of this planarization layer is to reduce the surface roughness to a few nanometers or less. Planarization layer 40 is patterned to form a uniform layer with several planarization layer via holes 41 exposed to subsequent layers. Planarization layer via holes 41 allow electrical conduction between vias 21 and subsequent conductive layers through which vias 21 extend.

[0089] In FIG. 13A (top view) and FIG. 13B (cross-sectional view taken along line X-X′ in FIG. 13A ), a first conductive material 101 is deposited over the planarization layer 40 and polished via 31. In some embodiments, the first conductive material 101 is patterned using lithography techniques, such as lift-off or etching of a blanket layer of conductive material. In some embodiments, the first conductive material 101 can be a layer of chromium, followed by a layer of gold, followed by a layer of chromium. In some embodiments, the first conductive material 101 can be deposited using a physical vapor deposition system, such as a sputtering system. A typical thickness of the first conductive material 101 is tens of nanometers (typically 100 nm) in some embodiments. The first conductive material 101 is patterned (in a geometric shape) to form contact areas 103 for the bottom electrode 102 and the top electrode. The bottom electrode 102 and the contact area 103 for the top electrode are made of the same first conductive material 101, but they are not electrically connected to each other, so there are areas where the planarization layer 40 is still exposed. The bottom electrode 102 provides the bottom electrode in the Poly-CMUT cell. The contact area 103 for the top electrode provides the electrical connection for the top electrode in the Poly-CMUT cell.

[0090] 14A (top view) and 14B (cross-sectional view taken along line X-X′ in FIG. 14A ), a sacrificial material 105 is deposited over the assembly 10, the overlying portion of the planarization layer 40, and the first conductive material 101. In some embodiments, the sacrificial material 105 can be patterned using lithographic techniques, such as lifting off or etching a blanket layer of sacrificial material. The sacrificial material 105 is, in some embodiments, a layer of LOR™ lift-off resist, followed in some embodiments by a layer of positive photoresist. The sacrificial material 105 is then patterned using, for example, wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, the sacrificial material 105 can be deposited using lithographic coating techniques (e.g., spin coating). Typical thicknesses of the sacrificial material 105 range from tens of nanometers to hundreds of nanometers in some embodiments (typically 200 nm), and even micrometers in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form sacrificial etch channels 106 that contact sacrificial membrane areas 107. These sacrificial membrane areas 107 will become the cavities in the poly-CMUT cell. Only the sacrificial membrane areas 107 are visible in the cross-section of Figure 14B.

[0091] In FIG. 15A (top view) and FIG. 15B (cross-sectional view taken along line X-X′ in FIG. 15A ), a first polymer layer 110 is deposited over the assembly 10, the covered portion of the planarization layer 40, the first conductive material 101, and the sacrificial material 105. This first polymer layer 110 can be a UV-sensitive material such as SU-8 photoresist, in some embodiments. In some embodiments, the first polymer layer 110 can be directly patterned using a UV exposure system, followed by wet etching using an SU-8 developer, including but not limited to. This first polymer layer 110 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. In some embodiments, this first polymer layer 110 can be deposited using lithographic coating techniques (e.g., spin coating). A typical thickness of this first polymer layer 110 ranges from tens of nanometers to several micrometers (typically 700 nm), in some embodiments. The thickness of this first polymer layer 110 is tailored to the specific design of the ultrasound transducer and to withstand the normal operating voltage. The first polymer layer 110 is patterned (geometrically) to form a uniform layer with several first polymer via holes 111. The first polymer via holes 111 provide direct external contact to certain portions of the sacrificial etching channels 106. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent, allowing the sacrificial membrane areas 107 to become cavities in the poly-CMUT cell. The sacrificial membrane areas 107 and the sacrificial etching channels 106 are shown by dashed lines in FIG. 15A. The first polymer layer 110 covers the unconnected areas of the planarization layer 40 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.

[0092] In FIG. 16A (top view) and FIG. 16B (cross-sectional view taken along line X-X′ in FIG. 16A ), a second conductive material 115 is deposited over the assembly 10, the covered portions of the first polymer layer 110, and some portions of the contact area 103 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques, such as lift-off or etching of a blanket layer of conductive material. In some embodiments, the second conductive material 115 can be a layer of titanium followed by a layer of gold. In some embodiments, the second conductive material 115 can be deposited using a physical vapor deposition system (e.g., a sputtering system) for conformal coverage. In some embodiments, the thickness of the second conductive material 115 is tens of nanometers (typically 100 nm). The second conductive material 115 is patterned (geometrically) to form the top electrode area 116 and the top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via hole 111. The second conductive material 115 is also patterned in a manner to avoid any electrical contact with the bottom electrode 102 so as not to create a short between the bottom and top electrodes of the poly-CMUT cell. The second conductive material 115 is also patterned in a manner to maintain electrical contact with the contact area 103 for the top electrode. Thus, an electrical connection is made between the second conductive material 115 and only one of the vias 21, which is the right-hand via 21 in FIG. 20 . The top electrode interconnect 117 is used to make an electrical connection with an adjacent poly-CMUT cell (not shown) and to enable fabrication of the poly-CMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the contact area 103 for the top electrode. The second conductive layer 115 becomes the bottom electrode in the poly-CMUT cell.

[0093] In FIG. 17A (top view) and FIG. 17B (cross-sectional view taken along line X-X′ in FIG. 17A ), a second polymer layer 120 is deposited over the assembly 10, the covered portion of the first polymer layer 110, and the second conductive material 115. This second polymer layer 120 can be a UV-sensitive material such as SU-8 photoresist, in some embodiments. In some embodiments, the second polymer layer 120 can be directly patterned using a UV exposure system, followed by wet etching using an SU-8 developer, including but not limited to. This second polymer layer 120 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This second polymer layer 120 can be deposited, in some embodiments, using lithographic coating techniques (e.g., spin coating). Typical thicknesses of this second polymer layer 120 range from hundreds of nanometers to tens of micrometers (typically 5 μm), in some embodiments. The thickness of this second polymer layer 120 is tailored to the specific design of the ultrasonic transducer to withstand normal operating voltages. The second polymer layer 120 is patterned (in a geometric shape) to form a second polymer membrane area 121 that avoids sealing or blocking the first polymer via hole 111. This second polymer layer 120 can also uniformly cover the entire assembly 10 except for the area where the first polymer via hole 111 is located (not shown in Figures 17A or 17B). One purpose of this second polymer layer 120 is to increase the overall membrane thickness of the poly-CMUT cell to increase its maximum operating frequency. The sacrificial membrane area 107 and the sacrificial etch channel 106 appear as dashed lines in Figure 17A.

[0094] 18A (top view) and 18B (cross-sectional view taken along line X-X′ in FIG. 18A ), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane areas 107) is etched, dissolved, or removed. In some embodiments, the sacrificial material 105 can be removed by wet etching using a solvent or dry etching using a gas. If wet etching is used, the assembly 10, in some embodiments, is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH), which dissolves the sacrificial material 105 without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 has dissolved, the assembly 10 is transferred into a container filled with isopropanol (IPA). The IPA is replaced with the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO2) enters the chamber and replaces the IPA. The liquid CO2 is then converted to gaseous CO2 as the pressure in the chamber is gradually reduced to atmospheric pressure. When the assembly is removed from the critical point dryer system, the areas where the sacrificial material 105 was located have been replaced with air areas 125. The air areas 125 allow for movement of the membrane of the poly-CMUT cell, but may not be suitable for operations involving water due to the presence of the first polymer via holes 111.

[0095] 19A (top view) and 19B (cross-sectional view taken along line X-X′ in FIG. 19A ), encapsulant material 130 is uniformly coated over the entire assembly 10, thereby covering planarization layer 40, first conductive material 101, first polymer layer 110, second conductive material 115, and portions of second polymer layer 120. In some embodiments, encapsulant material 130 may be Parylene C and, in some embodiments, may be deposited using a low-pressure chamber (considered a vacuum). The encapsulant material 130 conformally coats the top surface 12 of assembly 10 and gradually builds up against the inner walls of the sacrificial etching channels 106 until they are blocked. The thickness of this encapsulant material 130, in at least some embodiments, is half the thickness of the sacrificial material 105 to help ensure proper sealing of the sacrificial etching channels 106. The bottom surface 13 of the assembly 10 can be protected (e.g., using peelable tape) to prevent the encapsulating material 130 from covering the annular ring 22. The area where the air area 125 was is again replaced with a vacuum area 131. The vacuum area 131 allows for membrane movement in the Poly-CMUT cell in applications involving liquids, such as biomedical ultrasound testing. The vacuum area 131 becomes the sealed cavity in the Poly-CMUT cell.

[0096] In a third embodiment, as shown in FIG. 20A (top view) and FIG. 20B (cross-sectional view taken along line X-X′ in FIG. 20A ), assembly 10 comprises substrate 11 having exposed top surface 12, bottom surface 13, and via 21 fabricated in substrate 11. Bottom surface 13 has additional layers, including a protective layer for conductive via 21 or for protection of substrate 11 in some embodiments (not shown). Via 21 and annular ring 22 are exposed. Diameter D2 of annular ring 22 extends beyond diameter D1 of via 21. In this figure, via 21 is shown completely filled for illustrative purposes. The surface roughness of top surface 12 is determined by the manufacturing process for via 21 and the type of material used for substrate 11. Thickness TC of substrate conductive material 23 used for annular ring 22 is determined from manufacturing specifications. Thickness T1 of substrate 11 is determined from manufacturing specifications. In assembly 10, substrate conductive material 23 is patterned to provide substrate conductive areas 24 for the bottom electrode and substrate conductive areas 25 for the top electrode. In some embodiments, substrate conductive material 23 is patterned during fabrication of assembly 10 using lithographic techniques, such as masking and etching, such as those used in PCB fabrication facilities. Vias 21 provide direct electrical connections between substrate conductive areas 24 for the bottom electrode on top surface 12 and annular ring 22 on bottom surface 13. Vias 21 also provide direct electrical connections between substrate conductive areas 25 for the top electrode on top surface 12 and annular ring 22 on bottom surface 13. Although substrate conductive areas 24 for the bottom electrode and substrate conductive areas 25 for the top electrode are fabricated from the same substrate conductive material 23, they are not electrically connected to each other.

[0097] 21A (top view) and 21B (cross-sectional view taken along line X-X′ in FIG. 21A ), a planarization layer 40 is deposited over assembly 10, the covered portion of substrate 11, some portions of substrate conductive area 24 for the bottom electrode, and portions of substrate conductive area 25 for the top electrode. In some embodiments, planarization layer 40 may be an epoxy resin such as Epotek-302™ or Epotek-302-3M™. In some embodiments, planarization layer 40 may be deposited using a lithographic coating technique, such as a spin coater. The thickness of planarization layer 40, in at least some embodiments, is equal to or greater than the thickness TC of substrate conductive material 23. Planarization layer 40 conformally covers all surfaces of substrate conductive material 23 that are not in contact with substrate 11. An optional degassing stage can be used to remove any air bubbles that may be trapped during deposition of planarization layer 40. The purpose of this planarization layer 40 is to fill in the exposed areas on the top surface 12 of the substrate 11 that are not already covered by the substrate conductive material 23 .

[0098] 22A (top view) and 22B (cross-sectional view along line X-X′ in FIG. 22A ), a portion of the top surface 12 of the assembly 10 is removed by mechanical means (e.g., a grinder or polisher) or chemical means (e.g., a solvent that etches both the planarization layer 40 and the substrate conductive material 23). After material removal, the thickness TCP of the polished substrate conductive material 33 is smaller than the original thickness TC of the substrate conductive material 23. The result is an assembly 10 having a polished substrate conductive material 33 and a polished planarization layer 50 with a surface roughness of a few nanometers or even much less. The surface roughness depends on the removal mechanism. After this polishing step, the thicknesses of the polished substrate conductive material 33 and the polished planarization layer 50 have the same thickness TCP. Maintaining a flat and level surface is important for subsequent fabrication steps to create poly-CMUT cells, and ultimately, poly-CMUT elements 201 and poly-CMUT arrays 204. The portion of the polished planarization layer 50 between the polished conductive area that serves as the bottom electrode 34 and the polished conductive area 35 for the top electrode is flush with the bottom electrode 34 and the conductive area 35.

[0099] In FIG. 23A (top view) and FIG. 23B (cross-sectional view taken along line X-X′ in FIG. 23A ), sacrificial material 105 is deposited over assembly 10, the polished overlying portion of planarization layer 50, and the polished substrate conductive material 33. In some embodiments, sacrificial material 105 can be patterned using lithographic techniques, such as lifting off or etching a blanket layer of sacrificial material. In some embodiments, sacrificial material 105 is overlaid with a layer of LOR™ lift-off resist, followed in some embodiments by a layer of positive photoresist, which is then patterned by wet etching using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, sacrificial material 105 can be deposited using lithographic coating techniques, such as a spin coater. Typical thicknesses of sacrificial material 105 range from tens of nanometers to hundreds of nanometers in some embodiments (typically 200 nm), and even micrometers in some applications. The sacrificial material 105 is patterned into a geometric shape to form sacrificial etch channels 106 that contact sacrificial membrane areas 107. These sacrificial membrane areas 107 will become the cavities in the poly-CMUT cell. Only the sacrificial membrane areas 107 are visible in the cross-sectional view of Figure 23B.

[0100] 24A (top view) and 24B (cross-sectional view taken along line X-X' in FIG. 24), a first polymer layer 110 is deposited over the assembly 10, the polished overlying portion of the planarization layer 50, the polished substrate conductive material 33, and the sacrificial material 105. This first polymer layer 110, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the first polymer layer 110 can be directly patterned using a UV exposure system, followed by wet etching with an SU-8 developer in some embodiments. This first polymer layer 110 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This first polymer layer 110, in some embodiments, can be deposited using lithographic coating techniques (e.g., spin coating). A typical thickness of this first polymer layer 110, in some embodiments, ranges from tens of nanometers to several micrometers (typically 700 nm). The thickness of this first polymer layer 110 is tailored to the specific design of the ultrasound transducer and to withstand typical operating voltages ranging from 10V to 100V. The first polymer layer 110 is patterned (geometrically) to form a uniform layer with several first polymer via holes 111. The first polymer via holes 111 provide direct external connections to portions of the sacrificial etch channels 106. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent, allowing the sacrificial membrane areas 107 to become cavities in the poly-CMUT cell. The sacrificial membrane areas 107 and the sacrificial etch channels 106 are shown in dashed lines in Figure 24A. The first polymer layer 110 covers the unconnected areas of the polished planarization layer 50, preventing short circuits between the polished conductive area serving as the bottom electrode 34 and the polished conductive area 35 for the top electrode.

[0101] In FIG. 25A (top view) and FIG. 25B (cross-sectional view taken along line X-X′ in FIG. 25A ), a second conductive material 115 is deposited over the assembly 10, the covered portions of the first polymer layer 110, and portions of the polished conductive area 35 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques, such as lift-off or etching of a blanket layer of conductive material. In some embodiments, the second conductive material 115 can be a layer of titanium followed by a layer of gold. In some embodiments, the second conductive material 115 can be deposited using a physical vapor deposition system (e.g., a sputtering system) for conformal coverage. A typical thickness of the second conductive material 115 is tens of nanometers (typically 100 nm) in some embodiments. The second conductive material 115 is patterned (in a geometric shape) to form the top electrode area 116 and the top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via hole 111. The second conductive material 115 is patterned in a manner to avoid any electrical contact with the polished conductive area that serves as the bottom electrode 34 to avoid a short circuit between the bottom and top electrodes of the poly-CMUT cell. The second conductive material 115 is patterned in a manner to maintain electrical contact with the polished conductive area 35 for the top electrode. Thus, an electrical connection is made between the second conductive material 115 and only one of the vias 21, which is the right-hand via 21 in FIG. 25B . The top electrode interconnect 117 is used to make an electrical connection with an adjacent poly-CMUT cell (not shown) and to enable fabrication of the poly-CMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode. The second conductive layer 115 serves as the top electrode in the poly-CMUT cell.

[0102] 26A (top view) and 26B (cross-sectional view taken along line X-X′ in FIG. 26A ), a second polymer layer 120 is deposited over the assembly 10, the covered portion of the first polymer layer 110, and the second conductive material 115. This second polymer layer 120, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be directly patterned using a UV exposure system, followed by wet etching, for example, using an SU-8 developer. This second polymer layer 120 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This second polymer layer 120, in some embodiments, can be deposited using lithographic coating techniques (e.g., spin coating). A typical thickness of this second polymer layer 120, in some embodiments, ranges from hundreds of nanometers to tens of micrometers (typically 5 μm). The thickness of this second polymer layer 120 is tailored to the specific design of the ultrasound transducer and to withstand normal operating voltages. The second polymer layer 120 is patterned (geometrically) to form a second polymer membrane area 121 that avoids sealing or blocking the first polymer via hole 111. This second polymer layer 120 can also uniformly cover the entire assembly 10, except for the area where the first polymer via hole 111 is located (not shown in Figures 26A or 26B). The purpose of this second polymer layer 120 is to increase the overall membrane thickness of the poly-CMUT cell, enabling operation at frequencies between 1 MHz and 10 MHz. The sacrificial membrane area 107 and the sacrificial etch channel 106 are shown in Figure 26A by dashed lines.

[0103] In Figure 27A (top view) and Figure 27B (cross-sectional view taken along line X-X' in Figure 27A), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise (e.g., mechanically) removed. In some embodiments, the sacrificial material 105 can be removed by wet etching using a solvent or dry etching using a gas. When using wet etching, the assembly 10, in some embodiments, is immersed in an aqueous solution containing tetramethylammonium hydroxide (TMAH), which dissolves the sacrificial material 105 without damaging or dissolving the remaining materials (i.e., the first polymer layer 110, the second conductive material 115, and the second polymer layer 120). Once the sacrificial material 105 is dissolved, the assembly is transferred into a container filled with isopropanol (IPA). The IPA is replaced with the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressure and replaces the IPA. This liquid CO2 is then converted to gaseous CO2 as the pressure in the chamber is gradually reduced to atmospheric pressure. When the assembly 10 is removed from the critical point dryer system, the area where the sacrificial material 105 was located is now replaced by an air area 125. The air area 125 allows for movement of the membrane of the poly-CMUT cell, but is not suitable for operation with water due to the presence of the first polymer via hole 111.

[0104] In FIG. 28A (top view) and FIG. 28B (cross-sectional view taken along line X-X′ in FIG. 28A ), encapsulant material 130 is uniformly coated over the entire assembly 10, thereby covering polished planarization layer 50, polished substrate conductive material 33, first polymer layer 110, second conductive material 115, and portions of second polymer layer 120. The encapsulant material 130, in some embodiments, can be Parylene C. In several embodiments, the encapsulant material 130 can be deposited using a low-pressure chamber (e.g., vacuum). The encapsulant material 130 conformally coats the top surface 12 of the assembly 10 and gradually builds up until it seals to the inner walls of the sacrificial etching channels 106. The thickness of this encapsulant material 130, in at least some embodiments, is at least half the thickness of the sacrificial material 105 to obtain adequate sealing of the sacrificial etching channels 106. The bottom surface 13 of the assembly 10 can be protected (e.g., using peelable tape) to prevent the encapsulating material 130 from covering the annular ring 22. The area where the air area 125 was is replaced with a vacuum area 131. The vacuum area 131 allows for membrane movement in the Poly-CMUT cell in applications involving liquids, such as biomedical ultrasound testing. The vacuum area 131 becomes the sealed cavity in the Poly-CMUT cell.

[0105] In a fourth embodiment, as shown in FIG. 29A (top view) and FIG. 29B (cross-sectional view taken along line X-X′ in FIG. 29A ), assembly 10 comprises substrate 11 bonded and correspondingly adhered to upper substrate layer 14. This upper substrate layer 14 is made of the same material as substrate 11. The material of substrate 11 and upper substrate layer 14 typically includes, in some embodiments, a glass-reinforced epoxy laminate material (commonly known as “FR4”) or a hydrocarbon ceramic laminate (commonly known as “Rogers material”). Substrate 11 and upper substrate layer 14 are typically bonded in a vacuum at high temperature to prevent any air bubbles or voids from forming between them. Assembly 10 may also have an additional lower substrate layer 15 (not shown in FIG. 29A or FIG. 29B ) bonded onto bottom surface 13 of substrate 10. This optional lower substrate layer 15 has the same physical properties as upper substrate layer 14. The optional lower substrate layer 15 may have vias 21 to maintain electrical connection with the substrate conductive material 23. The bottom surface 13 of the substrate 11 may have additional layers (not shown), which may include protective layers for the conductive vias 21 or for protecting the substrate 11. The vias 21 and the annular ring 22 are exposed. The diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21. The via 21 is shown completely filled for illustrative purposes. The thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from manufacturing specifications. The thickness T1 of the substrate 11 and the thickness T3 of the upper substrate layer 14 are determined from manufacturing specifications, with T3 typically being greater than T1. In the assembly 10, the substrate conductive material 23 between the substrate 11 and the upper substrate layer 14 is patterned to provide a substrate conductive area 24 for the bottom electrode and a substrate conductive area 25 for the top electrode (shown by dashed lines in FIG. 29A ). In some embodiments, substrate conductive material 23 is patterned during manufacture of assembly 10 using lithographic techniques such as masking and etching, such as those used in PCB manufacturing facilities. Via 21 provides a direct electrical connection between substrate conductive area 24 for the bottom electrode on top surface 12 and annular ring 22 on bottom surface 13.Via 21 provides a direct electrical connection between substrate conductive area 25 for the top electrode and annular ring 22 on bottom surface 13. Substrate conductive area 24 for the bottom electrode and substrate conductive area 25 for the top electrode are made of the same substrate conductive material 23, but they are not electrically connected to each other.

[0106] 30A (top view) and 30B (cross-sectional view along line X-X′ in FIG. 30A ), a portion of assembly 10 is removed by mechanical means (e.g., a grinder or polisher) or chemical means (e.g., a solvent that etches both upper substrate layer 14 and substrate conductive material 23). After material removal, the thickness TCP of polished substrate conductive material 33 is less than the original thickness TC of substrate conductive material 23. The result is an assembly 10 having a polished substrate conductive material 33 and a polished upper substrate layer 36 with a surface roughness of a few nanometers or less. The surface roughness depends on the removal mechanism. After this polishing step, the thicknesses of polished substrate conductive material 33 and polished upper substrate layer 36 have the same thickness TCP. Fabrication according to this depicted embodiment can be performed without the deposition of planarization layer 40 discussed above with respect to FIG. 21A . Maintaining a flat and level surface is important for subsequent fabrication steps to create poly-CMUT cells, and ultimately poly-CMUT elements 201 and poly-CMUT arrays 204. The portion of the PCB itself (i.e., the polished upper substrate layer 36) between the polished conductive area that serves as the bottom electrode 34 and the polished conductive area 35 for the top electrode is flush with the bottom electrode 34 and the conductive area 35.

[0107] In FIG. 31A (top view) and FIG. 31B (cross-sectional view taken along line X-X′ in FIG. 31A ), sacrificial material 105 is deposited over assembly 10, the polished overlying portion of upper substrate layer 36, and the polished substrate conductive material 33. In some embodiments, sacrificial material 105 can be patterned using lithographic techniques, such as lifting off or etching a blanket layer of sacrificial material. Sacrificial material 105 is, in some embodiments, overlaid with a layer of LOR™ lift-off resist, followed in some embodiments by a layer of positive photoresist, which is then patterned by wet etching, for example, using an aqueous solution containing tetramethylammonium hydroxide (TMAH). In some embodiments, sacrificial material 105 can be deposited using lithographic coating techniques (e.g., spin coating). Typical thicknesses of sacrificial material 105 range from tens of nanometers to hundreds of nanometers in some embodiments (typically 200 nm), and even micrometers in some applications. The sacrificial material 105 is patterned (in a geometric shape) to form sacrificial etch channels 106 that contact sacrificial membrane areas 107. These sacrificial membrane areas 107 will become the cavities in the poly-CMUT cell. Only the sacrificial membrane areas 107 are visible in Figure 31B.

[0108] 32A (top view) and 32B (cross-sectional view taken along line X-X′ in FIG. 24 ), a first polymer layer 110 is deposited over the assembly 10, the polished overlying portion of the upper substrate layer 36, the polished substrate conductive material 33, and the sacrificial material 105. This first polymer layer 110, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the first polymer layer 110 can be directly patterned using a UV exposure system, followed by wet etching, for example, using an SU-8 developer. This first polymer layer 110 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This first polymer layer 110, in some embodiments, can be deposited using lithographic coating techniques (e.g., spin coater). A typical thickness of this first polymer layer 110, in some embodiments, ranges from tens of nanometers to several micrometers (typically 700 nm). The thickness of this first polymer layer 110 is tailored to the specific design of the ultrasound transducer and to withstand a typical operating voltage of 10V to 100V. The first polymer layer 110 is patterned (geometrically) to form a uniform layer with several first polymer via holes 111. The first polymer via holes 111 provide direct external connection to some portions of the sacrificial etch channels 106. The first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent, allowing the sacrificial membrane areas 107 to become cavities in the poly-CMUT cell. The sacrificial membrane areas 107 and the sacrificial etch channels 106 are shown by dashed lines in Figure 32A. The first polymer layer 110 covers the electrically unconnected areas of the polished upper substrate layer 36, preventing short circuits between the polished conductive area serving as the bottom electrode 34 and the polished conductive area 35 for the top electrode.

[0109] Referring now to FIG. 33A (top view) and FIG. 33B (cross-sectional view taken along line X-X′ in FIG. 33A ), a second conductive material 115 is deposited over the assembly 10, the covered portions of the first polymer layer 110, and portions of the polished conductive area 35 for the top electrode. In some embodiments, the second conductive material 115 can be patterned using lithography techniques, such as lift-off or etching of a blanket layer of conductive material. In some embodiments, the second conductive material 115 can be a layer of titanium followed by a layer of gold. In some embodiments, the second conductive material 115 can be deposited using a physical vapor deposition system (e.g., a sputtering system) for conformal coverage. A typical thickness of the second conductive material 115 is tens of nanometers (typically 100 nm) in some embodiments. The second conductive material 115 is patterned (in a geometric shape) to form the top electrode area 116 and the top electrode interconnect 117. The second conductive material 115 is patterned in a manner to avoid any overlap with the first polymer via hole 111. The second conductive material 115 is patterned in a manner to avoid any electrical contact with the polished conductive area that functions as the bottom electrode 34, which would otherwise result in a short circuit between the bottom and top electrodes of the poly-CMUT cell. The second conductive material 115 is patterned in a manner to maintain electrical contact with the polished conductive area 35 for the top electrode. Thus, an electrical connection is made between the second conductive material 115 and only one of the vias 21, which is the right-hand via 21 in FIG. 25B. The top electrode interconnect 117 is used to make an electrical connection with an adjacent poly-CMUT cell (not shown) and to enable fabrication of the poly-CMUT element 201. There is at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode. The second conductive layer 115 serves as the top electrode in the poly-CMUT cell.

[0110] 34A (top view) and 34B (cross-sectional view taken along line X-X′ in FIG. 34A ), a second polymer layer 120 is deposited over the assembly 10, the covered portion of the first polymer layer 110, and the second conductive material 115. This second polymer layer 120, in some embodiments, can be a UV-sensitive material such as SU-8 photoresist. In some embodiments, the second polymer layer 120 can be directly patterned using a UV exposure system, followed by wet etching, for example, using an SU-8 developer. This second polymer layer 120 can also be patterned using lithographic techniques, such as lift-off or etching of a blanket layer of polymer. This second polymer layer 120, in some embodiments, can be deposited using lithographic coating techniques (e.g., spin coating). A typical thickness of this second polymer layer 120, in some embodiments, ranges from hundreds of nanometers to tens of micrometers (typically 5 μm). The thickness of this second polymer layer 120 is tailored to the specific design of the ultrasound transducer to withstand a typical operating voltage of 10V to 100V. The second polymer layer 120 is patterned (geometrically) to form a second polymer membrane area 121 that avoids sealing or blocking the first polymer via hole 111. This second polymer layer 120 can also uniformly cover the entire assembly 10, except for the area where the first polymer via hole 111 is located (not shown in Figures 34A or 34B). The purpose of this second polymer layer 120 is to increase the overall membrane thickness of the poly-CMUT cell and enable the desired frequency of 1 MHz to 10 MHz to be reached. The sacrificial membrane area 107 and the sacrificial etch channel 106 are shown in Figure 34A by dashed lines.

[0111] 35A (top view) and 35B (cross-sectional view taken along line X-X′ in FIG. 35A ), the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane areas 107) is etched, dissolved, or otherwise (e.g., mechanically) removed. In some embodiments, the sacrificial material can be removed by wet etching using a solvent or dry etching using a gas. When using wet etching, the assembly 10 is immersed in an aqueous solution containing, in some embodiments, tetramethylammonium hydroxide (TMAH), which dissolves the sacrificial material 105 without damaging or dissolving the remaining materials (i.e., first polymer layer 110, second conductive material 115, and second polymer layer 120). Once the sacrificial material 105 is dissolved, the assembly is transferred into a container filled with isopropanol (IPA). The IPA is replaced with the aqueous solution containing TMAH. Finally, the assembly 10 is transferred into the chamber of a critical point dryer system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressure and replaces the IPA. The liquid CO2 is then converted to gaseous CO2 as the pressure in the chamber is gradually reduced to atmospheric pressure. When the assembly 10 is removed from the critical point dryer system, the area where the sacrificial material 105 was located is replaced with an air area 125. The air area 125 allows for movement of the membrane of the poly-CMUT cell, but may not be suitable for operations involving water due to the presence of the first polymer via hole 111.

[0112] 36A (top view) and 36B (cross-sectional view taken along line X-X′ in FIG. 36A ), encapsulation material 130 is uniformly coated over the entire assembly 10, covering polished upper substrate layer 36, polished substrate conductive material 33, first polymer layer 110, second conductive material 115, and portions of second polymer layer 120. The encapsulation material 130, in some embodiments, can be Parylene C. In some embodiments, the encapsulation material 130 can be deposited using a low-pressure chamber that can operate as a vacuum. The encapsulation material 130 conformally coats the top surface of the assembly 10 and gradually builds up on the inner walls of the sacrificial etching channels 106 until they are blocked and sealed. The thickness of this encapsulation material 130, in at least some embodiments, is at least half the thickness of the sacrificial material 105 to obtain adequate sealing of the sacrificial etching channels 106. The bottom surface 13 of the assembly 10 can be protected (e.g., using peelable tape) to prevent the encapsulating material 130 from covering the annular ring 22. The area where the air area 125 was is replaced with a vacuum area 131. The vacuum area 131 allows for membrane movement in the Poly-CMUT cell in applications involving liquids, such as biomedical ultrasound testing. The vacuum area 131 becomes the sealed cavity in the Poly-CMUT cell.

[0113] The solvent used for wet etching in the first through fourth embodiments depicted in Figures 1A-37B is selected to be chemically compatible with the substrate 11 and other materials deposited thereon, such as the various polymer layers 110, 120 and the conductive material 115 used for the electrodes. That is, the solvent is selected to etch away the sacrificial material 105 without dissolving or damaging the substrate 11 and these other materials. An example of a suitable solvent for wet etching is an SU-8 developer based on 1-methoxy-2-propanol acetate and tetramethylammonium hydroxide (TMAH). Other suitable solvents include 1-methoxy-2-propanol acetate, acetone, and isopropanol (IPA), either alone or as part of a composition other than an SU-8 developer.

[0114] 37A (top view) and 37B (cross-sectional view taken along line X-X′ in FIG. 37A ), encapsulation material 130 is uniformly coated over the entire assembly 10, covering the polished upper substrate layer 36, the polished substrate conductive material 33, the silicon-based material 110, and portions of the second conductive material 115. The encapsulation material 130 may, in some embodiments, be silicon nitride, silicon dioxide, or polysilicon. In some embodiments, the encapsulation material 130 may be deposited using a low-pressure chamber that can operate as a vacuum. The encapsulation material 130 conformally coats the top surface of the assembly 10, penetrates the via holes 141 in the silicon-based material, and gradually accumulates on the inner walls of the sacrificial etch channels 106 until they are blocked and sealed. The thickness of this encapsulation material 130 is, in at least some embodiments, at least half the thickness of the sacrificial material 105 to enable adequate sealing of the sacrificial etch channels 106. The bottom surface 13 of the assembly 10 can be protected (e.g., using a masking layer) to prevent the encapsulation material 130 from covering the annular ring 22. The area where the air area 125 was is replaced with a vacuum area 131. The vacuum area 131 allows for membrane movement in silicon-based CMUT cells for applications involving liquids, such as biomedical ultrasound testing. The vacuum area 131 becomes a sealed cavity in the silicon-based CMUT cell. The material of the substrate 11 can withstand the processing conditions used to deposit the silicon, polysilicon, silicon dioxide, and silicon nitride layers, which occur at temperatures above 400°C. The substrate 11 can also be the product of processes such as LTCC or HTCC.

[0115] Although the fabrication of the silicon-based CMUT is explicitly described in connection with FIGS. 37A and 37B, as long as the substrate 11 used is fabricated of a material capable of withstanding the temperatures required for the fabrication of the silicon-based CMUT (i.e., above 400° C.) and a solvent compatible with the selected substrate 11 and the materials deposited thereon is used, the fabrication processes of the first to fourth embodiments described in connection with FIGS. 1A to 36B can also be used for the fabrication of the silicon-based CMUT. Poly CMUT can be fabricated similarly on a ceramic substrate.

[0116] Operation FIGS. 38A and 38B depict respectively the front 211 and back side 212 of a wafer substrate 210 fabricated in a PCB manufacturing facility. The front 211 of the wafer substrate has hundreds of exposed vias 21 and annular rings 22, which are too small to be individually identified in FIG. 38A. The positions of these vias 21 and annular rings 22 coincide with the positions of the poly CMUT array 204 fabricated on this front 211 of the wafer substrate. The back side 212 of the wafer substrate has hundreds of contact pads each electrically connected to a via 21 on the front 211 of the wafer substrate. These electrical contact pads enable soldering of an electrical contact assembly 230, such as a header or receptacle used in the PCB industry (not shown in FIGS. 38A or 38B), to enable interaction with external electronic devices such as an ultrasonic pulser and amplifier.

[0117] 39A and 39B, a top isometric view and a top plan view, respectively, are shown of a 3D visualization of a poly-CMUT array 204 in the form of a poly-CMUT linear array 202 fabricated on a substrate 11. The poly-CMUT linear array 202 is one of multiple arrays 202 fabricated from the wafer substrate 210 of FIGS. 38A and 38B. The poly-CMUT linear array 202 is comprised of 128 poly-CMUT elements 201 stacked on top of each other along the length of the array 202, with each poly-CMUT element comprising approximately 300 poly-CMUT cells (not individually shown). Each poly-CMUT element is electrically connected to an individual via 21 (not individually shown) on the substrate 11 that extends to the bottom surface 13 of the substrate 11. An electrical contact assembly 230 is mounted on the bottom surface 13 of the substrate 11 and is electrically connected to the vias 21. Each of the 128 poly-CMUT elements is electrically coupled to one of the 128 vias 21. The poly-CMUT linear array 202 is fabricated on a polished substrate 30 according to the first embodiment described above and depicted in accordance with FIGS. 1A-9B.

[0118] 40A and 40B, there are shown isometric and bottom views, respectively, of a 3D visualization of the bottom surface 13 of the Poly-CMUT linear array 202 of FIGS. 39A and 39B. The Poly-CMUT linear array 202 on the top surface of the substrate 11 is not shown. The electrical contact assembly 230 has several dozen individual electrical contact assembly connections 231. Each of these electrical contact assembly connections 231 connects to a via 21 and is accordingly also electrically connected to the second conductive material 115 of their corresponding Poly-CMUT element 201 (not shown).

[0119] Referring now to Figure 41, a cross-sectional view of the poly-CMUT linear array 202 of Figures 39A and 39B is shown. Poly-CMUT elements 201 are fabricated on a polished substrate 30 on the top surface 12, through which vias 21 extend to annular rings 22 disposed on the bottom surface 13. Electrical contact assemblies 230, including electrical contact assembly connections 231, are bonded to substrate conductive contact areas 26. Each electrical contact assembly connection 231 is connected to each via 21 through a substrate conductive contact area 26 that is patterned on the bottom surface 13 of the substrate 11. This substrate conductive contact area 26 is typically patterned by the manufacturing facility (e.g., a PCB fab).

[0120] 42A and 42B, top and bottom isometric views of a poly-CMUT array 204 are shown, respectively. A poly-CMUT matrix array 203 comprising hundreds of poly-CMUT elements 201 organized into dozens of rows and columns is fabricated on a polished substrate 30. On the bottom surface 13, hundreds of electrically isolated substrate conductive contact areas 26 are present. Each of these substrate conductive contact areas 26 is directly accessible from the bottom surface 13 to an individual poly-CMUT element 201 on the top surface 12 through vias 21 (not shown) extending through the polished substrate 30. The polished substrate 30 may include one or more layers of substrate conductive material 23 that enable proper routing and distribution of the substrate conductive contact areas 26. For example, a printed circuit board may have two, four, six, or more layers interconnected by internal vias.

[0121] 43A and 43B, which show a top view and a detailed view of area A of the poly-CMUT array 204 of FIGS. 42A and 42B, respectively. A poly-CMUT matrix array 203 comprising several hundred poly-CMUT elements 201 arranged in dozens of rows and columns along the X and Y axes is fabricated on a polished substrate 30. The poly-CMUT matrix array 203, in some embodiments, has separate connections for the top and bottom electrodes of the poly-CMUT cells (not shown). The poly-CMUT matrix array 203, in some embodiments, has separate connections for the top electrodes and a common electrical connection (not shown) for the bottom electrodes.

[0122] 44A and 44B, there is shown a bottom view and a detailed view of area A, respectively, of the top view of the poly-CMUT array 204 of FIGS. 42A and 42B. There is an array of electrically isolated substrate conductive contact areas 26, each providing direct electrical access to an individual poly-CMUT element 201 on the top surface 12 through vias 21 (not shown) extending through the polished substrate 30. The polished substrate 30 may include one or more layers of substrate conductive material 23 that allow for proper routing and distribution of the substrate conductive contact areas 26. For example, a printed circuit board may have two, four, six, or more layers interconnected by internal vias.

[0123] 45A and 45B, a bottom view and a detailed view of area A of the poly-CMUT array 204 are shown, respectively. An electrical contact assembly 230 (shown as a dashed rectangle) is mounted on the bottom surface 13 of the poly-CMUT array 204. The detailed view shows the substrate conductive contact area 26 with divided sections, which then form substrate conductive contact tracks 27 that connect to the annular ring 22. Electronic components 241 (e.g., surface-mount devices such as inductors) can be soldered or glued between the substrate conductive contact tracks 27 to act as an electrical impedance matching circuit to cancel the capacitive reactance typical of CMUTs and poly-CMUTs. The substrate conductive contact area 26 can be divided into two or more substrate conductive contact tracks 27 (not shown) to accommodate the mounting of two or more electronic components 241. For example, an array comprising resistors and capacitors can be mounted to the corresponding substrate conductive contact tracks 27 to create a “bias-tee” circuit for applying DC and AC voltages.

[0124] Referring now to Figures 46A, 46B, 46C, and 46D, there are shown a top view, a cross-sectional view taken along line A-A' in Figure 46A, a back view, and a detailed view of area B in Figure 46B of the poly-CMUT array 204 of Figure 45A, respectively. A poly-CMUT linear array 202 composed of poly-CMUT elements 201 is constructed on a polished substrate 30. The substrate 11 is composed of two or more lower substrate layers 16 in a stacked configuration. Internal vias 21 and internal substrate conductive material 23 exist between the lower substrate layers 16 but are not depicted in Figures 46A-46D. The substrate 11 contains buried regions 250 that may contain multiple embedded electronic components 241, such as inductors, resistors, capacitors, and microprocessors, or circuits formed by these embedded electronic components 241. These embedded electronic components 241 may be electronically connected to individual poly-CMUT elements 201 or to multiple poly-CMUT elements 201. This integration helps reduce the overall footprint of the poly-CMUT array 204, which interacts with the embedded electronic components 241. These embedded electronic components 241 can be incorporated directly during manufacturing, or can be added after the substrate 11 is completed by etching areas on its bottom surface 13 and then filling those areas with a material that has similar mechanical and chemical properties to the substrate 11, such as FR4 resin.

[0125] Referring now to FIG. 47 , an exploded view of a transducer assembly 250 is shown. It includes an electrical contact assembly 230. The electrical contact assembly 230 includes a plurality of electrical contact assembly connections 231 and is attached (e.g., glued or soldered) to a poly-CMUT array 204. This poly-CMUT array 204 can be either a poly-CMUT linear array 202 or a poly-CMUT matrix array 203 (not shown). An acoustic lens 240 is also attached (e.g., glued or molded) to the top surface of the poly-CMUT array 204. The purpose of this acoustic lens 240 is to generate a focused ultrasound beam. In some embodiments, this acoustic lens 240 can be molded directly onto the poly-CMUT array 204 using a mold (not shown), or in other embodiments, it can be molded onto a separate mold and then glued in place using an adhesive compatible with the materials of the acoustic lens 240 and the poly-CMUT array 204.

[0126] 48A, 48B, and 48C, three cross-sectional views of a Poly-CMUT linear array 202 with different substrate 11 thicknesses (T4, T5, and T6) are shown, with individual Poly-CMUT elements 201 visible on their top surfaces. The thicker substrate (T4) results in a larger radius of curvature (R4) when the Poly-CMUT linear array 202 is bent about the X-axis (axis coming out of the page, not shown), with T4>T5>T6 and R4>R5>R6. In some embodiments, several substrates 11 with vias 21 (not shown) can be fabricated into thin substrates (typically 0.4 mm thick) that result in semi-rigid / bendable Poly-CMUT linear arrays 202. [Example]

[0127] Referring now to Figure 49A, a photograph of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown. The wafer substrate front surface 211 has hundreds of exposed vias 21 and annular rings 22 (too small to be individually discernible in Figure 49A). The locations of these vias 21 and annular rings 22 correspond to the locations of the poly-CMUT arrays 204 that will be fabricated on this wafer substrate front surface 211. A detailed view of area A is shown in Figure 51.

[0128] Referring now to Figure 49B, a photograph of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown. The wafer substrate backside 212 has hundreds of electrical contact pads that provide individual electrical access to the vias 21 on the wafer substrate frontside 211. These electrical contact pads allow electrical contact assemblies 230 (e.g., headers or receptacles used in the PCB industry) to be soldered to interface with external electronics such as ultrasonic pulsers and amplifiers. Figure 50A shows a detailed view of area B.

[0129] 50A, there is shown a detailed view of area B appearing in FIG. 49B, which corresponds to a microscopic view of the wafer substrate backside 212.

[0130] 50B, there is shown a detailed view of area C appearing in FIG. 50A, which corresponds to a microscopic view of the wafer substrate backside 212. The annular ring 22 is electrically connected to the substrate conductive contact area 26 through a plurality of substrate conductive tracks 27 patterned using the same substrate conductive material 23.

[0131] Referring now to Figure 51, there is shown a detailed view of area A appearing in Figure 49A. This corresponds to a microscopic view of the wafer substrate front surface 211. A mechanical grinding and polishing system was used in conjunction with abrasive chemicals and polishing agents to obtain a polished substrate 30. Several polished vias 31 are also shown. These polished vias will be used to connect to the top electrodes (not shown) of the individual Poly-CMUT elements 201 that will be fabricated on top. The polishing system uniformly planarized the wafer substrate front surface 211 until a surface roughness of a few nm was achieved.

[0132] Referring now to Figure 52A, there is shown a surface roughness measurement of the wafer substrate front surface 211 along the distance L (shown in Figure 51) before the polishing stage. The average surface roughness is 2.092 μm. This measurement was obtained using a DektakXT™ stylus surface profilometer.

[0133] Referring now to Figure 52B, there is shown a surface roughness measurement of the wafer substrate front surface 211 along the distance L (shown in Figure 51) after the polishing step. The average surface roughness is 52.805 nm. This measurement was obtained using a DektakXT™ stylus surface profilometer.

[0134] 53A, a photograph of a wafer substrate 210 is shown on which several Poly-CMUT arrays 204 have been fabricated after the wafer substrate 210 has been polished with a grinding / lapping machine. Seven identical Poly-CMUT linear arrays 202 are located in the center, with three additional Poly-CMUT linear arrays 202 located on the sides. There is also a small Poly-CMUT matrix array 203 located in the northwest corner. The wafer substrate 210 will later be diced with a dicing saw to separate the individual Poly-CMUT arrays 204.

[0135] 53B, a photograph of a group of Poly-CMUT arrays 205 is shown. The Poly-CMUT arrays 204 were separated using a dicing saw. Only a small number of the Poly-CMUT linear arrays 202 are shown in this photograph.

[0136] Referring now to Figure 54A, there is shown a photograph of a Poly-CMUT linear array 202 (also shown in Figure 53B) fabricated on a substrate 11. The Poly-CMUT linear array 202 is composed of 128 Poly-CMUT elements 201 electrically connected to individual vias 21 (too small to be individually signaled in Figure 54A) on the substrate 11. An electrical contact assembly 230 is attached to the bottom surface 13 of the substrate 11. The Poly-CMUT linear array 202 was fabricated on a polished substrate 30 according to the first embodiment described above.

[0137] 54B, a photograph of the Poly CMUT linear array 202 mounted on an electrical test circuit board 233 is shown. An electrical contact assembly 230 mounted on the backside of the Poly CMUT linear array 202 interfaces with an electrical contact mating connection 232 incorporated into the electrical test circuit board 233. The electrical test circuit board 233 is used to send and receive electrical signals to and from the Poly CMUT linear array 202.

[0138] The Poly-CMUT linear array 202 shown in Figure 54B was partially immersed (face down) in an acoustic evaluation chamber (not shown) containing deionized water (DI water). A calibrated hydrophone manufactured by Onda Corporation of Sunnyvale, California, was immersed in the chamber and positioned 20 mm from the surface of the Poly-CMUT linear array 202 to measure the acoustic signal generated by each individual Poly-CMUT element 201. The recorder signal over time is shown in the graph of Figure 55A. The hydrophone recorded an acoustic signal at 73 kPa.

[0139] Referring now to Figure 55B, a Fast Fourier Transform (FFT) signal corresponding to the time-domain signal shown in Figure 55A is shown, exhibiting a center frequency of 7.4 MHz and a fractional bandwidth of 83% when a combination of 30V AC and 30V DC voltages is applied to the Poly-CMUT element 201. This demonstrates that fabrication and operation of the Poly-CMUT array 204 is possible using a pre-fabricated substrate with vias and electrical connections on the backside.

[0140] 56A, there is shown a computer design of a wafer substrate 210 to be fabricated in a printed circuit board manufacturing facility. The polished substrate conductive material 33 and the polished conductive area 35 for the top electrode are shown in inset. The polished substrate conductive material 33 occupies over 95% of the total area of ​​the wafer substrate 210.

[0141] 56B, a photograph of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown. The wafer substrate backside 212 has hundreds of contact pads that are each electrically coupled to a via 21 on the wafer substrate frontside 211. These electrical contact pads allow electrical contact assemblies 230 (e.g., headers or receptacles used in the PCB industry) to be soldered to enable interaction with external electronics such as ultrasonic pulsers and amplifiers.

[0142] 57A, there is shown a photograph of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility. The substrate conductive material 23 (not shown) is protected by a planarization layer 40 created using a standard solder mask in the PCB manufacturing facility.

[0143] Referring now to Figure 57B, a photograph of the wafer substrate 210 of Figure 57A after polishing is shown. A chemical mechanical polishing (CMP) apparatus was used to simultaneously polish the substrate conductive area 24 for the bottom electrode, the substrate conductive area 25 for the top electrode, and the planarization layer 40. The result is a wafer substrate 210 having a polished conductive area that serves as the bottom electrode 34 with a mirror finish, a similarly polished conductive area 35 for the top electrode, and a polished planarization layer 50.

[0144] Referring now to Figure 58A, a photograph of a region of the substrate of Figure 57B taken using a microscope is shown. The mirror finish of the polished conductive area that serves as the bottom electrode 34 reflects some of the light from the microscope lamp.

[0145] Referring now to Figure 58B, an enlarged view of Figure 58A is shown, showing the polished conductive area that serves as the bottom electrode 34, the polished conductive area 35 for the top electrode, and the polished planarization layer 50.

[0146] Referring now to Figure 59A, a photograph of a stylus profilometer is shown with the substrate of Figure 57B. The profilometer is used to measure the surface roughness of the polished conductive area that serves as the bottom electrode 34.

[0147] Referring now to Figure 59B, there is shown a profilometer measurement along the longitudinal axis of the substrate of Figure 59A (see line Y-Y' in Figure 57B). The 80 mm long measurement shows the curvature or "warp" of the substrate along with several surface roughness parameters.

[0148] Referring now to Figure 59C, a profilometer measurement is shown along the lateral axis of the substrate of Figure 59A (see line X-X' in Figure 58B). The 1.6 mm long measurement shows the surface profile of the polished conductive area 35 for the top electrode and the polished planarization layer 50.

[0149] Referring now to Figure 60A, there is shown a surface profilometer measurement along the X and Y axes of a standard 100mm prime grade silicon wafer with an oxide layer. This was done to measure the curvature or "warp" of a typical silicon wafer used for microfabrication. The wafer warp is between 20um and 30um.

[0150] Referring now to Figure 60B, measurement data along the X and Y axes of the substrate of Figure 59A is shown. The wafer warpage is 30-40um, which is approximately the same as the warpage of a standard silicon wafer. This means that the wafer substrate 210 is compatible with processing using standard microfabrication equipment.

[0151] Referring now to Figure 61A, a surface profilometer measurement along the central region of a standard 100 mm prime-grade silicon wafer with an oxide layer is shown. This was performed to measure the surface roughness of a typical silicon wafer used for microfabrication. The wafer roughness is between 20 nm and 40 nm.

[0152] Referring now to Figure 61B, a surface profilometer measurement along the central region of the substrate of Figure 59A is shown. The surface roughness is between 0 nm and 30 nm, which is roughly comparable to the surface roughness of a standard silicon wafer. This means that the wafer substrate 210 is suitable for processing using standard microfabrication equipment and can be used for the direct fabrication of poly-CMUT arrays 205.

[0153] Referring now to Figure 62A, there is shown a surface profilometer measurement along the polished planarization layer 50 of the substrate of Figure 59A. The surface roughness is between -40 nm and 20 nm. This means that the first polymer layer 110 and top electrode interconnects 117 can be directly patterned, as discussed with respect to Figure 25B.

[0154] Referring now to Figure 62B, a 100um profilometer measurement along the area of ​​the substrate in Figure 59A is shown, with surface roughness ranging from -5nm to 5nm.

[0155] Referring now to Figure 63, in contrast to certain ringing effects in CMUTs fabricated on silicon substrates due to unwanted acoustic reflections occurring in the silicon substrate, which appear as notches in the frequency response [2], in the non-silicon fabrication approach of the present embodiment, any ringing effects are located outside the frequency range of interest. For example, the center frequency of the acoustic signal shown in Figure 55B is 7.4 MHz, but the ringing effect in this substrate appears around 1.68 MHz for a 1 mm thick substrate. This frequency is outside the -6 dB lower frequency limit (approximately 4.0 MHz).

[0156] advantage Poly-CMUTs fabricated according to at least some of the embodiments herein offer advantages over conventional silicon-based CMUTs. For example, the total manufacturing cost of a poly-CMUT can often be well below $100. Poly-CMUTs require minimal, inexpensive manufacturing equipment (e.g., mask aligners, metal evaporators, critical point dryers), an advantage over silicon-based CMUTs, which require expensive and cumbersome equipment. Poly-CMUT arrays of at least some embodiments are also flexible, as shown in Figures 48A, 48B, and 48C, which illustrate bending in either one dimension (x) or two dimensions (x, y). This is also shown in Figures 65A, 65B, 65C, 66A, 66B, and 66C. Polymer-based CMUTs can be fabricated on flexible substrates for wearable applications, and the PCBs can be flexible or rigid, as discussed above. This is not possible with silicon-based CMUTs, including the silicon-based CMUT embodiment of Figures 37A and 37B, because a rigid substrate is required. Similarly, flexible substrates cannot be used when fabricating CMUTs using ceramic piezoelectric materials.

[0157] Another advantage of the manufacturing techniques described with respect to the embodiments herein is that the multi-layer manufacturing techniques allow for electrical shielding of signal cables, for example, individual traces from a CMUT element can be shielded between two ground planes to minimize electromagnetic interference (EMI).

[0158] Epoxy resins used in PCB manufacturing, such as FR4, have a low X-ray mass absorption coefficient, and therefore the substrate is considered to be X-ray transparent.

[0159] The application techniques described in any of these embodiments are also compatible with wafer bonding manufacturing techniques such as those described in U.S. Patent Nos. 10,509,013, 10,564,132, and 10,598,632. The manufacturing techniques of the various embodiments herein are also compatible with more conventional chip bonding using solder bumps.

[0160] Application Examples 64A and 64B, a cross-sectional front view and a cross-sectional side view, respectively, of a probe assembly 251 are shown. A poly-CMUT array 204 with an acoustic lens 240 and an electrical contact assembly 230 is mounted in an existing probe case 252, which includes an electrical contact mating portion 232 that connects to an electrical interface board 234 containing multiple electronic components 241 (e.g., capacitors, inductors, resistors, etc.). An advantage of the manufacturing approach described in any of the embodiments herein is that it significantly simplifies the assembly or repair of an ultrasonic probe. This manufacturing approach avoids the wire bonding, encapsulation, and lens molding procedures of conventional piezoelectric and silicon-based transducers.

[0161] Referring now to Figures 65A, 65B, and 65C, a probe assembly 251 is shown, consisting of a sealed probe case 252 into which a poly-CMUT array 204 is mounted. The probe case 252 has a single passageway 260 leading to an internal chamber 261. This internal chamber 261 can be filled with gas or liquid at different pressures (P1, P2, or P3). The poly-CMUT array is thin enough to deflect due to the pressure within the internal chamber 261. At pressures below atmospheric pressure, as shown in Figures 65B and 65C, the poly-CMUT array 204 deflects inward toward the probe case 252. At pressures equal to atmospheric pressure, no deflection occurs, as shown in Figure 65A. At pressures above atmospheric pressure (not shown), the poly-CMUT array 204 deflects outward from the probe case. Many or all of the poly-CMUT elements in the poly-CMUT array 204 may operate simultaneously to generate individual ultrasonic waves 270. Depending on the deflection of the poly-CMUT array 204, an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained at various focal points 273. In some embodiments, this may be beneficial for ultrasound probes specialized for therapeutic applications, where a physically focused ultrasound beam 272 is desired over an electronically focused ultrasound beam to deliver relatively high acoustic energies that promote tissue healing.

[0162] Referring now to Figures 66A, 66B, and 66C, a probe assembly 251 is shown, comprising a probe case 252 into which a poly-CMUT array 204 is assembled to form an ultrasound probe. The probe case 252 has a deflection mechanism 262 attached to the backside of the poly-CMUT array 204. The deflection mechanism produces vertical displacements 263 (D1, D2, and D3) that induce deflection of the poly-CMUT array 204. The poly-CMUT array 204 is thin enough to be deflected by the deflection mechanism 262. Many or all of the poly-CMUT elements 201 in the poly-CMUT array 204 can operate simultaneously to generate individual ultrasound waves 270. Depending on the deflection of the poly-CMUT array 204, unfocused ultrasound beams 271 or focused ultrasound beams 272 can be obtained at various focal points 273. In some embodiments, this may be beneficial for ultrasound probes specialized for therapeutic applications. In therapeutic applications, a physically focused ultrasound beam 272 is preferred over an electronically focused ultrasound beam to deliver relatively high acoustic energies that promote tissue healing.

[0163] Referring now to FIG. 67, a poly-CMUT linear array 202 composed of poly-CMUT elements 201 (not individually identified) is constructed on a polished substrate 30. The polished substrate 30 is composed of two or more lower substrate layers 16 (not individually identified) stacked on top of each other. Internal vias 21 (not shown) and internal substrate conductive material 23 (not shown) are present between the lower substrate layers 16. One or more planar inductors 242 are fabricated on the surface of either of the substrate layers 16. These planar inductors 242 can generate and receive wireless signals, such as for power, similar to a wireless charger, or for data communication. A possible application of the array 202 of FIG. 67 is a completely wireless poly-CMUT array 204.

[0164] In this disclosure, the recitation of numerical ranges by endpoints includes all numbers subsumed within that range, including all whole numbers, all integers, and all fractional intermediates (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5, etc.).

[0165] When a value is referred to as "about" or "approximately" a quantity, it means that the value is within ±10% of that amount, unless the context dictates otherwise.

[0166] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Thus, as used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise (e.g., a reference in a claim to "a via" or "the via" does not exclude embodiments in which multiple vias are used, and a reference to fabricating "a bottom electrode" and "a top electrode" includes references in which arrays of multiple bottom electrodes and multiple top electrodes are fabricated). It will be further understood that the terms "comprises" and "comprising," as used herein, specify the presence of one or more stated features, integers, steps, operations, elements, and components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and groups. In the following description, directional terms such as "top," "bottom," "upwards," "downwards," "vertically," and "laterally" are used for relative reference purposes only and are not intended to suggest any limitations on how any item should be positioned during use or attached in an assembly or to its environment. Additionally, the term "connect," and variations thereof, such as "connected," "connects," and "connecting," as used herein, are intended to include indirect and direct connections unless otherwise noted. For example, when a first device is connected to a second device, the coupling may be by a direct connection or by an indirect connection via other devices and connections.Similarly, when a first device is communicatively connected to a second device, the communication may be by way of a direct connection or by way of an indirect connection via other devices and connections.

[0167] Phrases such as "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," and "A, B, and / or C" are intended to include both a single item from the list of enumerated items (i.e., A only, B only, or C only) and multiple items from the list (i.e., A and B, B and C, A and C, and A, B, and C). Thus, "at least one," "one or more," and similar phrases used in conjunction with a list do not require that every item in the list be present, although each item in the list may be present.

[0168] It is contemplated that any portion of any aspect or embodiment discussed herein can be implemented or combined with any portion of any other aspect or embodiment discussed herein, provided that such portions are not mutually exclusive.

[0169] The scope of the claims is not intended to be limited by the embodiments set forth in the examples above, but rather is to be accorded the broadest interpretation consistent with the specification as a whole.

[0170] It should be appreciated that features and aspects of the various examples provided above can be combined to produce additional examples that also fall within the scope of the present disclosure. Additionally, the figures are not drawn to scale, and sizes and shapes may be exaggerated for illustrative purposes.

[0171] References [1] O. Oralkan et al., "Capacitive micromachined ultrasonic transducers: Next-generation arrays for acoustic imaging?", Ultrason. Ferroelectr. Freq. Control IEEE Trans. On, Vol. 49, No. 11, pp. 1596-1610, 2002. [2] KR Chapagain, "Integration of Electronics and Mechanics in Next Generation Ultrasound Transducers in Medical Imaging," NTNU, 2014. Accessed: December 21, 2021. [Online]. Available: https: / / ntnuopen.ntnu.no / ntnu-xmlui / handle / 11250 / 2370933

Claims

1. A method for manufacturing a capacitive micromachine ultrasonic transducer, (i) Removing a layer from the top surface of a substrate, wherein at least one pair of electrical interconnects extends through at least a portion of the substrate and is exposed on the top surface, (ii) After removal, deposit a first conductive material on the top surface, wherein the first conductive material covers the pair of electrical interconnections, (iii) Patterning the first conductive material such that contact areas for a bottom electrode and a top electrode are formed, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects, and the contact area for the top electrode is electrically connected to the other of the pair of electrical interconnects, (iv) After the patterning, deposit the sacrificial material on the bottom electrode, (v) Patterning the sacrificial material such that a sacrificial film area connected to at least one sacrificial etching channel is formed, (vi) After patterning the sacrificial material, deposit a first polymer layer or silicon layer on the substrate, the bottom electrode, the contact area, and the sacrificial material, (vii) Patterning the first polymer layer or silicon layer such that at least one via leading to the at least one sacrificial etching channel is formed, (viiii) Depositing a second conductive material on the first polymer layer or silicon layer and on the contact area for the top electrode, (ix) Patterning the second conductive material to avoid electrical connection with the bottom electrode, (x) A method comprising etching away the sacrificial film area using the at least one via.

2. After the sacrificial material has been patterned, the first polymer layer is deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material. (i) Depositing a second polymer layer on the second conductive material and the sacrificial film area, (ii) The method according to claim 1, further comprising patterning the second polymer layer so as not to block at least one via.

3. The method according to claim 1, wherein after the sacrificial material has been patterned, the silicon layer is deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material.

4. The method according to any one of claims 1 to 3, wherein the substrate comprises a printed circuit board.

5. The method according to claim 4, wherein the printed circuit board is flexible.

6. The method according to any one of claims 1 to 3, wherein the substrate includes ceramic.

7. The method according to claim 1, wherein the removal of the aforementioned layer is performed mechanically.

8. The method according to claim 7, wherein removing the layer includes polishing or grinding the top surface of the substrate.

9. The method according to claim 1, wherein the removal of the aforementioned layer is carried out chemically.

10. The method according to claim 9, wherein removing the layer includes etching the top surface of the substrate.

11. The method according to claim 1, wherein, before removing the layer, there are pads of conductive material on the top surface that are electrically coupled to the pair of electrical interconnects, and removing the layer includes removing the pads and a portion of the substrate.

12. The method according to claim 1, wherein after the removal, the top surface has a surface roughness of 50 nanometers or less.

13. The method according to claim 1, wherein the first conductive material comprises a layer of gold between two layers of chromium.

14. The method according to claim 1, wherein the first conductive material has a thickness of approximately 100 nm.

15. The method according to claim 1, wherein the sacrificial material has a thickness of approximately 200 nm.

16. The method according to claim 1, wherein the deposition of the sacrificial material comprises depositing a lift-off resist layer and then depositing a positive-type photoresist layer.

17. The method according to claim 1, wherein the patterning of the sacrificial material is carried out by wet etching using an aqueous solution containing tetramethylammonium hydroxide.

18. The method according to claim 2, wherein the first polymer layer has a thickness of approximately 700 nm.

19. The method according to claim 1, wherein depositing the second conductive material comprises depositing a layer of titanium and then depositing a layer of gold.

20. The method according to claim 1, further comprising encapsulating the transducer using an encapsulation material.

21. The method according to claim 20, wherein the bottom surface of the substrate is provided with pads of a conductive material electrically coupled to the pair of electrical interconnects, and further comprising covering the pads on the bottom surface before encapsulating the transducer to prevent the pads from being covered by the encapsulation material.

22. After the top layer has been removed and before the first conductive material is deposited, (i) Depositing a flattening layer on the top surface, (ii) The method according to claim 1, further comprising patterning the planarization layer such that the electrical interconnects remain exposed on the top surface.

23. The method according to claim 22, wherein the planarization layer has a thickness of about 1 μm.

24. The method according to claim 22 or 23, wherein the planarization layer includes SU-8 photoresist.

25. The method according to claim 22, wherein the planarized layer has a roughness of 50 nanometers or less.

26. Before removing the layer from the top surface of the substrate, (i) Depositing a substrate conductive material on the surface of the substrate, (ii) Patterning the substrate conductive material such that a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode are formed, wherein the substrate conductive area for the bottom electrode is electrically connected to one of the pair of electrical interconnects, and the substrate conductive area for the top electrode is electrically connected to the other of the pair of electrical interconnects, (iii) Further comprising depositing a planarization layer on the substrate and the conductive area of ​​the substrate, The substrate conductive area for the bottom electrode and the bottom electrode are electrically connected to the same electrical interconnect, and the substrate conductive area for the top electrode and the contact area for the top electrode are electrically connected to the same electrical interconnect. The method according to claim 1, wherein the layer removed from the top surface of the substrate includes the planarization layer above the conductive material of the substrate.

27. The method according to claim 26, wherein the planarization layer comprises an epoxy resin.

28. The method according to claim 26 or 27, wherein the planarization layer has a thickness equal to or greater than the thickness of the substrate conductive material.

29. The method according to claim 26, further comprising degassing the planarization layer after depositing the planarization layer and before removing the layer from the top surface of the substrate.

30. The method according to claim 22 or 26, wherein the planarization layer includes a solder mask layer of a printed circuit board.

31. (i) The layer removed from the top surface of the substrate includes an upper substrate layer bonded to the substrate, (ii) Between the substrate and the upper substrate layer, there is a substrate conductive area for the bottom electrode and a substrate conductive area for the top electrode, the substrate conductive area for the bottom electrode is electrically connected to one of the pair of electrical interconnects, and the substrate conductive area for the top electrode is electrically connected to the other of the pair of electrical interconnects, (iii) The method according to claim 1, wherein the substrate conductive area for the bottom electrode and the bottom electrode are electrically connected to the same electrical interconnect, and the substrate conductive area for the top electrode and the contact area for the top electrode are electrically connected to the same electrical interconnect.

32. The method according to claim 1, wherein the electrical interconnection portion extends non-linearly through the substrate.

33. The method according to claim 1, wherein the capacitive micromachine ultrasonic transducer is one of an array of capacitive micromachine ultrasonic transducers manufactured simultaneously by the method described above.

34. (i) A printed circuit board (PCB) comprising at least one pair of electrical interconnects that extend through at least a portion of the PCB and are exposed on the top surface of the PCB, (ii) A capacitive micromachine ultrasonic transducer cell on the PCB, (A) A bottom electrode electrically connected to one of the pair of electrical interconnections on the top surface, (B) A top electrode that is electrically connected to the other of the pair of electrical interconnects on the top surface, (C) A polymer layer or silicon layer between the top electrode and the bottom electrode, and (D) The capacitive micromachine ultrasonic transducer cell comprising a sealed cavity between the polymer layer or silicon layer and the bottom electrode, A capacitive micromachine ultrasonic transducer assembly comprising:

35. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the PCB is flexible.

36. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the PCB comprises ceramic.

37. The capacitive micromachine ultrasonic transducer assembly according to any one of claims 34 to 36, wherein the bottom electrode is directly located on the PCB.

38. The capacitive micromachine ultrasonic transducer assembly according to any one of claims 34 to 36, wherein the bottom electrode is located on a planarization layer.

39. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the bottom electrode is located on a planarization layer, and the planarization layer includes a solder mask.

40. The capacitive micromachine ultrasonic transducer assembly according to claim 38, wherein the bottom electrode is located on a planarization layer and is in the same plane as a portion of the PCB layer.

41. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the bottom electrode is coplanar with a portion of the planarization layer.

42. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the bottom electrode is coplanar with the bottom portion of the polymer layer or silicon layer.

43. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the capacitive micromachine ultrasonic transducer cell is one of an array of capacitive micromachine ultrasonic transducer cells, the array comprises capacitive micromachine ultrasonic transducer elements corresponding to different groups selected from a plurality of capacitive micromachine ultrasonic transducer cells, and the capacitive micromachine ultrasonic transducer elements are each electrically connected to the electrical interconnection section.

44. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the polymer layer is located between the top electrode and the bottom electrode.

45. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the silicon layer is located between the top electrode and the bottom electrode.

46. The capacitive micromachine ultrasonic transducer assembly according to claim 34, wherein the electrical interconnection portion extends non-linearly through the PCB.

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